TWI808715B - How to make transistors - Google Patents
How to make transistors Download PDFInfo
- Publication number
- TWI808715B TWI808715B TW111113412A TW111113412A TWI808715B TW I808715 B TWI808715 B TW I808715B TW 111113412 A TW111113412 A TW 111113412A TW 111113412 A TW111113412 A TW 111113412A TW I808715 B TWI808715 B TW I808715B
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor layer
- layer
- channel
- manufacturing
- transistor
- Prior art date
Links
Abstract
一種電晶體的製作方法，包含：(a)在基板上成長由GaN所構成的緩衝層及第一半導體層，第一半導體層表面具有微凸點與微孔穴；(b)平坦化第一半導體層表面以於其表面留下微孔穴；(c)以ALD在第一半導體層上成長第二半導體層，其是由Ga與選自下列所構成之群組的至少一元素所構成：O與N，且表面具有Ga空缺與前述元素的空缺；(d)對第二半導體層施予含有蝕刻劑的蝕刻處理從而修補其表面的空缺，蝕刻劑含F與前述元素；(e)對緩衝層、第一、二半導體層定義出通道；(f)於通道上形成閘極介電層；(g)於閘極介電層上形成閘極；及(h)於通道的相反側各自形成源極、汲極。 A method for manufacturing a transistor, comprising: (a) growing a buffer layer made of GaN and a first semiconductor layer on a substrate, the surface of the first semiconductor layer having micro bumps and micro holes; (b) planarizing the surface of the first semiconductor layer to leave micro holes on the surface; (c) growing a second semiconductor layer on the first semiconductor layer by ALD, which is composed of Ga and at least one element selected from the group consisting of O and N, and has Ga vacancies and vacancies of the aforementioned elements on the surface; (e) define a channel for the buffer layer, first and second semiconductor layers; (f) form a gate dielectric layer on the channel; (g) form a gate electrode on the gate dielectric layer; and (h) form a source electrode and a drain electrode on opposite sides of the channel.
Description
本發明是有關於一種電晶體的製法，特別是指一漏電流低之電晶體的製作方法。 The present invention relates to a method for manufacturing a transistor, in particular to a method for manufacturing a transistor with low leakage current.
第一代半導體矽(Si)基於其具有1.17eV的能隙而使其適用於功率半導體裝置。然而，隨著IC製程技術不斷地演進，半導體裝置不斷地輕薄短小化以及IC之邏輯運算上等等的需求，相關技術產業也相繼地開發出砷化鎵(GaAs)及磷化銦(InP)等第二代半導體，與碳化矽(SiC)及氮化鎵(GaN)等第三代半導體，直至近年業界也關注到能隙高達4.9eV的氧化鎵(Ga2O3)此一***半導體。 The first generation semiconductor silicon (Si) is suitable for power semiconductor devices based on its energy gap of 1.17eV. However, with the continuous evolution of IC process technology, the continuous thinning and miniaturization of semiconductor devices , and the demand for IC logic operations, related technology industries have also successively developed second-generation semiconductors such as gallium arsenide (GaAs) and indium phosphide (InP), and third-generation semiconductors such as silicon carbide (SiC) and gallium nitride ( GaN ).
對於所屬技術領域的相關產業來說，在藍寶石基板或SOI基板上製作金氧半場效電晶體(MOSFET)目前所面臨到的挑戰不外乎有GaN緩衝層所致的厚度差、晶格不匹配(lattice mismatch)、表面缺陷(如，表面微凸點、微凹穴)與空缺等問題。 For the relevant industries in the technical field, the challenges currently faced in the fabrication of MOSFETs on sapphire substrates or SOI substrates are nothing more than the thickness difference caused by the GaN buffer layer, lattice mismatch (lattice mismatch), surface defects (such as surface micro-bumps, micro-cavities) and vacancies.
參閱圖1與圖2，如，中華民國第TWI715311證書號發明 專利案(以下稱前案1)公開一種具有寬能隙三五族汲極之金氧化物矽半導體場效電晶體(Si MOSFET)1及其造方法。前案1是採用有機金屬化學氣相沉積技術(MOCVD)在一SOI基板10之一矽晶圓11的(111)晶面的百奈米級孔洞100處選擇性成長一GaN汲極12，使單晶的六方晶體氮化鎵(h-GaN)可以由該矽晶圓11之(111)晶面上方開始成長，其在結晶過程的差排(dislocation)能終止於該百奈米級孔洞100的斜面，當h-GaN於該百奈米級孔洞100中間合併時可獲得高結晶度的立方晶體氮化鎵(c-GaN)。前案1一方面解決前述晶格不匹配的問題，另一方面也藉由該GaN汲極12來提高該矽半導體高場效電晶體1的擊穿電壓。 Refer to Figure 1 and Figure 2, for example, the invention of the Republic of China No. TWI715311 certificate The patent case (hereinafter referred to as the previous case 1) discloses a gold oxide silicon semiconductor field-effect transistor (Si MOSFET) 1 with a wide bandgap III-V drain and its manufacturing method. The previous case 1 is to selectively grow a GaN drain 12 at the 100nm-scale hole 100 of the (111) crystal plane of a silicon wafer 11 on an SOI substrate 10 by using metalorganic chemical vapor deposition (MOCVD), so that single-crystal hexagonal gallium nitride (h-GaN) can start to grow from above the (111) crystal plane of the silicon wafer 11, and its dislocation during the crystallization process can be terminated at the 100-nm scale hole 100 When h-GaN is merged in the center of the 100nm hole 100, cubic gallium nitride (c-GaN) with high crystallinity can be obtained. The previous proposal 1 solves the above-mentioned lattice mismatch problem on the one hand, and on the other hand improves the breakdown voltage of the silicon semiconductor high field effect transistor 1 through the GaN drain 12 .
雖然前案1可解決前述晶格不匹配的問題；然而，經由MOCVD成膜所致的厚度差(如，顯示於圖2的該GaN汲極12與該矽晶圓11間的微凸點/厚度差)，也是影響場效電晶體漏電流與擊穿電壓的主因。 Although the previous proposal 1 can solve the aforementioned lattice mismatch problem; however, the thickness difference caused by MOCVD film formation (such as the micro-bump/thickness difference between the GaN drain 12 and the silicon wafer 11 shown in FIG. 2 ) is also the main reason affecting the leakage current and breakdown voltage of the field effect transistor.
經上述說明可知，改善MOCVD成膜所致的厚度差問題從而解決電晶體的漏電流問題，是本案所屬技術領域中的相關技術人員有待突破的課題。 From the above description, it can be seen that improving the thickness difference problem caused by MOCVD film formation to solve the leakage current problem of transistors is a subject to be broken through by the relevant technical personnel in the technical field to which this case belongs.
因此，本發明的第一目的，即在提供一種改善MOCVD成膜所致的厚度差問題以減少漏電流問題之電晶體的製作方法。 Therefore, the first object of the present invention is to provide a method for manufacturing a transistor that improves the thickness difference problem caused by MOCVD film formation and reduces the leakage current problem.
於是，本發明之電晶體的製作方法，其包括以下步驟：一步驟(a)、一步驟(b)、一步驟(c)、一步驟(d)、一步驟(e)、一步驟(f)、一步驟(g)，及一步驟(h)。 Thus, the manufacturing method of the transistor of the present invention comprises the following steps: a step (a), a step (b), a step (c), a step (d), a step (e), a step (f), a step (g), and a step (h).
該步驟(a)是在一基板的一表面上依序磊晶成長有一緩衝層及一第一半導體層，該緩衝層與第一半導體層是由一以GaN為主(GaN-based)的半導體材料所構成，且該第一半導體層的一表面具有複數微凸點與複數微孔穴。 In the step (a), a buffer layer and a first semiconductor layer are sequentially epitaxially grown on a surface of a substrate. The buffer layer and the first semiconductor layer are composed of a GaN-based semiconductor material, and a surface of the first semiconductor layer has a plurality of micro bumps and a plurality of micro holes.
該步驟(b)是平坦化該第一半導體層以移除該第一半導體層表面的微凸點，並於該第一半導體層的表面留下該等微孔穴。 The step (b) is to planarize the first semiconductor layer to remove the micro bumps on the surface of the first semiconductor layer, and leave the micro holes on the surface of the first semiconductor layer.
該步驟(c)是以一原子層沉積(atomic layer deposition，ALD)技術在該步驟(b)之第一半導體層的表面上成長一第二半導體層以填補該等微孔穴，該第二半導體層是由Ga與選自由下列所構成之群組的至少一元素所構成：O與N，其中，該第二半導體層的一表面具有Ga空缺與至少一前述元素的空缺。 The step (c) grows a second semiconductor layer on the surface of the first semiconductor layer in the step (b) by an atomic layer deposition (ALD) technique to fill the microcavities, the second semiconductor layer is composed of Ga and at least one element selected from the group consisting of O and N, wherein a surface of the second semiconductor layer has Ga vacancies and at least one vacancy of the aforementioned elements.
該步驟(d)是對該步驟(c)之第二半導體層施予一含有一蝕刻劑的一蝕刻處理，從而修補該第二半導體層表面的空缺，其中，該蝕刻劑含有鹵素元素與至少一前述元素。 The step (d) is to apply an etching process containing an etchant to the second semiconductor layer in the step (c), so as to repair the vacancy on the surface of the second semiconductor layer, wherein the etchant contains halogen elements and at least one aforementioned element.
該步驟(e)是對該緩衝層、第一半導體層與第二半導體層定義出一通道。 The step (e) is to define a channel for the buffer layer, the first semiconductor layer and the second semiconductor layer.
該步驟(f)是於該通道上形成一閘極介電層。 The step (f) is to form a gate dielectric layer on the channel.
該步驟(g)是於該閘極介電層上形成一閘極。 The step (g) is to form a gate on the gate dielectric layer.
該步驟(h)是於該通道的一側及相反於該側的另一側分別形成一源極及一汲極。 The step (h) is to respectively form a source and a drain on one side of the channel and on the other side opposite to the channel.
本發明的功效在於：在實施完磊晶成長後透過平坦化的程序以初步改善磊晶成長所致的厚度差問題，且後續所實施的該ALD與含有蝕刻劑之蝕刻處理等程序，更能填補該第一半導體層表面因磊晶成長所致的微孔穴，也能修補該第二半導體層表面的Ga空缺使其達奈米等級的拋光作用，從而改善漏電流問題。 The effect of the present invention is: after the epitaxial growth is completed, the thickness difference problem caused by the epitaxial growth is initially improved through the planarization process, and the subsequent implementation of the ALD and etching treatment containing an etchant can fill the micro-cavities caused by the epitaxial growth on the surface of the first semiconductor layer, and can also repair Ga vacancies on the surface of the second semiconductor layer to achieve nanometer level polishing, thereby improving the leakage current problem.
2:基板 2: Substrate
3:通道 3: channel
31:第一半導體層 31: The first semiconductor layer
311:微凸點 311: micro bump
312:微孔穴 312: micro hole
32:第二半導體層 32: Second semiconductor layer
321:Ga空缺 321:Ga vacancies
322:N空缺 322: N vacancy
4:閘極介電層 4: Gate dielectric layer
5:閘極 5: gate
6:源極 6: Source
7:汲極 7: drain
8:蝕刻劑 8: etchant
80:副產物 80:By-products
本發明的其他的特徵及功效，將於參照圖式的實施方式中清楚地呈現，其中：圖1是一正視示意圖，說明中華民國第TWI715311證書號發明專利案所公開的具有寬能隙三五族汲極之金氧化物矽半導體場效電晶體；圖2是一掃描式電子顯微鏡(SEM)影像，說明圖1之金氧化物矽半導體場效電晶體的表面缺陷；圖3是一正視示意圖，說明本發之電晶體的製作方法的一實施例的一步驟(a)；圖4是一正視示意圖，說明本發該實施例之製作方法的一步驟 (b)；圖5是一正視示意圖，說明本發該實施例之製作方法的一步驟(c)；圖6是一正視示意圖，說明本發該實施例之製作方法的一步驟(d)；圖7是一原子力顯微鏡(atomic force microscope，以下稱AFM)影像圖，說明經本發明該實施例之製作方法的步驟(d)所得到的一第二半導體層的平均表面粗糙度(Ra)；圖8是一AFM立體影像圖，說明經本發明該實施例之製作方法的步驟(d)所得到的平均表面粗糙度(Ra)立體影像；圖9是一正視示意圖，說明本發明該實施例之製作方法的一步驟(e)；圖10是一正視示意圖，說明本發明該實施例之製作方法的一步驟(f)；圖11是一正視示意圖，說明本發明該實施例之製作方法的一步驟(g)；及圖12是一正視示意圖，說明本發明該實施例之製作方法的一步驟(h)並說明最終所製得的一電晶體。 Other features and functions of the present invention will be clearly presented in the embodiments with reference to the drawings, wherein: FIG. 1 is a schematic front view illustrating a gold oxide silicon semiconductor field effect transistor with a wide energy gap group III and V drain electrode disclosed in the invention patent of the Republic of China No. TWI715311; FIG. 2 is a scanning electron microscope (SEM) image illustrating surface defects of the gold oxide silicon semiconductor field effect transistor in FIG. 1; FIG. a step (a); Fig. 4 is a front schematic diagram illustrating a step of the manufacturing method of this embodiment of the present invention (b); Fig. 5 is a front schematic diagram illustrating a step (c) of the manufacturing method of this embodiment of the present invention; Fig. 6 is a front schematic diagram illustrating a step (d) of the manufacturing method of this embodiment of the present invention; Fig. 7 is an atomic force microscope (atomic force microscope, hereinafter referred to as AFM) image diagram illustrating the average surface roughness (Ra) of a second semiconductor layer obtained through step (d) of the manufacturing method of this embodiment of the present invention; The average surface roughness (Ra) stereoscopic image obtained in the step (d) of the manufacturing method of this embodiment of the present invention; FIG. 9 is a schematic front view illustrating a step (e) of the manufacturing method of this embodiment of the present invention; FIG. 10 is a schematic front view illustrating a step (f) of the manufacturing method of this embodiment of the present invention; FIG. h) and describe the final transistor.
本發明之電晶體的製作方法的一實施例，其包括以下步驟：一步驟(a)、一步驟(b)、一步驟(c)、一步驟(d)、一步驟(e)、一步驟(f)、一步驟(g)，及一步驟(h)。 An embodiment of the manufacturing method of the transistor of the present invention comprises the following steps: a step (a), a step (b), a step (c), a step (d), a step (e), a step (f), a step (g), and a step (h).
參閱圖3，該步驟(a)是透過MOCVD在一基板2的一表面上依序磊晶成長有一緩衝層(圖未示)及一第一半導體層31。該緩衝層與第一半導體層31是由一以GaN為主的半導體材料所構成，且該第一半導體層31的一表面具有複數MOCVD所致的微凸點311與複數微孔穴312。適用於本發明該實施例之基板2是選自一由下列所構成的群組的基板：藍寶石、矽、碳化矽(SiC)，及SOI。在本發明該實施例中，該基板2是一藍寶石基板，該緩衝層與第一半導體層31是由GaN所構成，且該緩衝層與第一半導體層31的厚度各介於0.1nm至50nm間與700μm至2000μm間，但其不限於此。 Referring to FIG. 3 , the step (a) is to sequentially epitaxially grow a buffer layer (not shown) and a first semiconductor layer 31 on a surface of a substrate 2 by MOCVD. The buffer layer and the first semiconductor layer 31 are made of GaN-based semiconductor material, and a surface of the first semiconductor layer 31 has a plurality of micro bumps 311 and a plurality of micro holes 312 caused by MOCVD. The substrate 2 suitable for this embodiment of the present invention is a substrate selected from a group consisting of sapphire, silicon, silicon carbide (SiC), and SOI. In this embodiment of the present invention, the substrate 2 is a sapphire substrate, the buffer layer and the first semiconductor layer 31 are made of GaN, and the thicknesses of the buffer layer and the first semiconductor layer 31 are respectively between 0.1 nm to 50 nm and 700 μm to 2000 μm, but it is not limited thereto.
參閱圖4，該步驟(b)是平坦化該第一半導體層31以移除該第一半導體層31表面的微凸點311，並於該第一半導體層31的表面留下該等微孔穴312。較佳地，本發明該步驟(b)之平坦化是對該第一半導體層31施予一化學機械研磨(chemical-mechanical polishing，簡稱CMP)技術。 Referring to FIG. 4 , the step (b) is to planarize the first semiconductor layer 31 to remove the micro bumps 311 on the surface of the first semiconductor layer 31 and leave the micro holes 312 on the surface of the first semiconductor layer 31 . Preferably, the planarization in the step (b) of the present invention is to apply a chemical-mechanical polishing (CMP) technique to the first semiconductor layer 31 .
參閱圖5，該步驟(c)是以一ALD技術在該步驟(b)之第一半導體層31的表面上成長一第二半導體層32，以填補該等微孔穴312。該第二半導體層32是由Ga與選自由下列所構成之群組的至少 一元素所構成：O與N；其中，該第二半導體層32的一表面具有在實施該ALD技術過程中未完全反應的前驅物(precursor)所構成的Ga空缺321與至少一前述元素的空缺(見圖6，如N空缺322)。在本發明該實施例中，該第二半導體層32是由GaN所構成。本發明該實施例雖以該第二半導體層32是由GaN所構成為例做說明，但其並不限於此。須知道的是，該第二半導體層32最終最製作成電晶體時是用來做為電晶體的通道使用；因此，該第二半導體層32也可以是由能隙大於GaN的Ga2O3所構成。 Referring to FIG. 5 , the step (c) grows a second semiconductor layer 32 on the surface of the first semiconductor layer 31 in the step (b) by an ALD technique to fill the micro-cavities 312 . The second semiconductor layer 32 is made of Ga and at least one element selected from the group consisting of: O and N; wherein, a surface of the second semiconductor layer 32 has a Ga vacancy 321 formed by a precursor (precursor) that is not fully reacted during the implementation of the ALD process and at least one vacancy of the aforementioned element (see FIG. 6, such as N vacancy 322). In this embodiment of the present invention, the second semiconductor layer 32 is made of GaN. Although the embodiment of the present invention is described by taking the second semiconductor layer 32 made of GaN as an example, it is not limited thereto. It should be noted that the second semiconductor layer 32 is used as a channel of the transistor when it is finally fabricated into a transistor; therefore, the second semiconductor layer 32 may also be composed of Ga 2 O 3 with an energy gap larger than GaN.
再參閱圖6，該步驟(d)是對該步驟(c)之第二半導體層32施予一含有一蝕刻劑8的一蝕刻處理，從而修補該第二半導體層32表面的空缺(如，該實施例之Ga空缺321與N空缺322)，以使該第二半導體層32的表面平坦化，並移除該第二半導體層32表面的缺陷(surface defect)；其中，該蝕刻劑8含有鹵素元素與至少一前述元素。適用於本發明該蝕刻劑8的鹵素元素是選自F或Cl。較佳地，該步驟(d)之蝕刻處理是選自一濕式蝕刻法(wet etching)或一乾式蝕刻法(dry etching)。更佳地，該步驟(d)之蝕刻處理是乾式蝕刻法。在本發明該實施例中，該乾式蝕刻法是實施原子層蝕刻(atomic layer etching，ALE)技術。適用於本發明該步驟(d)之ALE技術的蝕刻劑8是選自由下列所構成之群組的氣體分子：NF3，及POCl3。在本發明該實施例中，該蝕刻劑8是以NF3氣體分 子為例做說明，但不限於此。 Referring to FIG. 6 again, the step (d) is to apply an etching process containing an etchant 8 to the second semiconductor layer 32 of the step (c), so as to repair the vacancies on the surface of the second semiconductor layer 32 (such as Ga vacancies 321 and N vacancies 322 in this embodiment), so as to planarize the surface of the second semiconductor layer 32 and remove surface defects on the surface of the second semiconductor layer 32; wherein the etchant 8 contains halogen elements and at least one aforementioned element. The halogen element suitable for the etchant 8 of the present invention is selected from F or Cl. Preferably, the etching treatment in the step (d) is selected from a wet etching method or a dry etching method. More preferably, the etching treatment in step (d) is a dry etching method. In this embodiment of the present invention, the dry etching method is an atomic layer etching (ALE) technique. The etchant 8 suitable for the ALE technique of this step (d) of the present invention is a gas molecule selected from the group consisting of NF 3 , and POCl 3 . In this embodiment of the present invention, the etchant 8 is illustrated by taking NF 3 gas molecules as an example, but it is not limited thereto.
如圖6所示，詳細來說，該步驟(d)之第二半導體層32是放置於一ALE反應腔(圖未示)內來實施，當該反應劑8(NF3氣體分子)被引入該ALE反應腔時，NF3氣體分子中的氟原子經游離成陰離子(3F-)，且陰離子(3F-)會與第二半導體層32表面的吸附原子(adatom；即，Ga空缺321)化合成一奈米級的副產物(GaF3)80，隨後由引入該ALE反應腔內的氬氣(Ar，圖未示)使該奈米級的副產物(GaF3)80自該第二半導體層32表面脫附並且被帶離該ALE反應腔，而經游離後的N也能修補位在該第二半導體層32表面的N空缺322，以完成一次循環的ALE。由此可知，本發明該實施例之步驟(d)所實施的蝕刻處理可達到奈米級的拋光作用，不僅能使該第二半導體層32的表面平坦化，更能移除該第二半導體層32的表面缺陷以改善淺雜質(shallow impurity)的問題。因此，經實施完該步驟(d)後，該第二半導體層32具有一10nm以下的平均表面粗糙度(Ra)。在本發明該實施例中，該第二半導體層32的平均表面粗糙度(Ra)是如圖7與圖8所示，約0.31nm。 如圖6所示，詳細來說，該步驟(d)之第二半導體層32是放置於一ALE反應腔(圖未示)內來實施，當該反應劑8(NF 3氣體分子)被引入該ALE反應腔時，NF 3氣體分子中的氟原子經游離成陰離子(3F - )，且陰離子(3F - )會與第二半導體層32表面的吸附原子(adatom；即，Ga空缺321)化合成一奈米級的副產物(GaF 3 )80，隨後由引入該ALE反應腔內的氬氣(Ar，圖未示)使該奈米級的副產物(GaF 3 )80自該第二半導體層32表面脫附並且被帶離該ALE反應腔，而經游離後的N也能修補位在該第二半導體層32表面的N空缺322，以完成一次循環的ALE。 It can be seen that the etching process implemented in step (d) of this embodiment of the present invention can achieve nanometer-level polishing, which can not only planarize the surface of the second semiconductor layer 32, but also remove surface defects of the second semiconductor layer 32 to improve the shallow impurity problem. Therefore, after the step (d), the second semiconductor layer 32 has an average surface roughness (Ra) below 10 nm. In this embodiment of the present invention, the average surface roughness (Ra) of the second semiconductor layer 32 is about 0.31 nm as shown in FIG. 7 and FIG. 8 .
更具體地來說，該步驟(d)所述的每次ALE循環依序包括以下次步驟：一次步驟(d1)、一次步驟(d2)、一次步驟(d3)，及一次步驟(d4)。 More specifically, each ALE cycle described in the step (d) includes the following sub-steps in sequence: a step (d1), a step (d2), a step (d3), and a step (d4).
該次步驟(d1)是實施一表面處理程序。進一步來說，是 在該ALE反應腔(圖未示)內引入氧體以透過高電壓游離前述的氧氣成為氧電漿，令該第二半導體層32的表面氧化。 The sub-step (d1) is to implement a surface treatment procedure. Further, yes Oxygen is introduced into the ALE reaction chamber (not shown in the figure) to dissociate the aforementioned oxygen into oxygen plasma through high voltage, so as to oxidize the surface of the second semiconductor layer 32 .
該次步驟(d2)是實施一蝕刻劑浸泡(soaking)程序。進一步來說，是在該ALE反應腔內引入NF3氣體分子以透過高電壓游離前述的NF3氣體分子，使其F原子電解離成3F-以令3F-與第二半導體層32表面的Ga空缺321化合成該奈米級的副產物(GaF3)80。 The sub-step (d2) is to implement an etchant soaking (soaking) procedure. Furthermore, NF3 gas molecules are introduced into the ALE reaction chamber to dissociate the above-mentioned NF3 gas molecules through high voltage, so that the F atoms are electrolyzed into 3F- , so that 3F- combines with Ga vacancies 321 on the surface of the second semiconductor layer 32 to form the nanoscale by-product ( GaF3 ) 80.
該次步驟(d3)是實施一脫附程序。進一步來說，是在該ALE反應腔內引入Ar以透過高電壓游離前述的Ar成為Ar電漿，令該奈米級副產物(GaF3)80自第二半導體層32表面脫附。 This sub-step (d3) is to implement a desorption procedure. Furthermore, Ar is introduced into the ALE reaction chamber to dissociate the aforementioned Ar into Ar plasma through high voltage, so that the nanoscale by-product (GaF 3 ) 80 is desorbed from the surface of the second semiconductor layer 32 .
該次步驟(d4)是實施一清除(purge)程序。進一步來說，是在該ALE反應腔內引入Ar以移除自第二半導體層32表面脫附的奈米級副產物(GaF3)80並帶離該ALE反應腔。 The sub-step (d4) is to implement a purge procedure. Furthermore, Ar is introduced into the ALE reaction chamber to remove the nanoscale by-product (GaF 3 ) 80 desorbed from the surface of the second semiconductor layer 32 and carried away from the ALE reaction chamber.
較佳地，於實施該次步驟(d1)、次步驟(d2)，與次步驟(d3)時的一電極輸出功率、一反應時間與一循環次數，分別是介於100W至300W間、介於5秒至10秒間，與介於25次至100次間。 Preferably, when implementing the sub-step (d1), sub-step (d2), and sub-step (d3), an electrode output power, a response time and a cycle number are respectively between 100W to 300W, between 5 seconds to 10 seconds, and between 25 times to 100 times.
參閱圖9，該步驟(e)是對該緩衝層、第一半導體層31與第二半導體層32定義出一通道3。具體來說，該步驟(e)是經由微影、蝕刻等程序來定義出該通道3，其定義通道3的手段並非本發明之技術重點，於此不再多加贅述。由前述對該步驟(d)所記載之ALE的詳細說明可知，ALE能使該第二半導體層32達到奈米等級的拋光 作用。因此，較佳地，該通道3的第二半導體層32具有一500nm以下的厚度，且該通道3的第二半導體層32具有10nm以下的平均表面粗糙度。在本發明該實施例中，該第二半導體層32的厚度約100nm，且如上面所述，平均表面粗糙度(Ra)約0.31nm。 Referring to FIG. 9 , the step (e) is to define a channel 3 for the buffer layer, the first semiconductor layer 31 and the second semiconductor layer 32 . Specifically, the step (e) is to define the channel 3 through procedures such as lithography and etching, and the method for defining the channel 3 is not the technical focus of the present invention, so it will not be repeated here. As can be seen from the detailed description of ALE described in step (d) above, ALE can make the second semiconductor layer 32 achieve nanometer level polishing effect. Therefore, preferably, the second semiconductor layer 32 of the channel 3 has a thickness of less than 500 nm, and the second semiconductor layer 32 of the channel 3 has an average surface roughness of less than 10 nm. In this embodiment of the present invention, the thickness of the second semiconductor layer 32 is about 100 nm, and as mentioned above, the average surface roughness (Ra) is about 0.31 nm.
參閱圖10，該步驟(f)是於該通道3上形成一閘極介電層4。 Referring to FIG. 10 , the step (f) is to form a gate dielectric layer 4 on the channel 3 .
參閱圖11，該步驟(g)是於該閘極介電層4上形成一閘極5。 Referring to FIG. 11 , the step (g) is to form a gate 5 on the gate dielectric layer 4 .
參閱圖12，該步驟(h)是於該通道3的一側及相反於該側的另一側分別形成一源極6及一汲極7。 Referring to FIG. 12 , the step (h) is to form a source 6 and a drain 7 on one side of the channel 3 and on the other side opposite to this side, respectively.
經本發明該實施例之製作方法的詳細說明可知，本發明該實施例之製作方法所製得的電晶體是如圖12所示，其包括該基板2、形成於該基板2表面的通道3、該閘極介電層4、該閘極5、該源極6，及該汲極7。 From the detailed description of the manufacturing method of this embodiment of the present invention, it can be known that the transistor manufactured by the manufacturing method of this embodiment of the present invention is as shown in FIG.
該通道3具有該緩衝層(圖未示)、形成於該緩衝層上的第一半導體層31及形成於該第一半導體層31上的第二半導體層32，其中，該緩衝層與第一半導體層31是由以GaN為主的半導體材料所構成，該第一半導體層31的表面具有該等微孔穴312，該第二半導體層32填補該等微孔穴312且是依序經ALD與顯示於圖6之ALE所製成的GaN，或Ga2O3，或GaOxNy。 The channel 3 has the buffer layer (not shown), a first semiconductor layer 31 formed on the buffer layer, and a second semiconductor layer 32 formed on the first semiconductor layer 31, wherein the buffer layer and the first semiconductor layer 31 are made of GaN-based semiconductor material, the surface of the first semiconductor layer 31 has the micro-cavities 312, and the second semiconductor layer 32 fills the micro-cavities 312 and is GaN or GaN made by ALD and ALE shown in FIG . 2 O 3 , or GaO x N y .
該閘極介電層4形成於該通道3的第二半導體層32上；該閘極5形成於該閘極介電層4上。該源極6形成於該通道3的一側，並連接該通道3。該汲極7形成於相反於該通道3之該側的另一側，並連接該通道3。 The gate dielectric layer 4 is formed on the second semiconductor layer 32 of the channel 3 ; the gate 5 is formed on the gate dielectric layer 4 . The source 6 is formed on one side of the channel 3 and connected to the channel 3 . The drain 7 is formed on the other side opposite to the side of the channel 3 and connected to the channel 3 .
綜上所述，本發明之電晶體的製作方法及其製品，其在實施完MOCVD後透過CMP的程序，不僅能改善MOCVD所致的厚度差問題，而後續所實施的ALD與ALE等程序，更能填補該第一半導體層31表面因MOCVD所致的微孔穴312以解決漏電流問題，也能修補該第二半導體層32表面的Ga空缺321使其達奈米等級的拋光作用因而解決淺雜質的問題，故確實能達成本發明的目的。 In summary, the fabrication method of the transistor and its products of the present invention, through the CMP process after MOCVD, can not only improve the thickness difference problem caused by MOCVD, but also the subsequent ALD and ALE procedures can fill the micro-cavity 312 on the surface of the first semiconductor layer 31 caused by MOCVD to solve the leakage current problem, and can also repair the Ga vacancies 321 on the surface of the second semiconductor layer 32 to achieve nanometer-level polishing. Therefore, the problem of shallow impurities can be solved. purpose.
惟以上所述者，僅為本發明的實施例而已，當不能以此限定本發明實施的範圍，凡是依本發明申請專利範圍及專利說明書內容所作的簡單的等效變化與修飾，皆仍屬本發明專利涵蓋的範圍內。 But the above are only embodiments of the present invention, and should not limit the scope of the present invention. All simple equivalent changes and modifications made according to the patent scope of the present invention and the content of the patent specification are still within the scope of the patent of the present invention.
31:第一半導體層 31: The first semiconductor layer
312:微孔穴 312: micro hole
32:第二半導體層 32: Second semiconductor layer
321:Ga空缺 321:Ga vacancies
322:N空缺 322: N vacancy
8:蝕刻劑 8: etchant
80:副產物 80:By-products
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW111113412A TWI808715B (en) | 2022-04-08 | 2022-04-08 | How to make transistors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW111113412A TWI808715B (en) | 2022-04-08 | 2022-04-08 | How to make transistors |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TWI808715B true TWI808715B (en) | 2023-07-11 |
| TW202340553A TW202340553A (en) | 2023-10-16 |
Family
ID=88149307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW111113412A TWI808715B (en) | 2022-04-08 | 2022-04-08 | How to make transistors |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI808715B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201535618A (en) * | 2013-12-23 | 2015-09-16 | Intel Corp | Method of fabricating semiconductor structures on dissimilar substrates |
| US20160204222A1 (en) * | 2013-05-13 | 2016-07-14 | The Government Of The United States Of America, As Represented By The Secretary Of The Navy | Growth of High-Performance III-Nitride Transistor Passivation Layer for GaN Electronics |
| US20180323296A1 (en) * | 2015-11-12 | 2018-11-08 | Stmicroelectronics S.R.L. | Method for manufacturing a hemt transistor and hemt transistor with improved electron mobility |
| CN110797393A (en) * | 2018-08-01 | 2020-02-14 | 半导体元件工业有限责任公司 | Electronic device |
| CN111710651A (en) * | 2020-08-20 | 2020-09-25 | 浙江集迈科微电子有限公司 | Integrated GaN device and preparation method thereof |
-
2022
- 2022-04-08 TW TW111113412A patent/TWI808715B/en active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160204222A1 (en) * | 2013-05-13 | 2016-07-14 | The Government Of The United States Of America, As Represented By The Secretary Of The Navy | Growth of High-Performance III-Nitride Transistor Passivation Layer for GaN Electronics |
| TW201535618A (en) * | 2013-12-23 | 2015-09-16 | Intel Corp | Method of fabricating semiconductor structures on dissimilar substrates |
| US20180323296A1 (en) * | 2015-11-12 | 2018-11-08 | Stmicroelectronics S.R.L. | Method for manufacturing a hemt transistor and hemt transistor with improved electron mobility |
| CN110797393A (en) * | 2018-08-01 | 2020-02-14 | 半导体元件工业有限责任公司 | Electronic device |
| CN111710651A (en) * | 2020-08-20 | 2020-09-25 | 浙江集迈科微电子有限公司 | Integrated GaN device and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TW202340553A (en) | 2023-10-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9984872B2 (en) | Fabrication and structures of crystalline material | |
| TWI423439B (en) | Semiconductor device and method of manufacturing a semiconductor structure | |
| JP5018066B2 (en) | Method for manufacturing strained Si substrate | |
| JP5068635B2 (en) | Method for fabricating a semiconductor heterostructure | |
| JP4190906B2 (en) | Silicon semiconductor substrate and manufacturing method thereof | |
| US20060267024A1 (en) | Semiconductor layer structure and process for producing a semiconductor layer structure | |
| JP5088729B2 (en) | Method of manufacturing a semiconductor on insulator type wafer | |
| WO2020228164A1 (en) | Epitaxial growth method for reducing interfacial thermal resistance of gallium nitride high electron mobility field-effect transistor | |
| US20110108850A1 (en) | Method of manufacturing an integrated semiconductor substrate structure | |
| WO2005112079A1 (en) | Gallium oxide single crystal composite, process for producing the same, and process for producing nitride semiconductor film utilizing gallium oxide single crystal composite | |
| CN103165444B (en) | High-quality GaN high pressure HFET on silicon | |
| JP2007329470A6 (en) | Method for manufacturing semiconductor on-insulator wafer and semiconductor on-insulator wafer | |
| WO2013002212A1 (en) | Composite substrate and process for producing same | |
| JP6479198B2 (en) | Semiconductor wafer with single crystal IIIA nitride layer | |
| US7198997B2 (en) | Method for producing semiconductor substrate, method for producing field effect transistor, semiconductor substrate, and field effect transistor | |
| JP4449357B2 (en) | Method for manufacturing epitaxial wafer for field effect transistor | |
| TWI808715B (en) | How to make transistors | |
| CN217158196U (en) | Transistor with a metal gate electrode | |
| TWM631056U (en) | Transistor | |
| CN116978787A (en) | Method for manufacturing transistor and product thereof | |
| TW201737305A (en) | Method of fabricating a device on a carrier substrate and device fabricated thereby | |
| CN106783616B (en) | Semiconductor structure and preparation method | |
| JP2009302098A (en) | Method of manufacturing nitrogen compound semiconductor substrate, and nitrogen compound semiconductor substrate | |
| CN115863400B (en) | High-heat-conductivity GaN-based HEMT device and preparation method thereof | |
| JP2005223215A (en) | Method for producing silicon carbide single crystal film on si substrate and silicon carbide semiconductor device produced by using same |