TWI808338B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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TWI808338B
TWI808338B TW109126670A TW109126670A TWI808338B TW I808338 B TWI808338 B TW I808338B TW 109126670 A TW109126670 A TW 109126670A TW 109126670 A TW109126670 A TW 109126670A TW I808338 B TWI808338 B TW I808338B
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capacitor
aforementioned
electrode
conductor
capacitor bank
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TW202125782A (en
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岡野王俊
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日商鎧俠股份有限公司
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Abstract

實施形態提供抑制半導體基板之面積之增加的半導體裝置。 實施形態的半導體裝置(1)，係具備：半導體基板(10)，第1半導體層(12)，第1導電體(13)，第1電源線(PW)，第2電源線(GW)，及電路(3)。半導體基板(10)具有：第1面，與第1面呈對向的第2面，和設置於第1面與第2面之間的第3面。第1半導體層(12)係從第3面沿著第1面設置。第1導電體(13)設置於第1半導體層(12)上。第1電源線(PW)與第1導電體(13)電連接。第2電源線(GW)與半導體基板(10)電連接。電路(3)，係設置於半導體基板(10)，且與第1電源線(PW)及第2電源線(GW)連接。Embodiments provide a semiconductor device that suppresses an increase in the area of a semiconductor substrate. The semiconductor device (1) of the embodiment includes: a semiconductor substrate (10), a first semiconductor layer (12), a first conductor (13), a first power line (PW), a second power line (GW), and a circuit (3). The semiconductor substrate (10) has: a first surface, a second surface facing the first surface, and a third surface provided between the first surface and the second surface. The first semiconductor layer (12) is provided along the first surface from the third surface. The first conductor (13) is provided on the first semiconductor layer (12). The first power line (PW) is electrically connected to the first conductor (13). The second power line (GW) is electrically connected to the semiconductor substrate (10). The circuit (3) is provided on the semiconductor substrate (10) and connected to the first power line (PW) and the second power line (GW).

Description

半導體裝置Semiconductor device

本發明之實施形態關於包含旁路電容器的半導體裝置。 [關連申請]Embodiments of the present invention relate to a semiconductor device including a bypass capacitor. [Related application]

本申請主張日本專利申請2019-169564號(申請日：2019年9月18日)及日本專利申請2020-029110號(申請日：2020年2月25日)即基礎申請的優先權。本申請藉由參照該基礎申請而包含基礎申請之全部內容。This application claims the priority of Japanese Patent Application No. 2019-169564 (filing date: September 18, 2019) and Japanese Patent Application No. 2020-029110 (filing date: February 25, 2020), which are the basic applications. This application incorporates the entire content of the basic application by referring to this basic application.

已知為了抑制電源電壓之變動而在半導體基板上設置旁路電容器。It is known to provide bypass capacitors on semiconductor substrates in order to suppress fluctuations in power supply voltage.

本發明欲解決的課題為提供可以抑制半導體基板之面積之增加的半導體裝置。The problem to be solved by the present invention is to provide a semiconductor device capable of suppressing an increase in the area of a semiconductor substrate.

實施形態的半導體裝置，係具備：半導體基板、第1半導體層、第1導電體、第1電源線、第2電源線、及電路。半導體基板具有：第1面，與第1面呈對向的第2面，及設置於第1面與第2面之間的第3面。第1半導體層係從第3面沿著第1面而設置。第1導電體設置於第1半導體層上。第1電源線係與第1導電體電連接。第2電源線係與半導體基板電連接。電路設置於半導體基板，且與第1電源線及第2電源線連接。A semiconductor device according to an embodiment includes a semiconductor substrate, a first semiconductor layer, a first conductor, a first power line, a second power line, and a circuit. The semiconductor substrate has: a first surface, a second surface facing the first surface, and a third surface provided between the first surface and the second surface. The first semiconductor layer is provided along the first surface from the third surface. The first conductor is provided on the first semiconductor layer. The first power line is electrically connected to the first conductor. The second power line is electrically connected to the semiconductor substrate. The circuit is provided on the semiconductor substrate and connected to the first power line and the second power line.

以下參照圖面說明實施形態。各實施形態為將發明之技術思想具體化的裝置或方法之例。圖面為示意性或概念性表示者，各圖面之尺寸及比例等未必一定與實際者相同。本發明之技術思想並非由構成要素的形狀、結構、布置等界定者。Embodiments are described below with reference to the drawings. Each embodiment is an example of a device or a method that actualizes the technical idea of the invention. The drawings are schematic or conceptual representations, and the dimensions and proportions of the drawings may not necessarily be the same as the actual ones. The technical idea of the present invention is not defined by the shape, structure, arrangement, etc. of the constituent elements.

又，以下之說明中，針對具有大致相同之功能及構成的構成要素標記相同符號。構成參考符號的文字之後之數字，係藉由包含相同文字的參考符號進行參照，而且使用在對具有同樣構成的要素彼此進行區別時。針對包含相同文字的參考符號所表示的要素彼此無需區別之情況下，這些要素藉由分別僅包含文字的參考符號進行參照。In addition, in the following description, the same code|symbol is attached|subjected to the component which has substantially the same function and a structure. The numerals following the characters constituting the reference symbols are referred to by the reference symbols including the same characters, and are used when distinguishing elements having the same constitution from each other. When there is no need to distinguish elements indicated by reference symbols containing the same characters, these elements are referred to by reference symbols containing only characters, respectively.

[1]第1實施形態 以下對第1實施形態的半導體裝置1進行說明。[1] First Embodiment Next, the semiconductor device 1 according to the first embodiment will be described.

[1-1]半導體裝置1的構成 [1-1-1]半導體裝置1之整體構成 圖1係表示第1實施形態的半導體裝置1的構成例。半導體裝置1例如集成於1個半導體基板。如圖1所示，半導體裝置1具備電源線PW及GW、焊墊P1及P2、電容部2、及電路部3。[1-1] Configuration of semiconductor device 1 [1-1-1] Overall configuration of semiconductor device 1 FIG. 1 shows a configuration example of a semiconductor device 1 according to the first embodiment. The semiconductor device 1 is, for example, integrated on one semiconductor substrate. As shown in FIG. 1 , the semiconductor device 1 includes power lines PW and GW, pads P1 and P2 , a capacitor unit 2 , and a circuit unit 3 .

電源線PW及GW分別使用在對半導體裝置1所包含的各電路之電源電壓之供給。焊墊P1及P2分別構成為可與半導體裝置1之外部之機器連接。焊墊P1為半導體裝置1之正側之電源焊墊，連接於電源線PW。於焊墊P1例如被施加電源電壓VDD。焊墊P2為半導體裝置1之負側之電源焊墊，與電源線GW連接。焊墊P2例如與接地節點GND連接。The power supply lines PW and GW are used to supply the power supply voltage to each circuit included in the semiconductor device 1 . The pads P1 and P2 are respectively configured to be connectable to devices outside the semiconductor device 1 . The pad P1 is a power pad on the positive side of the semiconductor device 1 and is connected to the power line PW. For example, a power supply voltage VDD is applied to the pad P1. The pad P2 is a power pad on the negative side of the semiconductor device 1 and is connected to the power line GW. The pad P2 is connected to the ground node GND, for example.

電容部2連接於電源線PW與電源線GW之間。電容部2用於抑制電源線PW之電壓之變動。電路部3分別連接於電源線PW及GW。電路部3包含依據經由電源線PW供給的電壓動作的電路。電路部3所包含的電路例如可以是NAND型快閃記憶體之周邊電路。The capacitor unit 2 is connected between the power line PW and the power line GW. The capacitor unit 2 is used to suppress fluctuations in the voltage of the power line PW. The circuit unit 3 is connected to the power supply lines PW and GW, respectively. The circuit unit 3 includes a circuit that operates according to a voltage supplied via the power line PW. The circuit included in the circuit unit 3 may be, for example, a peripheral circuit of a NAND flash memory.

圖2係表示第1實施形態的半導體裝置1具備的電容部2的構成之一例。如圖2所示，電容部2例如包含多個電容器CP。多個電容器CP各自的一方電極連接於電源線PW，另一方電極連接於電源線GW。亦即，多個電容器CP在電源線PW與GW間並聯連接。多個電容器CP各自亦稱為例如旁路電容器。FIG. 2 shows an example of the configuration of the capacitor unit 2 included in the semiconductor device 1 according to the first embodiment. As shown in FIG. 2 , the capacitance unit 2 includes, for example, a plurality of capacitors CP. One electrode of each of the plurality of capacitors CP is connected to the power line PW, and the other electrode is connected to the power line GW. That is, a plurality of capacitors CP are connected in parallel between the power lines PW and GW. Each of the plurality of capacitors CP is also called, for example, a bypass capacitor.

[1-1-2]半導體裝置1之結構 以下，對第1實施形態中的電容部2之結構之一例進行說明。[1-1-2] Structure of semiconductor device 1 Hereinafter, an example of the configuration of the capacitor unit 2 in the first embodiment will be described.

又，以下參照的圖面中，由X方向與Y方向所確定的平面係對應於形成有半導體裝置1的半導體基板10之表面，Z方向係對應於形成有半導體裝置1的半導體基板10之表面之垂直方向。平面圖中，為了方便觀察圖而適當添加陰影線。添加於平面圖的陰影線未必與添加有陰影線的構成要素之素材或特性有關連。剖面圖中，為了方便觀察圖而適當省略絕緣層(層間絕緣膜)、布線、接觸部等之構成要素。Also, in the drawings referred to below, the plane defined by the X direction and the Y direction corresponds to the surface of the semiconductor substrate 10 on which the semiconductor device 1 is formed, and the Z direction corresponds to the vertical direction of the surface of the semiconductor substrate 10 on which the semiconductor device 1 is formed. In the plan view, hatching lines are added appropriately for the convenience of observing the figure. Hatching added to a plan view is not necessarily related to the material or characteristics of the elements to which the hatching is added. In the cross-sectional view, constituent elements such as an insulating layer (interlayer insulating film), wiring, and a contact portion are appropriately omitted for the convenience of viewing the drawing.

以下之說明中，將半導體基板10之中包含電容部2所包含的電容器CP的區域稱為電容器區域CA。此外，將半導體基板10之中包含電路部3所包含的電晶體的區域稱為電晶體區域TA。In the following description, a region of the semiconductor substrate 10 including the capacitor CP included in the capacitor unit 2 is referred to as a capacitor region CA. In addition, a region of the semiconductor substrate 10 including a transistor included in the circuit portion 3 is referred to as a transistor region TA.

圖3係表示第1實施形態的半導體裝置1之電容器區域CA中的平面布局之一例。如圖3所示，電容部2包含多個導電體13、導電體17及18、擴散區域19、以及多個接觸部CT。FIG. 3 shows an example of the planar layout in the capacitor region CA of the semiconductor device 1 according to the first embodiment. As shown in FIG. 3 , the capacitor unit 2 includes a plurality of conductors 13 , conductors 17 and 18 , a diffusion region 19 , and a plurality of contact portions CT.

每個導電體13對應於1個電容器CP之一方電極。多個導電體13布置為例如4行3列之行列狀。每個導電體13與導電體17重疊布置。導電體17作為電源線PW之功能。每個導電體13經由接觸部CT被電連接於導電體17。Each conductor 13 corresponds to one side electrode of one capacitor CP. The plurality of conductors 13 are arranged in a matrix of, for example, 4 rows and 3 columns. Each electrical conductor 13 is arranged overlapping with the electrical conductor 17 . The conductor 17 functions as a power line PW. Each electric conductor 13 is electrically connected to the electric conductor 17 via the contact portion CT.

擴散區域19設置於半導體基板10之表面。擴散區域19例如為P型之擴散區域，與半導體基板10電連接。導電體18重疊布置於擴散區域19之上。導電體18作為電源線GW之功能。擴散區域19經由接觸部CT電連接於導電體18。The diffusion region 19 is disposed on the surface of the semiconductor substrate 10 . The diffusion region 19 is, for example, a P-type diffusion region, and is electrically connected to the semiconductor substrate 10 . The conductor 18 is overlapped on the diffusion region 19 . The conductor 18 functions as the power line GW. Diffusion region 19 is electrically connected to conductor 18 via contact portion CT.

又，電容器CP之個數及布置不限定於圖3所示的例。此外，擴散區域19之面積或與導電體13之位置關係不限定於圖3所示的例。In addition, the number and arrangement of capacitors CP are not limited to the example shown in FIG. 3 . In addition, the area of the diffusion region 19 or the positional relationship with the conductor 13 is not limited to the example shown in FIG. 3 .

圖4係沿著圖3的IV-IV線的剖面圖，表示第1實施形態的半導體裝置1之電容器區域CA中的剖面結構之一例。如圖4所示，半導體裝置1進一步包含絕緣體層11與半導體層12。半導體基板10包含多個凹部CC。FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 3, showing an example of the cross-sectional structure in the capacitor region CA of the semiconductor device 1 according to the first embodiment. As shown in FIG. 4 , the semiconductor device 1 further includes an insulator layer 11 and a semiconductor layer 12 . The semiconductor substrate 10 includes a plurality of recesses CC.

絕緣體層11分別設置於半導體基板10之表面、凹部CC的側面及底部。設置於半導體基板10之表面的絕緣體層11，和設置於凹部CC的絕緣體層11係連續設置。半導體層12係在各電容器CP對應的區域中設置於絕緣體層11上。半導體層12具有沿著凹部CC設置的部分，例如在相鄰的凹部CC間被分開。導電體13設置於半導體層12上。凹部CC被導電體13填埋。在各電容器CP所對應的區域中，半導體層12與導電體13的側面被對齊。The insulator layer 11 is respectively provided on the surface of the semiconductor substrate 10 , the side surface and the bottom of the concave portion CC. The insulator layer 11 provided on the surface of the semiconductor substrate 10 and the insulator layer 11 provided in the concave portion CC are continuously provided. The semiconductor layer 12 is provided on the insulator layer 11 in a region corresponding to each capacitor CP. The semiconductor layer 12 has a portion provided along the recesses CC, and is divided, for example, between adjacent recesses CC. The conductor 13 is disposed on the semiconductor layer 12 . Recess CC is filled with conductor 13 . In the region corresponding to each capacitor CP, the side surfaces of the semiconductor layer 12 and the conductor 13 are aligned.

藉由這樣的構成，在各凹部CC中，半導體層12和導電體13作為電容器CP之一方電極之功能，絕緣體層11作為電容器CP之電極間之絕緣體之功能，半導體基板10作為電容器CP之另一方電極之功能。電容器CP之一方電極經由接觸部CT連接於作為電源線PW之功能的導電體17。作為電容器CP之另一方電極之功能的半導體基板10，係經由擴散區域19與接觸部CT連接於作為電源線GW之功能的導電體18。With such a configuration, in each recess CC, the semiconductor layer 12 and the conductor 13 function as one electrode of the capacitor CP, the insulator layer 11 functions as an insulator between electrodes of the capacitor CP, and the semiconductor substrate 10 functions as the other electrode of the capacitor CP. One electrode of the capacitor CP is connected to a conductor 17 that functions as a power supply line PW via a contact portion CT. The semiconductor substrate 10 that functions as the other electrode of the capacitor CP is connected to the conductor 18 that functions as the power line GW via the diffusion region 19 and the contact portion CT.

圖5係表示第1實施形態的半導體裝置1之電晶體區域TA中的剖面結構之一例。又，圖5所示的區域包含電容器區域CA之一部分。如圖5所示，電晶體區域TA例如包含電晶體TR。電晶體區域TA中，半導體裝置1進一步具備絕緣體14、阱區域15、擴散區域16和導電體30。FIG. 5 shows an example of a cross-sectional structure in the transistor region TA of the semiconductor device 1 according to the first embodiment. Also, the area shown in FIG. 5 includes a part of the capacitor area CA. As shown in FIG. 5 , the transistor area TA includes, for example, a transistor TR. In the transistor region TA, the semiconductor device 1 further includes an insulator 14 , a well region 15 , a diffusion region 16 , and a conductor 30 .

絕緣體14形成於半導體基板10之內部，且其上端接觸半導體基板10之上表面。絕緣體14作為相鄰的阱區域之間之絕緣區域STI(Shallow Trench Isolation)使用，在電晶體區域TA中劃分半導體基板10之一部分。阱區域15係在半導體基板10之內部形成於被絕緣體14劃分的區域，且上端與半導體基板10之上面接觸。2個擴散區域16形成於阱區域15之內部，且上端與半導體基板10之上面接觸。The insulator 14 is formed inside the semiconductor substrate 10 , and its upper end contacts the upper surface of the semiconductor substrate 10 . The insulator 14 is used as an insulating region STI (Shallow Trench Isolation) between adjacent well regions, and divides a part of the semiconductor substrate 10 in the transistor region TA. The well region 15 is formed in a region partitioned by the insulator 14 inside the semiconductor substrate 10 , and its upper end is in contact with the upper surface of the semiconductor substrate 10 . Two diffusion regions 16 are formed inside the well region 15 , and their upper ends are in contact with the upper surface of the semiconductor substrate 10 .

阱區域15之上方設置有多個導電體30。多個導電體30分別為與電晶體TR之汲極、源極和閘極對應的布線。2個擴散區域16分別作為電晶體TR之汲極或源極之功能。2個擴散區域16分別經由接觸部CT電連接於對應的導電體30。半導體層12設置於阱區域15之上方且在絕緣體層11上。導電體13設置於半導體層12上。半導體層12和導電體13作為電晶體TR的閘極電極之功能。半導體層12和導電體13之組係經由接觸部CT電連接於導電體30。A plurality of conductors 30 are disposed above the well region 15 . The plurality of conductors 30 are wirings corresponding to the drain, source and gate of the transistor TR, respectively. The two diffusion regions 16 function as the drain or the source of the transistor TR respectively. The two diffusion regions 16 are electrically connected to the corresponding conductors 30 via the contacts CT. The semiconductor layer 12 is disposed over the well region 15 and on the insulator layer 11 . The conductor 13 is disposed on the semiconductor layer 12 . The semiconductor layer 12 and the conductor 13 function as a gate electrode of the transistor TR. The set of the semiconductor layer 12 and the conductor 13 is electrically connected to the conductor 30 through the contact portion CT.

[1-2]製造方法 以下，適當參照圖6說明形成第1實施形態中的電容器CP及電晶體TR之一連串製造工程之一例。圖6係表示第1實施形態的半導體裝置1之製造工程之一例的流程圖。圖7~圖15分別表示第1實施形態的半導體裝置1之製造工程中包含與電容器CP及電晶體TR對應的結構體的剖面結構之一例。[1-2] Manufacturing method Hereinafter, an example of a series of manufacturing steps for forming the capacitor CP and the transistor TR in the first embodiment will be described with appropriate reference to FIG. 6 . FIG. 6 is a flow chart showing an example of the manufacturing process of the semiconductor device 1 according to the first embodiment. 7 to 15 each show an example of a cross-sectional structure including structures corresponding to the capacitor CP and the transistor TR in the manufacturing process of the semiconductor device 1 according to the first embodiment.

首先，如圖7所示，於半導體基板10上形成絕緣體層21(步驟S101)。絕緣體層21包含例如氮化矽(SiN)。First, as shown in FIG. 7 , an insulator layer 21 is formed on the semiconductor substrate 10 (step S101 ). The insulator layer 21 includes, for example, silicon nitride (SiN).

接著，如圖8所示，蝕刻部EP被加工(步驟S102)。具體而言，首先藉由微影成像等形成在與蝕刻部EP對應的區域具有開口的遮罩。接著，藉由使用所形成的遮罩的各向異性蝕刻形成蝕刻部EP。本工程中形成的蝕刻部EP，係貫穿絕緣體層21且停止於半導體基板10內。形成在電晶體區域TA的蝕刻部EP係具有向Y軸方向延伸的溝狀的形狀。和設置於電晶體區域的蝕刻部EP比較，形成在電容器區域CA的蝕刻部EP，其在Y軸方向之長度較短例如為孔狀。本工程中的各向異性蝕刻例如為RIE(Reactive Ion Etching)。Next, as shown in FIG. 8, the etching part EP is processed (step S102). Specifically, firstly, a mask having an opening in a region corresponding to the etching portion EP is formed by photolithography or the like. Next, the etched portion EP is formed by anisotropic etching using the formed mask. The etching portion EP formed in this process penetrates the insulator layer 21 and stops in the semiconductor substrate 10 . The etched portion EP formed in the transistor region TA has a groove-like shape extending in the Y-axis direction. Compared with the etched part EP provided in the transistor region, the etched part EP formed in the capacitor region CA has a shorter length in the Y-axis direction, for example, a hole shape. Anisotropic etching in this project is, for example, RIE (Reactive Ion Etching).

接著，如圖9所示，形成絕緣體14(步驟S103)。具體而言，首先，以填埋蝕刻部EP的方式形成絕緣體14。接著，藉由例如CMP(Chemical Mechanical Polishing)除去形成在蝕刻部EP外的絕緣體14。絕緣體14包含例如氧化矽(SiO2 )。Next, as shown in FIG. 9 , the insulator 14 is formed (step S103 ). Specifically, first, the insulator 14 is formed to fill the etched portion EP. Next, the insulator 14 formed outside the etched portion EP is removed by, for example, CMP (Chemical Mechanical Polishing). The insulator 14 includes, for example, silicon oxide (SiO 2 ).

接著，如圖10所示，形成阱區域15(步驟S104)。具體而言，於電晶體區域TA中，在被絕緣體14劃分的區域摻雜例如磷，形成阱區域15。Next, as shown in FIG. 10 , well region 15 is formed (step S104 ). Specifically, in the transistor region TA, the region partitioned by the insulator 14 is doped with, for example, phosphorus to form the well region 15 .

接著，以覆蓋電晶體區域TA之絕緣體14的方式形成絕緣體層22(步驟S105)。具體而言，首先在絕緣體層21及絕緣體14之上形成絕緣體層22。絕緣體層22包含例如氮化矽。接著，藉由微影成像等形成在與電容器區域CA對應的區域設置有開口的遮罩。接著，藉由使用所形成的遮罩的各向異性蝕刻除去形成在電容器區域CA的絕緣體層22。本工程中的各向異性蝕刻為例如RIE。Next, the insulator layer 22 is formed to cover the insulator 14 in the transistor region TA (step S105 ). Specifically, first, the insulator layer 22 is formed on the insulator layer 21 and the insulator 14 . The insulator layer 22 includes, for example, silicon nitride. Next, a mask having an opening in a region corresponding to the capacitor region CA is formed by lithography or the like. Next, the insulator layer 22 formed in the capacitor region CA is removed by anisotropic etching using the formed mask. Anisotropic etching in this project is, for example, RIE.

接著，如圖11所示，除去電容器區域CA之絕緣體14(步驟S106)。具體而言，例如藉由濕蝕刻除去電容器區域CA內未被絕緣體層22覆蓋的絕緣體14，使電容器區域CA內之蝕刻部EP露出。Next, as shown in FIG. 11, the insulator 14 of the capacitor region CA is removed (step S106). Specifically, for example, the insulator 14 not covered by the insulator layer 22 in the capacitor region CA is removed by wet etching to expose the etched portion EP in the capacitor region CA.

接著，如圖12所示，除去絕緣體層21及22(步驟S107)。具體而言，例如藉由濕蝕刻除去絕緣體層21及22。接著，例如藉由CMP除去從半導體基板10突出的絕緣體14。Next, as shown in FIG. 12 , the insulating layers 21 and 22 are removed (step S107 ). Specifically, for example, the insulator layers 21 and 22 are removed by wet etching. Next, the insulator 14 protruding from the semiconductor substrate 10 is removed, for example, by CMP.

接著，如圖13所示，形成絕緣體層11、半導體層12和導電體13(步驟S108)。具體而言，首先，在半導體基板10之表面、蝕刻部EP的側面及底部、絕緣體14之表面、阱區域15之表面形成絕緣體層11。接著，在絕緣體層11之表面形成半導體層12。此外，在半導體層12之表面以填埋蝕刻部EP的方式形成導電體13。絕緣體層11包含例如氧化矽。半導體層12包含例如矽(Si)。導電體13包含例如鎢(W)。Next, as shown in FIG. 13, the insulator layer 11, the semiconductor layer 12, and the conductor 13 are formed (step S108). Specifically, first, the insulator layer 11 is formed on the surface of the semiconductor substrate 10 , the side surfaces and the bottom of the etched portion EP, the surface of the insulator 14 , and the surface of the well region 15 . Next, the semiconductor layer 12 is formed on the surface of the insulator layer 11 . In addition, the conductor 13 is formed on the surface of the semiconductor layer 12 so as to fill the etched portion EP. Insulator layer 11 includes, for example, silicon oxide. The semiconductor layer 12 includes, for example, silicon (Si). Conductor 13 contains, for example, tungsten (W).

接著，進行遮罩23之形成及加工(步驟S109)。具體而言，藉由微影成像等在導電體13上形成遮罩23。遮罩23係覆蓋例如與電容器CP之一方電極對應的區域及與電晶體TR的閘極電極對應的區域，對其他區域設置有開口。Next, the mask 23 is formed and processed (step S109). Specifically, the mask 23 is formed on the conductor 13 by photolithography or the like. The mask 23 covers, for example, a region corresponding to one electrode of the capacitor CP and a region corresponding to the gate electrode of the transistor TR, and has openings in other regions.

接著，如圖14所示，半導體層12和導電體13被加工(步驟S110)。具體而言，藉由使用遮罩23的各向異性蝕刻除去半導體層12和導電體13之一部分，露出絕緣體層11之表面之一部分。之後例如藉由濕蝕刻除去遮罩23(步驟S111)。Next, as shown in FIG. 14, the semiconductor layer 12 and the conductor 13 are processed (step S110). Specifically, part of the semiconductor layer 12 and the conductor 13 are removed by anisotropic etching using the mask 23 to expose a part of the surface of the insulator layer 11 . The mask 23 is then removed, for example, by wet etching (step S111 ).

接著，如圖15所示，形成擴散區域16(步驟S112)。具體而言，在阱區域15內摻雜例如硼形成擴散區域16。之後，在半導體基板10之上方設包含導電體17及導電體30的各種布線。接著，藉由接觸部CT連接導電體17與電容器CP。導電體30與電晶體TR係藉由接觸部CT連接。Next, as shown in FIG. 15 , the diffusion region 16 is formed (step S112 ). Specifically, the diffusion region 16 is formed by doping, for example, boron in the well region 15 . Thereafter, various wirings including the conductor 17 and the conductor 30 are provided on the semiconductor substrate 10 . Next, the conductor 17 and the capacitor CP are connected through the contact portion CT. The conductor 30 is connected to the transistor TR through the contact portion CT.

藉由以上說明的製造工程分別形成電容器CP、電晶體TR。又，以上說明的製造工程僅為一例，在各製造工程之間可以***其他之處理。The capacitor CP and the transistor TR are respectively formed through the manufacturing process described above. In addition, the manufacturing process described above is only an example, and other processes may be inserted between each manufacturing process.

[1-3]第1實施形態之效果 依據以上說明的第1實施形態的半導體裝置1，可以抑制半導體裝置1之製造成本。以下，針對第1實施形態的半導體裝置1之詳細的效果進行說明。[1-3] Effects of the first embodiment According to the semiconductor device 1 of the first embodiment described above, the manufacturing cost of the semiconductor device 1 can be suppressed. Hereinafter, detailed effects of the semiconductor device 1 according to the first embodiment will be described.

電路之消費電流例如可能與電路之動作相應而變動。消費電流變化時為了抑制電源線之電壓之變動而使用例如旁路電容器。當電路之消費電流增加時，旁路電容器將充電的電荷供給至電路，由此，可以抑制電源線之電壓之變動。For example, the consumption current of a circuit may vary according to the operation of the circuit. For example, bypass capacitors are used to suppress fluctuations in the voltage of the power supply line when the consumption current changes. When the current consumption of the circuit increases, the bypass capacitor supplies the charged charge to the circuit, thereby suppressing fluctuations in the voltage of the power line.

但是，在半導體基板上設置旁路電容器的情況下，為了獲得期待之電容量，存在旁路電容器需要較大的面積。圖16表示第1實施形態的半導體裝置1之比較例所具備的電容部2之平面布局之一例。圖17表示與圖16之XVII-XVII線對應的剖面圖，表示比較例所具備的電容部2之剖面結構。However, when a bypass capacitor is provided on a semiconductor substrate, there is a problem that a large area is required for the bypass capacitor in order to obtain a desired capacitance. FIG. 16 shows an example of the planar layout of the capacitor unit 2 included in the comparative example of the semiconductor device 1 according to the first embodiment. FIG. 17 is a cross-sectional view corresponding to line XVII-XVII in FIG. 16 , showing a cross-sectional structure of the capacitor unit 2 included in the comparative example.

如圖16所示，比較例所具備的電容部2係包含平板電容器FC。如圖17所示，在半導體基板10之表面中設置有半導體層12和導電體13的區域係作為平板電容器FC之功能。在平板電容器FC中，半導體基板10上之佔有面積與一方電極之表面積大致相等。As shown in FIG. 16 , the capacitor unit 2 included in the comparative example includes a plate capacitor FC. As shown in FIG. 17, the region where the semiconductor layer 12 and the conductor 13 are provided on the surface of the semiconductor substrate 10 functions as a plate capacitor FC. In the flat panel capacitor FC, the occupied area on the semiconductor substrate 10 is substantially equal to the surface area of one electrode.

相對於此，第1實施形態的半導體裝置1係包含多個電容器CP，且每個電容器CP具有沿著凹部CC設置的部分。電容器CP的一方電極之表面積大於半導體基板10上之佔有面積。亦即，和比較例的平板電容器FC比較，第1實施形態的半導體裝置1的電容器CP中，相對於半導體基板10上之佔有面積，每單位面積之電容量更大。In contrast, the semiconductor device 1 according to the first embodiment includes a plurality of capacitors CP, and each capacitor CP has a portion provided along the concave portion CC. The surface area of one electrode of the capacitor CP is larger than the occupied area on the semiconductor substrate 10 . That is, compared with the plate capacitor FC of the comparative example, the capacitor CP of the semiconductor device 1 according to the first embodiment has a larger capacitance per unit area relative to the occupied area on the semiconductor substrate 10 .

藉此，依據第1實施形態的半導體裝置1，可以保持電容器之電容量之同時減少電容器之佔有面積。可以減少旁路電容器之佔有面積，因此可以減少設置半導體裝置1的半導體基板10之尺寸，可以抑制半導體裝置1之製造成本。Thereby, according to the semiconductor device 1 of the first embodiment, the area occupied by the capacitor can be reduced while maintaining the capacitance of the capacitor. Since the occupied area of the bypass capacitor can be reduced, the size of the semiconductor substrate 10 on which the semiconductor device 1 is provided can be reduced, and the manufacturing cost of the semiconductor device 1 can be suppressed.

此外，在第1實施形態的半導體裝置1中，可以整合形成電晶體TR與電容器CP的工程之一些步驟。具體而言，如圖6之步驟S102所示，與凹部CC和絕緣區域STI對應的形狀可以作為多個蝕刻部EP同時進行加工。此外，電容器CP之一方電極亦即半導體層12及導電體13，和電晶體的閘極電極亦即半導體層12及導電體13可以同時形成及加工。In addition, in the semiconductor device 1 of the first embodiment, some steps of the process of forming the transistor TR and the capacitor CP can be integrated. Specifically, as shown in step S102 of FIG. 6 , shapes corresponding to the concave portion CC and the insulating region STI can be simultaneously processed as a plurality of etching portions EP. In addition, the semiconductor layer 12 and the conductor 13 which is one electrode of the capacitor CP, and the gate electrode of the transistor which is the semiconductor layer 12 and the conductor 13 can be formed and processed simultaneously.

藉此，第1實施形態的半導體裝置1中，可以抑制伴隨著電容器CP之形成的工程數之增加。因此，第1實施形態的半導體裝置1可以抑制製造成本。Thereby, in the semiconductor device 1 according to the first embodiment, it is possible to suppress an increase in the number of processes accompanying the formation of the capacitor CP. Therefore, the semiconductor device 1 according to the first embodiment can suppress the manufacturing cost.

[2]第2實施形態 第2實施形態為第1實施形態的半導體裝置1所具備的電容器CP之布局之具體例。以下，針對第2實施形態的半導體裝置1說明其和第1實施形態不同的點。[2] Second Embodiment The second embodiment is a specific example of the layout of the capacitor CP included in the semiconductor device 1 of the first embodiment. Hereinafter, regarding the semiconductor device 1 of the second embodiment, points different from those of the first embodiment will be described.

[2-1]構成 圖18係表示第2實施形態的半導體裝置1之電路構成之一例。如圖18所示，第2實施形態的半導體裝置1包含作為電容部2的電容器單元CU1至CU4，包含作為電路部3的電路3a及3b，進一步包含信號線SW。此外，電源線PW之電阻成分使用電阻RP1及RP2表示。此外，省略與焊墊P2及電源線GW相關的記載，以接地記號表示。[2-1] Composition FIG. 18 shows an example of the circuit configuration of the semiconductor device 1 according to the second embodiment. As shown in FIG. 18 , a semiconductor device 1 according to the second embodiment includes capacitor units CU1 to CU4 as a capacitor unit 2 , includes circuits 3 a and 3 b as a circuit unit 3 , and further includes a signal line SW. In addition, the resistance component of the power supply line PW is represented by resistance RP1 and RP2. In addition, the description related to the pad P2 and the power line GW is omitted, and it shows with a ground symbol.

信號CLK被輸入至電路3a。接著，電路3a將基於信號CLK的信號經由信號線SW輸出至電路3b。電路3a及3b係由電源線PW供給電源電壓。以下將電源線PW與電路3a或3b之連接部稱為電路3a之電源端及電路3b之電源端。將電路3a之電源端之電壓稱為電壓VDD1，將電路3a消費的電流稱為電流I1。The signal CLK is input to the circuit 3a. Next, the circuit 3a outputs a signal based on the signal CLK to the circuit 3b via the signal line SW. The circuits 3a and 3b are supplied with a power supply voltage from the power supply line PW. Hereinafter, the connection part of the power line PW and the circuit 3a or 3b is called the power supply terminal of the circuit 3a and the power supply terminal of the circuit 3b. The voltage at the power supply terminal of the circuit 3a is called voltage VDD1, and the current consumed by the circuit 3a is called current I1.

電容器單元CU1至CU4分別包含例如多個並聯連接的電容器CP。電容器單元CU1及CU2各自的一方電極設置為與電路3a之電源端之間之距離變短。電容器單元CU3及CU4各自的一方電極設置為與電路3b之電源端之距離變短。此外，焊墊P1至電容器單元CU1及CU2以及電路3a為止的電源線PW之電阻成分以電阻RP1表示。電容器單元CU1及CU2以及電路3a至電容器單元CU3及CU4以及電路3b為止的電源線PW之電阻成分以電阻RP2表示。The capacitor units CU1 to CU4 respectively include, for example, a plurality of capacitors CP connected in parallel. One electrode of each of the capacitor units CU1 and CU2 is provided so that the distance from the power supply terminal of the circuit 3a becomes short. One electrode of each of the capacitor units CU3 and CU4 is provided so that the distance from the power supply terminal of the circuit 3b becomes short. In addition, the resistance component of the power supply line PW from the pad P1 to the capacitor units CU1 and CU2 and the circuit 3a is represented by the resistance RP1. The resistance component of the power line PW from the capacitor units CU1 and CU2 and the circuit 3a to the capacitor units CU3 and CU4 and the circuit 3b is represented by a resistance RP2.

圖19係表示第2實施形態的半導體裝置1之平面布局之一例。如圖19所示，第2實施形態的半導體裝置1係進一步包含接觸部CT1至CT8。如圖19所示，電源線PW係從焊墊P1向X方向延伸設置。FIG. 19 shows an example of the planar layout of the semiconductor device 1 according to the second embodiment. As shown in FIG. 19, the semiconductor device 1 according to the second embodiment further includes contacts CT1 to CT8. As shown in FIG. 19 , the power line PW extends from the pad P1 in the X direction.

電路3a及3b沿著電源線PW布置。電路3a比起電路3b布置於更接近焊墊P1的位置。電路3a及3b各自的電源端係與電源線PW連接。電路3a與電路3b係經由信號線SW連接。電容器單元CU1及CU2布置於電路3a之電源端之附近。電容器單元CU3及CU4布置於電路3b之電源端之附近。The circuits 3a and 3b are arranged along the power line PW. The circuit 3a is arranged closer to the pad P1 than the circuit 3b. The respective power supply terminals of the circuits 3a and 3b are connected to the power supply line PW. The circuit 3a and the circuit 3b are connected via a signal line SW. Capacitor units CU1 and CU2 are arranged in the vicinity of the power supply terminals of the circuit 3a. Capacitor units CU3 and CU4 are arranged in the vicinity of the power supply terminals of the circuit 3b.

接觸部CT1係將電源線PW與電容器單元CU1之一方電極予以連接。接觸部CT2係將電源線PW與電容器單元CU2之一方電極予以連接。接觸部CT3係將電源線PW與電容器單元CU3之一方電極予以連接。接觸部CT4係將電源線PW與電容器單元CU4之一方電極予以連接。接觸部CT5係將電源線PW與電路3a之電源端予以連接。接觸部CT6係將電源線PW與電路3b之電源端予以連接。接觸部CT7係將信號線SW與電路3a之信號輸出部予以連接。接觸部CT8係將信號線SW與電路3b之信號輸入部予以連接。The contact portion CT1 connects the power line PW to one electrode of the capacitor unit CU1. The contact portion CT2 connects the power line PW to one electrode of the capacitor unit CU2. The contact portion CT3 connects the power line PW to one electrode of the capacitor unit CU3. The contact portion CT4 connects the power line PW to one electrode of the capacitor unit CU4. The contact portion CT5 connects the power line PW to the power terminal of the circuit 3a. The contact portion CT6 connects the power line PW to the power terminal of the circuit 3b. The contact portion CT7 connects the signal line SW to the signal output portion of the circuit 3a. The contact portion CT8 connects the signal line SW to the signal input portion of the circuit 3b.

圖19所示的例中，電源線PW之中，自焊墊P1至接觸部CT1與CT2與CT5被連接的部分為止的電阻成分係對應於電阻RP1。此外，電源線PW之中自接觸部CT1與CT2與CT5被連接的部分至接觸部CT3與CT4與CT6被連接的部分為止的電阻成分係對應於電阻RP2。第2實施形態的半導體裝置1之其他構成係和第1實施形態同樣。In the example shown in FIG. 19 , the resistance component of the power line PW from the pad P1 to the portion where the contacts CT1 , CT2 , and CT5 are connected corresponds to the resistance RP1 . In addition, the resistance component from the part where contact part CT1, CT2 and CT5 are connected to the part where contact part CT3 and CT4 and CT6 are connected among power supply line PW corresponds to resistance RP2. Other configurations of the semiconductor device 1 of the second embodiment are the same as those of the first embodiment.

[2-2]第2實施形態之效果 依據以上說明的第2實施形態的半導體裝置1，可以提升半導體裝置1之動作可靠性。以下，針對第2實施形態的半導體裝置1之詳細的效果進行說明。[2-2] Effects of the second embodiment According to the semiconductor device 1 of the second embodiment described above, the operational reliability of the semiconductor device 1 can be improved. Hereinafter, detailed effects of the semiconductor device 1 according to the second embodiment will be described.

半導體裝置之設計中，密集地布局多個電路或多個電容器等之構成要素為較佳。當要素被密集地布局時，可以抑制半導體基板之尺寸變大，可以抑制半導體裝置之製造成本。此外，設置於旁路電容器與電路之電源端之間的布線之電阻成分較小為較佳。當設置於旁路電容器與電路之電源端之間的布線之電阻成分較小時，旁路電容器可以儘快地將電荷供給至電路，更能夠抑制電源電壓之變動。In the design of a semiconductor device, it is preferable to densely arrange components such as a plurality of circuits or capacitors. When elements are densely laid out, the size of the semiconductor substrate can be suppressed, and the manufacturing cost of the semiconductor device can be suppressed. In addition, it is preferable that the resistance component of the wiring provided between the bypass capacitor and the power supply terminal of the circuit is small. When the resistance component of the wiring provided between the bypass capacitor and the power supply terminal of the circuit is small, the bypass capacitor can supply charges to the circuit as soon as possible, and can further suppress fluctuations in the power supply voltage.

但是，某一要素之尺寸較大之情況下，例如電容器之尺寸較大之情況下，若將電路與旁路電容器密集地布置，會有連接旁路電容器與電路之電源端的布線變長之情況。圖20係表示第2實施形態之比較例的半導體裝置1之電路構成之一例。如圖20所示，比較例的半導體裝置1和第2實施形態之不同點在於，比較例中之電容部2包含平板電容器FC1至FC4，以及電源線PW之電阻成分以電阻RP3至RP5表示。However, when a certain element is large in size, for example, a capacitor is large in size, if the circuit and bypass capacitors are densely arranged, the wiring connecting the bypass capacitor and the power supply terminal of the circuit may become longer. FIG. 20 shows an example of a circuit configuration of a semiconductor device 1 as a comparative example of the second embodiment. As shown in FIG. 20, the difference between the semiconductor device 1 of the comparative example and the second embodiment is that the capacitor unit 2 in the comparative example includes plate capacitors FC1 to FC4, and the resistance components of the power line PW are represented by resistors RP3 to RP5.

平板電容器FC1至FC4彙整設置。電路3a不是靠***板電容器FC1至FC4而是靠近焊墊P1設置。電路3b比起平板電容器FC1至FC4更遠離焊墊P1設置。此外，焊墊P1至電路3a之電源端為止的電源線PW之電阻成分以電阻RP3表示。電路3a之電源端至平板電容器FC1~FC4為止的電源線PW之電阻成分以電阻RP4表示。平板電容器FC1~FC4至電路3b之電源端為止的電源線PW之電阻成分以電阻RP5表示。Plate capacitors FC1 to FC4 are integrated settings. The circuit 3a is arranged not close to the plate capacitors FC1 to FC4 but close to the pad P1. The circuit 3b is disposed farther from the pad P1 than the plate capacitors FC1 to FC4. In addition, the resistance component of the power supply line PW from the pad P1 to the power supply terminal of the circuit 3a is represented by the resistance RP3. The resistance component of the power line PW from the power supply end of the circuit 3a to the plate capacitors FC1-FC4 is represented by a resistance RP4. The resistance component of the power supply line PW from the plate capacitors FC1 to FC4 to the power supply terminal of the circuit 3b is represented by a resistance RP5.

圖21係表示第2實施形態之比較例的半導體裝置1之平面布局之一例。如圖21所示，比較例的半導體裝置1進一步包含接觸部CT1至CT8。包含於比較例的平板電容器FC1至FC4之各個，和包含於第2實施形態的半導體裝置1的電容器單元CU1至CU4之各個係具有大致相等的電容量。FIG. 21 shows an example of a planar layout of a semiconductor device 1 as a comparative example of the second embodiment. As shown in FIG. 21 , the semiconductor device 1 of the comparative example further includes contact portions CT1 to CT8 . Each of the plate capacitors FC1 to FC4 included in the comparative example and each of the capacitor units CU1 to CU4 included in the semiconductor device 1 of the second embodiment have substantially the same capacitance.

亦即，和第2實施形態所包含的電容器單元CU比較，比較例所包含的平板電容器FC在半導體基板10上的每單位面積之電容量較小。因此，平板電容器FC之半導體基板10上的佔有面積大於電容器單元CU。為了密集地布置較大的平板電容器FC，比較例之布局係和第2實施形態的半導體裝置1之布局不同。That is, the plate capacitor FC included in the comparative example has a smaller capacitance per unit area on the semiconductor substrate 10 than the capacitor unit CU included in the second embodiment. Therefore, the occupied area on the semiconductor substrate 10 of the plate capacitor FC is larger than that of the capacitor unit CU. The layout of the comparative example is different from the layout of the semiconductor device 1 of the second embodiment in order to densely arrange large plate capacitors FC.

具體而言，比較例中，電路3a、平板電容器FC1及FC2、平板電容器FC3及FC4、以及電路3b係沿著電源線PW而且從焊墊P1起依序布置。平板電容器FC1至FC4布置於電路3a與電路3b之間。電源線PW與平板電容器FC1及FC3重疊布置。信號線SW與平板電容器FC2及FC4重疊布置。比較例中，焊墊P1至接觸部CT5之連接部為止的電源線PW之電阻成分係與電阻RP3對應。接觸部CT5之連接部至接觸部CT1~CT4之連接部為止的電源線PW之電阻成分係對應於電阻RP4。接觸部CT1~CT4之連接部至接觸部CT6之連接部為止的電阻成分係對應於電阻RP5。Specifically, in the comparative example, the circuit 3a, the panel capacitors FC1 and FC2, the panel capacitors FC3 and FC4, and the circuit 3b are arranged along the power line PW in order from the pad P1. Plate capacitors FC1 to FC4 are arranged between the circuit 3a and the circuit 3b. The power line PW is arranged to overlap the panel capacitors FC1 and FC3. The signal line SW is arranged to overlap the plate capacitors FC2 and FC4. In the comparative example, the resistance component of the power supply line PW up to the connection portion from the pad P1 to the contact portion CT5 corresponds to the resistance RP3. The resistance component of the power line PW from the connection part of the contact part CT5 to the connection part of the contact part CT1-CT4 corresponds to resistance RP4. The resistance component from the connection part of the contact part CT1-CT4 to the connection part of the contact part CT6 corresponds to resistance RP5.

如上述這樣地，比較例的半導體裝置1中，連接電路3a之電源端與平板電容器FC1至FC4的電源線PW變長，且包含與電阻RP4相當的電阻成分。此外，連接電路3b與平板電容器FC1至FC4的電源線PW變長，且包含與電阻RP5相當的電阻成分。As described above, in the semiconductor device 1 of the comparative example, the power supply line PW connecting the power supply terminal of the circuit 3a and the panel capacitors FC1 to FC4 is long and includes a resistance component equivalent to the resistance RP4. In addition, the power line PW connecting the circuit 3b and the panel capacitors FC1 to FC4 is long and includes a resistance component equivalent to the resistance RP5.

相對於此，第2實施形態的半導體裝置1中，半導體基板10上的佔有面積比起平板電容器FC更小的電容器單元CU係接近電路之電源端布置。將電路3a之電源端與電容器單元CU1及CU2進行連接的部分之電源線PW變短，連接的部分之電源線PW之電阻成分變小。此外，連接電路3b之電源端與電容器單元CU3及CU4的電源線PW變短，電阻成分較小。On the other hand, in the semiconductor device 1 according to the second embodiment, the capacitor unit CU occupying an area on the semiconductor substrate 10 smaller than that of the plate capacitor FC is arranged close to the power supply terminal of the circuit. The power supply line PW of the portion connecting the power supply end of the circuit 3a and the capacitor units CU1 and CU2 is shortened, and the resistance component of the power supply line PW of the connected portion is reduced. In addition, the power supply line PW connecting the power supply terminal of the circuit 3b and the capacitor units CU3 and CU4 is shortened, and the resistance component is small.

藉此，第2實施形態的半導體裝置1中，將電路與電容器密集地布置之情況下，設置於旁路電容器與電路之電源端之間的布線之電阻成分可以減小。圖22係表示第2實施形態的半導體裝置與其變形例中的電壓及電流與時間之關係。如圖22所示的3個曲線圖從上起依序分別示出信號CLK與時間之關係、電流I1與時間之關係、和電壓VDD1與時間之關係。電壓VDD1之曲線圖中，實線表示第2實施形態，虛線表示比較例。Accordingly, in the semiconductor device 1 according to the second embodiment, when the circuits and capacitors are densely arranged, the resistance component of the wiring provided between the bypass capacitor and the power supply terminal of the circuit can be reduced. FIG. 22 shows the relationship between voltage and current and time in the semiconductor device of the second embodiment and its modification. The three graphs shown in FIG. 22 respectively show the relationship between the signal CLK and time, the relationship between the current I1 and time, and the relationship between the voltage VDD1 and time from the top. In the graph of the voltage VDD1, the solid line represents the second embodiment, and the dotted line represents the comparative example.

信號CLK，係在時刻t1、t2、t3和t4分別從“H”位準變化為“L”位準或從“L”位準變化為“H”位準。電路3a依據信號CLK而動作，與電路3a之消費電流對應的電流I1係在時刻t1、t2、t3和t4分別增加。電流I1增加時，旁路電容器供給電荷並抑制電壓VDD1之變動。比較例中，電路3a與旁路電容器之間之電阻成分較大，因此電壓VDD1大幅變動。相對於此，第2實施形態的半導體裝置1中，電路3a與旁路電容器之間之電阻成分較小，因此電壓VDD1之變動被抑制為較小。如上述這樣地，第2實施形態的半導體裝置1比起比較例更能夠抑制電源電壓之變動。因此，第2實施形態的半導體裝置1比起比較例更能夠提升動作可靠性。Signal CLK changes from "H" level to "L" level or from "L" level to "H" level at times t1, t2, t3 and t4, respectively. The circuit 3a operates according to the signal CLK, and the current I1 corresponding to the consumption current of the circuit 3a increases at times t1, t2, t3 and t4 respectively. When the current I1 increases, the bypass capacitor supplies the charge and suppresses the variation of the voltage VDD1. In the comparative example, the resistance component between the circuit 3a and the bypass capacitor is large, so the voltage VDD1 fluctuates greatly. On the other hand, in the semiconductor device 1 of the second embodiment, the resistance component between the circuit 3a and the bypass capacitor is small, so the variation of the voltage VDD1 is suppressed to be small. As described above, the semiconductor device 1 of the second embodiment can suppress fluctuations in the power supply voltage more than those of the comparative example. Therefore, the semiconductor device 1 of the second embodiment can improve the operational reliability more than that of the comparative example.

此外，電源電壓之變動也可能成為抖動之原因。電路欲高速動作時，抑制抖動之產生為較佳。相對於此，如上述這樣地，第2實施形態的半導體裝置1可以抑制電源電壓之變動，因此可以抑制抖動之產生。In addition, fluctuations in power supply voltage may also cause jitter. When the circuit intends to operate at high speed, it is better to suppress the generation of jitter. On the other hand, as described above, the semiconductor device 1 according to the second embodiment can suppress fluctuations in the power supply voltage, thereby suppressing occurrence of jitter.

此外，信號布線之寄生電阻及寄生電容量較小為較佳。信號布線之寄生電阻及寄生電容量較小之情況下，可以穩定地傳送高速的信號。In addition, it is better that the parasitic resistance and parasitic capacitance of the signal wiring are small. When the parasitic resistance and parasitic capacitance of the signal wiring are small, high-speed signals can be stably transmitted.

比較例的半導體裝置1中，電路3a與電路3b遠離設置，且以長的信號線SW連接。信號線SW之長度變長時，會有寄生電阻變大之情況。此外，信號線SW與平板電容器FC2及FC4重疊設置。信號線SW與其他之要素例如電容器重疊設置時，會有寄生電容量變大之情況。In the semiconductor device 1 of the comparative example, the circuit 3 a and the circuit 3 b are provided apart from each other and connected by a long signal line SW. When the length of the signal line SW becomes longer, the parasitic resistance may become larger. In addition, the signal line SW is provided to overlap the plate capacitors FC2 and FC4. When the signal line SW is overlapped with other elements such as capacitors, the parasitic capacitance may increase.

相對於此，第2實施形態的半導體裝置1中，電路3a與電路3b接近設置且以短的信號線SW連接。此外，信號線SW不與電路3a及電路3b以外的其他之要素重疊設置。On the other hand, in the semiconductor device 1 according to the second embodiment, the circuit 3a and the circuit 3b are provided close to each other and connected by a short signal line SW. In addition, the signal line SW is not overlapped with elements other than the circuit 3a and the circuit 3b.

藉此，第2實施形態的半導體裝置1中，信號線SW之寄生電阻及寄生電容量較小，因此可以穩定地傳送高速的信號，可以提升半導體裝置1之動作可靠性。Thereby, in the semiconductor device 1 of the second embodiment, the parasitic resistance and parasitic capacitance of the signal line SW are small, so high-speed signals can be stably transmitted, and the operation reliability of the semiconductor device 1 can be improved.

[3]第3實施形態 第3實施形態為第2實施形態的半導體裝置1所具備的電容器CP之布局及電容量設計之變形例。以下，針對第3實施形態的半導體裝置1說明和第2實施形態不同的點。[3] The third embodiment The third embodiment is a modified example of the layout and capacitance design of the capacitor CP included in the semiconductor device 1 of the second embodiment. Hereinafter, points different from those of the second embodiment will be described with respect to the semiconductor device 1 of the third embodiment.

[3-1]構成 圖23係表示第3實施形態的半導體裝置1之電路構成之一例。如圖23所示，第3實施形態的半導體裝置1中，作為電容部2係包含電容器組CS1至CS3，作為電路部3係包含電路3c。電源線PW包含節點N1至N3。此外，電源線PW之電阻成分以電阻RP6至RP8表示。[3-1] Composition FIG. 23 shows an example of the circuit configuration of the semiconductor device 1 according to the third embodiment. As shown in FIG. 23, the semiconductor device 1 according to the third embodiment includes capacitor banks CS1 to CS3 as the capacitance unit 2, and includes a circuit 3c as the circuit unit 3. The power line PW includes nodes N1 to N3. In addition, the resistance components of the power supply line PW are represented by resistors RP6 to RP8.

電源線PW係從焊墊P1至電路3c之電源端為止設置。電路3c之與電源端間之距離依節點N1、節點N2、節點N3之順序變長。此外，焊墊P1至節點N3為止的電源線PW之電阻成分以電阻RP6表示。節點N3至節點N2為止的電源線PW之電阻成分以電阻RP7表示。節點N2至節點N1為止的電源線PW之電阻成分以電阻RP8表示。The power line PW is provided from the pad P1 to the power end of the circuit 3c. The distance between the circuit 3c and the power supply end becomes longer in the order of the node N1, the node N2, and the node N3. In addition, the resistance component of the power supply line PW from the pad P1 to the node N3 is represented by the resistance RP6. The resistance component of the power supply line PW from the node N3 to the node N2 is represented by a resistance RP7. The resistance component of the power supply line PW from the node N2 to the node N1 is represented by a resistance RP8.

電容器組CS1至CS3分別包含多個電容器CP。電容器組CS1至CS3之電容量各自不同。電容器組CS2之電容量大於電容器組CS1之電容量。電容器組CS3之電容量大於電容器組CS2之電容量。例如電容器組CS2之電容量為電容器組CS1之電容量之10倍，電容器組CS3之電容量為電容器組CS2之電容量之10倍。例如電容器組CS1至CS3之電容量，係藉由各電容器組所包含的電容器CP之個數確定。電容器組CS1至CS3設置於電源線PW與接地節點之間。具體而言，電容器組CS1至CS3之一方電極分別連接於節點N1至N3。The capacitor banks CS1 to CS3 respectively include a plurality of capacitors CP. The capacitances of the capacitor banks CS1 to CS3 are different from each other. The capacitance of the capacitor bank CS2 is greater than the capacitance of the capacitor bank CS1. The capacitance of the capacitor bank CS3 is greater than the capacitance of the capacitor bank CS2. For example, the capacitance of the capacitor bank CS2 is 10 times that of the capacitor bank CS1, and the capacitance of the capacitor bank CS3 is 10 times that of the capacitor bank CS2. For example, the capacitance of the capacitor banks CS1 to CS3 is determined by the number of capacitors CP included in each capacitor bank. Capacitor banks CS1 to CS3 are provided between the power line PW and the ground node. Specifically, one side electrodes of the capacitor banks CS1 to CS3 are respectively connected to the nodes N1 to N3.

圖24係表示第3實施形態的半導體裝置1之平面布局之一例。圖24所示，第3實施形態的半導體裝置1進一步包含接觸部CT10至CT13。此外，電容器組CS1至CS3分別包含多個電容器CP。電容器組所包含的電容器CP之個數，係依電容器組CS1、電容器組CS2、電容器組CS3之順序變多。又，圖24所示的例中，電容器CP之個數被簡化表示。FIG. 24 shows an example of the planar layout of the semiconductor device 1 according to the third embodiment. As shown in FIG. 24, the semiconductor device 1 according to the third embodiment further includes contact portions CT10 to CT13. In addition, the capacitor banks CS1 to CS3 respectively include a plurality of capacitors CP. The number of capacitors CP included in the capacitor bank increases in the order of capacitor bank CS1, capacitor bank CS2, and capacitor bank CS3. Also, in the example shown in FIG. 24, the number of capacitors CP is simplified.

電源線PW從焊墊P1向X方向延伸布置。沿著電源線PW依接近焊墊P1的順序布置有電容器組CS3、電容器組CS2、電容器組CS1和電路3c。The power line PW is extended from the pad P1 to the X direction. Along the power supply line PW, a capacitor bank CS3 , a capacitor bank CS2 , a capacitor bank CS1 , and a circuit 3 c are arranged in order close to the pad P1 .

接觸部CT10將電源線PW與電路3c之電源端予以連接。接觸部CT11將電源線PW與電容器組CS1所包含的電容器CP之一方電極予以連接。多個接觸部CT12分別將電源線PW與電容器組CS2所包含的電容器CP之一方電極予以連接。接觸部CT13分別將電源線PW與電容器組CS3所包含的電容器CP之一方電極予以連接。The contact part CT10 connects the power line PW and the power terminal of the circuit 3c. The contact part CT11 connects the power supply line PW and one electrode of the capacitor CP included in the capacitor bank CS1. The plurality of contact portions CT12 each connect the power supply line PW and one electrode of the capacitor CP included in the capacitor bank CS2. The contact portions CT13 each connect the power supply line PW and one electrode of the capacitor CP included in the capacitor bank CS3.

圖24所示的例中，電源線PW之中，焊墊P1至多個接觸部CT13所連接的部分為止的電阻成分係對應於電阻RP6。電源線PW之中，多個接觸部CT13所連接的部分至多個接觸部CT12所連接的部分為止的電阻成分係對應於電阻RP7。電源線PW之中，多個接觸部CT12所連接的部分至接觸部CT11所連接的部分為止的電阻成分係對應於電阻RP8。第3實施形態的半導體裝置1之其他構成係和第2實施形態同樣。In the example shown in FIG. 24 , the resistance component of the power supply line PW from the pad P1 to the portion where the plurality of contact portions CT13 are connected corresponds to the resistance RP6 . Among the power supply lines PW, the resistance components from the part where the plurality of contact parts CT13 are connected to the part where the plurality of contact parts CT12 are connected correspond to the resistance RP7. Among the power supply line PW, the resistance component from the part where the some contact part CT12 is connected to the part where the contact part CT11 is connected corresponds to resistance RP8. Other configurations of the semiconductor device 1 of the third embodiment are the same as those of the second embodiment.

[3-2]第3實施形態之效果 依據以上說明的第3實施形態的半導體裝置1，可以提升半導體裝置1之動作可靠性。以下，針對第3實施形態的半導體裝置1之詳細的效果進行說明。[3-2] Effects of the third embodiment According to the semiconductor device 1 of the third embodiment described above, the operational reliability of the semiconductor device 1 can be improved. Hereinafter, detailed effects of the semiconductor device 1 according to the third embodiment will be described.

電源電壓可能會在從低頻到高頻的寬頻帶範圍內變動。較好是，旁路電容器能夠抑制從低頻到高頻的寬頻帶中的電源電壓的變動。為了抑制低頻帶中的電源電壓的變動，較好是旁路電容器的電容量大。另一方面，即使使用比低頻帶的情況下電容量小的旁路電容器，也可以抑制高頻帶的電源電壓的變動。此外，當不能確保電路周邊的面積時，可以考慮在遠離電路的位置設置旁路電容器，但是連接電路和旁路電容器的電源線可能較長。隨著連接電路和旁路電容器的電源線變長，布線的電阻值會變大。此外，隨著連接旁路電容器和電路的電源線的長度變長，旁路電容器抑制高頻帶中的電壓波動的能力可能受到限制。The power supply voltage may vary over a wide frequency range from low frequency to high frequency. Preferably, the bypass capacitor can suppress fluctuations in the power supply voltage in a wide frequency band from low frequency to high frequency. In order to suppress fluctuations in the power supply voltage in the low frequency band, it is preferable that the capacitance of the bypass capacitor is large. On the other hand, even if a bypass capacitor having a capacitance smaller than that in the low frequency band is used, fluctuations in the power supply voltage in the high frequency band can be suppressed. In addition, if the area around the circuit cannot be ensured, it is conceivable to install a bypass capacitor at a position away from the circuit, but the power supply line connecting the circuit and the bypass capacitor may be long. As the power line connecting the circuit and the bypass capacitor becomes longer, the resistance value of the wiring becomes larger. Furthermore, as the length of the power supply line connecting the bypass capacitor and the circuit becomes longer, the ability of the bypass capacitor to suppress voltage fluctuations in the high frequency band may be limited.

相對於此，第3實施形態的半導體裝置1包含具有不同電容量的電容器組CS1至CS3。電容器組CS1至CS3的電容量被設計為越接近電路時越小，越遠離電路時越大。In contrast, the semiconductor device 1 of the third embodiment includes capacitor banks CS1 to CS3 having different capacitances. The capacitances of the capacitor banks CS1 to CS3 are designed to be smaller as they are closer to the circuit and larger as they are farther away from the circuit.

例如電容器組CS1在電路3c的電源端附近設置為具有小的電容量。由於電容器組CS1經由短距離電源線PW連接至電路3c，因此即使在高頻帶下也具有優異的抑制電壓波動的能力。此外，由於電容器組CS1具有小電容量，佔用面積小且不會妨礙電路3c周邊的布局。電容器組CS1主要抑制高頻帶中的電源電壓的變動。For example, the capacitor bank CS1 is provided to have a small capacitance near the power supply terminal of the circuit 3c. Since the capacitor bank CS1 is connected to the circuit 3c via the short-distance power supply line PW, it has an excellent ability to suppress voltage fluctuations even in a high-frequency band. In addition, since the capacitor bank CS1 has a small capacitance, it occupies a small area and does not hinder the layout around the circuit 3c. The capacitor bank CS1 mainly suppresses fluctuations in the power supply voltage in the high frequency band.

電容器組CS2設置在電源線PW從電路3c的電源端延伸直到電阻值變為相當於電阻RP8的位置處，並且具有大於CS1的電容量。由於電容器組CS2具有大容量，其占有面積較大，但是由於與電路3c分離，因此不會阻礙其他電路的布局。此外，由於電容器組CS2具有大的電容量，可以期待直至比電容器組CS1的頻帶低的頻帶的效果。由於電容器組CS2經由中等距離的電源線PW連接至電路3c，因此抑制高頻帶中的電壓波動的能力可能受到適當限制。當電容量大小和布線長度的影響被組合時，電容器組CS2抑制了在比電容器組CS1低的頻帶中的電源電壓的變動。The capacitor bank CS2 is provided at a position where the power supply line PW extends from the power supply terminal of the circuit 3c until the resistance value becomes equivalent to the resistance RP8, and has a larger capacitance than CS1. Since the capacitor bank CS2 has a large capacity, it occupies a large area, but since it is separated from the circuit 3c, it does not hinder the layout of other circuits. In addition, since the capacitor bank CS2 has a large capacitance, an effect up to a frequency band lower than that of the capacitor bank CS1 can be expected. Since the capacitor bank CS2 is connected to the circuit 3c via the medium-distance power supply line PW, the ability to suppress voltage fluctuations in the high frequency band may be appropriately limited. When the effects of capacitance magnitude and wiring length are combined, the capacitor bank CS2 suppresses fluctuations in the power supply voltage in a lower frequency band than the capacitor bank CS1.

電容器組CS3設置在電源線PW從電路3c的電源端延伸直到電阻值等於RP7和RP8的合計的位置處，並且具有比CS2更大的電容量。由於電容器組CS3具有較大的電容量，因此佔用面積也較大，但是由於其遠離電路3c，因此不會干擾其他電路的布局。此外，由於電容器組CS3具有更大的電容量，因此可以期待直至更低於電容器組CS2的頻帶的效果。由於電容器組CS3經由長距離電源線PW連接至電路3c，因此抑制高頻帶中的電壓波動的能力可能受到大的限制。當電容和布線長度的影響被組合時，電容器組CS3抑制在更低於電容器組CS2的頻帶中的電源電壓的變動。The capacitor bank CS3 is provided at a position where the power supply line PW extends from the power supply terminal of the circuit 3c until the resistance value is equal to the sum of RP7 and RP8, and has a larger capacitance than CS2. Since the capacitor bank CS3 has a larger capacitance, it occupies a larger area, but because it is far away from the circuit 3c, it will not interfere with the layout of other circuits. In addition, since the capacitor bank CS3 has a larger capacitance, an effect up to a frequency band lower than that of the capacitor bank CS2 can be expected. Since the capacitor bank CS3 is connected to the circuit 3c via the long-distance power supply line PW, the ability to suppress voltage fluctuations in the high frequency band may be greatly limited. When the effects of capacitance and wiring length are combined, the capacitor bank CS3 suppresses fluctuations in the power supply voltage in a frequency band lower than that of the capacitor bank CS2.

如以上所述，依據第3實施形態的半導體裝置1，可以在寬頻帶內抑制電源電壓的波動，而無需在電路周邊集中設置電容器。此外，在第3實施形態的半導體裝置1中，藉由使用具有沿著凹部CC的部分的電容器CP，可以抑制電容器在電路周邊佔有的面積的變大。As described above, according to the semiconductor device 1 of the third embodiment, fluctuations in the power supply voltage can be suppressed over a wide frequency band without concentrating capacitors around the circuit. Furthermore, in the semiconductor device 1 according to the third embodiment, by using the capacitor CP having a portion along the recess CC, it is possible to suppress an increase in the area occupied by the capacitor around the circuit.

[4]其他之變形例等 第1實施形態中說明在電容器區域CA中半導體層12及導電體13在相鄰的凹部CC間被分開之情況下之例，但是電容器區域CA之結構不限定於此。例如在電容器區域CA中半導體層12與導電體13不分離亦可。圖25係表示變形例中的電容器區域CA中的剖面結構之一例。如圖25所示，在電容器區域CA中，半導體層12與導電體13連續設置，藉此而將多個電容器CP並聯連接亦可。此外，如圖25所示的例中，電容器CP之一方電極經由1個接觸部CT連接於導電體17，但是經由多個接觸部CT連接亦可。[4] Other modified examples, etc. In the first embodiment, an example is described in which the semiconductor layer 12 and the conductor 13 are separated between adjacent recesses CC in the capacitor region CA, but the structure of the capacitor region CA is not limited to this. For example, the semiconductor layer 12 and the conductor 13 may not be separated in the capacitor region CA. FIG. 25 shows an example of a cross-sectional structure in a capacitor region CA in a modified example. As shown in FIG. 25 , in the capacitor region CA, the semiconductor layer 12 and the conductor 13 are continuously provided, thereby connecting a plurality of capacitors CP in parallel. In addition, in the example shown in FIG. 25, one electrode of the capacitor CP is connected to the conductor 17 via one contact portion CT, but it may be connected via a plurality of contact portions CT.

第1實施形態中說明直至形成電容器CP及電晶體TR為止的一連串之製造工程之一例，但是製造工程不限定於此。例如絕緣體層可以是多層結構。例如絕緣體層21可以是氧化矽與氮化矽之多層結構。例如在半導體層12與導電體13之間設置阻障金屬亦可。例如在多晶矽與鎢之間設置氮化鈦(TiN)亦可。此外，在多晶矽與鎢之間設置氮化鎢亦可。In the first embodiment, an example of a series of manufacturing processes up to the formation of the capacitor CP and the transistor TR was described, but the manufacturing process is not limited to this. For example the insulator layer may be a multilayer structure. For example, the insulator layer 21 may be a multilayer structure of silicon oxide and silicon nitride. For example, a barrier metal may be provided between the semiconductor layer 12 and the conductor 13 . For example, titanium nitride (TiN) may be provided between polysilicon and tungsten. In addition, tungsten nitride may be provided between polysilicon and tungsten.

第1實施形態中示出1種類的電容器CP的形狀進行說明，但是電容器CP的形狀不限定於示例者。圖26係表示變形例中的電容器CPa至CPc之剖面結構之一例。如圖26所示，電容器CPa至CPc中，凹部CC的形狀各自不同。電容器CPa係和第1實施形態中說明的電容器CP同樣。和電容器CPa比較，電容器CPb設置於形成為比較寬且深的凹部CC。和電容器CPc比較，電容器CPc設置於形成為比較窄且淺的凹部CC。亦即，藉由變更凹部之寬度與深度來變化凹部之截面積。如上述這樣地例如藉由分開作成凹部CC，而分開作成不同截面形狀的電容器亦可。亦即，藉由分開作成不同截面積的凹部CC，而分開作成不同電容量之電容器亦可。In the first embodiment, one type of shape of the capacitor CP is shown and described, but the shape of the capacitor CP is not limited to the example. FIG. 26 shows an example of a cross-sectional structure of capacitors CPa to CPc in a modified example. As shown in FIG. 26 , among the capacitors CPa to CPc, the shape of the concave portion CC is different from each other. The capacitor CPa is the same as the capacitor CP described in the first embodiment. Compared with the capacitor CPa, the capacitor CPb is provided in the recess CC which is formed relatively wider and deeper. Compared with the capacitor CPc, the capacitor CPc is provided in the recess CC formed to be relatively narrow and shallow. That is, the cross-sectional area of the recess is changed by changing the width and depth of the recess. For example, by separately forming the recessed portion CC as described above, capacitors having different cross-sectional shapes may be formed separately. That is, capacitors having different capacitances may be formed separately by forming recesses CC of different cross-sectional areas separately.

第3實施形態中，針對電容器組CS，說明藉由所包含的電容器CP之個數來實現電容量之大小之情況之例，但是不限定於此。例如參照圖26之說明般，使用不同截面形狀的電容器來構成不同電容量的電容器組亦可。例如使用形成為寬度窄且淺的電容器CPc來構成小電容量的電容器組CS1，使用電容器CPa來構成電容器組CS2，使用形成為寬度較寬而且深度較深的電容器CPb來構成大電容量的電容器組CS3亦可。In the third embodiment, an example in which the magnitude of the capacitance is realized by the number of capacitors CP included is described for the capacitor bank CS, but the present invention is not limited thereto. For example, as described with reference to FIG. 26 , capacitor banks with different capacitances may be formed using capacitors with different cross-sectional shapes. For example, the small-capacity capacitor bank CS1 may be formed using a narrow and shallow capacitor CPc, the capacitor bank CS2 may be formed using a capacitor CPa, and the large-capacity capacitor bank CS3 may be formed using a wide and deep capacitor CPb.

第1至第3實施形態中示出電容器CP形成於凹部CC之情況之例，但是供作為形成電容器CP的部分的形狀不限定於凹部。例如電容器CP可以是形成在形成於半導體基板10的狹縫內。在這樣之情況下，電容器CP內之半導體層12具有向與半導體基板10之表面平行的方向延伸的部分。In the first to third embodiments, an example of the case where the capacitor CP is formed in the concave portion CC is shown, but the shape of the portion where the capacitor CP is formed is not limited to the concave portion. For example, the capacitor CP may be formed in a slit formed in the semiconductor substrate 10 . In such a case, the semiconductor layer 12 in the capacitor CP has a portion extending in a direction parallel to the surface of the semiconductor substrate 10 .

第3實施形態中，參照圖24之例說明電容器組CS1至CS3分別包含的電容器CP之個數，但電容器組CS1至CS3分別包含的電容器CP之個數不限定於此。此外，電容器組CS1至CS3各自之電容量之比例亦不限定於參照圖24說明的例。例如作為適用在高速動作的電路的布局之例，可以考慮將電容器組CS1至CS3各自之電容量之比例設為1：10：1000。此外，電容器組CS3之大小例如在電容器組CS2之10~1000倍之範圍內變更亦可。此外，例如電容器組CS2之電容量比電容器組CS1之電容量大1位數，電容器組CS3之電容量比電容器組CS2之電容量大1~3位數亦可。In the third embodiment, the number of capacitors CP respectively included in the capacitor banks CS1 to CS3 is described with reference to the example of FIG. 24 , but the number of capacitors CP respectively included in the capacitor banks CS1 to CS3 is not limited thereto. In addition, the ratio of the respective capacitances of the capacitor groups CS1 to CS3 is not limited to the example described with reference to FIG. 24 . For example, as an example of a circuit layout suitable for high-speed operation, it is conceivable to set the ratio of the respective capacitances of the capacitor banks CS1 to CS3 to 1:10:1000. In addition, the size of the capacitor bank CS3 may be changed within a range of, for example, 10 to 1000 times the capacitor bank CS2. In addition, for example, the capacitance of the capacitor bank CS2 may be greater than the capacitance of the capacitor bank CS1 by 1 digit, and the capacitance of the capacitor bank CS3 may be greater than the capacitance of the capacitor bank CS2 by 1 to 3 digits.

第1至第3實施形態中說明焊墊P1連接於電源線GW，電容部2連接於電源線GW之情況之例。但電容部2連接的布線不限定於連接於焊墊P1的電源線GW。圖27係表示變形例的半導體裝置1的構成例。如圖27所示，變形例的半導體裝置1和第1實施形態的半導體裝置1不同點為，進一步具備電壓生成電路4和電源線PW2，電容部2和電路部3連接於電源線PW2與電源線GW之間。如上述這樣地，電容部2連接於例如施加有在半導體裝置內部生成的電壓的布線亦可。In the first to third embodiments, an example of a case where the pad P1 is connected to the power supply line GW and the capacitor unit 2 is connected to the power supply line GW will be described. However, the wiring to which the capacitor unit 2 is connected is not limited to the power line GW connected to the pad P1. FIG. 27 shows a configuration example of a semiconductor device 1 according to a modified example. As shown in FIG. 27, the semiconductor device 1 of the modified example differs from the semiconductor device 1 of the first embodiment in that it further includes a voltage generating circuit 4 and a power line PW2, and the capacitor unit 2 and the circuit unit 3 are connected between the power line PW2 and the power line GW. As described above, the capacitor unit 2 may be connected to, for example, a wiring to which a voltage generated inside the semiconductor device is applied.

第1至第3實施形態中說明電源線PW與電容器CP經由1個接觸部CT連接之情況之例，但是電源線PW與電容器CP之間連接多個接觸部亦可，在中途經由不同的布線亦可。In the first to third embodiments, an example is described in which the power line PW and the capacitor CP are connected via one contact portion CT. However, a plurality of contact portions may be connected between the power line PW and the capacitor CP, and different wirings may be routed midway.

第3實施形態中，針對電容器組說明多個電容器CP經由接觸部CT連接於電源線PW之情況之例。但電容器組的構成不限定於第3實施形態中說明的例。例如藉由彙整設置在某個區域的多個電容器CP之各自的一方電極共通連接來構成電容器組。在半導體基板上設置多個電容器組之情況下，藉由各電容器組之電容量之大小、各電容器組與電源線PW之連接部位，可以將多個電容器組之每一個區分為獨立的電容器組。In the third embodiment, an example of a case where a plurality of capacitors CP is connected to the power line PW via the contact portion CT will be described for the capacitor bank. However, the configuration of the capacitor bank is not limited to the example described in the third embodiment. For example, a capacitor bank is formed by collectively connecting one electrode of a plurality of capacitors CP arranged collectively in a certain area. When a plurality of capacitor banks are provided on the semiconductor substrate, each of the plurality of capacitor banks can be divided into independent capacitor banks by the capacitance of each capacitor bank and the connection position between each capacitor bank and the power line PW.

本說明書中稱為凹部CC的形狀可以換個說法。例如具有凹部CC的半導體基板10，可以說成為具有第1面、與第1面呈對向的第2面、及設置於第1面與第2面之間的第3面的半導體基板10。第1面例如為半導體基板10之表面。第2面例如為半導體基板10之背面。第3面例如為凹部CC之底部。此外，沿著凹部CC設置的半導體層12，可以說成為從第3面沿著第1面設置的半導體層12。此外，例如在第1面與第2面之間設置第4面，具有從第4面沿著第1面設置的半導體層的電容器，其電容量可以和從第3面沿著第1面設置的半導體層的電容器之電容量不同。如上述這樣地，在第1面與第2面之間設置例如第3面和第4面等多個面，由此而分開作成具有不同電容量的電容器亦可。亦即，藉由設置第3面和第4面等多個面來分開作成不同截面積的凹部CC亦可。The shape referred to as the concave portion CC in this specification can be called differently. For example, the semiconductor substrate 10 having the recess CC can be said to be the semiconductor substrate 10 having a first surface, a second surface facing the first surface, and a third surface provided between the first surface and the second surface. The first surface is, for example, the surface of the semiconductor substrate 10 . The second surface is, for example, the back surface of the semiconductor substrate 10 . The third surface is, for example, the bottom of the concave portion CC. In addition, the semiconductor layer 12 provided along the concave portion CC can be said to be the semiconductor layer 12 provided along the first surface from the third surface. In addition, for example, a capacitor having a fourth surface provided between the first surface and the second surface and having a semiconductor layer arranged along the first surface from the fourth surface may have a capacitance different from that of a capacitor having a semiconductor layer arranged along the first surface from the third surface. As described above, capacitors having different capacitances may be formed separately by providing a plurality of surfaces such as the third surface and the fourth surface between the first surface and the second surface. That is, by providing a plurality of surfaces such as the third surface and the fourth surface, the recesses CC having different cross-sectional areas may be formed separately.

本說明書中“連接”係表示電連接，例如不排除在其間***其他元件。此外“電連接”可以經由絕緣體只要能夠與電連接者同樣地動作即可。"Connection" in this specification means electrical connection, for example, does not exclude the interposition of other elements therebetween. In addition, the "electrical connection" may be made via an insulator as long as it can operate in the same way as the electrical connector.

[5]第4實施形態 第4實施形態的半導體裝置為，第3實施形態的半導體裝置1包含多個電路之情況下之具體例。以下，針對第4實施形態的半導體裝置1說明其和第1~第3實施形態之不同點。[5] Fourth Embodiment The semiconductor device of the fourth embodiment is a specific example in which the semiconductor device 1 of the third embodiment includes a plurality of circuits. Hereinafter, the difference between the semiconductor device 1 of the fourth embodiment and the first to third embodiments will be described.

[5-1]構成 圖28係表示第4實施形態的半導體裝置1之電路構成之一例。如圖28所示，第4實施形態的半導體裝置1包含作為電容部2的電容器組CS10d、CS10e、CS10f、CS20和CS30，包含作為電路部3的電路3d、3e和3f。電源線PW包含節點N4。[5-1] Composition FIG. 28 shows an example of the circuit configuration of the semiconductor device 1 according to the fourth embodiment. As shown in FIG. 28 , the semiconductor device 1 according to the fourth embodiment includes capacitor banks CS10d, CS10e, CS10f, CS20 and CS30 as capacitor unit 2 and circuits 3d, 3e and 3f as circuit unit 3 . The power line PW includes a node N4.

電源線PW係從焊墊P1至電路3d、3e和3f各自的電源端為止設置。具體而言，電源線PW之從焊墊P1至節點N4為止所對應的部分，係由電路3d、3e和3f共用。另一方面，電源線PW之從節點N4至電路3d、3e和3f各自的電源端為止所對應的部分，係在電路3d、3e和3f獨立設置。The power line PW is provided from the pad P1 to the respective power terminals of the circuits 3d, 3e, and 3f. Specifically, the corresponding portion of the power line PW from the pad P1 to the node N4 is shared by the circuits 3d, 3e and 3f. On the other hand, the corresponding portions of the power supply line PW from the node N4 to the respective power supply terminals of the circuits 3d, 3e and 3f are independently provided in the circuits 3d, 3e and 3f.

電容器組CS10d、CS10e、CS10f、CS20和CS30各自的一方電極係連接於電源線PW，各自之另一方電極被接地。電容器組CS10d之一方電極連接於電路3d之電源端與節點N4之間。電容器組CS10e之一方電極連接於電路3e之電源端與節點N4之間。電容器組CS10f之一方電極連接於電路3f之電源端與節點N4之間。在節點N4與焊墊P1之間，從節點N4向焊墊P1之方向依序連接電容器組CS20及CS30各自的一方電極。One electrode of each of the capacitor banks CS10d, CS10e, CS10f, CS20, and CS30 is connected to the power supply line PW, and the other electrode of each is grounded. One electrode of the capacitor bank CS10d is connected between the power supply terminal of the circuit 3d and the node N4. One electrode of the capacitor bank CS10e is connected between the power supply terminal of the circuit 3e and the node N4. One electrode of the capacitor bank CS10f is connected between the power supply terminal of the circuit 3f and the node N4. Between the node N4 and the pad P1, one electrode of each of the capacitor banks CS20 and CS30 is sequentially connected in the direction from the node N4 to the pad P1.

電容器組CS10d、CS10e和CS10f各自之電容量例如大致相等。電容器組CS20之電容量大於電容器組CS10d、CS10e和CS10f任一之電容量。電容器組CS20之電容量例如為電容器組CS10d之電容量之10倍。電容器組CS30之電容量大於電容器組CS20之電容量。電容器組CS30之電容量例如為電容器組CS20之電容量之10倍。The respective capacitances of the capacitor banks CS10d, CS10e, and CS10f are, for example, substantially equal. The capacitance of the capacitor bank CS20 is greater than that of any one of the capacitor banks CS10d, CS10e, and CS10f. The capacitance of the capacitor bank CS20 is, for example, 10 times the capacitance of the capacitor bank CS10d. The capacitance of the capacitor bank CS30 is greater than the capacitance of the capacitor bank CS20. The capacitance of the capacitor bank CS30 is, for example, 10 times the capacitance of the capacitor bank CS20.

亦即，電容器組CS10d、CS20和CS30係從電路3d向焊墊P1按電容量小的順序布置。電容器組CS10e、CS20和CS30係從電路3e向焊墊P1按電容量小的順序布置。電容器組CS10f、CS20和CS30係從電路3f向焊墊P1按電容量小的順序布置。That is, the capacitor banks CS10d, CS20, and CS30 are arranged in order of smaller capacitance from the circuit 3d toward the pad P1. The capacitor banks CS10e, CS20, and CS30 are arranged in order of smaller capacitance from the circuit 3e toward the pad P1. The capacitor banks CS10f, CS20, and CS30 are arranged in order of smaller capacitance from the circuit 3f toward the pad P1.

圖29係表示第4實施形態的半導體裝置1之平面布局之一例。如圖29所示，第4實施形態的半導體裝置1進一步包含接觸部CT20d、CT20e、CT20f、CT21d、CT21e、CT21f、CT22和CT23。此外，電容器組CS10d、CS10e、CS10f、CS20和CS30分別包含多個電容器CP。電容器組所包含的電容器CP之個數例如按電容器組CS10d、電容器組CS20、電容器組CS30之順序變多。又，圖29所示的例中，電容器CP之個數被簡化表示。FIG. 29 shows an example of the planar layout of the semiconductor device 1 according to the fourth embodiment. As shown in FIG. 29, the semiconductor device 1 according to the fourth embodiment further includes contact portions CT20d, CT20e, CT20f, CT21d, CT21e, CT21f, CT22, and CT23. In addition, the capacitor banks CS10d, CS10e, CS10f, CS20, and CS30 each include a plurality of capacitors CP. The number of capacitors CP included in the capacitor bank increases, for example, in the order of capacitor bank CS10d, capacitor bank CS20, and capacitor bank CS30. Also, in the example shown in FIG. 29, the number of capacitors CP is simplified.

電源線PW從焊墊P1向X方向延伸布置。沿著電源線PW從接近焊墊P1之處起依序布置電容器組CS30、電容器組CS20、電容器組CS10d和電路3d。電路3e與電容器組CS20在Y方向並列布置。電路3f係與電容器組CS20在Y方向並列且布置於電路3e之相反側。電容器組CS10e，係與電路3e在X方向並列，而且在Y方向上布置於電容器組CS10d與電容器組CS20之間。電容器組CS10f，係與電路3f在X方向並列，而且在Y方向上布置於電容器組CS10d與電容器組CS20之間。此外，電源線PW在電容器組CS10d與電容器組CS20之間具有分歧部F1，且從分歧部F1向Y方向延伸。分歧部F1對應於節點N4。The power line PW is extended from the pad P1 to the X direction. The capacitor bank CS30, the capacitor bank CS20, the capacitor bank CS10d, and the circuit 3d are arranged in this order from a position close to the pad P1 along the power supply line PW. The circuit 3e is arranged in parallel with the capacitor bank CS20 in the Y direction. The circuit 3f is arranged in parallel with the capacitor bank CS20 in the Y direction and on the opposite side of the circuit 3e. The capacitor bank CS10e is arranged in parallel with the circuit 3e in the X direction and between the capacitor bank CS10d and the capacitor bank CS20 in the Y direction. The capacitor bank CS10f is arranged in parallel with the circuit 3f in the X direction and between the capacitor bank CS10d and the capacitor bank CS20 in the Y direction. Moreover, the power supply line PW has the branch part F1 between capacitor bank CS10d and capacitor bank CS20, and extends from branch part F1 to a Y direction. The branch part F1 corresponds to the node N4.

接觸部CT20d、CT20e和CT20f分別將電路3d、3e和3f各自的電源端與電源線PW予以連接。接觸部CT21d、CT21e、CT21f、CT22和CT23分別將電容器組CS10d、CS10e、CS10f、CS20和CS30各自的一方電極與電源線PW予以連接。第4實施形態的半導體裝置1之其他構成係和第3實施形態同樣。The contact portions CT20d, CT20e, and CT20f connect the respective power supply terminals of the circuits 3d, 3e, and 3f to the power supply line PW, respectively. The contacts CT21d, CT21e, CT21f, CT22, and CT23 connect one electrode of each of the capacitor banks CS10d, CS10e, CS10f, CS20, and CS30 to the power line PW, respectively. Other configurations of the semiconductor device 1 of the fourth embodiment are the same as those of the third embodiment.

[5-2]第4實施形態之效果 如以上說明，第4實施形態的半導體裝置1中，多個電路的電源線PW係具有：多個電路間共用的部分，和對應於多個電路分別獨立設置的部分。和第3實施形態同樣地，在分別連接於電路3d、3e和3f的電源線PW中，越接近電路連接越小電容量的電容器組，越遠離電路連接越大電容量的電容器組。第4實施形態的半導體裝置1中，藉由如上述這樣地布置電容器組，則即使有多個電路之情況下亦和第3實施形態同樣地可以抑制電源電壓之變動。[5-2] Effects of the fourth embodiment As described above, in the semiconductor device 1 according to the fourth embodiment, the power line PW of a plurality of circuits has a portion shared by the plurality of circuits and a portion independently provided corresponding to the plurality of circuits. Similar to the third embodiment, in the power lines PW connected to the circuits 3d, 3e, and 3f, capacitor banks with smaller capacitance are connected closer to the circuits, and capacitor banks with larger capacitance are connected farther from the circuits. In the semiconductor device 1 of the fourth embodiment, by arranging the capacitor bank as described above, even if there are a plurality of circuits, fluctuations in the power supply voltage can be suppressed similarly to the third embodiment.

[5-3]第4實施形態之變形例 第4實施形態的半導體裝置1可以有各種變形。以下，針對第4實施形態之第1~第5變形例依序進行說明。[5-3] Modification of the fourth embodiment The semiconductor device 1 of the fourth embodiment can be modified in various ways. Hereinafter, the first to fifth modifications of the fourth embodiment will be sequentially described.

[5-3-1]第1變形例 圖30係表示第4實施形態之第1變形例的半導體裝置1之平面布局之一例。如圖30所示，第1變形例的半導體裝置1，係在第4實施形態的半導體裝置1中，具有將電容器組CS10d、CS10e和CS10f分別替換為電容器組CS11d、CS11e和CS11f的構成。[5-3-1] Modification 1 FIG. 30 shows an example of the planar layout of the semiconductor device 1 according to the first modified example of the fourth embodiment. As shown in FIG. 30, the semiconductor device 1 of the first modified example has a configuration in which the capacitor banks CS10d, CS10e, and CS10f are replaced with capacitor banks CS11d, CS11e, and CS11f, respectively, in the semiconductor device 1 of the fourth embodiment.

電容器組CS11d、CS11e和CS11f分別包含平板電容器FC。亦即，第1變形例的半導體裝置1中，不同電容量的多個電容器組之中，小電容量的電容器組係包含平板電容器FC之構成。此外，和第4實施形態同樣地，多個電容器組CS中設置為，越接近電路者越小電容量，越遠離電路者越大電容量。第4實施形態之第1變形例中的其他構成係和第4實施形態同樣。The capacitor banks CS11d, CS11e, and CS11f each include a plate capacitor FC. That is, in the semiconductor device 1 according to the first modification, among a plurality of capacitor banks with different capacitances, the capacitor bank with a small capacitance includes the plate capacitor FC. In addition, similarly to the fourth embodiment, among the plurality of capacitor banks CS, the closer to the circuit, the smaller the capacitance, and the farther away from the circuit, the larger the capacitance. Other configurations in the first modified example of the fourth embodiment are the same as those of the fourth embodiment.

如以上所述，第4實施形態之第1變形例的半導體裝置1中，一些電容器組CS係包含平板電容器FC。半導體裝置1中，各電容器組之電容量係依據電路之消費電流或容許的電壓變動之量等進行設計。因此，當靠近電路的電容器組之電容量成為非常小的值時，即使靠近電路的電容器組包含平板電容器FC之構成時，亦可以獲得足夠的性能。因此，第4實施形態之第1變形例的半導體裝置1可以獲得和第4實施形態同樣之效果。As described above, in the semiconductor device 1 according to the first modified example of the fourth embodiment, some capacitor banks CS include plate capacitors FC. In the semiconductor device 1, the capacitance of each capacitor bank is designed according to the consumption current of the circuit, the amount of allowable voltage fluctuation, and the like. Therefore, when the capacitance of the capacitor bank close to the circuit is very small, sufficient performance can be obtained even if the capacitor bank close to the circuit includes the plate capacitor FC. Therefore, the semiconductor device 1 according to the first modified example of the fourth embodiment can obtain the same effect as that of the fourth embodiment.

[5-3-2]第2變形例 圖31係表示第4實施形態之第2變形例的半導體裝置1之平面布局之一例。如圖31所示，第2變形例的半導體裝置1，係在第4實施形態的半導體裝置1中，具有電容器組CS30被替換為電容器組CS31的構成。[5-3-2] Second modified example FIG. 31 shows an example of a planar layout of a semiconductor device 1 according to a second modified example of the fourth embodiment. As shown in FIG. 31, the semiconductor device 1 of the second modified example has a configuration in which the capacitor bank CS30 is replaced with the capacitor bank CS31 in the semiconductor device 1 of the fourth embodiment.

電容器組CS31包含平板電容器FC。亦即，第2變形例的半導體裝置1中，不同電容量的多個電容器組之中，大電容量的電容器組具有平板電容器FC之構成。此外，和第4實施形態同樣地，多個電容器組CS以越接近電路者越小電容量，越遠離電路者越大電容量設置。第4實施形態之第2變形例中的其他構成係和第4實施形態同樣。Capacitor bank CS31 includes plate capacitor FC. That is, in the semiconductor device 1 according to the second modified example, among a plurality of capacitor banks with different capacitances, the capacitor bank with a large capacitance has a configuration of the plate capacitor FC. In addition, similarly to the fourth embodiment, a plurality of capacitor banks CS are provided such that the closer to the circuit, the smaller the capacitance, and the farther away from the circuit, the larger the capacitance. Other configurations in the second modified example of the fourth embodiment are the same as those of the fourth embodiment.

如以上所述，第4實施形態之第2變形例的半導體裝置1中，一些電容器組CS係使用平板電容器FC來構成。半導體裝置1中，設置電容器組CS的區域之面積根據設計而不同。因此，電路不密集而基板之面積具有餘裕度之情況下，大電容量的電容器組亦可以由平板電容器FC構成。因此，第4實施形態之第2變形例的半導體裝置1可以獲得和第4實施形態同樣之效果。As described above, in the semiconductor device 1 according to the second modified example of the fourth embodiment, some of the capacitor banks CS are formed using the plate capacitors FC. In the semiconductor device 1, the area of the region where the capacitor bank CS is provided varies depending on the design. Therefore, when the circuit is not densely packed and the area of the substrate has a margin, the large-capacity capacitor bank can also be composed of the plate capacitor FC. Therefore, the semiconductor device 1 according to the second modified example of the fourth embodiment can obtain the same effect as that of the fourth embodiment.

[5-3-3]第3變形例 圖32係表示第4實施形態之第3變形例的半導體裝置1之電路構成之一例。如圖32所示，第3變形例的半導體裝置1，係在第4實施形態的半導體裝置1中，進一步包含作為電容部2的電容器組CS12e及CS21。電源線PW進一步包含節點N5。電路3e進一步包含第2電源端。又，以下將第4實施形態中說明的電路3e之電源端稱為電路3e之第1電源端，便於與電路3e之第2電源端區別。[5-3-3] The third modified example FIG. 32 shows an example of a circuit configuration of a semiconductor device 1 according to a third modified example of the fourth embodiment. As shown in FIG. 32 , a semiconductor device 1 according to the third modified example further includes capacitor banks CS12e and CS21 as capacitor units 2 in the semiconductor device 1 according to the fourth embodiment. The power line PW further includes a node N5. Circuit 3e further includes a second power supply terminal. Also, hereinafter, the power supply terminal of the circuit 3e described in the fourth embodiment is referred to as the first power supply terminal of the circuit 3e to distinguish it from the second power supply terminal of the circuit 3e.

電源線PW之節點N5對應於，電容器組CS30之一方電極所連接的點與電容器組CS20之一方電極所連接的點之間。節點N5與電路3e之第2電源端間藉由電源線PW連接。電源線PW中，在從節點N5直至電路3e之第2電源端之間，從節點N5向電路3e之第2電源端之方向依序連接有電容器組CS21之一方電極、電容器組CS12e之一方電極。The node N5 of the power supply line PW corresponds to a point where one electrode of the capacitor bank CS30 is connected and a point where one electrode of the capacitor bank CS20 is connected. The node N5 is connected to the second power supply end of the circuit 3e by a power supply line PW. In the power line PW, between the node N5 and the second power supply terminal of the circuit 3e, one electrode of the capacitor bank CS21 and one electrode of the capacitor bank CS12e are sequentially connected from the node N5 to the second power supply terminal of the circuit 3e.

電容器組CS12e之電容量例如與電容器組CS10e之電容量大致相等。電容器組CS21之電容量大於電容器組CS12e之電容量，且小於電容器組CS30之電容量。電容器組CS21之電容量例如與電容器組CS20大致相等。The capacitance of the capacitor bank CS12e is substantially equal to the capacitance of the capacitor bank CS10e, for example. The capacitance of the capacitor bank CS21 is larger than the capacitance of the capacitor bank CS12e and smaller than the capacitance of the capacitor bank CS30. Capacitance of the capacitor bank CS21 is substantially equal to that of the capacitor bank CS20, for example.

圖33係表示第3變形例的半導體裝置1之平面布局之一例。如圖33所示，第3變形例的半導體裝置1進一步包含接觸部CT20e2、CT21e2和CT24。電容器組CS12e所包含的電容器CP之個數例如與電容器組CS10e所包含的電容器CP之個數相等。電容器組CS21所包含的電容器CP之個數例如與電容器組CS20所包含的電容器CP之個數相等。FIG. 33 shows an example of a planar layout of a semiconductor device 1 according to a third modification. As shown in FIG. 33 , the semiconductor device 1 according to the third modification further includes contact portions CT20e2 , CT21e2 , and CT24 . The number of capacitors CP included in capacitor bank CS12e is equal to the number of capacitors CP included in capacitor bank CS10e, for example. The number of capacitors CP included in capacitor bank CS21 is equal to the number of capacitors CP included in capacitor bank CS20, for example.

電源線PW係在電容器組CS20與電容器組CS30之間具有分歧部F2，且從分歧部F2向Y方向延伸。分歧部F2對應於節點N5。沿著電源線PW從分歧部F2向Y方向延伸，而從分歧部F2起依序布置電容器組CS21、電容器組CS12e。The power line PW has a branch part F2 between the capacitor bank CS20 and the capacitor bank CS30, and extends from the branch part F2 in the Y direction. The divergence part F2 corresponds to the node N5. The branch portion F2 extends in the Y direction along the power line PW, and the capacitor bank CS21 and the capacitor bank CS12e are arranged in order from the branch portion F2.

接觸部CT20e2係將電路3e之第2電源端與電源線PW予以連接。接觸部CT21e2係將電容器組CS12e之一方電極與電源線PW予以連接。接觸部CT24係將電容器組CS21之一方電極與電源線PW予以連接。第3變形例的半導體裝置1之其他構成係和第4實施形態同樣。The contact portion CT20e2 connects the second power supply terminal of the circuit 3e and the power supply line PW. The contact portion CT21e2 connects one electrode of the capacitor bank CS12e to the power line PW. The contact portion CT24 connects one electrode of the capacitor bank CS21 to the power line PW. Other configurations of the semiconductor device 1 of the third modified example are the same as those of the fourth embodiment.

亦即，第3變形例的半導體裝置1中，在將電路3e之第1電源端及第2電源端分別連接的電源線PW中，越接近電路連接越小電容量的電容器組，越遠離電路布置越大電容量的電容器組。具體而言，在連接電路3e之第1電源端與焊墊P1的電源線PW中，從電路3e之第1電源端向焊墊P1依序布置電容器組CS10e、電容器組CS20、和電容器組CS30。在連接電路3e之第2電源端與焊墊P1的電源線PW中，從電路3e之第2電源端向焊墊P1依序布置電容器組CS12e、電容器組CS21、和電容器組CS30。That is, in the semiconductor device 1 of the third modified example, in the power line PW connecting the first power supply terminal and the second power supply terminal of the circuit 3e, a capacitor bank with a smaller capacitance is connected closer to the circuit, and a capacitor bank with a larger capacitance is arranged farther from the circuit. Specifically, on the power line PW connecting the first power supply terminal of the circuit 3e and the pad P1, the capacitor bank CS10e, the capacitor bank CS20, and the capacitor bank CS30 are sequentially arranged from the first power supply terminal of the circuit 3e to the pad P1. On the power line PW connecting the second power supply terminal of the circuit 3e and the pad P1, the capacitor bank CS12e, the capacitor bank CS21, and the capacitor bank CS30 are sequentially arranged from the second power supply terminal of the circuit 3e to the pad P1.

如以上所述，第4實施形態之第3變形例的半導體裝置1中，在同一電路區塊連接有不同的多個電源線之情況下，在多個電源線分別布置電容器組。藉此，可以極精細地抑制同一電路區塊內之電源電壓之抖動，可以促進減低抖動的效果。如上述這樣地，第4實施形態之第3變形例的半導體裝置1可以獲得和第4實施形態同樣之效果。As described above, in the semiconductor device 1 according to the third modified example of the fourth embodiment, when a plurality of different power supply lines are connected to the same circuit block, capacitor banks are respectively arranged on the plurality of power supply lines. Thereby, the jitter of the power supply voltage in the same circuit block can be suppressed very finely, and the effect of reducing jitter can be promoted. As described above, the semiconductor device 1 according to the third modified example of the fourth embodiment can obtain the same effect as that of the fourth embodiment.

又，電容器組CS12e之電容量與電容器組CS10e之電容量之關係，以及電容器組CS21之電容量與電容器組CS20之電容量之關係，分別不限定於和第3變形例中例示的大致相等之情況。電容器組CS12e及CS21各自之電容量，可以在電容器組CS21之電容量小於電容器組CS30之電容量，電容器組CS12e之電容量小於電容器組CS21之電容量之範圍內變更。Also, the relationship between the capacitance of the capacitor bank CS12e and the capacitance of the capacitor bank CS10e, and the relationship between the capacitance of the capacitor bank CS21 and the capacitance of the capacitor bank CS20 are not limited to being substantially equal to those illustrated in the third modified example. The respective capacitances of capacitor banks CS12e and CS21 can be changed within the range in which the capacitance of capacitor bank CS21 is smaller than that of capacitor bank CS30, and the capacitance of capacitor bank CS12e is smaller than that of capacitor bank CS21.

[5-3-4]第4變形例 圖34係表示第4實施形態之第4變形例的半導體裝置1之平面布局之一例。如圖34所示，第4變形例的半導體裝置1，係在第4實施形態的半導體裝置1中，具有電容器組CS10d、CS10e和CS10f分別替換為電容器組CS13d、CS13e和CS13f的構成。[5-3-4] Modification 4 FIG. 34 shows an example of a planar layout of a semiconductor device 1 according to a fourth modified example of the fourth embodiment. As shown in FIG. 34, the semiconductor device 1 of the fourth modification has a configuration in which the capacitor banks CS10d, CS10e, and CS10f are replaced with capacitor banks CS13d, CS13e, and CS13f, respectively, in the semiconductor device 1 of the fourth embodiment.

電路3d、3e和3f分別包含構成電路的多個要素，例如包含電晶體、電阻和電容器。電路3d所包含的多個要素，係布置於基板上之電路區域A1。電容器組CS13d布置於電路區域A1內。例如電路3d所包含的要素將電容器組CS13d之周圍予以包圍。The circuits 3d, 3e, and 3f each include a plurality of elements constituting the circuit, for example, transistors, resistors, and capacitors. The multiple elements included in the circuit 3d are arranged in the circuit area A1 on the substrate. The capacitor bank CS13d is arranged in the circuit area A1. For example, elements included in the circuit 3d surround the capacitor bank CS13d.

電路3e所包含的多個要素布置於基板上之電路區域A2。電容器組CS13e布置於電路區域A2內。例如電容器組CS13e之周圍被電路3e所包含的要素包圍。A plurality of elements included in the circuit 3e are arranged in the circuit area A2 on the substrate. The capacitor bank CS13e is arranged in the circuit area A2. For example, the capacitor bank CS13e is surrounded by elements included in the circuit 3e.

電路3f所包含的多個要素布置於基板上之電路區域A3。電容器組CS13f布置於電路區域A3內。例如電容器組CS13f之周圍被電路3f所包含的要素包圍。換言之，電容器組CS13d、CS13e和CS13f分別布置於設置有電路3d、3e和3f的各個區域內。A plurality of elements included in the circuit 3f are arranged in the circuit area A3 on the substrate. The capacitor bank CS13f is arranged in the circuit area A3. For example, the capacitor bank CS13f is surrounded by elements included in the circuit 3f. In other words, the capacitor groups CS13d, CS13e, and CS13f are respectively arranged in respective regions where the circuits 3d, 3e, and 3f are provided.

以上說明的第4變形例的半導體裝置1中，不同電容量的多個電容器組之中，小電容量的電容器組係設置於設置有電路的區域內。藉此，可以縮短電路之電源端與小電容量的電容器組之間之距離，可以進一步抑制電源電壓之變動，進一步減低抖動。因此，第4實施形態之第4變形例的半導體裝置1可以獲得和第4實施形態同樣之效果。In the semiconductor device 1 according to the fourth modified example described above, among a plurality of capacitor banks having different capacitances, a capacitor bank with a small capacitance is provided in the region where the circuit is provided. Thereby, the distance between the power supply terminal of the circuit and the capacitor bank with small capacity can be shortened, the fluctuation of the power supply voltage can be further suppressed, and the jitter can be further reduced. Therefore, the semiconductor device 1 according to the fourth modified example of the fourth embodiment can obtain the same effect as that of the fourth embodiment.

[5-3-5]第5變形例 圖35係表示第4實施形態之第5變形例的半導體裝置1的電容器組CS30之平面布局之一例。如圖35所示，第5變形例的半導體裝置1，係針對第4實施形態的半導體裝置1進一步包含布線W1、W2和W3。電容器組CS30包含電容器CPa、CPb和CPc。如參照圖26之說明，電容器CPa、CPb和CPc分別為不同大小的電容器。圖35中，為了便於觀察構成而省略電容器組CS30之一方電極所連接的電源線PW之記載。電容器組CS30所包含的多個電容器各自的一方電極係藉由接觸部CT連接於電源線PW。[5-3-5] Fifth modified example FIG. 35 shows an example of the planar layout of the capacitor bank CS30 of the semiconductor device 1 according to the fifth modified example of the fourth embodiment. As shown in FIG. 35, the semiconductor device 1 of the fifth modification further includes wirings W1, W2, and W3 compared to the semiconductor device 1 of the fourth embodiment. Capacitor bank CS30 includes capacitors CPa, CPb, and CPc. As explained with reference to FIG. 26, the capacitors CPa, CPb, and CPc are capacitors of different sizes. In FIG. 35 , the description of the power supply line PW connected to one electrode of the capacitor bank CS30 is omitted for the convenience of viewing the structure. One electrode of each of the plurality of capacitors included in the capacitor bank CS30 is connected to the power supply line PW through the contact portion CT.

如圖35所示，以與設置有電容器組CS30的區域重疊的方式布置布線W1、W2和W3。以與布線W1、W2和W3不重疊的方式布置多個電容器CPa、CPb和CPc。具體而言，在布線W1之附近及布線W1與布線W2之間之區域，以在布線W1與布線W2之間可以布置的方式布置多個較小尺寸的電容器CPc。在布線W2與布線W3之間之區域布置多個電容器CPa。在被布線W3劃分的區域，且不存在其他布線區域布置多個較大尺寸的電容器CPb。As shown in FIG. 35 , the wirings W1 , W2 , and W3 are arranged in such a manner as to overlap the area where the capacitor bank CS30 is provided. A plurality of capacitors CPa, CPb, and CPc are arranged so as not to overlap with the wirings W1, W2, and W3. Specifically, in the vicinity of the wiring W1 and in the region between the wiring W1 and the wiring W2, a plurality of small-sized capacitors CPc are arranged in such a manner that they can be arranged between the wiring W1 and the wiring W2. A plurality of capacitors CPa are arranged in a region between the wiring W2 and the wiring W3. A plurality of large-sized capacitors CPb are arranged in a region divided by the wiring W3 and where there is no other wiring region.

以上說明的第5變形例的半導體裝置1中，一個電容器組CS包含不同尺寸的多種類之電容器CP。設置電容器組CS的區域例如可以與設置布線的區域重疊。存在布線與電容器CP無法重疊設置的情況。避開布線而布置電容器CP之情況下，藉由使用多個尺寸之電容器，可以抑制藉由避開布線導致的電容器組之面積增加。因此，第4實施形態之第5變形例的半導體裝置1可以獲得和第4實施形態同樣之效果。In the semiconductor device 1 according to the fifth modified example described above, one capacitor bank CS includes a plurality of types of capacitors CP of different sizes. The region where the capacitor bank CS is provided may overlap with the region where wiring is provided, for example. There are cases where the wiring and the capacitor CP cannot be installed overlapping each other. In the case where the capacitor CP is arranged avoiding the wiring, by using capacitors of a plurality of sizes, it is possible to suppress an increase in the area of the capacitor bank caused by avoiding the wiring. Therefore, the semiconductor device 1 according to the fifth modified example of the fourth embodiment can obtain the same effect as that of the fourth embodiment.

又，無法與電容器CP重疊設置之要素不限定於布線。例如在避開與半導體基板連接的接觸部或虛擬圖案等而布置電容器CP時，第5變形例所示的構成有效。In addition, elements that cannot be provided overlapping the capacitor CP are not limited to wiring. For example, the configuration shown in the fifth modification is effective when the capacitor CP is arranged avoiding the contact portion connected to the semiconductor substrate, the dummy pattern, and the like.

可以將以上說明的第4實施形態之第1至第5變形例組合。例如可以組合第1變形例與第5變形例。此外，組合電容器CP與平板電容器FC來構成1個電容器組CS亦可。The first to fifth modifications of the fourth embodiment described above can be combined. For example, the first modification and the fifth modification may be combined. In addition, capacitor CP and plate capacitor FC may be combined to form one capacitor bank CS.

以上說明的實施形態及變形例中舉出一些例說明了，以沿著凹部CC設置的半導體層12和導電體13作為一方電極之功能的電容器CP，以及以設置於半導體基板之上的半導體層12和導電體13作為一方電極之功能的平板電容器FC。此外，說明了半導體基板10作為電容器CP之另一方電極及平板電容器FC之另一方電極之功能的例。又，電容器CP例如可以說成溝槽式電容器。平板電容器FC例如可以說成平面型電容器。In the embodiments and modifications described above, some examples were given to illustrate the capacitor CP having the semiconductor layer 12 and the conductor 13 provided along the recess CC as one electrode and the plate capacitor FC having the semiconductor layer 12 and the conductor 13 provided on the semiconductor substrate as one electrode. In addition, an example in which the semiconductor substrate 10 functions as the other electrode of the capacitor CP and the other electrode of the plate capacitor FC has been described. Also, the capacitor CP can be said to be, for example, a trench capacitor. The plate capacitor FC can be said to be, for example, a planar capacitor.

對本發明之幾個實施形態進行了說明，但是這些實施形態僅為例示，並非意圖用來限定發明之範圍者。這些新穎的實施形態，可以藉由其他之各種形態實施，在不脫離發明之主旨之範圍內可以進行各種省略、替換、變更。這些實施形態或其變形亦包含於發明之範圍或主旨，同時亦包含於申請專利範圍記載的發明以及其之均等範圍內。Although several embodiments of the present invention have been described, these embodiments are merely examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are also included in the scope and gist of the invention, and are also included in the invention described in the claims and their equivalent scope.

1:半導體裝置 2:電容部 3:電路部 P1,P2:焊墊 PW,GW:電源線 CP:電容器 10:半導體基板 11:絕緣體層 12:半導體層 13:導電體 14:絕緣體 15:阱區域 16,19:擴散區域 17,18:導電體 30:導電體 CC:凹部 CT:接觸部 TR:電晶體 CA:電容器區域 TA:電晶體區域1: Semiconductor device 2: capacitor part 3: Circuit department P1, P2: Welding pads PW, GW: power cord CP: Capacitor 10: Semiconductor substrate 11: Insulator layer 12: Semiconductor layer 13: Conductor 14: Insulator 15: well area 16,19: Spread area 17,18: Conductor 30: Conductor CC: Concave CT: contact part TR: Transistor CA: capacitor area TA: Transistor area

[圖1]表示第1實施形態的半導體裝置的構成例的方塊圖。 [圖2]表示第1實施形態的半導體裝置具備的電容部2的構成例的電路圖。 [圖3]表示第1實施形態的半導體裝置之電容器區域中的平面布局之一例的平面圖。 [圖4]表示沿著圖3的IV-IV線的電容器區域之剖面結構之一例的剖面圖。 [圖5]表示第1實施形態的半導體裝置之電晶體區域之剖面結構之一例的剖面圖。 [圖6]表示第1實施形態的半導體裝置之製造工程之一例的流程圖。 [圖7]表示第1實施形態的半導體裝置之製造工程之一例的剖面圖。 [圖8]表示第1實施形態的半導體裝置之製造工程之一例的剖面圖。 [圖9]表示第1實施形態的半導體裝置之製造工程之一例的剖面圖。 [圖10]表示第1實施形態的半導體裝置之製造工程之一例的剖面圖。 [圖11]表示第1實施形態的半導體裝置之製造工程之一例的剖面圖。 [圖12]表示第1實施形態的半導體裝置之製造工程之一例的剖面圖。 [圖13]表示第1實施形態的半導體裝置之製造工程之一例的剖面圖。 [圖14]表示第1實施形態的半導體裝置之製造工程之一例的剖面圖。 [圖15]表示第1實施形態的半導體裝置之製造工程之一例的剖面圖。 [圖16]表示第1實施形態之比較例的半導體裝置之電容器區域中的平面布局之一例的平面圖。 [圖17]表示沿著圖16之XVII-XVII線的電容器區域之剖面結構之一例的剖面圖。 [圖18]表示第2實施形態的半導體裝置的構成例的方塊圖。 [圖19]表示第2實施形態的半導體裝置之平面布局之一例的平面圖。 [圖20]表示第2實施形態之比較例的半導體裝置的構成例的方塊圖。 [圖21]表示第2實施形態之比較例的半導體裝置之平面布局之一例的平面圖。 [圖22]表示第2實施形態的半導體裝置及其之比較例中的電壓與電流之時間變化的曲線圖。 [圖23]表示第3實施形態的半導體裝置的構成例的方塊圖。 [圖24]表示第3實施形態的半導體裝置之平面布局之一例的平面圖。 [圖25]表示第1至第3實施形態之第1變形例的電容器區域之剖面結構之一例的剖面圖。 [圖26]表示第1至第3實施形態之第2變形例的電容器區域之剖面結構之一例的剖面圖。 [圖27]表示第1至第3實施形態之第3變形例的半導體裝置的構成例的方塊圖。 [圖28]表示第4實施形態的半導體裝置的構成例的方塊圖。 [圖29]表示第4實施形態的半導體裝置之平面布局之一例的平面圖。 [圖30]表示第4實施形態之第1變形例的半導體裝置之平面布局之一例的平面圖。 [圖31]表示第4實施形態之第2變形例的半導體裝置之平面布局之一例的平面圖。 [圖32]表示第4實施形態之第3變形例的半導體裝置的構成例的方塊圖。 [圖33]表示第4實施形態之第3變形例的半導體裝置之平面布局之一例的平面圖。 [圖34]表示第4實施形態之第4變形例的半導體裝置之平面布局之一例的平面圖。 [圖35]表示第4實施形態之第5變形例的半導體裝置包含的電容器組之平面布局之一例的平面圖。[ Fig. 1] Fig. 1 is a block diagram showing a configuration example of a semiconductor device according to a first embodiment. [ Fig. 2] Fig. 2 is a circuit diagram showing a configuration example of the capacitor unit 2 included in the semiconductor device according to the first embodiment. [ Fig. 3] Fig. 3 is a plan view showing an example of a planar layout in a capacitor region of the semiconductor device according to the first embodiment. [ Fig. 4] Fig. 4 is a cross-sectional view showing an example of a cross-sectional structure of a capacitor region along line IV-IV in Fig. 3 . [ Fig. 5] Fig. 5 is a cross-sectional view showing an example of a cross-sectional structure of a transistor region of the semiconductor device according to the first embodiment. [ Fig. 6] Fig. 6 is a flow chart showing an example of the manufacturing process of the semiconductor device according to the first embodiment. [ Fig. 7] Fig. 7 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device according to the first embodiment. [ Fig. 8] Fig. 8 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device according to the first embodiment. [ Fig. 9] Fig. 9 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device according to the first embodiment. [ Fig. 10] Fig. 10 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device according to the first embodiment. [ Fig. 11] Fig. 11 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device according to the first embodiment. [ Fig. 12] Fig. 12 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device according to the first embodiment. [ Fig. 13] Fig. 13 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device according to the first embodiment. [ Fig. 14] Fig. 14 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device according to the first embodiment. [ Fig. 15] Fig. 15 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device according to the first embodiment. [ Fig. 16] Fig. 16 is a plan view showing an example of a planar layout in a capacitor region of a semiconductor device according to a comparative example of the first embodiment. [ Fig. 17 ] A cross-sectional view showing an example of a cross-sectional structure of a capacitor region along line XVII-XVII in Fig. 16 . [ Fig. 18 ] A block diagram showing a configuration example of a semiconductor device according to the second embodiment. [ Fig. 19 ] A plan view showing an example of a planar layout of a semiconductor device according to a second embodiment. [ Fig. 20 ] A block diagram showing a configuration example of a semiconductor device as a comparative example of the second embodiment. [ Fig. 21 ] A plan view showing an example of a planar layout of a semiconductor device as a comparative example of the second embodiment. [ Fig. 22] Fig. 22 is a graph showing temporal changes of voltage and current in the semiconductor device of the second embodiment and its comparative example. [FIG. 23] A block diagram showing a configuration example of a semiconductor device according to a third embodiment. [ Fig. 24 ] A plan view showing an example of a planar layout of a semiconductor device according to a third embodiment. [ Fig. 25] Fig. 25 is a cross-sectional view showing an example of a cross-sectional structure of a capacitor region in a first modified example of the first to third embodiments. [ Fig. 26] Fig. 26 is a cross-sectional view showing an example of a cross-sectional structure of a capacitor region in a second modified example of the first to third embodiments. [FIG. 27] A block diagram showing a configuration example of a semiconductor device according to a third modified example of the first to third embodiments. [FIG. 28] A block diagram showing a configuration example of a semiconductor device according to a fourth embodiment. [ Fig. 29 ] A plan view showing an example of a planar layout of a semiconductor device according to a fourth embodiment. [ Fig. 30 ] A plan view showing an example of a planar layout of a semiconductor device according to a first modified example of the fourth embodiment. [ Fig. 31] Fig. 31 is a plan view showing an example of a planar layout of a semiconductor device according to a second modified example of the fourth embodiment. [FIG. 32] A block diagram showing a configuration example of a semiconductor device according to a third modified example of the fourth embodiment. [ Fig. 33 ] A plan view showing an example of a planar layout of a semiconductor device according to a third modified example of the fourth embodiment. [ Fig. 34 ] A plan view showing an example of a planar layout of a semiconductor device according to a fourth modification example of the fourth embodiment. [ Fig. 35 ] A plan view showing an example of a planar layout of a capacitor bank included in a semiconductor device according to a fifth modified example of the fourth embodiment.

CA:電容器區域 CA: capacitor area

TA:電晶體區域 TA: Transistor area

PW:電源線 PW: power cord

CP:電容器 CP: Capacitor

TR:電晶體 TR: Transistor

10:半導體基板 10: Semiconductor substrate

11:絕緣體層 11: Insulator layer

12:半導體層 12: Semiconductor layer

13:導電體 13: Conductor

14:絕緣體 14: Insulator

15:阱區域 15: well area

16:擴散區域 16: Diffusion area

17:導電體 17: Conductor

30:導電體 30: Conductor

CT:接觸部 CT: contact part

Claims (12)

一種半導體裝置，係具備：半導體基板，該半導體基板具有第1凹部和第2凹部，並且具有表面、與前述表面呈對向的背面、和設置於前述表面與前述背面之間的前述第1凹部的第1底部；從前述第1底部沿著前述表面設置的第1半導體層；設置於前述第1半導體層上的第1導電體；電連接於前述第1導電體的第1電源線；電連接於前述半導體基板的第2電源線；及電路，該電路設置於前述半導體基板，且連接於前述第1電源線及前述第2電源線；前述半導體基板還包含：設置於前述表面與前述背面之間的前述第2凹部的第2底部，還具備：從前述第2底部沿著前述表面設置的第3半導體層，及設置於前述第3半導體層上而且電連接於前述第1電源線的第3導電體，前述電路還具有電晶體，該電晶體包含：包含與前述第1半導體層設置於同一層的第2半導體層、和與前述第1導電體設置於同一層的第2導電體的閘極電極，前述第1導電體作為第1電容器之一方電極之功能，前述半導體基板作為前述第1電容器之另一方電極之功能，前述第3導電體作為第2電容器之一方電極之功能，前述半導體基板亦作為前述第2電容器之另一方電極之功能，前述第2電容器之電容量大於前述第1電容器之電容 量。 A semiconductor device comprising: a semiconductor substrate having a first concave portion and a second concave portion, and having a surface, a back surface opposite to the surface, and a first bottom portion of the first concave portion disposed between the surface and the back surface; a first semiconductor layer disposed along the surface from the first bottom portion; a first conductor disposed on the first semiconductor layer; a first power line electrically connected to the first conductor; a second power line electrically connected to the semiconductor substrate; The substrate is connected to the first power line and the second power line; the semiconductor substrate further includes: the second bottom of the second recess disposed between the front surface and the back surface, and also includes: a third semiconductor layer disposed along the surface from the second bottom, and a third conductor disposed on the third semiconductor layer and electrically connected to the first power line. The gate electrode of the second conductor of the first layer, the first conductor functions as one electrode of the first capacitor, the semiconductor substrate functions as the other electrode of the first capacitor, the third conductor functions as one electrode of the second capacitor, the semiconductor substrate also functions as the other electrode of the second capacitor, and the capacitance of the second capacitor is greater than that of the first capacitor quantity. 一種半導體裝置，係具備：半導體基板，該半導體基板具有第1凹部和第2凹部，並且具有表面、與前述表面呈對向的背面、和設置於前述表面與前述背面之間的前述第1凹部的第1底部；從前述第1底部沿著前述表面設置的第1半導體層；設置於前述第1半導體層上的第1導電體；電連接於前述第1導電體的第1電源線；電連接於前述半導體基板的第2電源線；及電路，該電路設置於前述半導體基板，且連接於前述第1電源線及前述第2電源線；前述半導體基板還包含：設置於前述表面與前述背面之間的前述第2凹部的第2底部，還具備：從前述第2底部沿著前述表面設置的第3半導體層，及設置於前述第3半導體層上而且電連接於前述第1電源線的第3導電體，前述電路還具備電晶體，該電晶體包含作為閘極電極之功能的第2半導體層和第2導電體；前述第1半導體層與前述第2半導體層係由同一材料形成，前述第1導電體與前述第2導電體係由同一材料形成，前述第1導電體作為第1電容器之一方電極之功能，前述半導體基板作為前述第1電容器之另一方電極之功能，前述第3導電體作為第2電容器之一方電極之功能，前述半導體基板亦作為前述第2電容器之另一方電極之功能， 前述第2電容器之電容量大於前述第1電容器之電容量。 A semiconductor device comprising: a semiconductor substrate having a first concave portion and a second concave portion, and having a surface, a back surface opposite to the surface, and a first bottom portion of the first concave portion disposed between the surface and the back surface; a first semiconductor layer disposed along the surface from the first bottom portion; a first conductor disposed on the first semiconductor layer; a first power line electrically connected to the first conductor; a second power line electrically connected to the semiconductor substrate; The substrate is connected to the first power line and the second power line; the semiconductor substrate further includes: the second bottom of the second recess disposed between the front surface and the back surface, and further includes: a third semiconductor layer disposed along the surface from the second bottom, and a third conductor disposed on the third semiconductor layer and electrically connected to the first power line; It is formed of the same material, the aforementioned first electrical conductor and the aforementioned second conductive system are formed of the same material, the aforementioned first electrical conductor functions as one electrode of the first capacitor, the aforementioned semiconductor substrate functions as the other electrode of the aforementioned first capacitor, the aforementioned third electrical conductor functions as one electrode of the second capacitor, and the aforementioned semiconductor substrate also functions as the other electrode of the aforementioned second capacitor, The capacitance of the aforementioned second capacitor is greater than that of the aforementioned first capacitor. 如請求項1或2之半導體裝置，其中前述第1電容器之一方電極包含前述第1半導體層，前述第2電容器之一方電極包含前述第3半導體層。 The semiconductor device according to claim 1 or 2, wherein one electrode of the first capacitor includes the first semiconductor layer, and one electrode of the second capacitor includes the third semiconductor layer. 一種半導體裝置，係具備：半導體基板，該半導體基板具有第1凹部和第2凹部，並且具有表面、與前述表面呈對向的背面、和設置於前述表面與前述背面之間的前述第1凹部的第1底部；從前述第1底部沿著前述表面設置的第1半導體層；設置於前述第1半導體層上的第1導電體；電連接於前述第1導電體的第1電源線；電連接於前述半導體基板的第2電源線；及電路，該電路設置於前述半導體基板，且連接於前述第1電源線及前述第2電源線；前述半導體基板還包含：設置於前述表面與前述背面之間的前述第2凹部的第2底部，還具備：從前述第2底部沿著前述表面設置的第3半導體層，及設置於前述第3半導體層上而且電連接於前述第1電源線的第3導電體，前述第1導電體作為第1電容器之一方電極之功能，前述半導體基板作為前述第1電容器之另一方電極之功能，前述第3導電體作為第2電容器之一方電極之功能，前述半導體基板亦作為前述第2電容器之另一方電極之功能， 前述第2電容器之電容量大於前述第1電容器之電容量，還包含：包含多個前述第1電容器的第1電容器組，及包含多個前述第2電容器且電容量比前述第1電容器組大的第2電容器組，前述第1電容器組及前述第2電容器組，係從前述電路沿著前述第1電源線依前述第1電容器組、前述第2電容器組之順序布置。 A semiconductor device comprising: a semiconductor substrate having a first concave portion and a second concave portion, and having a surface, a back surface opposite to the surface, and a first bottom portion of the first concave portion disposed between the surface and the back surface; a first semiconductor layer disposed along the surface from the first bottom portion; a first conductor disposed on the first semiconductor layer; a first power line electrically connected to the first conductor; a second power line electrically connected to the semiconductor substrate; The substrate is connected to the first power line and the second power line; the semiconductor substrate also includes: the second bottom of the second recess disposed between the surface and the back surface, and also has: a third semiconductor layer disposed along the surface from the second bottom, and a third conductor disposed on the third semiconductor layer and electrically connected to the first power line, the first conductor functions as one electrode of the first capacitor, the semiconductor substrate functions as the other electrode of the first capacitor, and the third conductor functions as a second capacitor The function of one electrode, the aforementioned semiconductor substrate also serves as the function of the other electrode of the aforementioned second capacitor, The capacitance of the aforementioned second capacitor is greater than that of the aforementioned first capacitor, and further includes: a first capacitor bank comprising a plurality of the aforementioned first capacitors, and a second capacitor bank comprising a plurality of the aforementioned second capacitors and having a capacitance greater than that of the aforementioned first capacitor bank. 一種半導體裝置，係具備：半導體基板，該半導體基板具有第1凹部和第2凹部，並且具有表面、與前述表面呈對向的背面、和設置於前述表面與前述背面之間的前述第1凹部的第1底部；從前述第1底部沿著前述表面設置的第1半導體層；設置於前述第1半導體層上的第1導電體；在前述表面之上且與前述第1半導體層分開設置的第2半導體層；設置於前述第2半導體層上的第2導電體；電連接於前述第1導電體的第1電源線；電連接於前述半導體基板的第2電源線；及電路，該電路設置於前述半導體基板，且連接於前述第1電源線及前述第2電源線；前述半導體基板還包含：設置於前述表面與前述背面之間的前述第2凹部的第2底部，還具備：從前述第2底部沿著前述表面設置的第3半導體層，及設置於前述第3半導 體層上而且電連接於前述第1電源線的第3導電體，前述第2導電體電連接於前述第1電源線，前述第1導電體作為第1電容器之一方電極之功能，前述半導體基板作為前述第1電容器之另一方電極之功能，前述第3導電體作為第2電容器之一方電極之功能，前述半導體基板亦作為前述第2電容器之另一方電極之功能，前述第2電容器之電容量大於前述第1電容器之電容量，前述第1導電體作為溝槽式電容器之一方電極之功能，前述第2導電體作為平面型電容器之一方電極之功能，前述半導體基板作為前述溝槽式電容器之另一方電極和前述平面型電容器之另一方電極之功能，還包含：多個電容器組，且每個電容器組包含多個前述溝槽式電容器及/或前述平面型電容器，前述多個電容器組之中電容量最小的電容器組最接近前述電路布置。 A semiconductor device comprising: a semiconductor substrate having a first recess and a second recess, and having a surface, a back surface opposite to the surface, and a first bottom of the first recess provided between the surface and the back surface; a first semiconductor layer provided along the surface from the first bottom; a first conductor provided on the first semiconductor layer; a second semiconductor layer provided on the surface and separately from the first semiconductor layer; a second conductor provided on the second semiconductor layer; The first power line on the first electrical conductor; the second power line electrically connected to the semiconductor substrate; and the circuit, which is provided on the semiconductor substrate and connected to the first power line and the second power line; The third conductor on the body layer and electrically connected to the first power line, the second conductor is electrically connected to the first power line, the first conductor functions as one electrode of the first capacitor, the semiconductor substrate functions as the other electrode of the first capacitor, the third conductor functions as one electrode of the second capacitor, the semiconductor substrate also functions as the other electrode of the second capacitor, the capacitance of the second capacitor is greater than that of the first capacitor, and the first conductor functions as one of the trench capacitors The function of the electrodes, the function of the aforementioned second conductor as one electrode of the planar capacitor, the function of the aforementioned semiconductor substrate as the other electrode of the aforementioned trench capacitor and the function of the other electrode of the aforementioned planar capacitor, also includes: a plurality of capacitor banks, and each capacitor bank includes a plurality of the aforementioned trench capacitors and/or the aforementioned planar capacitors, and among the aforementioned plurality of capacitor banks, the capacitor bank with the smallest capacitance is closest to the aforementioned circuit arrangement. 如請求項5之半導體裝置，其中前述電容量最小的電容器組，係包含前述平面型電容器且不包含前述溝槽式電容器。 The semiconductor device according to claim 5, wherein the capacitor bank with the smallest capacitance includes the planar capacitor and does not include the trench capacitor. 如請求項5之半導體裝置，其中前述多個電容器組還包含：第1電容器組，及電容量 比前述第1電容器組大的第2電容器組，前述第1電容器組及前述第2電容器組，係從前述電路沿著前述第1電源線依前述第1電容器組、前述第2電容器組之順序布置。 Such as the semiconductor device of claim 5, wherein the plurality of capacitor banks further include: a first capacitor bank, and a capacitance The second capacitor bank larger than the first capacitor bank, the first capacitor bank and the second capacitor bank are arranged in the order of the first capacitor bank and the second capacitor bank along the first power supply line from the aforementioned circuit. 如請求項7之半導體裝置，其中前述多個電容器組還包含：電容量比前述第2電容器組大的第3電容器組，前述第3電容器組，係從前述電路沿著前述第1電源線依前述第1電容器組、前述第2電容器組、前述第3電容器組之順序布置。 The semiconductor device according to claim 7, wherein the plurality of capacitor banks further include: a third capacitor bank having a larger capacitance than the second capacitor bank, and the third capacitor bank is arranged in the order of the first capacitor bank, the second capacitor bank, and the third capacitor bank from the circuit along the first power line. 如請求項8之半導體裝置，其中前述第2電容器組之電容量係前述第1電容器組之電容量之10倍以上，前述第3電容器組之電容量係前述第2電容器組之電容量之10倍以上。 The semiconductor device according to claim 8, wherein the capacitance of the second capacitor bank is more than 10 times the capacitance of the first capacitor bank, and the capacitance of the third capacitor bank is more than 10 times the capacitance of the second capacitor bank. 一種半導體裝置，係具備：半導體基板，該半導體基板具有第1凹部和第2凹部，並且具有表面、與前述表面呈對向的背面、和設置於前述表面與前述背面之間的前述第1凹部的第1底部；從前述第1底部沿著前述表面設置的第1半導體層；設置於前述第1半導體層上的第1導電體；在前述表面之上且與前述第1半導體層分開設置的第2半導體層；設置於前述第2半導體層上的第2導電體； 電連接於前述第1導電體的第1電源線；電連接於前述半導體基板的第2電源線；及電路，該電路設置於前述半導體基板，且連接於前述第1電源線及前述第2電源線；前述半導體基板還包含：設置於前述表面與前述背面之間的前述第2凹部的第2底部，還具備：從前述第2底部沿著前述表面設置的第3半導體層，及設置於前述第3半導體層上而且電連接於前述第1電源線的第3導電體，前述第2導電體電連接於前述第1電源線，前述第1導電體作為第1電容器之一方電極之功能，前述半導體基板作為前述第1電容器之另一方電極之功能，前述第3導電體作為第2電容器之一方電極之功能，前述半導體基板亦作為前述第2電容器之另一方電極之功能，前述第2電容器之電容量大於前述第1電容器之電容量，前述第1導電體作為溝槽式電容器之一方電極之功能，前述第2導電體作為平面型電容器之一方電極之功能，前述半導體基板作為前述溝槽式電容器之另一方電極和前述平面型電容器之另一方電極之功能，還包含：連接於前述第1電源線的焊墊；及 第1至第5電容器組，其分別包含多個前述溝槽式電容器及/或前述平面型電容器；前述電路包含電連接於前述第1電源線的第1電源端和第2電源端，前述第1電源線包含：從前述焊墊直至分歧部的第1部分，從前述分歧部直至前述第1電源端的第2部分，和從前述分歧部直至前述第2電源端的第3部分，前述第1電容器組和前述第2電容器組布置於前述第2部分，前述第1電容器組布置為比前述第2電容器組更靠近前述第1電源端，前述第3電容器組和前述第4電容器組布置於前述第3部分，前述第3電容器組布置為比前述第4電容器組更靠近前述第2電源端，前述第5電容器組布置於前述第1部分，前述第2電容器組之電容量大於前述第1電容器組之電容量，前述第4電容器組之電容量大於前述第3電容器組之電容量，前述第5電容器組之電容量大於前述第2電容器組和前述第4電容器組之任一之電容量。 A semiconductor device comprising: a semiconductor substrate having a first recess and a second recess, and having a surface, a back surface opposite to the surface, and a first bottom of the first recess provided between the surface and the back surface; a first semiconductor layer provided along the surface from the first bottom; a first conductor provided on the first semiconductor layer; a second semiconductor layer provided on the surface and separately from the first semiconductor layer; a second conductor provided on the second semiconductor layer; a first power line electrically connected to the first electrical conductor; a second power line electrically connected to the semiconductor substrate; and a circuit provided on the semiconductor substrate and connected to the first power line and the second power line; the semiconductor substrate further includes: a second bottom of the second recess disposed between the surface and the back surface, a third semiconductor layer disposed along the surface from the second bottom, and a third conductor disposed on the third semiconductor layer and electrically connected to the first power line. 2. The conductor is electrically connected to the first power line. The first conductor functions as one electrode of the first capacitor. The semiconductor substrate functions as the other electrode of the first capacitor. The third conductor functions as one electrode of the second capacitor. The semiconductor substrate also functions as the other electrode of the second capacitor. The capacitance of the second capacitor is greater than that of the first capacitor. As the function of the other electrode of the trench capacitor and the other electrode of the planar capacitor, it also includes: a pad connected to the first power line; and The 1st to 5th capacitor groups, which respectively include a plurality of the aforementioned trench capacitors and/or the aforementioned planar capacitors; the aforementioned circuit includes a first power supply terminal and a second power supply terminal electrically connected to the aforementioned first power supply line, and the aforementioned first power supply line includes: a first part from the aforementioned welding pad to the branch part, a second part from the aforementioned branch part to the aforementioned first power supply terminal, and a third part from the aforementioned branch part to the aforementioned second power supply terminal, the aforementioned first capacitor bank and the aforementioned second capacitor bank are arranged in the aforementioned second part, and the aforementioned first capacitor bank is arranged as follows: The third capacitor bank and the fourth capacitor bank are arranged in the third part, the third capacitor bank is arranged closer to the second power supply terminal than the fourth capacitor bank, the fifth capacitor bank is arranged in the first part, the capacitance of the second capacitor bank is greater than that of the first capacitor bank, the capacitance of the fourth capacitor bank is greater than that of the third capacitor bank, and the capacitance of the fifth capacitor bank is greater than either of the second capacitor bank and the fourth capacitor bank. The capacitance. 一種半導體裝置，係具備：半導體基板，該半導體基板具有第1凹部和第2凹部，並且具有表面、與前述表面呈對向的背面、和設置於前述表面與前述背面之間的前述第1凹部的第1底部； 從前述第1底部沿著前述表面設置的第1半導體層；設置於前述第1半導體層上的第1導電體；在前述表面之上且與前述第1半導體層分開設置的第2半導體層；設置於前述第2半導體層上的第2導電體；電連接於前述第1導電體的第1電源線；電連接於前述半導體基板的第2電源線；及電路，該電路設置於前述半導體基板，且連接於前述第1電源線及前述第2電源線；前述半導體基板還包含：設置於前述表面與前述背面之間的前述第2凹部的第2底部，還具備：從前述第2底部沿著前述表面設置的第3半導體層，及設置於前述第3半導體層上而且電連接於前述第1電源線的第3導電體，前述第2導電體電連接於前述第1電源線，前述第1導電體作為第1電容器之一方電極之功能，前述半導體基板作為前述第1電容器之另一方電極之功能，前述第3導電體作為第2電容器之一方電極之功能，前述半導體基板亦作為前述第2電容器之另一方電極之功能，前述第2電容器之電容量大於前述第1電容器之電容量，前述第1導電體作為溝槽式電容器之一方電極之功能，前述第2導電體作為平面型電容器之一方電極之功 能，前述半導體基板作為前述溝槽式電容器之另一方電極和前述平面型電容器之另一方電極之功能，還包含：多個電容器組，每個電容器組包含多個前述溝槽式電容器及/或前述平面型電容器，前述電路設置於前述半導體基板上之第1區域，前述多個電容器組之中電容量最小的電容器組布置於前述第1區域內。 A semiconductor device comprising: a semiconductor substrate having a first recess and a second recess, and having a surface, a back surface opposite to the surface, and a first bottom of the first recess provided between the surface and the back surface; The first semiconductor layer arranged along the aforementioned surface from the aforementioned first bottom; the first conductor arranged on the aforementioned first semiconductor layer; the second semiconductor layer arranged on the aforementioned surface and separated from the aforementioned first semiconductor layer; the second conductor arranged on the aforementioned second semiconductor layer; the first power line electrically connected to the aforementioned first electrical conductor; The second bottom of the aforementioned second concave portion between the aforementioned surface and the aforementioned back surface further includes: a third semiconductor layer disposed along the aforementioned surface from the aforementioned second bottom, and a third electrical conductor disposed on the aforementioned third semiconductor layer and electrically connected to the aforementioned first power supply line, the aforementioned second electrical conductor is electrically connected to the aforementioned first power supply line, the aforementioned first electrical conductor functions as one electrode of the first capacitor, the aforementioned semiconductor substrate functions as the other electrode of the aforementioned first capacitor, the aforementioned third electrical conductor functions as one electrode of the second capacitor, and the aforementioned semiconductor substrate also functions as The function of the other electrode of the second capacitor, the capacitance of the second capacitor is greater than the capacitance of the first capacitor, the function of the first conductor as one electrode of the trench capacitor, and the function of the second conductor as one electrode of the planar capacitor Able, the aforementioned semiconductor substrate functions as the other electrode of the aforementioned trench capacitor and the other electrode of the aforementioned planar capacitor, and also includes: a plurality of capacitor banks, each capacitor bank comprising a plurality of the aforementioned trench capacitors and/or the aforementioned planar capacitors, the aforementioned circuit is arranged on the first area on the aforementioned semiconductor substrate, and the capacitor bank with the smallest capacitance among the aforementioned plurality of capacitor banks is arranged in the aforementioned first area. 一種半導體裝置，係具備：半導體基板，該半導體基板具有第1凹部和第2凹部，並且具有表面、與前述表面呈對向的背面、和設置於前述表面與前述背面之間的前述第1凹部的第1底部；從前述第1底部沿著前述表面設置的第1半導體層；設置於前述第1半導體層上的第1導電體；電連接於前述第1導電體的第1電源線；電連接於前述半導體基板的第2電源線；及電路，該電路設置於前述半導體基板，且連接於前述第1電源線及前述第2電源線；前述半導體基板還包含：設置於前述表面與前述背面之間的前述第2凹部的第2底部，還具備：從前述第2底部沿著前述表面設置的第3半導體層，及設置於前述第3半導體層上而且電連接於前述第1電源線的第3導電體，前述第1導電體作為第1電容器之一方電極之功能，前述半導體基板作為前述第1電容器之另一方電極之功能， 前述第3導電體作為第2電容器之一方電極之功能，前述半導體基板亦作為前述第2電容器之另一方電極之功能，前述第2電容器之電容量大於前述第1電容器之電容量，還包含：包含多個前述第1電容器的第1電容器組，以及包含多個前述第1電容器和多個前述第2電容器的第2電容器組，前述第2電容器組之電容量大於前述第1電容器組之電容量，前述第1電容器組和前述第2電容器組，係從前述電路沿著前述第1電源線依前述第1電容器組、前述第2電容器組之順序布置。 A semiconductor device comprising: a semiconductor substrate having a first concave portion and a second concave portion, and having a surface, a back surface opposite to the surface, and a first bottom portion of the first concave portion disposed between the surface and the back surface; a first semiconductor layer disposed along the surface from the first bottom portion; a first conductor disposed on the first semiconductor layer; a first power line electrically connected to the first conductor; a second power line electrically connected to the semiconductor substrate; The substrate is connected to the aforementioned first power line and the aforementioned second power line; the aforementioned semiconductor substrate also includes: the second bottom of the aforementioned second concave portion disposed between the aforementioned surface and the aforementioned back surface, and also includes: a third semiconductor layer disposed along the aforementioned surface from the aforementioned second bottom, and a third conductor disposed on the aforementioned third semiconductor layer and electrically connected to the aforementioned first power line, the aforementioned first electrical conductor functions as one electrode of the first capacitor, and the aforementioned semiconductor substrate functions as the other electrode of the aforementioned first capacitor, The aforementioned third conductor functions as one electrode of the second capacitor, and the aforementioned semiconductor substrate also functions as the other electrode of the aforementioned second capacitor. The capacitance of the aforementioned second capacitor is greater than that of the aforementioned first capacitor. It also includes: a first capacitor bank comprising a plurality of the aforementioned first capacitors, and a second capacitor bank comprising a plurality of the aforementioned first capacitors and a plurality of the aforementioned second capacitors. The capacity of the aforementioned second capacitor bank is greater than that of the aforementioned first capacitor bank. Arrange according to the order of the aforementioned first capacitor bank and the aforementioned second capacitor bank.
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JP2007012694A (en) * 2005-06-28 2007-01-18 Toshiba Corp Semiconductor integrated circuit device of standard cell system
US20120091559A1 (en) * 2009-11-13 2012-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor and Method for Making Same
TWI406391B (en) * 2005-06-30 2013-08-21 Globalfoundries Us Inc A semiconductor device including a vertical decoupling capacitor

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JP2007012694A (en) * 2005-06-28 2007-01-18 Toshiba Corp Semiconductor integrated circuit device of standard cell system
TWI406391B (en) * 2005-06-30 2013-08-21 Globalfoundries Us Inc A semiconductor device including a vertical decoupling capacitor
US20120091559A1 (en) * 2009-11-13 2012-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor and Method for Making Same

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