TWI807991B

TWI807991B - Semiconductor device and method for fabricating the same

Info

Publication number: TWI807991B
Application number: TW111134066A
Authority: TW
Inventors: 廖廷豐
Original assignee: 旺宏電子股份有限公司
Priority date: 2022-09-08
Filing date: 2022-09-08
Publication date: 2023-07-01

Abstract

A semiconductor device includes a ground layer, a stacked structure, and a conductive pillar. The ground layer includes a lower semiconductor material layer, a refilled semiconductor material layer, and an upper semiconductor material layer. The stacked structure is disposed on the ground layer and includes insulating layers and conductive layers alternately stacked along a first direction. The conductive pillar penetrates the stacked structure and extends into the ground layer along the first direction. The conductive pillar includes a bottom body portion, a middle body portion, and a plug connected to each other. In a second direction different from the first direction, a portion of the bottom body portion overlapping the upper semiconductor material layer has a first size, a portion of the middle body portion overlapping a bottommost insulating layer of the stacked structure has a second size, and the first size is larger than the second size.

Description

半導體裝置及其製作方法 Semiconductor device and manufacturing method thereof

本發明是有關於一種半導體裝置及其製作方法，且特別是有關於一種三維半導體裝置及其製作方法。 The present invention relates to a semiconductor device and its manufacturing method, and in particular to a three-dimensional semiconductor device and its manufacturing method.

近年來，半導體裝置的尺寸必須逐漸縮小。隨著半導體裝置的尺寸縮小，在製作半導體裝置的過程更容易發生製程上的失誤，製程上的失誤會影響半導體裝置的電特性，嚴重的話甚至導致晶片失效。因此，目前仍亟需改善微型化半導體裝置在製程上的失誤。 In recent years, semiconductor devices have to be gradually reduced in size. As the size of the semiconductor device shrinks, manufacturing errors are more likely to occur in the process of manufacturing the semiconductor device. The manufacturing error will affect the electrical characteristics of the semiconductor device, and even cause the chip to fail. Therefore, there is still an urgent need to improve the manufacturing process errors of miniaturized semiconductor devices.

本發明係有關於一種半導體裝置及其製作方法。由於本案半導體裝置的製作方法包括形成導電材料層，導電材料層可作為蝕刻停止層，並不會有過蝕刻的問題產生。 The invention relates to a semiconductor device and a manufacturing method thereof. Since the manufacturing method of the semiconductor device in this case includes forming a conductive material layer, the conductive material layer can be used as an etching stop layer, and there is no problem of over-etching.

根據本發明之一實施例，提出一種半導體裝置。半導體裝置包括一接地層、一堆疊結構以及至少一導電柱。接地層包括一下部半導體材料層、設置於下部半導體材料層上的一回填半導體材料層及設置於回填半導體材料層上的一上部導電層。堆疊結構設置於接地層上，且堆疊結構包括沿著一第一方向交替堆疊的複數個絕緣層及複數個導電層。導電柱沿著第一方向貫穿堆疊結構並延伸至接地層中，其中導電柱包括彼此連接的底部本體部、中間本體部、及插塞，其中底部本體部對應於接地層，中間本體部對應於堆疊結構的中間及底部部分。其中，在不同於第一方向的一第二方向上，底部本體部之重疊於上部導電層的部分具有一第一尺寸，中間本體部重疊於堆疊結構之最底層絕緣層的部分具有一第二尺寸，第一尺寸大於第二尺寸。 According to an embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes a ground layer, a stack structure and at least one conductive column. The ground layer includes a lower semiconductor material layer, a backfill semiconductor material layer disposed on the lower semiconductor material layer, and an upper conductive layer disposed on the backfill semiconductor material layer. The stack structure is disposed on the ground layer, and the stack structure includes a plurality of insulating layers and a plurality of conductive layers alternately stacked along a first direction. The conductive column penetrates the stack structure along the first direction and extends to the ground layer , wherein the conductive post includes a bottom body part, a middle body part, and a plug connected to each other, wherein the bottom body part corresponds to the ground layer, and the middle body part corresponds to the middle and bottom parts of the stacked structure. Wherein, in a second direction different from the first direction, the portion of the bottom body portion overlapping the upper conductive layer has a first size, the portion of the middle body portion overlapping the bottommost insulating layer of the stack structure has a second size, and the first size is greater than the second size.

根據本發明之另一實施例，提出一種半導體裝置。半導體裝置包括一接地層以及一堆疊結構。接地層包括一下部半導體材料層、設置於下部半導體材料層上的一回填半導體材料層及設置於回填半導體材料層上的一上部導電層。堆疊結構設置於接地層上，且堆疊結構包括沿著一第一方向交替堆疊的複數個絕緣層及複數個導電層。其中，上部導電層包括一導電材料層，且導電材料層的材料包括金屬材料。 According to another embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes a ground layer and a stack structure. The ground layer includes a lower semiconductor material layer, a backfill semiconductor material layer disposed on the lower semiconductor material layer, and an upper conductive layer disposed on the backfill semiconductor material layer. The stack structure is disposed on the ground layer, and the stack structure includes a plurality of insulating layers and a plurality of conductive layers alternately stacked along a first direction. Wherein, the upper conductive layer includes a conductive material layer, and the material of the conductive material layer includes metal material.

根據本發明之又一實施例，提出一種半導體裝置的製作方法。方法包括下列步驟：提供一多層結構於一電路板上，多層結構包括沿著一第一方向由下往上依序堆疊於電路板上的一下部半導體材料層、一第一層間絕緣層、一中間半導體材料層、一第二層間絕緣層及一上部導電層；在上部導電層中形成一導電材料層，其中導電材料層包括金屬材料；在上部導電層上形成一層疊體，層疊體包括交替堆疊的複數個絕緣層及複數個犧牲層；以及在層疊體中形成至少一溝槽，其中溝槽沿著第一方向向下延伸，貫穿層疊體並停止於導電材料層。 According to yet another embodiment of the present invention, a method for fabricating a semiconductor device is provided. The method comprises the following steps: providing a multilayer structure on a circuit board, the multilayer structure comprising a lower semiconductor material layer, a first interlayer insulating layer, an intermediate semiconductor material layer, a second interlayer insulating layer and an upper conductive layer stacked on the circuit board from bottom to top along a first direction; forming a conductive material layer in the upper conductive layer, wherein the conductive material layer includes a metal material; At least one trench is formed in the center, wherein the trench extends downward along the first direction, penetrates the laminated body and stops at the conductive material layer.

為了對本發明之上述及其他方面有更佳的瞭解，下文特舉實施例，並配合所附圖式詳細說明如下： In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given in detail with the accompanying drawings as follows:

10,30:半導體裝置 10,30: Semiconductor device

110:電路板 110: circuit board

120,320:接地層 120,320: ground plane

120’,320’:多層結構 120', 320': multi-layer structure

121:下部半導體材料層 121: lower semiconductor material layer

123:第一層間絕緣層 123: The first interlayer insulating layer

124:回填半導體材料層 124: Backfilling the semiconductor material layer

125:中間半導體材料層 125: intermediate semiconductor material layer

127:第二層間絕緣層 127: The second interlayer insulating layer

129,329:上部導電層 129,329: upper conductive layer

130:堆疊結構 130:Stack structure

130’:層疊體 130': laminated body

131:絕緣層 131: insulation layer

133:犧牲層 133: sacrificial layer

134:導電層 134: conductive layer

134r:凹室 134r: alcove

140:垂直開口 140: vertical opening

141:記憶膜 141: memory film

141E:頂部移除部分 141E: Top removal part

143:通道膜 143: channel membrane

145:絕緣柱 145: Insulation column

147:接墊 147: Pad

149:通道結構 149: Channel structure

149b:下通道端部 149b: end of lower channel

151,153,155:絕緣膜 151, 153, 155: insulating film

157:間隔結構 157:Interval structure

161,361:保護層 161,361: protective layer

163,363:隔離材料層 163,363: layers of isolation material

171,371:本體阻障層 171,371: bulk barrier layer

173,373:下部導電層 173,373: lower conductive layer

175,375:上部阻障層 175,375: upper barrier layer

177,377:上部導體 177,377: Upper conductor

179,379:導電柱 179,379: conductive pillar

179A,379A:底部本體部 179A, 379A: Bottom body part

179B,379B:中間本體部 179B, 379B: middle body part

179C,379C:插塞 179C, 379C: plug

210:槽口 210: notch

220,420:導電材料層 220,420: layer of conductive material

230,430:溝槽 230,430: Groove

250:缺口 250: Gap

270,470:狹縫 270,470: Slits

272,472:延伸開口 272,472: Extended opening

274:空間 274: space

411:孔洞 411: hole

422:絕緣材料層 422: insulating material layer

F1:第一表面 F1: first surface

F2:第二表面 F2: second surface

H1,H2:高度 H1, H2: Height

S1:第一尺寸 S1: first size

S2:第二尺寸 S2: second size

S3:第三尺寸 S3: third size

S4,S5:最大尺寸 S4, S5: Maximum size

W1,W2:寬度 W1, W2: width

α:夾角 α: included angle

第1至16圖繪示依照本發明一實施例的半導體裝置的製作方法的剖面圖；及第17至32圖繪示依照本發明另一實施例的半導體裝置的製作方法的剖面圖。 1 to 16 are cross-sectional views of a manufacturing method of a semiconductor device according to an embodiment of the present invention; and FIGS. 17 to 32 are cross-sectional views of a manufacturing method of a semiconductor device according to another embodiment of the present invention.

以下係提出相關實施例，配合圖式以詳細說明本發明所提出之半導體結構及其製造方法。然而，本發明並不以此為限。實施例中之敘述，例如細部結構、製造方法之步驟和材料應用等，僅為舉例說明之用，本發明欲保護之範圍並非僅限於所述態樣。 The relevant embodiments are provided below, and the semiconductor structure and its manufacturing method proposed by the present invention are described in detail in conjunction with the drawings. However, the present invention is not limited thereto. The descriptions in the embodiments, such as the detailed structure, steps of the manufacturing method and application of materials, etc., are for illustration purposes only, and the protection scope of the present invention is not limited to the above-mentioned aspects.

同時，須注意的是，本發明並非顯示出所有可能的實施例。相關技術領域者當可在不脫離本發明之精神和範圍之前提下，對實施例之結構和製造方法加以變化與修飾，以符合實際應用所需。因此，未於本發明提出的其他實施態樣也可能可以應用。再者，圖式係簡化以利清楚說明實施例之內容，圖式上的尺寸比例並非按照實際產品等比例繪製。圖式中相同或相似的元件符號用以代表相同或相似的元件。可以理解的是，一個實施例的元件和特徵可以有益地結合於另一個實施例中，而無需進一步敘述。 At the same time, it should be noted that not all possible embodiments of the present invention are shown. Those skilled in the art may change and modify the structures and manufacturing methods of the embodiments without departing from the spirit and scope of the present invention, so as to meet the needs of practical applications. Therefore, other implementation aspects not proposed in the present invention may also be applicable. Furthermore, the drawings are simplified to clearly illustrate the content of the embodiments, and the size ratios in the drawings are not drawn according to the proportion of the actual product. In the drawings, the same or similar element symbols are used to represent the same or similar elements. It is contemplated that elements and features of one embodiment may be beneficially incorporated in another embodiment without further recitation.

再者，說明書與申請專利範圍中所使用的序數例如「第一」、「第二」、「第三」等用詞是為了修飾元件，其本身並不意含及代表該元件有任何之前的序數，也不代表某一元件與另一元件的順序、或是製造方法上的順序，該些序數的使用，僅是用來使具有某命名的一元件得以和另一具有相同命名的元件能作出清楚區分。 Furthermore, ordinal numbers such as "first", "second", and "third" used in the specification and claims are intended to modify elements and do not imply And it means that the element has any previous ordinal number, nor does it represent the order of one element with another element, or the order in the manufacturing method. The use of these ordinal numbers is only used to clearly distinguish an element with a certain name from another element with the same name.

依照本發明之實施例的半導體裝置可應用於多種不同的三維(three-dimensional,3D)堆疊半導體結構。例如，實施例可應用於三維垂直通道(vertical channel,VC)反及閘(NAND)記憶裝置、或其它種類記憶裝置。 The semiconductor device according to the embodiments of the present invention can be applied to various three-dimensional (3D) stacked semiconductor structures. For example, the embodiments can be applied to three-dimensional vertical channel (VC) NAND memory devices, or other types of memory devices.

第1至16圖繪示依照本發明一實施例的半導體裝置10的製作方法的剖面圖。 1 to 16 are cross-sectional views illustrating a method for fabricating a semiconductor device 10 according to an embodiment of the present invention.

請參照第1圖。提供多層結構120’於電路板110上。多層結構120’包括沿著Z方向(例如第一方向)由下往上依序堆疊於電路板110上的下部半導體材料層121、第一層間絕緣層123、中間半導體材料層125、第二層間絕緣層127及上部導電層129。 Please refer to Figure 1. A multilayer structure 120' is provided on the circuit board 110. The multilayer structure 120' includes a lower semiconductor material layer 121, a first interlayer insulating layer 123, an intermediate semiconductor material layer 125, a second interlayer insulating layer 127 and an upper conductive layer 129 stacked on the circuit board 110 from bottom to top along the Z direction (for example, the first direction).

在一實施例中，下部半導體材料層121、中間半導體材料層125與上部導電層129可包含摻雜的(doped)或未摻雜的(undoped)半導體材料，例如摻雜的或未摻雜的多晶矽(polysilicon)。第一層間絕緣層123與第二層間絕緣層127可包含絕緣材料，絕緣材料包括氧化物，例如氧化矽(silicon oxide)。在一實施例中，可藉由依序沉積下部半導體材料層121、第一層間絕緣層123、中間半導體材料層125、第二層間絕緣層127與上部導電層129以在電路板110上形成多層結構120’，例如是藉由化學氣相沉積處理(chemical vapor deposition,CVD)。 In one embodiment, the lower semiconductor material layer 121 , the middle semiconductor material layer 125 and the upper conductive layer 129 may include doped or undoped semiconductor materials, such as doped or undoped polysilicon. The first interlayer insulating layer 123 and the second interlayer insulating layer 127 may include insulating materials, and the insulating materials include oxides, such as silicon oxide. In one embodiment, the multilayer structure 120' can be formed on the circuit board 110 by sequentially depositing the lower semiconductor material layer 121, the first interlayer insulating layer 123, the middle semiconductor material layer 125, the second interlayer insulating layer 127, and the upper conductive layer 129, such as by chemical vapor deposition (CVD).

請參照第2圖。在形成多層結構120’之後，移除一部分的上部導電層129以形成暴露第二層間絕緣層127的槽口(groove)210。例如，可藉由微影製程於預定位置蝕刻一部分的上部導電層129。所述預定位置在Z方向上重疊於欲形成溝槽230(trench)(繪示於第5圖中)的位置，且槽口210在Y方向(例如第二方向)上的寬度可大於溝槽230(繪示於第5圖中)在Y方向上的寬度，其中溝槽230(繪示於第5圖中)係用於形成導電柱179(繪示於第16圖中)。槽口210可沿著X方向(例如第三方向)延伸。 Please refer to Figure 2. After forming the multi-layer structure 120', a portion of the upper conductive layer 129 is removed to form a groove 210 exposing the second interlayer insulating layer 127. Referring to FIG. For example, a part of the upper conductive layer 129 may be etched at a predetermined position by a photolithography process. The predetermined position overlaps the position where the trench 230 (shown in FIG. 5 ) is to be formed in the Z direction, and the width of the notch 210 in the Y direction (eg, the second direction) may be greater than the width of the trench 230 (shown in FIG. 5 ), wherein the trench 230 (shown in FIG. 5 ) is used to form the conductive pillar 179 (shown in FIG. 16 ). The notch 210 may extend along the X direction (eg, the third direction).

請參照第3圖。在槽口210中填入導電材料，以形成位於槽口210中的導電材料層220。換言之，可在上部導電層129中形成導電材料層220。依據一實施例，可將導電材料沉積於槽口210中，此後進行化學機械平坦化(Chemical-Mechanical Planarization,CMP)，使得導電材料層220的頂面與上部導電層129的頂面可共平面。在一些實施例中，導電材料層220的材料包括金屬材料，例如是鎢。 Please refer to Figure 3. A conductive material is filled in the notch 210 to form a conductive material layer 220 in the notch 210 . In other words, the conductive material layer 220 may be formed in the upper conductive layer 129 . According to an embodiment, a conductive material can be deposited in the slot 210 , followed by chemical-mechanical planarization (CMP), so that the top surface of the conductive material layer 220 and the top surface of the upper conductive layer 129 can be coplanar. In some embodiments, the material of the conductive material layer 220 includes a metal material, such as tungsten.

請參照第4圖。在上部導電層129及導電材料層220上形成一層疊體130’，此後形成沿著Z方向穿過層疊體130’及部分多層結構120’的複數個通道結構149。層疊體130’包括交替堆疊的複數個絕緣層131及犧牲層133，其中層疊體130’的最底層及最頂層可為絕緣層131。通道結構149的下通道端部149b可位於下部半導體材料層121中。各個通道結構149可包含記憶膜141、通道膜143、絕緣柱145與接墊147。 Please refer to Figure 4. A laminated body 130' is formed on the upper conductive layer 129 and the conductive material layer 220, and then a plurality of channel structures 149 passing through the laminated body 130' and part of the multilayered structure 120' along the Z direction are formed. The stacked body 130' includes a plurality of insulating layers 131 and sacrificial layers 133 stacked alternately, wherein the bottommost and topmost layers of the stacked body 130' can be insulating layers 131. The lower channel end 149b of the channel structure 149 may be located in the lower semiconductor material layer 121 . Each channel structure 149 may include a memory film 141 , a channel film 143 , insulating columns 145 and pads 147 .

記憶膜141可包含記憶體技術領域中已知的多層結構(multilayer structure)，例如ONO(氧化物-氮化物-氧化物)結構、 ONONO(氧化物-氮化物-氧化物-氮化物-氧化物)結構、ONONONO(氧化物-氮化物-氧化物-氮化物-氧化物-氮化物-氧化物)結構、SONOS(矽-氧化矽-氮化矽-氧化矽-矽)結構、BE-SONOS(能隙工程矽-氧化矽-氮化矽-氧化矽-矽)結構、TANOS(氮化鉭-氧化鋁-氮化矽-氧化矽-矽)結構、MA BE-SONOS(金屬-高介電常數材料能帶隙矽-氧化矽-氮化矽-氧化矽-矽)結構及其組合。 The memory film 141 may comprise a multilayer structure (multilayer structure) known in the field of memory technology, such as an ONO (Oxide-Nitride-Oxide) structure, ONONO (oxide-nitride-oxide-nitride-oxide) structure, ONONONO (oxide-nitride-oxide-nitride-oxide-nitride-oxide) structure, SONOS (silicon-oxide-silicon nitride-silicon oxide-silicon) structure, BE-SONOS (energy gap engineering silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, TANOS (tantalum nitride-aluminum oxide-silicon nitride-silicon oxide-silicon) structure, MA BE-SONOS ( Metal-high dielectric constant material energy bandgap silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure and its combination.

通道膜143可包含摻雜的或未摻雜的半導體材料，例如摻雜的多晶矽或未摻雜的多晶矽。絕緣柱145可包含介電材料，介電材料包含氧化物(例如氧化矽)。接墊147可包含摻雜的或未摻雜的半導體材料，例如摻雜的多晶矽或未摻雜的多晶矽。 The channel film 143 may include doped or undoped semiconductor material, such as doped polysilicon or undoped polysilicon. The insulating pillar 145 may include a dielectric material including an oxide (eg, silicon oxide). The pad 147 may include doped or undoped semiconductor material, such as doped polysilicon or undoped polysilicon.

根據一些實施例，可在上部導電層129及導電材料層220上交替沉積複數個絕緣層131及複數個犧牲層133，以形成層疊體130’。此後，藉由圖案化(pattern)製程以在層疊體130’中形成複數個垂直開口140。例如，可藉由微影製程(photolithography process)以圖案化層疊體130’。垂直開口140可沿著Z方向貫穿過層疊體130’、上部導電層129、第二層間絕緣層127、中間半導體材料層125與第一層間絕緣層123，並停止於下部半導體材料層121，亦即是暴露下部半導體材料層121。接著，在各個垂直開口140中依序沉積記憶膜141、通道膜143、絕緣柱145與接墊147，以形成通道結構149。絕緣層131可包括氧化物，例如是氧化矽。犧牲層133可包括氮化物，例如是氮化矽。 According to some embodiments, a plurality of insulating layers 131 and a plurality of sacrificial layers 133 may be alternately deposited on the upper conductive layer 129 and the conductive material layer 220 to form a stack 130'. Thereafter, a plurality of vertical openings 140 are formed in the stacked body 130' through a patterning process. For example, the laminated body 130' can be patterned by a photolithography process. The vertical opening 140 can pass through the stack 130', the upper conductive layer 129, the second interlayer insulating layer 127, the intermediate semiconductor material layer 125, and the first interlayer insulating layer 123 along the Z direction, and stop at the lower semiconductor material layer 121, that is, expose the lower semiconductor material layer 121. Next, a memory film 141 , a channel film 143 , an insulating pillar 145 and a pad 147 are sequentially deposited in each vertical opening 140 to form a channel structure 149 . The insulating layer 131 may include oxide, such as silicon oxide. The sacrificial layer 133 may include nitride, such as silicon nitride.

請參照第5圖。對層疊體130’進行圖案化製程以在層疊體130’中形成至少一溝槽230。舉例而言，可藉由微影製程以圖案化層疊體130’。溝槽230可沿著Z方向向下延伸，貫穿層疊體130’並停止於導電材料層220。導電材料層220可作為蝕刻停止層。溝槽230使層疊體130’和導電材料層220暴露(同時也作為溝槽230之側壁)。在一實施例中，可透過一蝕刻製程(例如是深蝕刻)形成溝槽230。由於蝕刻製程對於層疊體130’的材料和導電材料層220的材料之間具有高度的選擇性，故可確保蝕刻製程停止於導電材料層220，並不會有過蝕刻的問題產生。 Please refer to Figure 5. A patterning process is performed on the stack 130' to form at least one groove 230 in the stack 130'. For example, the laminated body 130' can be patterned by a lithography process. The trench 230 may extend downward along the Z direction, pass through the stack 130' and stop at the conductive material layer 220. The conductive material layer 220 may serve as an etch stop layer. The trench 230 exposes the stack 130' and the conductive material layer 220 (also serves as the sidewall of the trench 230). In one embodiment, the trench 230 may be formed through an etching process (eg, etch back). Since the etching process has a high degree of selectivity between the material of the laminated body 130' and the material of the conductive material layer 220, it can be ensured that the etching process stops at the conductive material layer 220, and there is no problem of over-etching.

雖然本案圖式未繪示出，應理解的是，由於溝槽230具有高深寬比，溝槽230在Y方向上的寬度是由上向下遞減。 Although not shown in the drawings, it should be understood that since the trench 230 has a high aspect ratio, the width of the trench 230 in the Y direction decreases from top to bottom.

請參照第6圖。移除導電材料層220並暴露上部導電層129及第二層間絕緣層127(即再次暴露槽口210)，使得溝槽230與槽口210彼此連通。如第6圖所示，溝槽230與槽口210在Z方向上彼此重疊，且槽口210在Y方向(例如第二方向)上的寬度W1可大於溝槽230在Y方向上的寬度W2，槽口210在Z方向(例如第一方向)上的深度小於溝槽230在Z方向上的深度。 Please refer to Figure 6. The conductive material layer 220 is removed and the upper conductive layer 129 and the second interlayer insulating layer 127 are exposed (ie, the notch 210 is exposed again), so that the trench 230 and the notch 210 communicate with each other. As shown in FIG. 6, the groove 230 and the notch 210 overlap each other in the Z direction, and the width W1 of the notch 210 in the Y direction (such as the second direction) may be greater than the width W2 of the groove 230 in the Y direction, and the depth of the notch 210 in the Z direction (such as the first direction) is smaller than the depth of the groove 230 in the Z direction.

在一比較例中，可透過兩次蝕刻步驟來形成暴露上部導電層及第二層間絕緣層的溝槽，並沒有在形成溝槽之前先形成槽口及填入槽口中的導電材料層。相較於沒有導電材料層做為蝕刻停止層的比較例而言，由於本案的實施例係形成導電材料層220作為蝕刻停止層，用於形成溝槽230的蝕刻製程可安全地停止於導電材料層220，亦即可精準地控制溝槽230的深度，並不會有過蝕刻的問題，故在後續形成導電柱(例如共同源極線)的製程中不易因過蝕刻及導電材料無法填滿用於形成導電柱的溝槽而生成孔隙，能夠避免導電材料透過孔隙使得導電柱與通道結構發生短路的情況，因此所形成的半導體裝置10可具有較佳的電特性。 In a comparative example, the trench exposing the upper conductive layer and the second interlayer insulating layer can be formed through two etching steps, and the notch and the conductive material layer filled in the notch are not formed before the trench is formed. Compared with the comparative example without the conductive material layer as the etch stop layer, since the embodiment of the case forms the conductive material layer 220 as the etch stop layer, the etching process for forming the trench 230 can be safely stopped at the conductive The material layer 220 can accurately control the depth of the trench 230 without the problem of over-etching. Therefore, in the subsequent process of forming the conductive pillar (such as the common source line), it is not easy to generate pores due to over-etching and the conductive material cannot fill the groove for forming the conductive pillar. It can avoid the situation that the conductive material penetrates through the hole and causes the conductive pillar and the channel structure to be short-circuited. Therefore, the formed semiconductor device 10 can have better electrical characteristics.

請參照第7圖。在第6圖所示之溝槽230的側壁、槽口210的側壁上形成間隔結構(spacer structure)157，間隔結構157可包括絕緣膜151、絕緣膜153與絕緣膜155。舉例來說，可藉由沉積處理使絕緣膜151形成於層疊體130’的上表面上且襯裡式地形成於溝槽230及槽口210中，再藉由蝕刻步驟移除槽口210底部上的部分絕緣膜151；接著，可藉由沉積處理使絕緣膜153形成於絕緣膜151上，再藉由蝕刻步驟移除槽口210底部上的部分絕緣膜153；然後，可藉由沉積處理使絕緣膜155形成於絕緣膜153上，再藉由蝕刻步驟移除槽口210底部上的部分絕緣膜155，此時，槽口210的底部可使部分的第二層間絕緣層127暴露。接著，可進行化學機械平坦化移除層疊體130’的上表面上的絕緣膜151、絕緣膜153與絕緣膜155。絕緣膜151可包含絕緣材料，絕緣材料包括氮化物，例如氮化矽。絕緣膜153可包含絕緣材料，絕緣材料包括氧化物，例如氧化矽。絕緣膜155可包含絕緣材料，絕緣材料包括氮化物，例如氮化矽。 Please refer to Figure 7. A spacer structure 157 is formed on the sidewall of the trench 230 and the sidewall of the notch 210 shown in FIG. 6 . The spacer structure 157 may include an insulating film 151 , an insulating film 153 and an insulating film 155 . For example, the insulating film 151 may be formed on the upper surface of the laminated body 130' by a deposition process and lined in the trench 230 and the notch 210, and then part of the insulating film 151 on the bottom of the notch 210 may be removed by an etching step; then, the insulating film 153 may be formed on the insulating film 151 by a deposition process, and part of the insulating film 153 on the bottom of the notch 210 may be removed by an etching step; then, the insulating film may be formed by a deposition process. 155 is formed on the insulating film 153, and then part of the insulating film 155 on the bottom of the notch 210 is removed by an etching step. At this time, the bottom of the notch 210 can expose part of the second interlayer insulating layer 127. Next, the insulating film 151, the insulating film 153 and the insulating film 155 on the upper surface of the laminated body 130' may be removed by chemical mechanical planarization. The insulating film 151 may include an insulating material, and the insulating material includes nitride, such as silicon nitride. The insulating film 153 may include an insulating material including an oxide such as silicon oxide. The insulating film 155 may include an insulating material including nitride, such as silicon nitride.

如第7圖所示，在形成間隔結構157之後進行蝕刻步驟。蝕刻步驟停止於中間半導體材料層125，以形成貫穿第二層間絕緣層127並暴露中間半導體材料層125的缺口(notch)250。缺口250在Y方向上的寬度小於溝槽230及槽口210在Y方向上的寬度。溝槽230、槽口210與缺口250彼此連通。 As shown in FIG. 7, an etching step is performed after the spacer structure 157 is formed. The etch step stops at the intermediate semiconductor material layer 125 to form a through second layer The insulating layer 127 is exposed and the notch 250 of the intermediate semiconductor material layer 125 is exposed. The width of the notch 250 in the Y direction is smaller than the widths of the groove 230 and the notch 210 in the Y direction. The groove 230 , the notch 210 and the notch 250 communicate with each other.

請參照第8圖。可進行蝕刻步驟以透過溝槽230、槽口210與缺口250移除中間半導體材料層125，從而形成狹縫270。狹縫270在第一層間絕緣層123與第二層間絕緣層127之間。此蝕刻步驟可實質上移除中間半導體材料層125，而不會移除第一層間絕緣層123下方的下部半導體材料層121與第二層間絕緣層127上方的上部導電層129。狹縫270使通道結構149的部分側壁暴露。具體而言，狹縫270使通道結構149的記憶膜141的部分側壁暴露。 Please refer to Figure 8. An etching step may be performed to remove the intermediate semiconductor material layer 125 through the trench 230 , the notch 210 and the gap 250 to form the slit 270 . The slit 270 is between the first insulating interlayer 123 and the second insulating interlayer 127 . This etching step can substantially remove the middle semiconductor material layer 125 without removing the lower semiconductor material layer 121 below the first interlayer insulating layer 123 and the upper conductive layer 129 above the second interlayer insulating layer 127 . The slit 270 exposes part of the sidewall of the channel structure 149 . Specifically, the slit 270 exposes part of the sidewall of the memory film 141 of the channel structure 149 .

請參照第9圖。可進行一或更多的蝕刻步驟以移除通道結構149之記憶膜141之一部分、第一層間絕緣層123、第二層間絕緣層127、部分的絕緣膜(即絕緣膜153與絕緣膜155)。在一實施例中，溝槽230之側壁及槽口210之側壁上的絕緣膜151可被保留。經蝕刻步驟所移除的各個記憶膜141包括一頂部移除部分141E，頂部移除部分141E連接於記憶膜141之對應於上部導電層129的底面。 Please refer to Figure 9. One or more etching steps may be performed to remove a part of the memory film 141 of the channel structure 149 , the first interlayer insulating layer 123 , the second interlayer insulating layer 127 , and part of the insulating films (ie, the insulating film 153 and the insulating film 155 ). In one embodiment, the insulating film 151 on the sidewalls of the trench 230 and the sidewalls of the notch 210 may be retained. Each memory film 141 removed by the etching step includes a top removal portion 141E, and the top removal portion 141E is connected to the bottom surface of the memory film 141 corresponding to the upper conductive layer 129 .

請參照第10圖。可藉由沉積處理以在下部半導體材料層121與上部導電層129之間形成回填半導體材料層124。例如，可藉由沉積處理將半導體材料沉積於狹縫270之中，此後利用一回蝕製程移除部分的回填半導體材料層124以形成延伸開口 272，延伸開口272暴露回填半導體材料層124。溝槽230、槽口210與延伸開口272可彼此連通。在一實施例中，回填半導體材料層124可連接或接觸記憶膜141、通道膜143、下部半導體材料層121與上部導電層129。在一實施例中，回填半導體材料層124可包含摻雜的或未摻雜的半導體材料，例如摻雜的或未摻雜的多晶矽。下部半導體材料層121、回填半導體材料層124與上部導電層129可形成接地層120。接地層120可包含摻雜的或未摻雜的半導體材料，例如摻雜的或未摻雜的多晶矽。下部半導體材料層121、回填半導體材料層124與上部導電層129的摻雜濃度可彼此不同，然本發明並不限於此。 Please refer to Figure 10. A backfill semiconductor material layer 124 may be formed between the lower semiconductor material layer 121 and the upper conductive layer 129 by a deposition process. For example, a semiconductor material may be deposited in the slit 270 by a deposition process, and then a portion of the backfilled semiconductor material layer 124 is removed using an etch-back process to form the extended opening. 272 , extending the opening 272 to expose the backfill semiconductor material layer 124 . The groove 230 , the notch 210 and the extension opening 272 can communicate with each other. In one embodiment, the backfill semiconductor material layer 124 can connect or contact the memory film 141 , the channel film 143 , the lower semiconductor material layer 121 and the upper conductive layer 129 . In one embodiment, the backfill semiconductor material layer 124 may include doped or undoped semiconductor material, such as doped or undoped polysilicon. The lower semiconductor material layer 121 , the backfill semiconductor material layer 124 and the upper conductive layer 129 can form the ground layer 120 . The ground layer 120 may include doped or undoped semiconductor material, such as doped or undoped polysilicon. Doping concentrations of the lower semiconductor material layer 121 , the backfill semiconductor material layer 124 and the upper conductive layer 129 may be different from each other, but the invention is not limited thereto.

請參照第11圖。可進行蝕刻步驟以移除剩餘的絕緣膜151，並在槽口210及延伸開口272的側壁上及延伸開口272的底部上形成保護層161。保護層161可覆蓋被槽口210及延伸開口272暴露之接地層120。在一實施例中，保護層161可包含絕緣材料，絕緣材料包含氧化物，例如氧化矽。舉例而言，可藉由氧化製程將接地層120之由槽口210及延伸開口272所暴露出之表面氧化為保護層161。 Please refer to Figure 11. An etching step may be performed to remove the remaining insulating film 151 and form the protection layer 161 on the sidewalls of the notch 210 and the extension opening 272 and on the bottom of the extension opening 272 . The protective layer 161 can cover the ground layer 120 exposed by the notch 210 and the extended opening 272 . In one embodiment, the passivation layer 161 may include an insulating material, and the insulating material includes oxide, such as silicon oxide. For example, the surface of the ground layer 120 exposed by the notch 210 and the extended opening 272 can be oxidized into the protection layer 161 through an oxidation process.

請參照第12圖。可透過溝槽230進行蝕刻步驟以移除層疊體130’之犧牲層133，形成絕緣層131之間的多個空間274。在此蝕刻步驟中，保護層161可保護接地層120，以避免接地層120在蝕刻步驟中被移除。在一實施例中，蝕刻步驟可包含溼式蝕刻方式，例如使用熱磷酸(phosphoric acid；H₃PO₄)或其他合適的化學物。 Please refer to Figure 12. An etching step may be performed through the trenches 230 to remove the sacrificial layer 133 of the stack 130 ′ to form a plurality of spaces 274 between the insulating layers 131 . During this etching step, the passivation layer 161 can protect the ground layer 120 to prevent the ground layer 120 from being removed during the etching step. In one embodiment, the etching step may include wet etching, such as using phosphoric acid (H ₃ PO ₄ ) or other suitable chemicals.

請參照第13圖。以導電材料填充多個空間274，形成在多個絕緣層131之間的多個導電層134。例如，將導電材料沉積於多個空間274中，此後進行回蝕製程將鄰接於溝槽230的每個導電層134移除一小部分，以形成介於絕緣層131與導電層134之間的多個凹室134r。溝槽230與凹室134r彼此連通。交替堆疊的絕緣層131與導電層134可共同形成堆疊結構130。 Please refer to Figure 13. Fill the plurality of spaces 274 with conductive material to form the plurality of conductive layers 134 between the plurality of insulating layers 131 . For example, conductive material is deposited in the plurality of spaces 274 , and then an etch-back process is performed to remove a small portion of each conductive layer 134 adjacent to the trench 230 to form a plurality of recesses 134 r between the insulating layer 131 and the conductive layer 134 . The groove 230 and the alcove 134r communicate with each other. The alternately stacked insulating layers 131 and conductive layers 134 can jointly form a stacked structure 130 .

在一實施例中，包含於第12至13圖之步驟可被理解為閘極取代(gate replacement)製程。在一實施例中，導電層134可包含導電材料，例如鎢(tungsten,W)。 In one embodiment, the steps included in FIGS. 12-13 can be understood as a gate replacement process. In one embodiment, the conductive layer 134 may include a conductive material, such as tungsten (W).

請參照第14圖。可藉由沉積處理以形成隔離材料層163填充於凹室134r中，並襯裡式地形成於溝槽230、槽口210及延伸開口272中，此後可進行蝕刻步驟以移除延伸開口272底部的部分的隔離材料層163和保護層161，並暴露出接地層120。藉此，可形成覆蓋溝槽230、槽口210及延伸開口272的側壁的隔離材料層163。亦即，隔離材料層163可覆蓋堆疊結構130之導電層131與絕緣層134之暴露的側壁，且覆蓋保護層161。在一實施例中，隔離材料層163可包含氧化物，例如低溫氧化物(low temperature oxide,LTO)。 Please refer to Figure 14. The isolation material layer 163 can be formed by a deposition process to fill the cavity 134r and line the trench 230, the notch 210 and the extension opening 272, and then an etching step can be performed to remove the isolation material layer 163 and the protection layer 161 at the bottom of the extension opening 272, and expose the ground layer 120. Thereby, the isolation material layer 163 covering the sidewalls of the trench 230 , the notch 210 and the extension opening 272 can be formed. That is, the isolation material layer 163 can cover the exposed sidewalls of the conductive layer 131 and the insulating layer 134 of the stack structure 130 , and cover the passivation layer 161 . In one embodiment, the isolation material layer 163 may include oxide, such as low temperature oxide (LTO).

在形成隔離材料層163之後，形成導電柱179於隔離材料層163與接地層120之間，如第15~16圖所示。第15~16 圖繪示根據本發明一實施例的導電柱179的形成方法，然本發明並不限於此。 After forming the isolation material layer 163 , a conductive column 179 is formed between the isolation material layer 163 and the ground layer 120 , as shown in FIGS. 15-16 . 15th~16th The figure shows a method for forming the conductive pillar 179 according to an embodiment of the present invention, but the present invention is not limited thereto.

請參照第15圖。在形成隔離材料層163之後，可藉由沉積處理以使本體阻障層171襯裡式地形成於堆疊結構130上及溝槽230、槽口210及延伸開口272中。本體阻障層171可直接接觸於接地層120。 Please refer to Figure 15. After the isolation material layer 163 is formed, the body barrier layer 171 can be formed lining the stacked structure 130 and in the trench 230 , the notch 210 and the extension opening 272 by a deposition process. The body barrier layer 171 can directly contact the ground layer 120 .

請參照第16圖。可移除堆疊結構130上多餘的本體阻障層171，並形成下部導電層173於溝槽230、槽口210及延伸開口272中，此後移除位於溝槽230之上部中的部分隔離材料層163、本體阻障層171、下部導電層173以形成一上部開口(未繪示)，於上部開口中形成包括上部阻障層175及上部導體177的插塞179C。插塞179C之下的本體阻障層171及下部導電層173形成中間本體部179B及底部本體部179A。亦即，中間本體部179B及底部本體部179A包括本體阻障層171及下部導電層173。如此一來，即形成包括底部本體部179A、中間本體部179B、及插塞179C的導電柱179。 Please refer to Figure 16. The excess body barrier layer 171 on the stacked structure 130 can be removed, and the lower conductive layer 173 is formed in the trench 230, the notch 210 and the extension opening 272, and then part of the isolation material layer 163, the body barrier layer 171, and the lower conductive layer 173 located in the upper part of the trench 230 are removed to form an upper opening (not shown), and the plug 1 including the upper barrier layer 175 and the upper conductor 177 is formed in the upper opening. 79C. Body barrier layer 171 and lower conductive layer 173 below plug 179C form middle body portion 179B and bottom body portion 179A. That is, the middle body portion 179B and the bottom body portion 179A include the body barrier layer 171 and the lower conductive layer 173 . In this way, the conductive pillar 179 including the bottom body portion 179A, the middle body portion 179B, and the plug 179C is formed.

本體阻障層171及上部阻障層175可防止異質原子藉由擴散行為進入元件中。在一實施例中，本體阻障層171及上部阻障層175的材料可各自獨立地為鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)或其他合適的阻障材料。 The body barrier layer 171 and the upper barrier layer 175 can prevent foreign atoms from entering the device through diffusion. In one embodiment, the materials of the body barrier layer 171 and the upper barrier layer 175 can be independently titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or other suitable barrier materials.

在本實施例中，上部導體177的材料不同於下部導電層173的材料，上部導體177的材料可包含金屬材料，例如鎢；下部導電層173的材料可包含摻雜的或未摻雜的半導體材料，例如摻雜的或未摻雜的多晶矽。在另一實施例中，上部導體177和下部導電層173可皆包含金屬材料，例如鎢。在其他實施例中，上部導體177和下部導電層173可皆包含摻雜的或未摻雜的半導體材料，例如摻雜的或未摻雜的多晶矽，且上部導體177和隔離材料層163之間以及下部導電層173和隔離材料層163之間不存在上部阻障層175及本體阻障層171，亦即上部導體177和下部導電層173可直接接觸於隔離材料層163。 In this embodiment, the material of the upper conductor 177 is different from the material of the lower conductive layer 173, and the material of the upper conductor 177 may include a metal material, such as tungsten; The material of the lower conductive layer 173 may include doped or undoped semiconductor material, such as doped or undoped polysilicon. In another embodiment, both the upper conductor 177 and the lower conductive layer 173 may include a metal material, such as tungsten. In other embodiments, both the upper conductor 177 and the lower conductive layer 173 may include doped or undoped semiconductor material, such as doped or undoped polysilicon, and there is no upper barrier layer 175 and body barrier layer 171 between the upper conductor 177 and the isolation material layer 163 and between the lower conductive layer 173 and the isolation material layer 163, that is, the upper conductor 177 and the lower conductive layer 173 may directly contact the isolation material layer 163.

如第16圖所示，半導體裝置10包括一電路板110、一接地層120、一堆疊結構130、複數個通道結構149、一隔離材料層163及至少一導電柱179。接地層120設置於電路板110上，堆疊結構130設置於接地層120上。 As shown in FIG. 16 , the semiconductor device 10 includes a circuit board 110 , a ground layer 120 , a stack structure 130 , a plurality of channel structures 149 , an isolation material layer 163 and at least one conductive pillar 179 . The ground layer 120 is disposed on the circuit board 110 , and the stack structure 130 is disposed on the ground layer 120 .

堆疊結構130包括沿著Z方向(例如第一方向)交替堆疊於接地層120上的複數個絕緣層131及複數個導電層134。通道結構149沿著Z方向(例如第一方向)貫穿堆疊結構130並延伸至接地層120中，更切確地說，接地層120包括沿著Z方向依序堆疊於電路板110上的下部半導體材料層121、回填半導體材料層124及上部導電層129，通道結構149的下通道端部149b可延伸至下部半導體材料層121中。 The stack structure 130 includes a plurality of insulating layers 131 and a plurality of conductive layers 134 alternately stacked on the ground layer 120 along the Z direction (eg, the first direction). The channel structure 149 penetrates the stacked structure 130 along the Z direction (for example, the first direction) and extends into the ground layer 120. More specifically, the ground layer 120 includes the lower semiconductor material layer 121, the backfill semiconductor material layer 124, and the upper conductive layer 129 stacked on the circuit board 110 along the Z direction. The lower channel end 149b of the channel structure 149 can extend into the lower semiconductor material layer 121.

每個通道結構149可包含記憶膜141、通道膜143、絕緣柱145與接墊147，通道膜143環繞絕緣柱145，記憶膜141環繞通道膜143，接墊147設置於通道膜143與絕緣柱145上，各元件的材料如上所述。部分的通道膜143由記憶膜141暴露出，使得接地層120直接接觸於通道膜143與記憶膜141。 Each channel structure 149 may include a memory film 141, a channel film 143, an insulating post 145 and a pad 147. The channel film 143 surrounds the insulating post 145, the memory film 141 surrounds the channel film 143, and the contact pad 147 is arranged on the channel film 143 and the insulating post 145. Materials are as described above. Part of the channel film 143 is exposed by the memory film 141 , so that the ground layer 120 directly contacts the channel film 143 and the memory film 141 .

導電柱179沿著Z方向(例如第一方向)貫穿堆疊結構130並延伸至接地層120中。導電柱179包括彼此連接的底部本體部179A、中間本體部179B、及插塞179C，中間本體部179B設置於底部本體部179A及插塞179C之間。亦即，中間本體部179B設置於底部本體部179A之上，插塞179C設置於中間本體部179B之上。 The conductive pillar 179 penetrates the stack structure 130 along the Z direction (eg, the first direction) and extends into the ground layer 120 . The conductive post 179 includes a bottom body portion 179A, a middle body portion 179B, and a plug 179C connected to each other, and the middle body portion 179B is disposed between the bottom body portion 179A and the plug 179C. That is, the middle body portion 179B is disposed on the bottom body portion 179A, and the plug 179C is disposed on the middle body portion 179B.

底部本體部179A對應於接地層120，例如，底部本體部179A延伸至接地層120中，在Y方向上(例如第二方向)，底部本體部179A重疊於接地層120。中間本體部179B對應於堆疊結構130的中間及底部部分；插塞179C對應於堆疊結構130的頂部部分。例如，在Y方向上，中間本體部179B重疊於堆疊結構130的中間及底部部分，插塞179C重疊於堆疊結構130的頂部部分。導電柱179例如是做為共同源極線(common source line,CSL)，電性接觸於接地層120。 The bottom body portion 179A corresponds to the ground layer 120 , for example, the bottom body portion 179A extends into the ground layer 120 , and the bottom body portion 179A overlaps the ground layer 120 in the Y direction (eg, the second direction). The middle body portion 179B corresponds to the middle and bottom portions of the stack structure 130 ; the plug 179C corresponds to the top portion of the stack structure 130 . For example, in the Y direction, the middle body portion 179B overlaps the middle and bottom portions of the stack structure 130 , and the plug 179C overlaps the top portion of the stack structure 130 . The conductive pillar 179 is, for example, used as a common source line (CSL), electrically contacting the ground layer 120 .

根據一實施例，導電柱179的外側壁在鄰近於堆疊結構130之最底層絕緣層131的部分具有轉角外觀(kink profile)，即在Y方向上的尺寸有所變化。舉例而言，導電柱179的外側壁在對應於底部本體部179A且鄰接於轉角外觀的部分具有一第一表面F1，導電柱179的外側壁在對應於中間本體部179B且鄰接於轉角外觀的部分具有一第二表面F2，第一表面F1與第二表面 F2之間的夾角α可趨近於90度，例如是70~90度。由於溝槽230具有高深寬比，故形成於溝槽230中的中間本體部179B(在Y方向上重疊於堆疊結構130)在Y方向上的寬度是由上往下遞減。進一步而言，在Y方向上，底部本體部179A之重疊於接地層120的上部導電層129的部分具有一第一尺寸S1，中間本體部179B重疊於堆疊結構130之最底層絕緣層131的部分具有一第二尺寸S2，中間本體部179B重疊於堆疊結構130之最底層絕緣層131之上的部分具有一第三尺寸S3，第一尺寸S1大於第二尺寸S2及第三尺寸S3，且第三尺寸S3大於第二尺寸S2，例如是滿足”S1>S3>S2”的關係式。在接地層120中，回填半導體材料層124填充於記憶膜141的頂部移除部分141E。與頂部移除部分141E對應的底部本體部179A亦可具有第一尺寸S1。換言之，在Y方向上，底部本體部179A之重疊於回填半導體材料層124之頂部突起部(即回填半導體材料層124填充於頂部移除部分141E中所形成的頂部突起部)的部分亦可具有第一尺寸S1。根據一實施例，在Z方向(例如第一方向)上，堆疊結構130之最底層絕緣層131的一底面與上部導電層129的一底面之間具有一高度H1，高度H1大於0奈米且小於或等於60奈米(0nm<H1

60nm)，例如20~60奈米、25~55奈米或其他合適的範圍。在一些實施例中，下部半導體材料層121的厚度大於回填半導體材料層124的厚度及上部導電層129的厚度。 According to an embodiment, the outer sidewall of the conductive pillar 179 has a kink profile at a portion adjacent to the bottommost insulating layer 131 of the stack structure 130 , that is, the dimension in the Y direction changes. For example, the outer wall of the conductive post 179 has a first surface F1 at a portion corresponding to the bottom body portion 179A and adjacent to the corner appearance, and the outer wall of the conductive post 179 has a second surface F2 at a portion corresponding to the middle body portion 179B and adjacent to the corner appearance. Since the trench 230 has a high aspect ratio, the width of the middle body portion 179B formed in the trench 230 (overlapping the stack structure 130 in the Y direction) decreases gradually from top to bottom in the Y direction. Further, in the Y direction, the portion of the bottom body portion 179A overlapping the upper conductive layer 129 of the ground layer 120 has a first size S1, the portion of the middle body portion 179B overlapping the bottommost insulating layer 131 of the stacked structure 130 has a second size S2, the portion of the middle body portion 179B overlapping the bottommost insulating layer 131 of the stacked structure 130 has a third size S3, the first size S1 is larger than the second size S2 and the third size S3, and The third size S3 is larger than the second size S2, for example, satisfying the relationship "S1>S3>S2". In the ground layer 120 , the backfill semiconductor material layer 124 fills the top removed portion 141E of the memory film 141 . The bottom body portion 179A corresponding to the top removed portion 141E may also have a first dimension S1. In other words, in the Y direction, the portion of the bottom body portion 179A overlapping the top protrusion of the backfilled semiconductor material layer 124 (ie, the top protrusion formed in the top removal portion 141E filled with the backfilled semiconductor material layer 124 ) may also have the first size S1. According to an embodiment, in the Z direction (for example, the first direction), there is a height H1 between a bottom surface of the bottom insulating layer 131 of the stacked structure 130 and a bottom surface of the upper conductive layer 129, and the height H1 is greater than 0 nm and less than or equal to 60 nm (0nm<H1

60nm), such as 20~60nm, 25~55nm or other suitable ranges. In some embodiments, the thickness of the lower semiconductor material layer 121 is greater than the thickness of the backfill semiconductor material layer 124 and the thickness of the upper conductive layer 129 .

根據一實施例，隔離材料層163設置於導電柱179與堆疊結構130之間以及導電柱179與接地層120之間。在Y方向上，隔離材料層163之重疊於接地層120的上部導電層129的部分的最大尺寸S4大於隔離材料層163之重疊於堆疊結構130之部分(例如是導電層134之間的部分)的最大尺寸S5。 According to an embodiment, the isolation material layer 163 is disposed between the conductive pillar 179 and the stack structure 130 and between the conductive pillar 179 and the ground layer 120 . In the Y direction, the maximum dimension S4 of the portion of the isolation material layer 163 overlapping the upper conductive layer 129 of the ground layer 120 is larger than the maximum dimension S5 of the portion of the isolation material layer 163 overlapping the stacked structure 130 (for example, the portion between the conductive layers 134).

第17至32圖繪示依照本發明另一實施例的半導體裝置30的製作方法的剖面圖。 17 to 32 are cross-sectional views illustrating a method for fabricating a semiconductor device 30 according to another embodiment of the present invention.

半導體裝置30的製作方法與半導體裝置10的製作方法之間的主要差異在於上部導電層129置換為上部導電層329，上部導電層329包括導電材料層420。半導體裝置30及其製作方法係部份類似或相同於半導體裝置10及其製作方法，類似或相同的元件是標示為類似或相同的元件符號，且具有類似或相同的位置、形成方式、結構、材料或功能，重複的內容將不再詳細描述。 The main difference between the fabrication method of the semiconductor device 30 and the fabrication method of the semiconductor device 10 is that the upper conductive layer 129 is replaced by the upper conductive layer 329 , and the upper conductive layer 329 includes the conductive material layer 420 . The semiconductor device 30 and its manufacturing method are partly similar or identical to the semiconductor device 10 and its manufacturing method. Similar or identical components are marked with similar or identical component symbols, and have similar or identical positions, formation methods, structures, materials or functions. The repeated content will not be described in detail.

請參照第17圖。提供多層結構320’於電路板110上。多層結構320’包括沿著Z方向(例如第一方向)由下往上依序堆疊於電路板110上的下部半導體材料層121、第一層間絕緣層123、中間半導體材料層125、第二層間絕緣層127及上部導電層329。上部導電層329包括導電材料層420及絕緣材料層422。也可以說是在上部導電層329中形成一導電材料層420。在一些實施例中，導電材料層420的材料包括金屬材料，例如是鎢。絕緣材料層422可包含絕緣材料，絕緣材料包括氧化物，例如氧化矽(silicon oxide)。 Please refer to Figure 17. A multilayer structure 320' is provided on the circuit board 110. The multilayer structure 320' includes a lower semiconductor material layer 121, a first interlayer insulating layer 123, an intermediate semiconductor material layer 125, a second interlayer insulating layer 127 and an upper conductive layer 329 stacked on the circuit board 110 from bottom to top along the Z direction (for example, the first direction). The upper conductive layer 329 includes a conductive material layer 420 and an insulating material layer 422 . It can also be said that a conductive material layer 420 is formed in the upper conductive layer 329 . In some embodiments, the material of the conductive material layer 420 includes a metal material, such as tungsten. The insulating material layer 422 may include an insulating material, and the insulating material includes an oxide, such as silicon oxide.

在一實施例中，可藉由依序沉積下部半導體材料層121、第一層間絕緣層123、中間半導體材料層125、第二層間絕緣層127、導電材料層420及絕緣材料層422以在電路板110上形成多層結構320’，例如是藉由化學氣相沉積處理(chemical vapor deposition,CVD)。 In one embodiment, the multilayer structure 320' can be formed on the circuit board 110 by sequentially depositing the lower semiconductor material layer 121, the first interlayer insulating layer 123, the middle semiconductor material layer 125, the second interlayer insulating layer 127, the conductive material layer 420, and the insulating material layer 422, such as by chemical vapor deposition (CVD).

請參照第18圖。在形成多層結構320’之後，移除部分的上部導電層329以形成暴露中間半導體材料層125的孔洞411。例如，可藉由微影製程於預定位置蝕刻一部分的上部導電層329。所述預定位置在Z方向上重疊於欲形成通道結構149(繪示於第20圖中)的位置。 Please refer to Figure 18. After forming the multilayer structure 320', a portion of the upper conductive layer 329 is removed to form a hole 411 exposing the middle semiconductor material layer 125. For example, a part of the upper conductive layer 329 may be etched at a predetermined position by a lithography process. The predetermined position overlaps the position where the channel structure 149 (shown in FIG. 20 ) is to be formed in the Z direction.

請參照第19圖。可藉由沉積處理在孔洞411中填入絕緣材料。此後，可進行化學機械平坦化(Chemical-Mechanical Planarization,CMP)。 Please refer to Figure 19. The insulating material may be filled in the hole 411 by a deposition process. Thereafter, chemical-mechanical planarization (Chemical-Mechanical Planarization, CMP) may be performed.

請參照第20圖。在上部導電層329上形成一層疊體130’，此後形成沿著Z方向穿過層疊體130’及部分多層結構120’的複數個通道結構149。層疊體130’包括交替堆疊的複數個絕緣層131及犧牲層133，其中層疊體130’的最底層及最頂層可為絕緣層131。通道結構149的下通道端部149b可位於下部半導體材料層121中。各個通道結構149可包含記憶膜141、通道膜143、絕緣柱145與接墊147。 Please refer to Figure 20. A stack 130' is formed on the upper conductive layer 329, and then a plurality of channel structures 149 passing through the stack 130' and part of the multilayer structure 120' along the Z direction are formed. The stacked body 130' includes a plurality of insulating layers 131 and sacrificial layers 133 stacked alternately, wherein the bottommost and topmost layers of the stacked body 130' can be insulating layers 131. The lower channel end 149b of the channel structure 149 may be located in the lower semiconductor material layer 121 . Each channel structure 149 may include a memory film 141 , a channel film 143 , insulating columns 145 and pads 147 .

請參照第21圖。對層疊體130’進行圖案化製程以在層疊體130’中形成至少一溝槽430。舉例而言，可藉由微影製程以圖案化層疊體130’。溝槽430可沿著Z方向向下延伸，貫穿層疊體130’並停止於導電材料層420。導電材料層420可作為蝕刻停止層。溝槽430使層疊體130’、導電材料層420和絕緣材料層422暴露(層疊體130’、導電材料層420和絕緣材料層422同時也作為溝槽430之側壁)。在一實施例中，可透過一蝕刻製程(例如是深蝕刻)形成溝槽430。由於蝕刻製程對於層疊體130’的材料和導電材料層420的材料之間具有高度的選擇性，故可確保蝕刻製程停止於導電材料層420，並不會有過蝕刻的問題產生。 Please refer to Figure 21. A patterning process is performed on the stack 130' to form at least one groove 430 in the stack 130'. For example, the laminated body 130' can be patterned by a lithography process. The trench 430 may extend downward along the Z direction, through the stack 130' and stop at the conductive material layer 420. Conductive material layer 420 can be used as an etch stop layer. The trench 430 exposes the stack 130', the conductive material layer 420, and the insulating material layer 422 (the stack 130', the conductive material layer 420, and the insulating material layer 422 also serve as sidewalls of the trench 430). In one embodiment, the trench 430 may be formed by an etching process (eg, etch back). Since the etching process has a high degree of selectivity between the material of the laminated body 130' and the material of the conductive material layer 420, it is ensured that the etching process stops at the conductive material layer 420, and there is no problem of over-etching.

請參照第22圖。可藉由蝕刻步驟移除部分導電材料層420並暴露第二層間絕緣層127，使得溝槽430的深度延長。 Please refer to Figure 22. Part of the conductive material layer 420 may be removed by an etching step to expose the second interlayer insulating layer 127 , so that the depth of the trench 430 is extended.

請參照第23圖。在第22圖所示之溝槽430的側壁上形成間隔結構(spacer structure)157，間隔結構157可包括絕緣膜151、絕緣膜153與絕緣膜155。在形成間隔結構157之後進行蝕刻步驟。蝕刻步驟停止於中間半導體材料層125，並暴露中間半導體材料層125。 Please refer to Figure 23. A spacer structure 157 is formed on the sidewall of the trench 430 shown in FIG. 22 . The spacer structure 157 may include an insulating film 151 , an insulating film 153 and an insulating film 155 . An etching step is performed after the spacer structures 157 are formed. The etching step stops at the intermediate semiconductor material layer 125 and exposes the intermediate semiconductor material layer 125 .

請參照第24圖。可進行蝕刻步驟以透過溝槽430移除中間半導體材料層125，從而形成狹縫470。狹縫470在第一層間絕緣層123與第二層間絕緣層127之間。狹縫470使通道結構149的部分側壁暴露。具體而言，狹縫470使通道結構149的記憶膜141的部分側壁暴露。 Please refer to Figure 24. An etching step may be performed to remove the intermediate semiconductor material layer 125 through the trench 430 to form the slit 470 . The slit 470 is between the first insulating interlayer 123 and the second insulating interlayer 127 . The slit 470 exposes part of the sidewall of the channel structure 149 . Specifically, the slit 470 exposes part of the sidewall of the memory film 141 of the channel structure 149 .

請參照第25圖。可進行一或更多的蝕刻步驟以移除通道結構149之記憶膜141之一部分、第一層間絕緣層123、第二層間絕緣層127、部分的絕緣膜(即絕緣膜153與絕緣膜155)。在一實施例中，溝槽430之側壁上的絕緣膜151可被保留。 Please refer to Figure 25. One or more etching steps may be performed to remove a part of the memory film 141 of the channel structure 149 , the first interlayer insulating layer 123 , the second interlayer insulating layer 127 , and part of the insulating films (ie, the insulating film 153 and the insulating film 155 ). In one embodiment, the insulating film 151 on the sidewall of the trench 430 may be left.

請參照第26圖。可藉由沉積處理以在下部半導體材料層121與上部導電層329之間形成回填半導體材料層124。例如，可藉由沉積處理將半導體材料沉積於狹縫470之中，此後利用一回蝕製程移除部分的回填半導體材料層124以形成延伸開口472，延伸開口472暴露回填半導體材料層124。溝槽430與延伸開口472可彼此連通。在一實施例中，回填半導體材料層124可連接或接觸記憶膜141、通道膜143、下部半導體材料層121與上部導電層329。下部半導體材料層121、回填半導體材料層124與上部導電層329可形成接地層320。 Please refer to Figure 26. A backfill semiconductor material layer 124 may be formed between the lower semiconductor material layer 121 and the upper conductive layer 329 by a deposition process. For example, a semiconductor material may be deposited in the slot 470 by a deposition process, and then an etch-back process is used to remove a portion of the backfill semiconductor material layer 124 to form an extended opening 472 exposing the backfill semiconductor material layer 124 . The groove 430 and the extension opening 472 may communicate with each other. In one embodiment, the backfill semiconductor material layer 124 can connect or contact the memory film 141 , the channel film 143 , the lower semiconductor material layer 121 and the upper conductive layer 329 . The lower semiconductor material layer 121 , the backfill semiconductor material layer 124 and the upper conductive layer 329 can form the ground layer 320 .

請參照第27圖。可進行蝕刻步驟以移除剩餘的絕緣膜151，並在延伸開口472的側壁及底部上形成保護層361。保護層361可覆蓋被延伸開口472暴露之接地層320。在一實施例中，保護層361可包含絕緣材料，絕緣材料包含氧化物，例如氧化矽。舉例而言，可藉由氧化製程將接地層320之由延伸開口472所暴露出之表面氧化為保護層361。 Please refer to Figure 27. An etching step may be performed to remove the remaining insulating film 151 and form the protection layer 361 on the sidewalls and bottom of the extension opening 472 . The protective layer 361 can cover the ground layer 320 exposed by the extended opening 472 . In one embodiment, the passivation layer 361 may include an insulating material, and the insulating material includes oxide, such as silicon oxide. For example, the surface of the ground layer 320 exposed by the extending opening 472 can be oxidized into the protection layer 361 through an oxidation process.

請參照第28圖。可透過溝槽430進行蝕刻步驟以移除層疊體130’之犧牲層133，形成絕緣層131之間的多個空間274。在此蝕刻步驟中，保護層361可保護接地層320，以避免接地層320在蝕刻步驟中被移除。在一實施例中，蝕刻步驟可包含溼式蝕刻方式，例如使用熱磷酸(phosphoric acid；H₃PO₄)或其他合適的化學物。 Please refer to Figure 28. An etching step may be performed through the trenches 430 to remove the sacrificial layer 133 of the stack 130 ′ to form a plurality of spaces 274 between the insulating layers 131 . During this etching step, the passivation layer 361 can protect the ground layer 320 to prevent the ground layer 320 from being removed during the etching step. In one embodiment, the etching step may include wet etching, such as using phosphoric acid (H ₃ PO ₄ ) or other suitable chemicals.

請參照第29圖。以導電材料填充多個空間274，形成在多個絕緣層131之間的多個導電層134。例如，將導電材料沉積於多個空間274中，此後進行回蝕製程將鄰接於溝槽430的每個導電層134移除一小部分，亦將鄰接於溝槽430的導電材料層420移除一小部分，以形成介於絕緣層131與導電層134之間以及絕緣材料層422與導電材料層420之間的多個凹室134r。溝槽430與凹室134r彼此連通。交替堆疊的絕緣層131與導電層134可共同形成堆疊結構130。 Please refer to Figure 29. Fill the plurality of spaces 274 with conductive material, forming A plurality of conductive layers 134 are formed between a plurality of insulating layers 131. For example, conductive material is deposited in the plurality of spaces 274, and then an etch-back process is performed to remove a small portion of each conductive layer 134 adjacent to the trench 430, and also remove a small portion of the conductive material layer 420 adjacent to the trench 430, so as to form a plurality of recesses 134r between the insulating layer 131 and the conductive layer 134 and between the insulating material layer 422 and the conductive material layer 420. The groove 430 and the alcove 134r communicate with each other. The alternately stacked insulating layers 131 and conductive layers 134 can jointly form a stacked structure 130 .

請參照第30圖。可藉由沉積處理以形成隔離材料層363填充於凹室134r中，並襯裡式地形成於溝槽430及延伸開口472中，此後可進行蝕刻步驟以移除延伸開口472底部的部分的隔離材料層363和保護層361，並暴露出接地層320。藉此，可形成覆蓋溝槽430及延伸開口472的側壁的隔離材料層363。亦即，隔離材料層363可覆蓋堆疊結構130之導電層131與絕緣層134之暴露的側壁，且覆蓋保護層361。在一實施例中，隔離材料層363可包含氧化物，例如低溫氧化物(low temperature oxide；LTO)。 Please refer to Figure 30. The isolation material layer 363 may be formed by a deposition process to fill the cavity 134r and line the trench 430 and the extension opening 472 . Afterwards, an etching step may be performed to remove the isolation material layer 363 and the passivation layer 361 at the bottom of the extension opening 472 and expose the ground layer 320 . Thereby, the isolation material layer 363 covering the sidewalls of the trench 430 and the extension opening 472 can be formed. That is, the isolation material layer 363 can cover the exposed sidewalls of the conductive layer 131 and the insulating layer 134 of the stack structure 130 , and cover the passivation layer 361 . In one embodiment, the isolation material layer 363 may include oxide, such as low temperature oxide (LTO).

請參照第31圖。在形成隔離材料層363之後，可藉由沉積處理以使本體阻障層371襯裡式地形成於堆疊結構130上及溝槽430及延伸開口472中。本體阻障層371可直接接觸於接地層320。 Please refer to Figure 31. After the isolation material layer 363 is formed, the body barrier layer 371 can be formed in a liner manner on the stack structure 130 and in the trench 430 and the extension opening 472 by a deposition process. The body barrier layer 371 can directly contact the ground layer 320 .

請參照第32圖。可移除堆疊結構130上多餘的本體阻障層371，並形成下部導電層373於溝槽430及延伸開口472中，此後移除位於溝槽430之上部中的部分隔離材料層363、本體阻障層371、下部導電層373以形成一上部開口(未繪示)，於上部開口中形成包括上部阻障層375及上部導體377的插塞379C。插塞379C之下的本體阻障層371及下部導電層373形成中間本體部379B及底部本體部379A。亦即，中間本體部379B及底部本體部379A包括本體阻障層371及下部導電層373。如此一來，即形成包括底部本體部379A、中間本體部379B、及插塞379C的導電柱379。 Please refer to Figure 32. The excess body barrier layer 371 on the stacked structure 130 can be removed, and the lower conductive layer 373 is formed in the trench 430 and the extension opening 472, and then part of the isolation material layer 363 located in the upper part of the trench 430 is removed. The bulk barrier layer 371 and the lower conductive layer 373 form an upper opening (not shown), and a plug 379C including the upper barrier layer 375 and the upper conductor 377 is formed in the upper opening. Body barrier layer 371 and lower conductive layer 373 below plug 379C form middle body portion 379B and bottom body portion 379A. That is, the middle body portion 379B and the bottom body portion 379A include a body barrier layer 371 and a lower conductive layer 373 . In this way, the conductive pillar 379 including the bottom body portion 379A, the middle body portion 379B, and the plug 379C is formed.

在一實施例中，本體阻障層371及上部阻障層375的材料可各自獨立地為鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)或其他合適的阻障材料。在本實施例中，導電柱379的形成方法是相同或類似於導電柱179的形成方法，應理解的是，導電柱379可應用於本案的上述實施例或其他實施例。 In one embodiment, the material of the bulk barrier layer 371 and the upper barrier layer 375 can be independently titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or other suitable barrier materials. In this embodiment, the method for forming the conductive pillar 379 is the same as or similar to the method for forming the conductive pillar 179 . It should be understood that the conductive pillar 379 can be applied to the above-mentioned embodiment or other embodiments of the present invention.

如第32圖所示，半導體裝置30包括一電路板110、一接地層320、一堆疊結構130、複數個通道結構149、一隔離材料層363及至少一導電柱379。接地層320設置於電路板110上，堆疊結構130設置於接地層320上。 As shown in FIG. 32 , the semiconductor device 30 includes a circuit board 110 , a ground layer 320 , a stack structure 130 , a plurality of channel structures 149 , an isolation material layer 363 and at least one conductive column 379 . The ground layer 320 is disposed on the circuit board 110 , and the stack structure 130 is disposed on the ground layer 320 .

接地層320包括一下部半導體材料層121、設置於下部半導體材料層121上的一回填半導體材料層124、及設置於回填半導體材料層121上的一上部導電層329。上部導電層329可為複合層，例如上部導電層329包括導電材料層420和絕緣材料層422。導電材料層420的材料包括金屬材料，例如是鎢。 The ground layer 320 includes a lower semiconductor material layer 121 , a backfill semiconductor material layer 124 disposed on the lower semiconductor material layer 121 , and an upper conductive layer 329 disposed on the backfill semiconductor material layer 121 . The upper conductive layer 329 may be a composite layer, for example, the upper conductive layer 329 includes a conductive material layer 420 and an insulating material layer 422 . The material of the conductive material layer 420 includes metal material, such as tungsten.

堆疊結構130包括沿著Z方向(例如第一方向)交替堆疊於接地層320上的複數個絕緣層131及複數個導電層134。通道結構149沿著Z方向(例如第一方向)貫穿堆疊結構130並延伸至接地層320中，更切確地說，接地層320包括沿著Z方向依序堆疊於電路板110上的下部半導體材料層121、回填半導體材料124及上部導電層329，通道結構149的下通道端部149b可延伸至下部半導體材料層121中。導電材料層420與通道結構149之間藉由絕緣材料所隔開，且導電材料層420環繞通道結構149。 The stack structure 130 includes a plurality of insulating layers 131 and a plurality of conductive layers 134 alternately stacked on the ground layer 320 along the Z direction (eg, the first direction). The channel structure 149 penetrates the stacked structure 130 along the Z direction (for example, the first direction) and extends into the ground layer 320. More specifically, the ground layer 320 includes the lower semiconductor material layer 121, the backfill semiconductor material 124, and the upper conductive layer 329 stacked on the circuit board 110 along the Z direction. The lower channel end 149b of the channel structure 149 can extend into the lower semiconductor material layer 121. The conductive material layer 420 is separated from the channel structure 149 by an insulating material, and the conductive material layer 420 surrounds the channel structure 149 .

根據一實施例，在Z方向(例如第一方向)上，堆疊結構130之最底層絕緣層131的一底面與上部導電層329的一底面之間具有一高度H2，高度H2大於0奈米且小於或等於60奈米(0nm<H2

60nm)，例如20~60奈米、25~55奈米或其他合適的範圍。其中，導電材料層420在第一方向上的高度可大於絕緣材料層422在第一方向上的高度。 According to an embodiment, in the Z direction (for example, the first direction), there is a height H2 between a bottom surface of the bottom insulating layer 131 of the stacked structure 130 and a bottom surface of the upper conductive layer 329, and the height H2 is greater than 0 nm and less than or equal to 60 nm (0 nm<H2

60nm), such as 20~60nm, 25~55nm or other suitable ranges. Wherein, the height of the conductive material layer 420 in the first direction may be greater than the height of the insulating material layer 422 in the first direction.

相較於沒有導電材料層做為蝕刻停止層的比較例而言，在本案一些實施例的半導體裝置中，由於係形成導電材料層作為蝕刻停止層，用於形成溝槽的蝕刻製程可安全地停止於導電材料層，亦即可精準地控制溝槽的深度，並不會有過蝕刻的問題，故在後續形成導電柱的製程中，導電柱的深度可受到良好的控制，且不易在導電柱下方生成孔隙，能夠避免導電材料透過孔隙使得導電柱與通道結構發生短路的情況，因此本案所形成的半導體裝置或可具有較佳的電特性。 Compared with the comparative example without the conductive material layer as the etch stop layer, in the semiconductor device of some embodiments of the present application, since the conductive material layer is formed as the etch stop layer, the etching process for forming the trench can be safely stopped on the conductive material layer, that is, the depth of the trench can be precisely controlled, and there is no problem of over-etching. Therefore, in the subsequent process of forming the conductive pillar, the depth of the conductive pillar can be well controlled, and it is not easy to form pores under the conductive pillar. , so the semiconductor device formed in this case may have better electrical characteristics.

綜上所述，雖然本發明已以實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。 To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

10:半導體裝置 10: Semiconductor device

110:電路板 110: circuit board

120:接地層 120: ground plane

121:下部半導體材料層 121: lower semiconductor material layer

124:回填半導體材料層 124: Backfilling the semiconductor material layer

129:上部導電層 129: upper conductive layer

130:堆疊結構 130:Stack structure

131:絕緣層 131: insulation layer

134:導電層 134: conductive layer

140:垂直開口 140: vertical opening

141:記憶膜 141: memory film

141E:頂部移除部分 141E: Top removal part

143:通道膜 143: channel membrane

145:絕緣柱 145: Insulation column

147:接墊 147: Pad

149:通道結構 149: Channel structure

149b:下通道端部 149b: end of lower channel

163:隔離材料層 163: isolation material layer

171:本體阻障層 171: Body barrier layer

173:下部導電層 173: Lower conductive layer

175:上部阻障層 175: Upper barrier layer

177:上部導體 177: Upper conductor

179:導電柱 179: Conductive column

179A:底部本體部 179A: Bottom body part

179B:中間本體部 179B: middle body part

179C:插塞 179C: plug

F1:第一表面 F1: first surface

F2:第二表面 F2: second surface

H1:高度 H1: height

S1:第一尺寸 S1: first size

S2:第二尺寸 S2: second size

S3:第三尺寸 S3: third size

S4,S5:最大尺寸 S4, S5: Maximum size

α:夾角 α: included angle

Claims

一種半導體裝置，包括：一接地層，包括一下部半導體材料層、設置於該下部半導體材料層上的一回填半導體材料層及設置於該回填半導體材料層上的一上部導電層；一堆疊結構，設置於該接地層上，且該堆疊結構包括沿著一第一方向交替堆疊的複數個絕緣層及複數個導電層；以及至少一導電柱沿著該第一方向貫穿該堆疊結構並延伸至該接地層中，其中該至少一導電柱包括彼此連接的一底部本體部、一中間本體部及一插塞，其中該底部本體部對應於該接地層，該中間本體部對應於該堆疊結構的中間及底部部分；其中，在不同於該第一方向的一第二方向上，該底部本體部之重疊於該上部導電層的部分具有一第一尺寸，該中間本體部重疊於該堆疊結構之一最底層絕緣層的部分具有一第二尺寸，該第一尺寸大於第二尺寸。 A semiconductor device, comprising: a ground layer, including a lower semiconductor material layer, a backfill semiconductor material layer arranged on the lower semiconductor material layer, and an upper conductive layer arranged on the backfill semiconductor material layer; a stack structure, arranged on the ground layer, and the stack structure includes a plurality of insulating layers and a plurality of conductive layers alternately stacked along a first direction; and at least one conductive column penetrates the stack structure along the first direction and extends into the ground layer, wherein the at least one conductive column includes a pair of connected to each other A bottom body portion, a middle body portion and a plug, wherein the bottom body portion corresponds to the ground layer, and the middle body portion corresponds to the middle and bottom portions of the stack structure; wherein, in a second direction different from the first direction, the portion of the bottom body portion overlapping the upper conductive layer has a first size, and the portion of the middle body portion overlapping a bottommost insulating layer of the stack structure has a second size, and the first size is greater than the second size.

如請求項1所述之半導體裝置，其中，在該第二方向上，該中間本體部重疊於該堆疊結構之該最底層絕緣層之上的部分具有一第三尺寸，該第一尺寸大於該第三尺寸，且該第三尺寸大於該第二尺寸。 The semiconductor device according to claim 1, wherein, in the second direction, the portion of the intermediate body portion overlapping the bottommost insulating layer of the stacked structure has a third size, the first size is larger than the third size, and the third size is larger than the second size.

如請求項1所述之半導體裝置，更包括一隔離材料層，該隔離材料層設置於該導電柱與該堆疊結構之間以及該導電柱與該接地層之間，其中在該第二方向上，該隔離材料層之重疊於該上部導電層的部分的最大尺寸大於該隔離材料層之重疊於該堆疊結構之部分的最大尺寸。 The semiconductor device according to claim 1, further comprising an isolation material layer disposed between the conductive pillar and the stack structure and Between the conductive column and the ground layer, in the second direction, the maximum dimension of the portion of the isolation material layer overlapping the upper conductive layer is greater than the maximum dimension of the portion of the isolation material layer overlapping the stacked structure.

如請求項1所述之半導體裝置，其中該中間本體部及該底部本體部包括一本體阻障層及一下部導電層，該插塞包括一上部阻障層及一上部導體，且該下部導電層的材料不同於該上部導體的材料。 The semiconductor device according to claim 1, wherein the middle body portion and the bottom body portion include a body barrier layer and a lower conductive layer, the plug includes an upper barrier layer and an upper conductor, and a material of the lower conductive layer is different from a material of the upper conductor.

如請求項1所述之半導體裝置，其中該導電柱的外側壁在鄰近於該堆疊結構之該最底層絕緣層的部分具有轉角外觀。 The semiconductor device as claimed in claim 1, wherein the outer sidewall of the conductive pillar has a corner appearance at a portion adjacent to the bottommost insulating layer of the stacked structure.

如請求項1所述之半導體裝置，更包括一電路板，該接地層設置於該電路板上。 The semiconductor device according to claim 1 further includes a circuit board, the ground layer is provided on the circuit board.

如請求項1所述之半導體裝置，更包括複數個通道結構，其中該些通道結構沿著該第一方向貫穿該堆疊結構並延伸至該接地層中。 The semiconductor device according to claim 1 further includes a plurality of channel structures, wherein the channel structures penetrate the stacked structure along the first direction and extend into the ground layer.

如請求項1所述之半導體裝置，其中在該第一方向上，該堆疊結構之該最底層絕緣層的一底面與該上部導電層的一底面之間具有一高度，該高度大於0奈米且小於或等於60奈米。 The semiconductor device according to claim 1, wherein in the first direction, there is a height between a bottom surface of the bottom insulating layer of the stacked structure and a bottom surface of the upper conductive layer, and the height is greater than 0 nm and less than or equal to 60 nm.

如請求項1所述之半導體裝置，其中在該第二方向上，該底部本體部之重疊於該回填半導體材料層的頂部突起部的部分具有該第一尺寸。 The semiconductor device as claimed in claim 1, wherein in the second direction, a portion of the bottom body portion overlapping the top protrusion portion of the backfill semiconductor material layer has the first dimension.

一種半導體裝置，包括：一接地層，包括一下部半導體材料層、設置於該下部半導體材料層上的一回填半導體材料層及設置於該回填半導體材料層上的一上部導電層；以及一堆疊結構，設置於該接地層上，且該堆疊結構包括沿著一第一方向交替堆疊的複數個絕緣層及複數個導電層；其中，該上部導電層包括一導電材料層，且該導電材料層的材料包括金屬材料。 A semiconductor device, comprising: a ground layer, including a lower semiconductor material layer, a backfill semiconductor material layer arranged on the lower semiconductor material layer, and an upper conductive layer arranged on the backfill semiconductor material layer; and a stack structure, arranged on the ground layer, and the stack structure includes a plurality of insulating layers and a plurality of conductive layers alternately stacked along a first direction; wherein, the upper conductive layer includes a conductive material layer, and the material of the conductive material layer includes a metal material.

一種半導體裝置的製作方法，包括：提供一多層結構於一電路板上，該多層結構包括沿著一第一方向依序堆疊於該電路板上的一下部半導體材料層、一第一層間絕緣層、一中間半導體材料層、一第二層間絕緣層及一上部導電層；在該上部導電層中形成一導電材料層，其中該導電材料層包括金屬材料；在該上部導電層上形成一層疊體，該層疊體包括交替堆疊的複數個絕緣層及複數個犧牲層；以及在該層疊體中形成至少一溝槽，其中該至少一溝槽沿著該第一方向延伸，貫穿該層疊體並停止於該導電材料層。 A method for manufacturing a semiconductor device, comprising: providing a multilayer structure on a circuit board, the multilayer structure comprising a lower semiconductor material layer, a first interlayer insulating layer, an intermediate semiconductor material layer, a second interlayer insulating layer and an upper conductive layer sequentially stacked on the circuit board along a first direction; forming a conductive material layer in the upper conductive layer, wherein the conductive material layer includes a metal material; and forming at least one groove in the laminate, wherein the at least one groove extends along the first direction, penetrates the laminate and stops at the conductive material layer.

如請求項11所述之半導體裝置的製作方法，更包括：移除一部分的該上部導電層以形成暴露該第二層間絕緣層的一槽口；以及在該槽口中填入導電材料，以形成該導電材料層。 The method for manufacturing a semiconductor device as described in Claim 11, further comprising: removing a portion of the upper conductive layer to form a notch exposing the second interlayer insulating layer; and filling the notch with conductive material to form the conductive material layer.

如請求項12所述之半導體裝置的製作方法，更包括：在該層疊體中形成複數個垂直開口，其中該些垂直開口沿著該第一方向貫穿過該層疊體、該上部導電層、該第二層間絕緣層、該中間半導體材料層與該第一層間絕緣層，並停止於該下部半導體材料層；在各該垂直開口中依序沉積一記憶膜、一通道膜、一絕緣柱與一接墊，以形成複數個通道結構；以及移除該導電材料層並暴露該槽口。 The manufacturing method of a semiconductor device as described in claim 12, further comprising: forming a plurality of vertical openings in the stack, wherein the vertical openings pass through the stack, the upper conductive layer, the second interlayer insulating layer, the intermediate semiconductor material layer and the first interlayer insulating layer along the first direction, and stop at the lower semiconductor material layer; sequentially depositing a memory film, a channel film, an insulating column and a contact pad in each of the vertical openings to form a plurality of channel structures; and removing the conductive material layer and exposing The notch.

如請求項12所述之半導體裝置的製作方法，其中在不同於該第一方向的一第二方向上，該槽口的寬度大於該溝槽的寬度。 The method of manufacturing a semiconductor device as claimed in claim 12, wherein in a second direction different from the first direction, the width of the notch is larger than the width of the trench.

如請求項13所述之半導體裝置的製作方法，更包括：在該溝槽的側壁、該槽口的側壁上形成一間隔結構，該間隔結構包括複數個絕緣膜；形成貫穿該第二層間絕緣層並暴露該中間半導體材料層的一缺口；透過該溝槽、該槽口與該缺口移除該中間半導體材料層，從而形成一狹縫；移除該記憶膜之一部分、該第一層間絕緣層、該第二層間絕緣層、及部分的該些絕緣膜；在該下部半導體材料層與該上部導電層之間形成一回填半導體材料層，該下部半導體材料層、該回填半導體材料層與該上部導電層形成一接地層；移除部分的該回填半導體材料層以形成一延伸開口；以及移除剩餘的該些絕緣膜，並在該槽口及該延伸開口的側壁上及該延伸開口的底部上形成一保護層。 The method for manufacturing a semiconductor device according to claim 13, further comprising: forming a spacer structure on the sidewall of the trench and the sidewall of the notch, the spacer structure including a plurality of insulating films; forming a gap that penetrates the second interlayer insulating layer and exposes the intermediate semiconductor material layer; removing a part of the memory film, the first interlayer insulating layer, the second interlayer insulating layer, and parts of the insulating films; forming a backfill semiconductor material layer between the lower semiconductor material layer and the upper conductive layer, the lower semiconductor material layer, the backfill semiconductor material layer and the upper conductive layer forming a ground layer; removing part of the backfill semiconductor material layer to form an extended opening; an insulating film, and a protective layer is formed on the sidewalls of the notch and the extended opening and the bottom of the extended opening.

如請求項15所述之半導體裝置的製作方法，更包括：透過該溝槽移除該層疊體之該些犧牲層，形成該些絕緣層之間的複數個空間；以導電材料填充該些空間，形成在該些絕緣層之間的複數個導電層，並形成包括沿著該第一方向交替堆疊的該些絕緣層及該些導電層的一堆疊結構；形成介於該些絕緣層與該些導電層之間的複數個凹室；形成一隔離材料層於該些凹室、該溝槽、該槽口及該延伸開口中；移除該延伸開口底部的部分的該隔離材料層和該保護層，並暴露出該接地層；以及形成一導電柱於該隔離材料層與該接地層之間。 The method for manufacturing a semiconductor device as described in claim 15, further comprising: removing the sacrificial layers of the stacked body through the trench to form a plurality of spaces between the insulating layers; filling the spaces with a conductive material to form a plurality of conductive layers between the insulating layers, and forming a stack structure including the insulating layers and the conductive layers alternately stacked along the first direction; forming a plurality of recesses between the insulating layers and the conductive layers; in the groove, the notch and the extension opening; removing the isolation material layer and the protection layer at the bottom of the extension opening to expose the ground layer; and forming a conductive post between the isolation material layer and the ground layer.

如請求項16所述之半導體裝置的製作方法，其中該導電柱的形成方法更包括：使一本體阻障層襯裡式地形成於該堆疊結構上及該溝槽、該槽口及該延伸開口中；移除該堆疊結構上多餘的該本體阻障層；形成一下部導電層於該溝槽、該槽口及該延伸開口中；以及移除位於該溝槽之上部中的部分該隔離材料層、該本體阻障層、該下部導電層，以形成一上部開口，於該上部開口中形成一插塞。 The method for manufacturing a semiconductor device as described in claim 16, wherein the forming method of the conductive pillar further comprises: forming a body barrier layer as a lining on the stacked structure and in the trench, the notch and the extended opening; removing the excess body barrier layer on the stacked structure; forming a lower conductive layer in the trench, the notch and the extended opening; A plug is formed in the upper opening.

如請求項17所述之半導體裝置的製作方法，其中該記憶膜被移除的該部分包括一頂部移除部分，該至少一導電柱包括彼此連接的一底部本體部、一中間本體部及一插塞，其中，與該頂部移除部分對應的該底部本體部具有一第一尺寸，在不同於該第一方向的一第二方向上，該中間本體部重疊於該堆疊結構之一最底層絕緣層的部分具有一第二尺寸，該第一尺寸大於第二尺寸。 The manufacturing method of a semiconductor device as described in claim 17, wherein the portion where the memory film is removed includes a top removal portion, and the at least one conductive pillar includes a bottom body portion, a middle body portion and a plug connected to each other, wherein the bottom body portion corresponding to the top removal portion has a first size, and in a second direction different from the first direction, a portion of the middle body portion overlapping a bottommost insulating layer of the stacked structure has a second size, and the first size is greater than the second size.

如請求項11所述之半導體裝置的製作方法，更包括：移除一部分的該上部導電層以形成暴露該第二層間絕緣層的複數個孔洞；以及在該些孔洞中填入絕緣材料。 The manufacturing method of the semiconductor device as claimed in claim 11, further comprising: removing a part of the upper conductive layer to form a plurality of holes exposing the second interlayer insulating layer; and filling the holes with insulating material.

如請求項11所述之半導體裝置的製作方法，更包括：在該層疊體中形成複數個垂直開口，其中該些垂直開口沿著該第一方向貫穿過該層疊體、該上部導電層、該第二層間絕緣層、該中間半導體材料層與該第一層間絕緣層，並停止於該下部半導體材料層；以及在各該垂直開口中依序沉積一記憶膜、一通道膜、一絕緣柱與一接墊，以形成複數個通道結構，其中該導電材料層環繞該些通道結構。 The method for manufacturing a semiconductor device as described in Claim 11, further comprising: forming a plurality of vertical openings in the stack, wherein the vertical openings pass through the stack, the upper conductive layer, the second interlayer insulating layer, the intermediate semiconductor material layer, and the first interlayer insulating layer along the first direction, and stop at the lower semiconductor material layer; some channel structures.