TWI807786B - Display panel - Google Patents
Display panel Download PDFInfo
- Publication number
- TWI807786B TWI807786B TW111114681A TW111114681A TWI807786B TW I807786 B TWI807786 B TW I807786B TW 111114681 A TW111114681 A TW 111114681A TW 111114681 A TW111114681 A TW 111114681A TW I807786 B TWI807786 B TW I807786B
- Authority
- TW
- Taiwan
- Prior art keywords
- transistor
- terminal
- coupled
- receives
- control
- Prior art date
Links
Images
Landscapes
- Electrochromic Elements, Electrophoresis, Or Variable Reflection Or Absorption Elements (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Illuminated Signs And Luminous Advertising (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
Description
本發明是有關於一種顯示面板。 The invention relates to a display panel.
對於發光二極體(light emitting diode，LED)顯示裝置而言，脈波寬度調變(pulse width modulation，PWM)驅動架構相較於脈波振幅調變(pulse amplitude modulation，PAM)驅動架構，在色彩偏移(color shift)與功率消耗上都有較佳的表現。因此，PWM驅動架構通常被應用在高階的LED顯示裝置。然而，現有的PWM驅動架構仍面臨許多技術問題有待解決，其中掃除(sweep)信號用於發光控制容易使得亮度不均勻(mura)現象變得嚴重。在無邊框(zero border)設計中，採用雙驅動電路甚至四驅動電路的架構來解決亮度不均勻現象的效果有限。若要繼續增加驅動電路的數量則會大幅增加電路的複雜度與製程難度。有鑑於此，針對上述技術問題，有必要找尋其他更為有效的解決方案。 For light emitting diode (LED) display devices, the pulse width modulation (PWM) driving architecture has better performance in terms of color shift and power consumption than the pulse amplitude modulation (PAM) driving architecture. Therefore, the PWM driving architecture is usually applied in high-end LED display devices. However, the existing PWM driving architecture still faces many technical problems to be solved, wherein the use of the sweep signal for light emission control tends to cause serious brightness non-uniformity (mura). In a zero border design, the effect of adopting the architecture of dual driving circuits or even four driving circuits to solve the phenomenon of uneven brightness is limited. To continue to increase the number of driving circuits will greatly increase the complexity of the circuit and the difficulty of manufacturing. In view of this, it is necessary to find other more effective solutions to the above-mentioned technical problems.
本發明實施例係揭露一種顯示面板。顯示面板包括複數個畫素電路及一或多個驅動電路。該些驅動電路耦接至該些畫素電路。各該驅動電路包括複數級第一子電路及複數級第二子電路。第i級的該第一子電路耦接至第i級的該第二子電路，i為正 整數。第i級的該第一子電路包括一第一電晶體、一第二電晶體、一第三電晶體及一第一電容器。該第一電晶體的一控制端接收來自第i級的該第二子電路的第i級的一發光控制信號，該第一電晶體的一第一端接收一第一偏壓，該第二電晶體的一第一端接收一第二偏壓，該第二電晶體的一控制端接收一開關控制電壓，該第二電晶體的一第二端，並用以產生第i級的一掃除信號，該第三電晶體的一第一端耦接至該第二電晶體的該第二端，該第三電晶體的一控制端耦接至該第一電晶體的一第二端，該第三電晶體的一第二端接收一第三偏壓，該第一電容器的一第一端耦接至該第一電晶體的該第二端，該電容器的一第二端接收一全域掃除時脈信號，該全域掃除時脈信號為三角波。 The embodiment of the invention discloses a display panel. The display panel includes a plurality of pixel circuits and one or more driving circuits. The driving circuits are coupled to the pixel circuits. Each of the drive circuits includes a plurality of first sub-circuits and a plurality of second sub-circuits. The first sub-circuit of the i-th stage is coupled to the second sub-circuit of the i-th stage, i is positive integer. The first sub-circuit of the i-th stage includes a first transistor, a second transistor, a third transistor and a first capacitor. A control end of the first transistor receives a light emission control signal from the i-th stage of the second sub-circuit of the i-th stage, a first end of the first transistor receives a first bias voltage, a first end of the second transistor receives a second bias voltage, a control end of the second transistor receives a switching control voltage, a second end of the second transistor is used to generate a sweep signal of the i-th stage, a first end of the third transistor is coupled to the second end of the second transistor, a control end of the third transistor is coupled to To a second end of the first transistor, a second end of the third transistor receives a third bias voltage, a first end of the first capacitor is coupled to the second end of the first transistor, a second end of the capacitor receives a global sweep clock signal, and the global sweep clock signal is a triangular wave.
為了對本發明之上述及其他方面有更佳的瞭解，下文特舉實施例，並配合所附圖式詳細說明如下： In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given in detail with the accompanying drawings as follows:
10、20:顯示面板 10, 20: display panel
102、202:主動區域 102, 202: active area
104-1、104-2、204-1、204-2、30:驅動電路 104-1, 104-2, 204-1, 204-2, 30: drive circuit
106、206、600、700:畫素電路 106, 206, 600, 700: pixel circuit
301-1~301-n、401-i、701-i:第一子電路 301-1~301-n, 401-i, 701-i: the first sub-circuit
302-1~302-:第二子電路 302-1~302-: the second sub-circuit
CKE:第一發光時脈信號 CKE: The first luminescent clock signal
XCKE:第二發光時脈信號 XCKE: The second luminescent clock signal
GSWEEP:全域掃除時脈信號 GSWEEP: global sweep clock signal
EM[1]~EM[n]、EM[i]、EM[i-1]:發光控制信號 EM[1]~EM[n], EM[i], EM[i-1]: light control signal
SWEEP[1]~SWEEP[n]、SWEEP[i]:掃除信號 SWEEP[1]~SWEEP[n], SWEEP[i]: sweep signal
T1~T19:電晶體 T1~T19: Transistor
C1~C5:電容器 C1~C5: Capacitor
STV:起始信號 STV: start signal
601:發光元件 601: Light emitting element
602:PAM控制區塊 602: PAM control block
SVGH:第一偏壓 SVGH: first bias
VGH:第二偏壓 VGH: second bias voltage
VSS:第三偏壓 VSS: the third bias voltage
VGL:第四偏壓 VGL: fourth bias voltage
VDD_PWM:第五偏壓 VDD_PWM: fifth bias voltage
VDD_PAM:第六偏壓 VDD_PAM: the sixth bias voltage
CT[i]:控制信號 CT[i]: control signal
Vop:開關控制電壓 Vop: switch control voltage
603、703:PWM控制區塊 603, 703: PWM control block
第1圖繪示根據本發明一實施例的顯示面板的示意圖；第2圖繪示根據本發明另一實施例的顯示面板的示意圖；第3圖繪示根據本發明一實施例的驅動電路的電路方塊圖；第4圖繪示根據本發明一實施例的第一子電路與第二子電路的電路圖；第5圖繪示根據本發明一實施例的信號時序圖； 第6A圖繪示根據本發明一實施例的畫素電路與第二子電路的電路方塊圖；第6B圖繪示根據本發明一實施例的訊號時序圖；第7圖繪示根據本發明另一實施例的畫素電路與第二子電路的電路方塊圖。 FIG. 1 shows a schematic diagram of a display panel according to an embodiment of the present invention; FIG. 2 shows a schematic diagram of a display panel according to another embodiment of the present invention; FIG. 3 shows a circuit block diagram of a driving circuit according to an embodiment of the present invention; FIG. 4 shows a circuit diagram of a first sub-circuit and a second sub-circuit according to an embodiment of the present invention; FIG. 5 shows a signal timing diagram according to an embodiment of the present invention; FIG. 6A shows a circuit block diagram of a pixel circuit and a second sub-circuit according to an embodiment of the present invention; FIG. 6B shows a signal timing diagram according to an embodiment of the present invention; FIG. 7 shows a circuit block diagram of a pixel circuit and a second sub-circuit according to another embodiment of the present invention.
請參照第1圖，第1圖繪示根部本發明一實施例的顯示面板的示意圖。顯示面板10包括一主動區域(active area，AA)102以及一或多個驅動電路104-1、104-2。主動區域102包括多個畫素電路106。驅動電路104-1、104-2係配置於主動區域102之外的空間，並且耦接至畫素電路106，以及用以驅動畫素電路106。在顯示面板10中，驅動電路104-1、104-2所在的空間通常是做為邊框(border)。
Please refer to FIG. 1 , which is a schematic diagram of a display panel according to an embodiment of the present invention. The
請參照第2圖，第2圖繪示根據本發明另一實施例的顯示面板的示意圖。顯示面板20包括一主動區域202以及一或多個驅動電路204-1、204-2。主動區域202包括多個畫素電路206。驅動電路204-1、204-2係配置於主動區域202之內，並且耦接至畫素電路206，以及用以驅動畫素電路206。在顯示面板20中，由於驅動電路204-1、204-2是配置在主動區域之內，故而顯示面板20通常適用於無邊框設計(zero border design)。
Please refer to FIG. 2 , which is a schematic diagram of a display panel according to another embodiment of the present invention. The
請參照第3圖，第3圖繪示根據本發明一實施例的驅動電路的方塊圖。驅動電路30包括多級第一子電路301-1~301-n以及多級第二子電路302-1~302-n。第i級第一子電路301-i耦接至第i級第二子電路
302-i，其中i=1、2、...、n。第i級第一子電路301-i用以根據一全域掃除時脈信號GSWEEP及一第i級發光控制信號EM[i]產生一第i級掃除信號SWEEP[i]。
Please refer to FIG. 3 , which is a block diagram of a driving circuit according to an embodiment of the present invention. The
第一級第二子電路302-1用以根據一第一發光時脈信號CKE、一第二發光時脈信號XCKE以及一起始信號STV產生一第一級發光控制信號EM[1]。第j級第二子電路302-j耦接至第(j-1)級第二子電路302-(j-1)，其中j=2、3、...、n。第j級第二子電路302-j用以根據第一發光時脈信號CKE、第二發光時脈信號XCKE以及第(j-1)級發光控制信號EM[j-1]產生第j級發光控制信號EM[j]。 The first-stage second sub-circuit 302-1 is used for generating a first-stage light-emitting control signal EM[1] according to a first light-emitting clock signal CKE, a second light-emitting clock signal XCKE, and a start signal STV. The j-th stage second sub-circuit 302-j is coupled to the (j-1)-th stage second sub-circuit 302-(j-1), where j=2, 3, . . . , n. The j-th stage second sub-circuit 302-j is used to generate the j-stage light emission control signal EM[j] according to the first light emission clock signal CKE, the second light emission clock signal XCKE and the (j-1) stage light emission control signal EM[j-1].
在一實施例中，起始信號STV、全域掃除時脈信號GSWEEP、第一發光時脈信號CKE及第二發光時脈信號XCKE可由一控制晶片(未繪出)產生並傳送至驅動電路30。
In one embodiment, the start signal STV, the global sweep clock signal GSWEEP, the first light-emitting clock signal CKE and the second light-emitting clock signal XCKE can be generated by a control chip (not shown) and sent to the
請參照第4圖，第4圖繪示根據本發明一實施例的第一子電路與第二子電路的電路圖。第一子電路401-i可用以實現任一級的第一子電路301-i，第二子電路402-i可用以實現任一級的第二子電路302-i。 Please refer to FIG. 4 , which shows a circuit diagram of a first sub-circuit and a second sub-circuit according to an embodiment of the present invention. The first sub-circuit 401-i can be used to realize the first sub-circuit 301-i of any stage, and the second sub-circuit 402-i can be used to realize the second sub-circuit 302-i of any stage.
第一子電路401-i包括多個電晶體T8~T10以及一電容器C3。電晶體T8的一控制端(即閘極)接收第i級發光控制信號EM[i]。電晶體T8的一第一端接收一第一偏壓SVGH(例如7.5V)。電晶體T9的一第一端接收一第二偏壓VGH(例如15V)。電晶體T9的一控制端接收一開關控制電壓Vop(例如12.5v)。電晶體T9的一第二端，並用以產生第i級掃除信號SWEEP[i]。電晶體T10的一第一端耦接至電晶體T9的第二 端。電晶體T10的一控制端耦接至電晶體T8的一第二端。電晶體T10的一第二端接收一第三偏壓VSS(例如0V)。電容器C3的一第一端耦接至電晶體T8的第二端。電容器C3的一第二端接收全域掃除時脈信號GSWEEP。掃除信號SWEEP[i]可出輸出至其中一列(row)的畫素電路。 The first sub-circuit 401-i includes a plurality of transistors T8-T10 and a capacitor C3. A control terminal (ie, the gate) of the transistor T8 receives the ith-level light emission control signal EM[i]. A first terminal of the transistor T8 receives a first bias voltage SVGH (for example, 7.5V). A first end of the transistor T9 receives a second bias voltage VGH (for example, 15V). A control terminal of the transistor T9 receives a switch control voltage Vop (for example, 12.5v). A second terminal of the transistor T9 is used to generate the i-th level sweep signal SWEEP[i]. A first end of the transistor T10 is coupled to a second end of the transistor T9 end. A control terminal of the transistor T10 is coupled to a second terminal of the transistor T8. A second terminal of the transistor T10 receives a third bias voltage VSS (for example, 0V). A first terminal of the capacitor C3 is coupled to a second terminal of the transistor T8. A second terminal of the capacitor C3 receives the global sweep clock signal GSWEEP. The sweeping signal SWEEP[i] can be output to the pixel circuit of one row.
第二子電路402-i包括多個電晶體T1~T7以及多個電容器C1~C2。電晶體T1的一第一端接收起始信號STV(i=1)或發光控制信號EM[i-1](i=2、3、...、n)。電晶體T1的一控制端接收第一發光時脈信號CKE及第二發光時脈信號XCKE其中之一。電晶體T2的一控制端耦接至電晶體T1的一第二端。電晶體T2的一第一端接收第四偏壓VGL(例如-5V)。電晶體T3的一第一端耦接至電晶體T2的一第二端，並用以產生發光控制信號EM[i]。電晶體T3的一第二端接收第二偏壓VGH。電晶體T4的一第一端耦接至電晶體T1的第二端。電晶體T4的一第二端接收第二偏壓VGH。電晶體T5的一第一端接收第四偏壓VGL。電晶體T5的一第二端耦接至電晶體T3的一控制端及電晶體T4的一控制端。電晶體T6的一第一端耦接至電晶體T5的第二端。電晶體T6的一第二端接收第四偏壓VGL。電晶體T6的一控制端耦接至電晶體T1的第二端。電晶體T7的一第一端耦接至電晶體T5的一控制端。電晶體T7的一第二端接收第四偏壓VGL。電晶體T7的一控制端耦接至電晶體T1的第一端。電容器C1的一第一端接收第一發光時脈信號CKE及第二發光時脈信號XCKE其中之一(相同於電晶體T1的控制端接收的信號)。電容器C1的一第二端耦接至電晶體T5的控制端。電容器C2的一第一端接收第一發光時脈信號CKE及第二發光時脈信號XCKE其中另一(不同於電 晶體T1的控制端接收的信號)。電容器C2的一第二端耦接至電晶體T2的控制端。 The second sub-circuit 402-i includes a plurality of transistors T1-T7 and a plurality of capacitors C1-C2. A first end of the transistor T1 receives a start signal STV (i=1) or an emission control signal EM[i−1] (i=2, 3, . . . , n). A control terminal of the transistor T1 receives one of the first light emitting clock signal CKE and the second light emitting clock signal XCKE. A control terminal of the transistor T2 is coupled to a second terminal of the transistor T1. A first end of the transistor T2 receives a fourth bias voltage VGL (eg -5V). A first terminal of the transistor T3 is coupled to a second terminal of the transistor T2 for generating the light emission control signal EM[i]. A second terminal of the transistor T3 receives the second bias voltage VGH. A first terminal of the transistor T4 is coupled to a second terminal of the transistor T1. A second terminal of the transistor T4 receives the second bias voltage VGH. A first terminal of the transistor T5 receives the fourth bias voltage VGL. A second terminal of the transistor T5 is coupled to a control terminal of the transistor T3 and a control terminal of the transistor T4. A first terminal of the transistor T6 is coupled to a second terminal of the transistor T5. A second terminal of the transistor T6 receives the fourth bias voltage VGL. A control terminal of the transistor T6 is coupled to the second terminal of the transistor T1. A first terminal of the transistor T7 is coupled to a control terminal of the transistor T5. A second terminal of the transistor T7 receives the fourth bias voltage VGL. A control terminal of the transistor T7 is coupled to the first terminal of the transistor T1. A first terminal of the capacitor C1 receives one of the first light-emitting clock signal CKE and the second light-emitting clock signal XCKE (the same signal received by the control terminal of the transistor T1 ). A second terminal of the capacitor C1 is coupled to the control terminal of the transistor T5. A first terminal of the capacitor C2 receives the other of the first light-emitting clock signal CKE and the second light-emitting clock signal XCKE (different from the electric The signal received by the control terminal of crystal T1). A second terminal of the capacitor C2 is coupled to the control terminal of the transistor T2.
在一實施例中，第二子電路402-i進一步包括一重置電晶體Tres。重置電晶體Tres的一第一端接收第四偏壓VGL。重置電晶體Tres的一第二端耦接至電晶體T4的控制端。重置電晶體Tres的一控制端接收一重置信號RESET。 In one embodiment, the second sub-circuit 402-i further includes a reset transistor Tres. A first terminal of the reset transistor Tres receives the fourth bias voltage VGL. A second terminal of the reset transistor Tres is coupled to the control terminal of the transistor T4. A control terminal of the reset transistor Tres receives a reset signal RESET.
在本實施例的第一子電路的架構下，所有級的第一子電路可共用一個全域掃除時脈信號，來產生不同相(phase)的掃除信號。而現有技術中，若要產生不同相的掃除信號，需要使用到多個不同相的掃除時脈信號。第一子電路401-i的主要功能係將交流(AC)的小信號轉換為直流(DC)的電流源來提供穩定的掃除信號推動負載。 Under the architecture of the first sub-circuit in this embodiment, the first sub-circuits of all stages can share a global sweep clock signal to generate sweep signals of different phases. However, in the prior art, to generate sweeping signals of different phases, multiple sweeping clock signals of different phases need to be used. The main function of the first sub-circuit 401-i is to convert a small alternating current (AC) signal into a direct current (DC) current source to provide a stable sweep signal to drive the load.
請參照第5圖，第5圖繪示根據本發明一實施例的信號時序圖。從第5圖中可看出，全域掃除時脈信號GSWEEP為三角波。當發光控制信號EM[i]處於低電壓準位(例如0V)時，掃除信號SWEEP[i]會維持在一第一電壓V1，而在發光控制信號EM[i]處於高電壓準位(例如>0V)的期間，掃除信號SWEEP[i]會從第一電壓V1開始下降到一第二電壓V2，下降的斜率會相同於全域掃除時脈信號GSWEEP的斜率。在本實施例中，第一電壓V1為10V，第二電壓V2為5V。也就是說，第一子電路401-i係透過根據發光控制信號EM[i]控制電晶體T8的導通與否，決定是否耦合全域掃除時脈信號GSEEP，並透過電晶體T9、T10組成的源隨耦(source fallower)系統在掃除信號SWEEP[i]上「複製」出全域掃除時脈信號GSWEEP的斜率。 Please refer to FIG. 5 , which shows a signal timing diagram according to an embodiment of the present invention. It can be seen from FIG. 5 that the global sweep clock signal GSWEEP is a triangular wave. When the light emission control signal EM[i] is at a low voltage level (for example, 0V), the sweep signal SWEEP[i] will maintain a first voltage V1, and when the light emission control signal EM[i] is at a high voltage level (for example, >0V), the sweep signal SWEEP[i] will drop from the first voltage V1 to a second voltage V2, and the falling slope will be the same as the slope of the global sweep clock signal GSWEEP. In this embodiment, the first voltage V1 is 10V, and the second voltage V2 is 5V. That is to say, the first sub-circuit 401-i controls whether the transistor T8 is turned on or not according to the light emission control signal EM[i], determines whether to couple the global sweep clock signal GSEEP, and “replicates” the slope of the global sweep clock signal GSWEEP on the sweep signal SWEEP[i] through the source follower system composed of the transistors T9 and T10.
在這樣的第一子電路的架構下，第二子電路並不限於第4圖所繪示的例子。 Under such a structure of the first sub-circuit, the second sub-circuit is not limited to the example shown in FIG. 4 .
另一方面，為了解決從輸出掃除信號SWEEP[i]的節點會看到(需要推動)高RC負載的問題，本發明針對畫素電路的PWM控制區塊亦進行改善。 On the other hand, in order to solve the problem that the node outputting the sweep signal SWEEP[i] will see (need to push) a high RC load, the present invention also improves the PWM control block of the pixel circuit.
請參照第6A圖，第6A圖繪示根據本發明一實施例的第一子電路及畫素電路的電路圖方塊圖。請搭配第6B圖的訊號時序圖以利理解。 Please refer to FIG. 6A . FIG. 6A shows a circuit block diagram of a first sub-circuit and a pixel circuit according to an embodiment of the present invention. Please match the signal timing diagram in Figure 6B for easy understanding.
畫素電路600包括一發光元件601、一PAM控制區塊602及一PWM控制區塊603。畫素電路600例如是屬於第i列。第六偏壓VDD_PAM為供應PAM區塊運作的電壓。
The
發光元件601的一第一端接收第三偏壓VSS。發光元件601可為任何適用的發光二極體(light emitting diode，LED)。
A first end of the
PAM控制區塊602耦接至發光元件601，用以根據一PAM控制信號(未繪示)決定發光元件601發光的亮度。需要注意的是，PAM控制區塊602可採用任何適用的電路設計，本發明不予以限定。
The
PWM控制區塊603包括電晶體T11~T17及電容器C4~C5。電晶體T11的一控制端接收掃除信號SWEEP[i]。電晶體T11的一第一端接收第三偏壓VSS。電晶體T12的一第一端耦接至電晶體T11的一第二端。電晶體T12的一第二端接收第二偏壓VGH。電晶體T12的一控制端接收開關控制電壓Vop。電容器C4的一第一端耦接至電晶體T11的第二端。電晶體T13的一第一端耦接至電容器C4的一第二端。
電晶體T13的一第二端接收第一偏壓SVGH。電晶體T13的一控制端接收一信號SEN[i]。電容器C5的一第一端耦接至電容器C4的第二端。電晶體T14的一第一端耦接至電容器C5的一第二端。電晶體T14的一第二端接收電壓VST。電晶體T14的一控制端耦接至電晶體T14的第二端。電晶體T15的一控制端耦接至電容器C5的第二端。電晶體T15的一第一端耦接至PAM控制區塊602。電晶體T15的一第二端接收一第五偏壓VDD_PWM。電晶體T16的一第一端耦接至電容器C5的第二端。電晶體T16的一第二端耦接至電晶體T15的第一端。電晶體T16的一控制端接收信號SPWM[i]。電晶體T17的一第一端耦接至電晶體T15的第二端。電晶體T17的一第二端接收信號Sig。電晶體T17的一控制端接收信號SPWM[i]。
The PWM control block 603 includes transistors T11-T17 and capacitors C4-C5. A control terminal of the transistor T11 receives the sweep signal SWEEP[i]. A first end of the transistor T11 receives the third bias voltage VSS. A first terminal of the transistor T12 is coupled to a second terminal of the transistor T11. A second end of the transistor T12 receives the second bias voltage VGH. A control terminal of the transistor T12 receives the switch control voltage Vop. A first terminal of the capacitor C4 is coupled to the second terminal of the transistor T11. A first terminal of the transistor T13 is coupled to a second terminal of the capacitor C4.
A second end of the transistor T13 receives the first bias voltage SVGH. A control terminal of the transistor T13 receives a signal SEN[i]. A first terminal of the capacitor C5 is coupled to a second terminal of the capacitor C4. A first terminal of the transistor T14 is coupled to a second terminal of the capacitor C5. A second terminal of the transistor T14 receives the voltage VST. A control terminal of the transistor T14 is coupled to a second terminal of the transistor T14. A control terminal of the transistor T15 is coupled to a second terminal of the capacitor C5. A first terminal of the transistor T15 is coupled to the
在本實施例中，PWM控制區塊603係在畫素電壓寫入階段更新畫素資料，接著在發光階段透過電晶體T11、T12組成的源隨耦系統將掃除信號SWEEP[i]的斜率擷取出來，並透過電容器C4與電晶體T13組成的耦合系統將擷取出來的信號耦合至電容器C5而產生具有相同斜率的訊號SWEEP[Pixel]。 In this embodiment, the PWM control block 603 updates the pixel data during the pixel voltage write-in phase, and then extracts the slope of the sweep signal SWEEP[i] through the source-following coupling system composed of the transistors T11 and T12 during the light-emitting phase, and couples the extracted signal to the capacitor C5 through the coupling system composed of the capacitor C4 and the transistor T13 to generate a signal SWEEP[Pixel] with the same slope.
請參照第7圖，第7圖繪示根據本發明另一實施例的第一子電路及畫素電路的電路方塊圖。相較於第一子電路401-i，第一子電路701-i進一步包括一電晶體T18。電晶體T10的第二端係通過電晶體T18接收第三偏壓VSS。電晶體T18的一控制端接收一控制信號CT[i]。 Please refer to FIG. 7 , which is a circuit block diagram of a first sub-circuit and a pixel circuit according to another embodiment of the present invention. Compared with the first sub-circuit 401-i, the first sub-circuit 701-i further includes a transistor T18. The second terminal of the transistor T10 receives the third bias voltage VSS through the transistor T18. A control terminal of the transistor T18 receives a control signal CT[i].
相較於及畫素電路600，畫素電路700進一步包括一電晶體T19。電晶體T11的第一端係通過電晶體T19接收第三偏壓VSS。電晶體T19的一控制端接收控制信號CT[i]。
Compared with the
控制信號CT[i]經過配置以使得電晶體T18、T19於第i列的畫素電路不工作(例如不執行發光任務)時關閉，且於第i列的畫素電路工作(執行發光任務)時導通。 The control signal CT[i] is configured so that the transistors T18 and T19 are turned off when the pixel circuit in the i-th column is not working (for example, not performing a light-emitting task), and turned on when the pixel circuit in the i-th column is working (performing a light-emitting task).
在本實施例中，藉由控制電晶體T18、T19只在第i列畫素電路運作時導通，可以減少不必要的功率消耗。 In this embodiment, unnecessary power consumption can be reduced by controlling the transistors T18 and T19 to be turned on only when the i-th pixel circuit is in operation.
需要注意的是，在替代的實施例中，可僅在第一子電路中配置電晶體T18，而在畫素電路中不配置電晶體T19，亦或者僅在畫素電路中配置電晶體T19，而在第一子電路中不配置電晶體T18。 It should be noted that, in an alternative embodiment, only the transistor T18 may be configured in the first sub-circuit, and the transistor T19 may not be configured in the pixel circuit, or only the transistor T19 may be configured in the pixel circuit, and the transistor T18 may not be configured in the first sub-circuit.
綜上所述，雖然本發明已以實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。 To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.
401-i:第一子電路 401-i: first subcircuit
402-i:第二子電路 402-i: Second sub-circuit
T1~T10:電晶體 T1~T10: Transistor
C1~C3:電容器 C1~C3: Capacitor
SWEEP[i]:掃除信號 SWEEP[i]: sweep signal
CKE:第一發光時脈信號 CKE: The first luminescent clock signal
XCKE:第二發光時脈信號 XCKE: The second luminescent clock signal
GSWEEP:全域掃除時脈信號 GSWEEP: global sweep clock signal
EM[i]、EM[i-1]:發光控制信號 EM[i], EM[i-1]: lighting control signal
STV:起始信號 STV: start signal
SVGH:第一偏壓 SVGH: first bias
VGH:第二偏壓 VGH: second bias voltage
VSS:第三偏壓 VSS: the third bias voltage
VGL:第四偏壓 VGL: fourth bias voltage
Vop:開關控制電壓 Vop: switch control voltage
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW111114681A TWI807786B (en) | 2022-04-18 | 2022-04-18 | Display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW111114681A TWI807786B (en) | 2022-04-18 | 2022-04-18 | Display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TWI807786B true TWI807786B (en) | 2023-07-01 |
| TW202343413A TW202343413A (en) | 2023-11-01 |
Family
ID=88149207
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW111114681A TWI807786B (en) | 2022-04-18 | 2022-04-18 | Display panel |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI807786B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019214304A1 (en) * | 2018-05-09 | 2019-11-14 | 京东方科技集团股份有限公司 | Pixel circuit and driving method thereof, display substrate, and display device |
| TW202001851A (en) * | 2018-06-06 | 2020-01-01 | 日商日本顯示器股份有限公司 | Display device and display device drive method |
| US20210375185A1 (en) * | 2019-03-29 | 2021-12-02 | Samsung Electronics Co., Ltd. | Display panel and driving method of the display panel |
-
2022
- 2022-04-18 TW TW111114681A patent/TWI807786B/en active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019214304A1 (en) * | 2018-05-09 | 2019-11-14 | 京东方科技集团股份有限公司 | Pixel circuit and driving method thereof, display substrate, and display device |
| TW202001851A (en) * | 2018-06-06 | 2020-01-01 | 日商日本顯示器股份有限公司 | Display device and display device drive method |
| US20210375185A1 (en) * | 2019-03-29 | 2021-12-02 | Samsung Electronics Co., Ltd. | Display panel and driving method of the display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| TW202343413A (en) | 2023-11-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP2672479B1 (en) | Gate on array driver unit, gate on array driver circuit, and display device | |
| TWI534781B (en) | Scan drive circuit and organic light shower display | |
| US9113534B2 (en) | Light-emitting control circuit, light-emitting control method and shift register | |
| US20170116926A1 (en) | Scan driver, display device, and method of driving display device | |
| WO2021000233A1 (en) | Display panel and display device | |
| WO2023005661A1 (en) | Pixel circuit, drive method and display apparatus | |
| WO2021000234A1 (en) | Display panel, display device, and driving method | |
| US10140930B2 (en) | Signal generating unit, shift register, display device and signal generating method | |
| CN112820234B (en) | Shift register circuit and display device | |
| KR20170126567A (en) | Driver for display panel and display apparatus having the same | |
| WO2021000235A1 (en) | Display panel, display device and driving method | |
| TWI799055B (en) | Pixel circuit, display panel and driving method thereof | |
| WO2023115533A1 (en) | Pixel circuit and display panel | |
| WO2021077487A1 (en) | Pixel unit and display panel | |
| CN110738964A (en) | Pixel circuit and display device | |
| WO2022233083A1 (en) | Pixel driving circuit, pixel driving method, and display device | |
| CN112735350A (en) | GIP circuit and driving method thereof | |
| TWI807786B (en) | Display panel | |
| WO2024000787A1 (en) | Scan driving circuit and display panel | |
| KR102380765B1 (en) | Gate shift register and organic light emitting display device including the same | |
| WO2020006854A1 (en) | Pixel driving circuit and display panel | |
| CN107909958B (en) | GOA circuit unit, GOA circuit and display panel | |
| KR102149945B1 (en) | Display device and method of driving the same | |
| WO2023092538A1 (en) | Shift register and driving method therefor, and light emission control driver and display apparatus | |
| US11430383B2 (en) | Light emitting device, display device, and LED display device |