TWI807667B - Three dimensional integrated circuit and fabrication thereof - Google Patents

Three dimensional integrated circuit and fabrication thereof Download PDF

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TWI807667B
TWI807667B TW111108054A TW111108054A TWI807667B TW I807667 B TWI807667 B TW I807667B TW 111108054 A TW111108054 A TW 111108054A TW 111108054 A TW111108054 A TW 111108054A TW I807667 B TWI807667 B TW I807667B
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dimensional semiconductor
layer
seeds
dielectric
dimensional
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TW202243126A (en
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正明 胡
張書睿
周承翰
何焱騰
吳家興
彭凱鈺
沈承宏
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台灣積體電路製造股份有限公司
國立陽明交通大學
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Abstract

An IC structure comprises a first transistor formed on a substrate, a first interconnect structure over the first transistor, a dielectric layer over the first interconnect structure, a plurality of 2D semiconductor islands on the dielectric layer, and a plurality of second transistors formed on the plurality of 2D semiconductor islands.

Description

積體電路結構及其製造方法 Integrated circuit structure and manufacturing method thereof

本揭露係關於一種積體電路，特別係關於三維積體電路結構及其製造方法。 The present disclosure relates to an integrated circuit, in particular to a three-dimensional integrated circuit structure and a manufacturing method thereof.

由於各種電子元件(即電晶體、二極體、電阻器、電容器等)的積體密度不斷提高，半導體工業經歷了快速增長。在很大程度上，積體密度的此種提高源於最小特徵尺寸的持續微縮。此允許更多的部件整合到單位面積中。 The semiconductor industry has experienced rapid growth due to the increasing bulk density of various electronic components (ie, transistors, diodes, resistors, capacitors, etc.). In large part, this increase in bulk density is due to the continued shrinking of the smallest feature size. This allows more components to be integrated into a unit area.

在一些實施例中，一種積體電路結構包含一第一電晶體、一第一內連接結構、一介電層、複數二維半導體島、及複數第二電晶體。第一電晶體形成在一基板上。第一內連接結構在該第一電晶體上。介電層在該內連接結構上。該些二維半導體島在該介電層上。該些第二電晶體形成在該些二維半導體島上。 In some embodiments, an integrated circuit structure includes a first transistor, a first interconnection structure, a dielectric layer, a plurality of two-dimensional semiconductor islands, and a plurality of second transistors. The first transistor is formed on a substrate. A first interconnect structure is on the first transistor. A dielectric layer is on the interconnect structure. The two-dimensional semiconductor islands are on the dielectric layer. The second transistors are formed on the two-dimensional semiconductor islands.

在一些實施例中，一種積體電路結構包含一內連接結構、一介電層、複數二維半導體種子、複數二維半導體膜、以及複數電晶體。該內連接結構在一基板上，並包含 縱向延伸於該基板上的一導電通孔及橫向延伸於該導電通孔上的一導電線。介電層在該內連接結構上。該些二維半導體種子呈多行及多列地排列於該介電層上。該些二維半導體膜分別橫向地圍繞該些二維半導體種子。該些電晶體在該些二維半導體膜上。 In some embodiments, an integrated circuit structure includes an interconnection structure, a dielectric layer, a plurality of two-dimensional semiconductor seeds, a plurality of two-dimensional semiconductor films, and a plurality of transistors. The interconnect structure is on a substrate and includes A conductive via hole extending vertically on the substrate and a conductive line extending laterally on the conductive via hole. A dielectric layer is on the interconnect structure. The two-dimensional semiconductor seeds are arranged on the dielectric layer in rows and columns. The two-dimensional semiconductor films laterally surround the two-dimensional semiconductor seeds respectively. The transistors are on the two-dimensional semiconductor films.

在一些實施例中，一種積體電路之製造方法包含形成複數第一電晶體於一基板上；形成一內連接結構於該些第一電晶體上；形成一介電層於該內連接結構上；形成複數二維半導體種子於該介電層上；對該些二維半導體種子退火；在對該些二維半導體種子退火後，進行一磊晶製程以從該些二維半導體種子分別橫向成長複數二維半導體膜；及形成複數第二電晶體於該些二維半導體膜上。 In some embodiments, a method of manufacturing an integrated circuit includes forming a plurality of first transistors on a substrate; forming an interconnection structure on the first transistors; forming a dielectric layer on the interconnection structure; forming a plurality of two-dimensional semiconductor seeds on the dielectric layer; annealing the two-dimensional semiconductor seeds;

102:基板 102: Substrate

103:鰭 103: Fins

104:元件 104: Elements

104G:閘極結構 104 G : gate structure

104GD:替換閘極介電層 104 GD : Replacement gate dielectric layer

104GM:閘極結構層 104 GM : gate structure layer

104SD:源極/汲極區 104 SD : source/drain region

104SP:間隔物 104 SP : spacer

105:STI區 105: STI area

106:內連接結構 106: Internal connection structure

1081:金屬化層 108 1 : metallization layer

108M-1:金屬化層 108 M-1 : metallization layer

108M:金屬化層 108 M : metallization layer

1100:ILD層 110 0 : ILD layer

1101:IMD層 110 1 : IMD layer

110M-1:IMD層 110 M-1 : IMD layer

110M:IMD層 110 M : IMD layer

1111:IMD層 111 1 : IMD layer

111M-1:IMD層 111 M-1 : IMD layer

111M:IMD層 111 M : IMD layer

1120:接觸窗 112 0 : contact window

1141:導線 114 1 : Wire

114M-1:導線 114 M-1 : Wire

114M:導線 114 M : Wire

1161:導電通孔 116 1 : Conductive via

116M-1:導電通孔 116 M-1 : Conductive vias

116M:導電通孔 116 M : Conductive Via

120:ILD層 120: ILD layer

120t:受處理區域 120t: Treated area

120u:未處理區域 120u: untreated area

160:虛設閘極結構 160:Dummy gate structure

160GD:虛設閘極介電質 160 GD : Dummy gate dielectric

160GP:虛設閘極材料 160 GP : Dummy gate material

160HM:硬遮罩 160 HM : hard mask

170G:閘極結構 170 G : gate structure

170GD:替換閘極介電層 170 GD : Replacement gate dielectric

170GM:替換閘極金屬層 170 GM : Replacement gate metal layer

170SD:源極/汲極區 170 SD : source/drain region

170SP:間隔物 170 SP : spacer

182:ILD層 182: ILD layer

184:ILD層 184: ILD layer

186:接觸窗 186: contact window

190:內連接結構 190: Internal connection structure

192:金屬化層 192: metallization layer

194:介電層 194: dielectric layer

196:金屬線 196: metal wire

198:金屬通孔 198: metal through hole

200:結晶基板 200: Crystalline substrate

202:二維半導體層 202: Two-dimensional semiconductor layer

204:單層 204: single layer

204X:過渡金屬原子 204X: transition metal atom

204M:硫族元素原子 204M: chalcogen atoms

206:保護膜 206: Protective film

208:熱解膠 208: pyrolytic glue

210:二維半導體種子 210: Two-dimensional semiconductor seeds

212:介電網格 212:Dielectric mesh

2122:第一網格線 2122: The first grid line

2124:第二網格線 2124: The second grid line

212o:網格單元 212o: grid unit

214:二維半導體種子 214: Two-dimensional semiconductor seeds

216:二維半導體膜 216: Two-dimensional semiconductor film

218:二維半導體島 218: Two-dimensional semiconductor island

302:含過渡金屬層 302: transition metal layer

310:含過渡金屬塊 310: containing transition metal blocks

400:遮罩層 400: mask layer

400h:開口 400h: opening

410:二維半導體種子 410: 2D Semiconductor Seeds

414:二維半導體種子 414: Two-dimensional semiconductor seeds

416:二維半導體膜 416: Two-dimensional semiconductor film

418:二維半導體島 418: Two-dimensional semiconductor island

500:遮罩層 500: mask layer

500h:開口 500h: opening

502:過渡金屬氧化物層 502: transition metal oxide layer

510:過渡金屬氧化物塊 510: transition metal oxide block

512:TMD種子 512: TMD seed

514:二維半導體種子 514: Two-dimensional semiconductor seeds

516:二維半導體膜 516: Two-dimensional semiconductor film

518:二維半導體島 518: Two-dimensional semiconductor island

AL1:退火製程 AL1: Annealing process

AL2:退火製程 AL2: Annealing process

AL3:退火製程 AL3: Annealing process

AL4:退火製程 AL4: Annealing process

AL5:退火製程 AL5: Annealing process

AL6:退火製程 AL6: Annealing process

EPI1:磊晶製程 EPI1: Epitaxy process

EPI2:磊晶製程 EPI2: Epitaxy process

EPI3:磊晶製程 EPI3: Epitaxy process

EPI4:磊晶製程 EPI4: Epitaxy process

EPI5:磊晶製程 EPI5: Epitaxy process

D1:第一方向 D1: the first direction

D2:第二方向 D2: Second direction

DL1:虛線 DL1: dotted line

GB:晶界 GB: grain boundary

GB1:晶界 GB1: Grain Boundary

GB2:晶界 GB2: Grain Boundary

W1:晶圓 W1: Wafer

本揭露之態樣在結合附圖閱讀以下詳細說明時得以最清晰地理解。應注意，依據產業中的標準實務，各種特徵不按比例繪製。事實上，各種特徵的尺寸可任意增大或減小，以便於論述明晰。 Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

第1A-11圖示出了根據一些實施例的形成三維積體電路的方法的各個中間階段的立體圖及剖面圖。 1A-11 illustrate perspective and cross-sectional views of various intermediate stages of a method of forming a three-dimensional integrated circuit in accordance with some embodiments.

第12A-14圖示出了根據一些實施例的形成三維積體電路的方法的各個中間階段的立體圖及剖面圖。 12A-14 illustrate perspective and cross-sectional views of various intermediate stages of a method of forming a three-dimensional integrated circuit in accordance with some embodiments.

第15A-17圖示出了根據一些實施例的形成三維積體電路的方法的各個中間階段的立體圖及剖面圖。 15A-17 illustrate perspective and cross-sectional views of various intermediate stages of a method of forming a three-dimensional integrated circuit in accordance with some embodiments.

第18-22圖示出了根據一些實施例的形成三維積體電路的方法的各個中間階段的立體圖及剖面圖。 Figures 18-22 illustrate perspective and cross-sectional views of various intermediate stages of a method of forming a three-dimensional integrated circuit in accordance with some embodiments.

第23-25A、26A-27A及28圖示出了根據一些實施例的形成三維積體電路的方法的各個中間階段的立體圖及剖面圖。 Figures 23-25A, 26A-27A and 28 show perspective and cross-sectional views of various intermediate stages of a method of forming a three-dimensional integrated circuit according to some embodiments.

第25B圖繪示依據一些實施例的採用第23至25A圖的步驟所產生的WS2種子的拉曼光譜(Raman spectrum)圖。 Figure 25B shows a graph of the Raman spectrum of WS 2 seeds produced using the steps of Figures 23-25A, according to some embodiments.

第27B圖繪示依據一些實施例的二維半導體種子的光致發光光譜(photoluminescence spectra)圖。 Figure 27B shows a graph of the photoluminescence spectrum of a two-dimensional semiconductor seed according to some embodiments.

第29至31A及32至34圖示出了根據本揭示案的一些其他實施例的用於製造三維積體電路的各個階段的示例性剖面圖。 Figures 29-31A and 32-34 show exemplary cross-sectional views of various stages for fabricating three-dimensional integrated circuits according to some other embodiments of the present disclosure.

第31B圖繪示依據一些實施例的由第29至31A圖的步驟所形成的WS2種子的拉曼光譜圖。 Figure 31B shows a Raman spectrum of WS 2 seeds formed by the steps of Figures 29-31A, according to some embodiments.

以下揭示案提供眾多不同實施例或實施例以用於實施本案提供標的的不同特徵。下文描述部件及配置的特定實施例以簡化本揭露。當然，此僅係實施例，並非係用於限制。例如，下文描述中第一特徵於第二特徵上方或之上的形成可包括第一特徵與第二特徵直接接觸而形成的實施例，及亦可包括第一特徵與第二特徵之間可能形成額外特徵，以使得第一特徵與第二特徵不可直接接觸的實施例。 此外，本揭露可在各種實施例中重複元件符號及/或字母。此重複係以簡單與明晰為目的，且其自身不規定本文論述的各種實施例及/或配置之間的關係。 The following disclosure provides a number of different embodiments or implementations for implementing different features of the subject matter provided by the present disclosure. Specific embodiments of components and arrangements are described below to simplify the present disclosure. Of course, this is only an embodiment, not a limitation. For example, the formation of the first feature on or over the second feature in the following description may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature cannot be in direct contact. In addition, the present disclosure may repeat element symbols and/or letters in various embodiments. This repetition is for simplicity and clarity, and does not in itself dictate a relationship between the various embodiments and/or configurations discussed herein.

而且，本案可能使用諸如「在...之下」、「在...下方」、「下部」、「在...之上」、「上部」等等空間相對術語以便於描述，以描述一個元件或特徵與另一(或多個)元件或特徵的關係，如圖式中所示。除圖式中繪示的方向之外，空間相對術語係用於包括元件在使用或處理中的不同方向。設備可能以其他方式方向(旋轉90度或其他方向)，且本案所使用的空間相對描述詞可由此進行同樣理解。在本文中，「約」、「大約」、或「實質上」可概括地代表在給定值或範圍的百分之二十內、或百分之十內、或百分之五內。本文中所提出的數值是概略性的，代表數值暗示了「約」、「大約」、或「實質上」，即使未明確表示。 Furthermore, the present application may use spatially relative terms such as "under", "under", "lower", "over", "upper", etc. for convenience of description to describe the relationship of one element or feature to another element or feature(s) as shown in the drawings. Spatially relative terms are used to encompass different orientations of elements in use or handling in addition to the orientation depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptors used in this case may be construed similarly thereby. As used herein, "about", "approximately", or "substantially" may generally mean within twenty percent, or within ten percent, or within five percent of a given value or range. Numerical values presented herein are approximate and represent numerical values implying "about", "approximately", or "substantially", even if not expressly stated.

半導體元件的微縮大致上是二維的(two-dimensional；2D)，因為積體電路元件所佔據的體積基本上是在半導體晶圓的表面上。儘管微影技術的改良已在2D積體電路(IC)製程產生重要改良，但在兩個維度中可達成的密度仍存在物理限制。此些限制中之一個限制為製造此些元件所需要的最小尺寸。 The scaling of semiconductor devices is roughly two-dimensional (2D), because the volume occupied by the integrated circuit devices is substantially on the surface of the semiconductor wafer. Although improvements in lithography have produced important improvements in 2D integrated circuit (IC) processing, there are still physical limits to the achievable densities in both dimensions. One of these constraints is the minimum size required to manufacture such elements.

因此，本揭露在一些實施方式中提供一或多個半導體島，其形成於內連接結構之非晶表面上。這些半導體島可作為電晶體的主動區，因此允許形成3D積體電路。3D 積體電路具有位於較低位置(低於內連接結構)的較低電晶體以及位於較高位置(高於內連接結構)的較高電晶體，藉此助於放置更多電晶體於一給定區域中。此外，本揭露於一些實施方式中，半導體島的形成方式係藉由先退火有缺陷二維半導體種子形成實質上無缺陷(defect-free或defect-less)的二維半導體種子，接著橫向成長二維半導體島自這些實質上無缺陷的二維半導體種子，因此允許形成的半導體島無晶體缺陷或具有可忽略的晶體缺陷。 Accordingly, the present disclosure provides, in some embodiments, one or more semiconductor islands formed on an amorphous surface of an interconnect structure. These semiconductor islands serve as the active regions of the transistors, thus allowing the formation of 3D integrated circuits. 3D Integrated circuits have lower transistors located lower (below the interconnect structures) and taller transistors located higher (above the interconnect structures), thereby facilitating placement of more transistors in a given area. Furthermore, in some embodiments of the present disclosure, semiconductor islands are formed by first annealing defective 2D semiconductor seeds to form substantially defect-free or defect-less 2D semiconductor seeds, and then laterally growing 2D semiconductor islands from these substantially defect-free 2D semiconductor seeds, thus allowing the formation of semiconductor islands with no crystal defects or negligible crystal defects.

第1A-11圖示出了根據一些實施例的形成三維積體電路(integrated circuit；IC)的方法的各個中間階段的立體圖及剖面圖。可了解到，額外的步驟可在第1A-11圖所示的流程之前、之中、及之後進行，且在一些額外實施利中，在下文中所提到的步驟可被替代或省略。步驟的順序可被改變。 1A-11 illustrate perspective and cross-sectional views of various intermediate stages of a method of forming a three-dimensional integrated circuit (IC) according to some embodiments. It can be appreciated that additional steps can be performed before, during, and after the processes shown in Figures 1A-11, and that in some additional implementations, steps mentioned hereinafter can be substituted or omitted. The order of steps may be changed.

第1A圖示出了在IC製程中的一中間階段，晶圓W1的立體圖，第1B圖是第1A圖的剖面圖。在第1A及1B圖中，半導體晶圓W1是積體電路製造製程的中間結構，其中電晶體與內連接結構已被形成。在一些實施例中，半導體晶圓W1可包括基板102。基板102可包括例如摻雜或未摻雜的塊體矽，或者絕緣體上半導體(semiconductor-on-insulator；SOI)基板的主動層。大體上，SOI基板是形成於絕緣體層上的諸如矽的半導體材料層。絕緣體層可例如為埋置式氧化物(buried oxide；BOX)層，或氧化矽層。絕緣體層設置在諸如矽 或玻璃基板的基板上。或者，基板102可包括另一元素半導體，如矽；鍺；化合物半導體，包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP，及/或GaInAsP；或上述各者之組合。亦可使用其他基板，如多層基板或漸變(gradient)基板。 FIG. 1A shows a perspective view of wafer W1 at an intermediate stage in the IC manufacturing process, and FIG. 1B is a cross-sectional view of FIG. 1A . In FIGS. 1A and 1B , the semiconductor wafer W1 is an intermediate structure of the integrated circuit manufacturing process, in which transistors and interconnection structures have been formed. In some embodiments, semiconductor wafer W1 may include a substrate 102 . The substrate 102 may include, for example, doped or undoped bulk silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. In general, an SOI substrate is a layer of semiconductor material, such as silicon, formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, or a silicon oxide layer. insulator layers such as silicon or glass substrate on the substrate. Alternatively, the substrate 102 may include another elemental semiconductor, such as silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multilayer substrates or gradient substrates, may also be used.

在一些實施例中，一或多個主動及/或被動元件104(在第1B圖中示為單個電晶體)形成在基板102上。一或多個主動及/或被動元件104可包括各種N型金屬氧化物半導體(N-type metal-oxide semiconductor；NMOS)及/或P型金屬氧化物半導體(P-type metal-oxide semiconductor；PMOS)元件，如電晶體、電容器、電阻器、二極體、光電二極體、熔絲等。本領域通常知識者將會理解，提供上述實施例僅以說明為目的，並不意味著以任何方式限制本揭露。在特定的應用中，亦可適當地形成其他電路元件。 In some embodiments, one or more active and/or passive elements 104 (shown as a single transistor in FIG. 1B ) are formed on the substrate 102 . The one or more active and/or passive devices 104 may include various N-type metal-oxide semiconductor (NMOS) and/or P-type metal-oxide semiconductor (PMOS) devices, such as transistors, capacitors, resistors, diodes, photodiodes, fuses, and the like. Those skilled in the art will appreciate that the above-mentioned embodiments are provided for illustrative purposes only and are not meant to limit the present disclosure in any way. In specific applications, other circuit elements may also be appropriately formed.

在一些實施例中，內連接結構106形成在一或多個主動及/或被動元件104及基板102上。內連接結構106使一或多個主動及/或被動元件104電性互連，以在半導體結構100內形成功能電路。內連接結構106可包括一或多個金屬化層1081至108M，其中M+1是一或多個金屬化層1081至108M的數目。在一些實施例中，M的值可根據半導體結構100的設計規格而變化。在下文中，一或多個金屬化層1081至108M亦可統稱為一或多個金屬化層 108。金屬化層1081至108M分別包括介電層1101至110M及介電層1111至111M。介電層1111至111M形成在對應的介電層1101至110M上。金屬化層1081至108M包括分別在介電層1111至111M中水平或橫向延伸的一或多個水平互連，如導線1141至114M，及分別在介電層1101至110M中垂直延伸的垂直互連，如導電通孔1161至116M。內連接結構106的形成可被稱為後端(back-end-of-line；BEOL)製程。 In some embodiments, interconnect structure 106 is formed on one or more active and/or passive devices 104 and substrate 102 . The interconnect structure 106 electrically interconnects one or more active and/or passive devices 104 to form a functional circuit within the semiconductor structure 100 . The interconnect structure 106 may include one or more metallization layers 108 1 to 108 M , where M+1 is the number of the one or more metallization layers 108 1 to 108 M. In some embodiments, the value of M may vary according to the design specifications of the semiconductor structure 100 . Hereinafter, the one or more metallization layers 108 1 to 108 M may also be collectively referred to as one or more metallization layers 108 . The metallization layers 108 1 to 108 M respectively include dielectric layers 110 1 to 110 M and dielectric layers 111 1 to 111 M . The dielectric layers 1111 to 111M are formed on the corresponding dielectric layers 1101 to 110M . Metallization layers 108 1 to 108 M include one or more horizontal interconnects, such as wires 1141 to 114 M , extending horizontally or laterally in dielectric layers 111 1 to 111 M , respectively, and vertical interconnects, such as conductive vias 116 1 to 116 M, extending vertically in dielectric layers 110 1 to 110 M , respectively. The formation of the interconnect structure 106 may be referred to as a back-end-of-line (BEOL) process.

接觸插塞1120將上方的內連接結構106電性耦接到下方的元件104。在繪示的實施例中，元件104是鰭式場效應電晶體(fin field-effect transistor；FinFET)，此些電晶體是形成在被稱為鰭的半導體突起物103的鰭狀條帶中的三維金屬氧化物半導體場效應電晶體結構。第1B圖所示的剖面是在平行於源極/汲極區104SD之間的電流流動方向的方向上，沿著鰭的縱軸截取。鰭103可透過使用光微影術及蝕刻技術圖案化基板102來形成。例如，可使用間隔物圖像轉印(spacer image transfer；SIT)圖案化技術。在此方法中，犧牲層形成在基板上方，並藉由使用合適的光微影術及蝕刻製程進行圖案化以形成心軸(mandrel)。間隔物藉由使用自對準製程沿心軸側邊而形成。隨後，透過適當的選擇性蝕刻製程移除犧牲層。隨後，藉由使用例如反應離子蝕刻(reactive ion etching；RIE)在基板102中蝕刻溝槽，來使每個剩餘的間隔物用作硬遮罩來圖案化相應的鰭 103。第1A及1B圖示出了單個鰭103，但基板102可包括任意數目的鰭。在其他實施例中，元件104為平面電晶體或閘極環(gate-all-around；GAA)電晶體。 The contact plug 112 0 electrically couples the upper interconnection structure 106 to the lower component 104 . In the illustrated embodiment, elements 104 are fin field-effect transistors (FinFETs), which are three-dimensional MOSFET structures formed in fin-like strips of semiconductor protrusions 103 called fins. The cross-section shown in FIG. 1B is taken along the longitudinal axis of the fin in a direction parallel to the direction of current flow between the source/drain regions 104 SD . The fins 103 may be formed by patterning the substrate 102 using photolithography and etching techniques. For example, a spacer image transfer (SIT) patterning technique may be used. In this method, a sacrificial layer is formed over a substrate and patterned to form a mandrel by using suitable photolithography and etching processes. Spacers are formed along the sides of the mandrel by using a self-aligned process. Subsequently, the sacrificial layer is removed by a suitable selective etching process. Each remaining spacer is then used as a hard mask to pattern the corresponding fin 103 by etching trenches in the substrate 102 using, for example, reactive ion etching (RIE). Figures 1A and 1B show a single fin 103, but the substrate 102 may include any number of fins. In other embodiments, the device 104 is a planar transistor or a gate-all-around (GAA) transistor.

在第1B圖中示出了沿著鰭103的相對側壁形成的淺溝槽隔離(shallow trench isolation；STI)區105。STI區105可透過沉積一或多種介電材料(例如氧化矽)來形成，以完全填充鰭周圍的溝槽，隨後退回介電材料的頂表面。可使用高密度電漿化學氣相沉積(high density plasma chemical vapor deposition；HDP CVD)、低壓化學氣相沉積(low-pressure CVD；LPCVD)、低於大氣壓的化學氣相沉積(sub-atmospheric CVD；SACVD)、可流動化學氣相沉積(flowable CVD；FCVD)、旋塗及/或類似方法，或者上述各者之組合來沉積STI區105的介電材料。在沉積之後，可執行退火製程或固化製程。在一些情況下，STI區105可包括襯層，如藉由氧化矽表面而生長的熱氧化物襯墊層。退回製程可使用例如平坦化製程(例如化學機械拋光(chemical mechanical polish；CMP))，接著使用選擇性蝕刻製程(例如濕式蝕刻、乾式蝕刻或上述各者之組合)，此選擇性蝕刻製程可退回STI區105中的介電材料的頂表面，使得鰭103的上部從周圍的絕緣STI區105突出。在一些情況下，用於形成鰭103的圖案化硬遮罩亦可透過平坦化製程移除。 Shallow trench isolation (STI) regions 105 formed along opposing sidewalls of the fin 103 are shown in FIG. 1B . STI regions 105 may be formed by depositing one or more dielectric materials, such as silicon oxide, to completely fill the trenches around the fins, and then retreat to the top surface of the dielectric material. The STI region 1 may be deposited using high density plasma chemical vapor deposition (HDP CVD), low-pressure chemical vapor deposition (low-pressure CVD; LPCVD), sub-atmospheric chemical vapor deposition (sub-atmospheric CVD; SACVD), flowable chemical vapor deposition (flowable CVD; FCVD), spin coating, and/or the like, or combinations thereof. 05 dielectric material. After deposition, an annealing process or a curing process may be performed. In some cases, the STI region 105 may include a liner layer, such as a thermal oxide liner layer grown by oxidizing the silicon surface. The retraction process may use, for example, a planarization process (eg, chemical mechanical polish (CMP)) followed by a selective etch process (eg, wet etch, dry etch, or a combination thereof) that retracts the top surface of the dielectric material in the STI region 105 such that the upper portion of the fin 103 protrudes from the surrounding insulating STI region 105 . In some cases, the patterned hard mask used to form the fins 103 can also be removed through the planarization process.

在一些實施例中，第1B圖所示的FinFET元件 104的閘極結構104G是可使用閘極後(gate-last)製程流程形成的高k金屬閘極(high-k,metal gate；HKMG)閘極結構。在閘極後製程流程中，在形成STI區105之後形成犧牲虛設閘極結構(未示出)。虛設閘極結構可包括虛設閘極介電質、虛設閘電極及硬遮罩。首先，可沉積虛設閘極介電材料(例如氧化矽、氮化矽等)。接下來，可在虛設閘極介電質上沉積虛設閘極材料(例如非晶矽、多晶矽等)，隨後平面化(例如透過化學機械研磨(chemical mechanical polishing；CMP))。硬遮罩層(例如氮化矽、碳化矽等)可形成在虛設閘極材料上方。隨後，透過圖案化硬遮罩，並使用合適的光微影術及蝕刻技術將此圖案轉移到虛設閘極介電質及虛設閘極材料，以此形成虛設閘極結構。虛設閘極結構可沿著突出鰭的多個側面延伸，並且在鰭之間延伸到STI區105的表面上方。如下文更詳細描述的，虛設閘極結構可由如第1B圖所示的HKMG閘極結構104G代替。用於形成虛設閘極結構及硬遮罩的材料可使用任何合適的方法來沉積，如CVD、電漿增強CVD(plasma-enhanced CVD；PECVD)、原子層沉積(atomic layer deposition；ALD)、電漿增強ALD(plasma-enhanced ALD；PEALD)等，或者透過半導體表面的熱氧化，或者上述各者之組合。 In some embodiments, the gate structure 104G of the FinFET device 104 shown in FIG. 1B is a high-k metal gate (HKMG) gate structure that can be formed using a gate-last process flow. In a last-gate process flow, a sacrificial dummy gate structure (not shown) is formed after the STI region 105 is formed. The dummy gate structure may include a dummy gate dielectric, a dummy gate electrode, and a hard mask. First, a dummy gate dielectric material (such as silicon oxide, silicon nitride, etc.) can be deposited. Next, a dummy gate material (eg, amorphous silicon, polysilicon, etc.) may be deposited on the dummy gate dielectric, followed by planarization (eg, by chemical mechanical polishing (CMP)). A hard mask layer (eg, silicon nitride, silicon carbide, etc.) can be formed over the dummy gate material. The dummy gate structure is then formed by patterning the hard mask and transferring this pattern to the dummy gate dielectric and dummy gate material using suitable photolithography and etching techniques. The dummy gate structures may extend along multiple sides of the protruding fins and between the fins above the surface of the STI region 105 . As described in more detail below, the dummy gate structure may be replaced by an HKMG gate structure 104G as shown in FIG. 1B. The materials for forming the dummy gate structure and the hard mask can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), etc., or by thermal oxidation of the semiconductor surface, or a combination of the above.

如第1B圖所示，FinFET 104的源極/汲極區104SD及間隔物104SP例如被形成為與虛設閘極結構自對 準。間隔物104SP可透過在虛設閘極圖案化完成之後執行的間隔物介電層的沉積及非等向性蝕刻來形成。間隔介電層可包括一或多種介電質，如氧化矽、氮化矽、氮氧化矽、碳化矽、碳氮化矽等，或者上述各者之組合。非等向性蝕刻製程從虛設閘極結構的頂部移除間隔物介電層，留下沿著虛設閘極結構的側壁橫向延伸到鰭103的一部分表面上的間隔物104SP。 As shown in FIG. 1B , the source/drain regions 104 SD and spacers 104 SP of the FinFET 104 are formed, for example, in self-alignment with the dummy gate structure. The spacers 104 SP may be formed by deposition of a spacer dielectric layer and anisotropic etching performed after dummy gate patterning is completed. The spacer dielectric layer may include one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, etc., or a combination thereof. The anisotropic etch process removes the spacer dielectric layer from the top of the dummy gate structure, leaving the spacer 104 sp extending laterally onto a portion of the surface of the fin 103 along the sidewall of the dummy gate structure.

源極/汲極區104SD是與半導體鰭103直接接觸的半導體區。在一些實施例中，源極/汲極區104SD可包括重摻雜區及相對輕摻雜的汲極延伸(lightly-doped drain；LDD)區。大體上，使用間隔物104SP將重摻雜區與虛設閘極結構隔開，而LDD區可在形成間隔物104SP之前形成，並且因此在間隔物104SP下方延伸，並且在一些實施例中，進一步延伸到虛設閘極結構下方的半導體鰭103的一部分中。例如，可透過使用離子佈植製程佈植摻雜劑(例如砷、磷、硼、銦等)來形成LDD區。 The source/drain regions 104 SD are semiconductor regions in direct contact with the semiconductor fins 103 . In some embodiments, the source/drain region 104 SD may include a heavily doped region and a relatively lightly-doped drain (LDD) region. In general, a spacer 104 SP is used to separate the heavily doped region from the dummy gate structure, while the LDD region may be formed prior to forming the spacer 104 SP , and thus extend under the spacer 104 SP , and in some embodiments, further into a portion of the semiconductor fin 103 below the dummy gate structure. For example, the LDD region can be formed by implanting dopants (eg, arsenic, phosphorus, boron, indium, etc.) using an ion implantation process.

源極/汲極區104SD可包括磊晶生長區。例如，在形成LDD區之後，可形成間隔物104SP，並且隨後，可透過首先蝕刻鰭以形成凹陷，隨後透過選擇性磊晶生長(selective epitaxial growth；SEG)製程在凹陷中沉積晶態半導體材料(此半導體材料可填充凹陷並且可進一步延伸超過鰭103的原始表面以形成凸起的源極/汲極磊晶結構)，從而形成與間隔物104SP自對準的重摻雜源極及汲極區。晶態半導體材料可為元素(例如矽或鍺等) 或合金(例如Si1-xCx或Si1-xGex等)。磊晶生長製程可使用任何合適的磊晶生長方法，如氣相/固相/液相磊晶(VPE、SPE、LPE)，或金屬有機化學氣相沉積(metal-organic CVD；MOCVD)，或分子束磊晶(molecular beam epitaxy；MBE)等。高劑量(例如，從大約1014cm-2到1016cm-2)的摻雜劑可在SEG期間原位植入重摻雜源極及汲極區104SD，或者透過SEG之後執行的離子佈植製程，或者透過上述各者之組合來引入。 The source/drain regions 104 SD may include epitaxial growth regions. For example, after forming the LDD region, the spacer 104 SP can be formed, and then, heavily doped source and drain self-aligned with the spacer 104 SP can be formed by first etching the fin to form a recess, and then depositing a crystalline semiconductor material in the recess by a selective epitaxial growth (SEG) process (this semiconductor material can fill the recess and can extend further beyond the original surface of the fin 103 to form a raised source/drain epitaxial structure). polar region. The crystalline semiconductor material can be an element (such as silicon or germanium, etc.) or an alloy (such as Si 1-x C x or Si 1-x Ge x , etc.). The epitaxial growth process can use any suitable epitaxial growth method, such as vapor phase/solid phase/liquid phase epitaxy (VPE, SPE, LPE), or metal-organic chemical vapor deposition (metal-organic CVD; MOCVD), or molecular beam epitaxy (molecular beam epitaxy; MBE). High doses (eg, from about 10 14 cm −2 to 10 16 cm −2 ) of dopants can be introduced by in-situ implantation of heavily doped source and drain regions 104 SD during SEG, by an ion implantation process performed after SEG, or by a combination of the above.

一旦形成源極/汲極區104SD，第一ILD層(例如，ILD層1100的下部)沉積在源極/汲極區104SD上。在一些實施例中，可在沉積ILD材料之前沉積合適介電質(例如氮化矽、碳化矽等或其組合)的接觸蝕刻停止層(contact etch stop layer；CESL)(未示出)。可執行平坦化製程(例如，CMP)，以從虛設閘極上方移除多餘的ILD材料及任何剩餘的硬遮罩材料，從而形成頂表面，其中虛設閘極材料的頂表面被曝露，並且可與第一ILD層的頂表面大致上共平面。隨後，第1B圖所示的HKMG閘極結構104G可透過以下方式形成。首先，使用一或多種蝕刻技術移除虛設閘極結構，從而在相應的間隔物104SP之間產生凹陷。接下來，沉積包括一或多種介電質的替換閘極介電層104GD，隨後沉積包括一或多種金屬的替換閘極金屬層104GE，以完全填充間隔物104SP之間產生的凹陷。閘極結構層104GD及104GM的多餘部分可使 用例如CMP製程從第一ILD的頂表面上移除。如第1B圖所示，所得結構可包括嵌入在相應間隔物104SP之間的HKMG閘極層104GD及104GM的剩餘部分。 Once the source/drain regions 104 SD are formed, a first ILD layer (eg, the lower portion of the ILD layer 110 0 ) is deposited on the source/drain regions 104 SD . In some embodiments, a contact etch stop layer (CESL) (not shown) of a suitable dielectric (eg, silicon nitride, silicon carbide, etc., or a combination thereof) may be deposited prior to depositing the ILD material. A planarization process (e.g., CMP) may be performed to remove excess ILD material and any remaining hard mask material from above the dummy gate to form a top surface, wherein the top surface of the dummy gate material is exposed and may be substantially coplanar with the top surface of the first ILD layer. Subsequently, the HKMG gate structure 104G shown in FIG. 1B can be formed in the following manner. First, the dummy gate structures are removed using one or more etching techniques, thereby creating recesses between corresponding spacers 104 SP . Next, a replacement gate dielectric layer 104 GD comprising one or more dielectrics is deposited, followed by a replacement gate metal layer 104 GE comprising one or more metals to completely fill the recesses created between the spacers 104 SP . Excess portions of gate structure layers 104 GD and 104 GM may be removed from the top surface of the first ILD using, for example, a CMP process. As shown in FIG. 1B , the resulting structure may include the remainder of the HKMG gate layers 104 GD and 104 GM embedded between respective spacers 104 SP .

閘極介電層104GD包括例如高k介電材料，例如金屬的氧化物及/或矽酸鹽(例如鉿、鋁、鋯、鑭、鎂、鋇、鈦及其他金屬的氧化物及/或矽酸鹽)、氮化矽、氧化矽等，或者上述各者之組合，或者上述各者之多層。在一些實施例中，閘極金屬層104GM可為多層金屬閘極堆疊層，包括在閘極介電層104GD頂部連續形成的阻障層、功函數層及閘極填充層。阻障層的示例材料包括TiN、TaN、鈦、鉭等，或者上述各者之多層組合。p型場效應電晶體的功函數層可包括TiN、TaN、釕、鉬、鋁，n型場效應電晶體的功函數層可包括鈦、銀、TaAl、TaAlC、TiAlN、TaC、TaCN、TaSiN、錳、鋯。可使用其他合適的功函數材料或其組合或多層。填充凹槽剩餘部分的閘極填充層可包括金屬，如銅、鋁、鎢、鈷、釕等，或者上述各者之組合，或者上述各者之多層。用於形成閘極結構的材料可透過任何合適的方法沉積，例如CVD、PECVD、PVD、ALD、PEALD、電化學電鍍(electrochemical plating；ECP)、無電極電鍍及/或類似方法。 The gate dielectric layer 104 GD includes, for example, high-k dielectric materials, such as metal oxides and/or silicates (such as oxides and/or silicates of hafnium, aluminum, zirconium, lanthanum, magnesium, barium, titanium, and other metals), silicon nitride, silicon oxide, etc., or a combination of the above, or multiple layers of the above. In some embodiments, the gate metal layer 104 GM may be a multi-layer metal gate stack, including a barrier layer, a work function layer, and a gate filling layer continuously formed on top of the gate dielectric layer 104 GD . Exemplary materials for the barrier layer include TiN, TaN, titanium, tantalum, etc., or a combination of layers thereof. The work function layer of the p-type field effect transistor can include TiN, TaN, ruthenium, molybdenum, aluminum, and the work function layer of the n-type field effect transistor can include titanium, silver, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, manganese, zirconium. Other suitable work function materials or combinations or layers thereof may be used. The gate fill layer filling the remainder of the recess may include metals such as copper, aluminum, tungsten, cobalt, ruthenium, etc., or combinations thereof, or multiple layers thereof. Materials used to form the gate structures may be deposited by any suitable method, such as CVD, PECVD, PVD, ALD, PEALD, electrochemical plating (ECP), electroless plating, and/or the like.

在形成HKMG結構104G之後，在第一ILD層上沉積第二ILD層，並且此些第一及第二ILD層在本文中可一起稱為ILD層1100，如第1B圖所示。在一些實施例中，形成第一ILD層及第二ILD層的絕緣材料可包 括氧化矽、磷矽酸鹽玻璃(phosphosilicate glass；PSG)、硼矽酸鹽玻璃(borosilicate glass；BSG)、硼摻雜磷矽酸鹽玻璃(boron-doped phosphosilicate glass；BPSG)、未摻雜矽酸鹽玻璃(undoped silicate glass；USG)、低介電常數(低k)介電質，如氟矽酸鹽玻璃(fluorosilicate glass；FSG)、碳氧化矽(SiOCH)、碳摻雜氧化物(carbon-doped oxide；CDO)、可流動氧化物或多孔氧化物(例如乾凝膠/氣凝膠)等，或者上述各者之組合。用於形成第一ILD層及第二ILD層的介電材料可使用任何合適的方法來沉積，如CVD、物理氣相沉積(physical vapor deposition；PVD)、ALD、PEALD、PECVD、SACVD、FCVD、旋塗等，或者上述各者之組合。 After forming the HKMG structure 104G , a second ILD layer is deposited on the first ILD layer, and these first and second ILD layers may be collectively referred to herein as ILD layer 110 0 , as shown in FIG. 1B . In some embodiments, the insulating material forming the first ILD layer and the second ILD layer may include silicon oxide, phosphosilicate glass (phosphosilicate glass; PSG), borosilicate glass (borosilicate glass; BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (undoped silicate glass; USG), low dielectric constant (low-k) dielectric. Electrodes, such as fluorosilicate glass (fluorosilicate glass; FSG), silicon oxycarbide (SiOCH), carbon-doped oxide (carbon-doped oxide; CDO), flowable oxides or porous oxides (such as xerogel/aerogel), etc., or a combination of the above. The dielectric material used to form the first and second ILD layers may be deposited using any suitable method, such as CVD, physical vapor deposition (PVD), ALD, PEALD, PECVD, SACVD, FCVD, spin coating, etc., or combinations thereof.

如第1B圖所示，形成在基板102中的電子元件的電極可使用穿過中間介電層形成的接觸窗(contact)1120電連接到導線1141至114M及導電通孔1161至116M。在第1B圖所示的實施例中，接觸窗1120電連接到FinFET 104的閘極結構104G及源極/汲極區104SD。接觸窗1120可使用光微影術、蝕刻及沉積技術形成。 As shown in FIG. 1B , the electrodes of the electronic components formed in the substrate 102 can be electrically connected to the conductive lines 114 1 to 114 M and the conductive vias 116 1 to 116 M using contacts 112 0 formed through the intervening dielectric layer. In the embodiment shown in FIG. 1B , contact 112 0 is electrically connected to gate structure 104 G and source/drain region 104 SD of FinFET 104 . The contact window 1120 can be formed using photolithography, etching and deposition techniques.

例如，圖案化遮罩可形成在ILD層1100上方，並用於蝕刻延伸穿過ILD層1100的開口，以曝露閘極結構104G及源極/汲極區104SD。此後，可在ILD層1100中的開口中形成導電襯墊。隨後，用導電填充材料填充開口。襯墊包括阻障金屬，用於減少導電材料從接觸窗1120 向外擴散到周圍的介電材料中。在一些實施例中，襯墊可包括兩個阻障金屬層。第一阻障金屬與源極/汲極區104SD中的半導體材料接觸，並且隨後可與源極/汲極區104SD中的重摻雜半導體化學反應以形成低電阻的歐姆接觸，之後可移除未反應的金屬。例如，若源極/汲極區104SD中的重摻雜半導體是矽或矽鍺合金半導體，則第一阻障金屬可包括鈦、鎳、鉑、鈷、其他合適的金屬或上述各者之合金。導電襯墊的第二阻障金屬層可額外包括其他金屬(例如，TiN、TaN、鉭或其他合適的金屬，或上述各者之合金)。導電填充材料(例如，鎢、鋁、銅、釕、鎳、鈷、上述各者之合金、上述各者之組合等)可使用任何可接受的沉積技術(例如，CVD、ALD、PEALD、PECVD、PVD、ECP、無電極電鍍等或上述各者之任意組合)沉積在導電襯墊層上以填充接觸開口。接著，可使用平坦化製程(例如CMP)從ILD 1100的表面上移除所有導電材料的多餘部分。所得導電插塞延伸到ILD層1100中，並構成接觸窗1120，此接觸窗1120與電子元件的電極進行實體及電連接，該等電子元件例如第1B圖所示的三閘極(tri-gate)FinFET 104。 For example, a patterned mask may be formed over the ILD layer 110 0 and used to etch openings extending through the ILD layer 110 0 to expose the gate structures 104 G and the source/drain regions 104 SD . Thereafter, conductive liners may be formed in the openings in the ILD layer 1100 . Subsequently, the opening is filled with a conductive filling material. The liner includes a barrier metal to reduce the out-diffusion of conductive material from the contact 1120 into the surrounding dielectric material. In some embodiments, the liner may include two barrier metal layers. The first barrier metal is in contact with the semiconductor material in the source/drain region 104 SD and may subsequently chemically react with the heavily doped semiconductor in the source/drain region 104 SD to form a low resistance ohmic contact after which unreacted metal may be removed. For example, if the heavily doped semiconductor in the source/drain region 104 SD is silicon or a silicon-germanium alloy semiconductor, the first barrier metal may include titanium, nickel, platinum, cobalt, other suitable metals or alloys thereof. The second barrier metal layer of the conductive liner may additionally include other metals (eg, TiN, TaN, tantalum, or other suitable metals, or alloys thereof). A conductive fill material (e.g., tungsten, aluminum, copper, ruthenium, nickel, cobalt, alloys of the foregoing, combinations of the foregoing, etc.) may be deposited on the conductive liner layer to fill the contact openings using any acceptable deposition technique (e.g., CVD, ALD, PEALD, PECVD, PVD, ECP, electroless plating, etc., or any combination of the foregoing). Next, any excess of conductive material may be removed from the surface of ILD 1100 using a planarization process such as CMP. The resulting conductive plugs extend into the ILD layer 110 0 and form contacts 112 0 that make physical and electrical connections to electrodes of electronic components, such as the tri-gate FinFET 104 shown in FIG. 1B .

在形成接觸窗1120之後，根據積體電路設計採用的後端製程(back end of line；BEOL)方案，可形成包括多個內連接層的內連接結構106，垂直堆疊在形成於ILD層1100中的接觸插塞1120上方。在第1B圖所示的BEOL方案中，各種內連接層具有相似的特徵。然而，應 當理解，其他實施例可利用替代的整合方案，其中各個內連接層可使用不同的特徵。例如，圖示為垂直連接的源極/汲極接觸窗1120可橫向延伸以形成橫向傳輸電流的導線。 After forming the contact window 1120 , according to the back end of line (BEOL) scheme adopted by the integrated circuit design, an interconnection structure 106 including a plurality of interconnection layers can be formed, vertically stacked above the contact plug 1120 formed in the ILD layer 1100 . In the BEOL scheme shown in Figure 1B, the various interconnection layers share similar characteristics. However, it should be understood that other embodiments may utilize alternative integration schemes in which different features may be used for each interconnection layer. For example, the source/drain contacts 1120 shown as vertically connected may extend laterally to form conductive lines for laterally carrying current.

多個內連接層包括例如導線1141至114M及導電通孔1161至116M，此等導線及通孔可使用任何合適的方法形成在相應的IMD層1101至110M及1111至111M中，諸如單鑲嵌製程、雙鑲嵌製程等。在一些實施例中，IMD層1101至110M及1111至111M可包括設置在此些導電特徵之間的低k介電材料，例如，具有k值低於約4.0或者甚至2.0的介電材料。在一些實施例中，IMD層可由例如磷矽酸鹽玻璃(phosphosilicate glass；PSG)、硼磷矽酸鹽玻璃(borophosphosilicate glass；BPSG)、氟矽酸鹽玻璃(fluorosilicate glass；FSG)、SiOxCy、旋塗玻璃、旋塗聚合物、氧化矽、氮氧化矽、上述各者之組合等製成，上述各者透過任何合適的方法形成，如旋塗、化學氣相沉積(chemical vapor deposition；CVD)、電漿增強化學氣相沉積(plasma-enhanced CVD；PECVD)等。導線1141至114M及導電通孔1161至116M可包括導電材料，如銅、鋁、鎢、上述各者之組合等。在一些實施例中，導線1141至114M及導電通孔1161至116M可進一步包括一或多個阻障/黏附層(未示出)，以保護相應的IMD層1101至110M及1111至111M免受金屬擴散(例如，銅擴散)及金屬毒害的影響。一或 多個阻障層/黏合層可包括鈦、氮化鈦、鉭、氮化鉭等，並且可使用物理氣相沉積(physical vapor deposition；PVD)、CVD、ALD等形成。 The plurality of interconnection layers include, for example, wires 114 1 - 114 M and conductive vias 116 1 - 116 M , which wires and vias may be formed in respective IMD layers 110 1 - 110 M and 111 1 - 111 M using any suitable method, such as single damascene processing, dual damascene processing, and the like. In some embodiments, IMD layers 110 1 - 110 M and 111 1 - 111 M may include a low-k dielectric material disposed between such conductive features, eg, a dielectric material having a k value below about 4.0 or even 2.0. In some embodiments, the IMD layer can be made of, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass ( FSG ), SiOxCy , spin-on-glass, spin-on-polymer, silicon oxide, silicon oxynitride, combinations thereof, etc., each of which is formed by any suitable method, such as spin coating, chemical vapor phase deposition (chemical vapor deposition; CVD), plasma-enhanced chemical vapor deposition (plasma-enhanced CVD; PECVD), etc. The wires 114 1 - 114 M and the conductive vias 116 1 - 116 M may include conductive materials such as copper, aluminum, tungsten, combinations thereof, and the like. In some embodiments, the wires 1141-114M and the conductive vias 1161-116M may further include one or more barrier/adhesion layers (not shown ) to protect the corresponding IMD layers 1101-110M and 1111-111M from metal diffusion (eg, copper diffusion ) and metal poisoning. The one or more barrier/adhesion layers may include titanium, titanium nitride, tantalum, tantalum nitride, etc., and may be formed using physical vapor deposition (PVD), CVD, ALD, or the like.

使用例如PVD、CVD、ALD等，在內連接結構106的金屬化層108M上形成額外的ILD層120。此ILD層係做為支撐二維半導體材料的基板，細節將於下文中討論。因此，ILD層120起到了與下方的與下層的IMD層1101至110M及1111至111M及ILD層1100不同的作用，並且因此可具有與IMD層1101至110M及1111至111M及ILD層1100不同的厚度及/或材料。例如，ILD層120可比IMD層1101至110M及1111至111M及ILD層1100中的一或更多者更厚或更薄。或者，ILD層120可具有與IMD層1101至110M及1111至111M及ILD層1100中的一或更多者相同的厚度及/或材料。 An additional ILD layer 120 is formed on the metallization layer 108M of the interconnect structure 106 using, for example, PVD, CVD, ALD, or the like. The ILD layer acts as a substrate supporting the two-dimensional semiconductor material, as discussed in detail below. Thus, the ILD layer 120 functions differently than the underlying and underlying IMD layers 1101-110M and 1111-111M and the ILD layer 1100 , and thus may have a different thickness and/or material than the IMD layers 1101-110M and 1111-111M and the ILD layer 1100 . For example, ILD layer 120 may be thicker or thinner than one or more of IMD layers 110 1 - 110 M and 111 1 - 111 M and ILD layer 110 0 . Alternatively, ILD layer 120 may have the same thickness and/or material as one or more of IMD layers 110 1 - 110 M and 111 1 - 111 M and ILD layer 110 0 .

在一些實施例中，ILD層120可包括低k介電材料，例如，k值低於大約4.0或者甚至2.0。例如，ILD層120可由例如磷矽酸鹽玻璃(phosphosilicate glass；PSG)、硼磷矽酸鹽玻璃(borophosphosilicate glass；BPSG)、氟矽酸鹽玻璃(fluorosilicate glass；FSG)、SiOxCy、旋塗玻璃、旋塗聚合物、氧化矽、氮氧化矽、上述各者之組合等製成，上述各者可透過任何合適的方法形成，如旋塗、化學氣相沉積(chemical vapor deposition；CVD)、電漿增強化學氣相沉積(plasma-enhanced CVD；PECVD)等。 In some embodiments, ILD layer 120 may include a low-k dielectric material, eg, a k value below about 4.0 or even 2.0. For example, the ILD layer 120 can be made of, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass ( FSG ), SiOxCy , spin-on-glass, spin-on-polymer, silicon oxide, silicon oxynitride, combinations thereof, etc., which can be formed by any suitable method, such as spin coating, chemical gas phase deposition (chemical vapor deposition; CVD), plasma-enhanced chemical vapor deposition (plasma-enhanced CVD; PECVD), etc.

第2A圖繪示依據本揭露一些實施例之二維半導體層202的形成的一中間階段的立體圖。二維半導體材料通常僅為幾層厚且以一種強鍵結層的形式存在，而層與層間僅具有微弱的凡得瓦力(Van der Waals force)，能藉機械或化學的方法將其剝離為單獨、原子級薄度之層。二維半導體材料為電晶體之通道、源極、汲極材料具潛力之候選。二維材料之例子如過渡金屬二硫族化物(transition metal dichalcogenides；TMD)、石墨烯(graphene)、層狀的III-VI硫化物、六方氮化硼(hexagonal boron nitride；h-BN)、黑磷(black phosphorus)或類似物。在一些實施例中，二維半導體可包含一或多層且具有0.5至100奈米的厚度。幾層厚的二維半導體的優勢在於高載子遷移率，其可為約50-1000cm2/V-sec或更高。可瞭解到，當塊材矽被切至與二維材料厚度相近的低厚度(約2奈米)時，其載子遷移率會大幅下降。 FIG. 2A illustrates a perspective view of an intermediate stage in the formation of a two-dimensional semiconductor layer 202 according to some embodiments of the present disclosure. Two-dimensional semiconductor materials are usually only a few layers thick and exist in the form of a strong bonding layer, and there is only a weak Van der Waals force between the layers, which can be peeled off into individual, atomically thin layers by mechanical or chemical methods. Two-dimensional semiconductor materials are potential candidates for channel, source, and drain materials of transistors. Examples of two-dimensional materials are transition metal dichalcogenides (TMD), graphene, layered III-VI sulfides, hexagonal boron nitride (h-BN), black phosphorus, or the like. In some embodiments, the two-dimensional semiconductor may include one or more layers and have a thickness of 0.5 to 100 nm. Two-dimensional semiconductors several layers thick have the advantage of high carrier mobility, which can be about 50-1000 cm 2 /V-sec or higher. It can be seen that when bulk silicon is cut to a low thickness (about 2 nanometers) similar to the thickness of two-dimensional materials, its carrier mobility will be greatly reduced.

在第2A圖中，二維半導體層202成長在結晶基板200上以利晶向控制。在一些實施例中，結晶基板200可包含，例如，塊材矽、摻雜或非摻雜、或絕緣體上半導體(semiconductor-on-insulator；SOI)基板。在一些實施例中，結晶基板200可包含藍寶石基板。藍寶石基板200可為c-plane藍寶石基板(亦可稱為c-藍寶石)基板。在一些其他實施例中，具有其他plane的基板(例如M plane、R plane或A plane)亦可被採用。基板 200可為晶圓，且具有圓形俯視形狀或矩形俯視形狀。基板200的直徑可為3吋、12吋或更多。在一些實施例中，結晶基板200可為單晶基板，因此形成的二維半導體層202可為單晶結構，其因為結晶基板200而具有受控的晶向。 In FIG. 2A, a two-dimensional semiconductor layer 202 is grown on a crystalline substrate 200 to facilitate crystal orientation control. In some embodiments, the crystalline substrate 200 may include, for example, bulk silicon, doped or undoped, or a semiconductor-on-insulator (SOI) substrate. In some embodiments, the crystalline substrate 200 may include a sapphire substrate. The sapphire substrate 200 can be a c-plane sapphire substrate (also called c-sapphire) substrate. In some other embodiments, substrates with other planes (such as M plane, R plane or A plane) can also be used. Substrate 200 may be a wafer and have a circular top view shape or a rectangular top view shape. The diameter of the substrate 200 may be 3 inches, 12 inches or more. In some embodiments, the crystalline substrate 200 may be a single crystal substrate, and thus the formed two-dimensional semiconductor layer 202 may be a single crystal structure, which has a controlled crystallographic orientation due to the crystalline substrate 200 .

在一些實施例中，二維半導體層202為具有式MX2的過渡金屬二硫族化物(transition metal dichalcogenide；TMD)材料，其中M為過渡金屬元素，例如，鈦、釩、鈷、鎳、鋯、鉬、鍀、銠、鈀、鉿、鉭、鎢、錸、銥、鉑，且X為硫族元素，例如，硫、硒或碲。適合於二維半導體層202的二硫族化物材料的範例包含MoS2、WS2、WSe2、MoSe2、MoTe2、WTe2等或其組合。然而，可替代地使用任何合適過渡金屬二硫族化物材料。一旦經形成，過渡金屬二硫族化物材料呈具有通式X-M-X的多個二維層的分層結構，其中兩個平面中的硫族元素原子由金屬原子的平面分開。 In some embodiments, the two-dimensional semiconductor layer 202 is a transition metal dichalcogenide (TMD) material having the formula MX2 , wherein M is a transition metal element, such as titanium, vanadium, cobalt, nickel, zirconium, molybdenum, hafnium, rhodium, palladium, hafnium, tantalum, tungsten, rhenium, iridium, platinum, and X is a chalcogen element, such as sulfur, selenium, or tellurium. Examples of dichalcogenide materials suitable for the two-dimensional semiconductor layer 202 include MoS 2 , WS 2 , WSe 2 , MoSe 2 , MoTe 2 , WTe 2 , etc., or combinations thereof. However, any suitable transition metal dichalcogenide material may be used instead. Once formed, transition metal dichalcogenide materials exhibit a hierarchical structure of multiple two-dimensional layers having the general formula XMX, wherein the chalcogen atoms in two planes are separated by a plane of metal atoms.

二維半導體層202可為一單層(mono-layer)或具有一些單層。第2B圖繪示依據一些實施例的一範例性TMD的一單層204。在第2B圖中，一個分子厚的TMD材料層包括過渡金屬原子204M和硫族元素原子204X。過渡金屬原子204M可形成一個分子厚的TMD材料層的中間區域的層，且硫族元素原子204X可形成位於過渡金屬原子204M層上方的第一層，和位於過渡金屬原子204X層的下方的第二層。過渡金屬原子204M可為W原子或 Mo原子，而硫族元素原子204X可為S原子、Se原子或Te原子。在第2圖的範例中，過渡金屬原子204M中的每一者鍵結(例如，藉由共價鍵)到六個硫族元素原子204X，且硫族元素原子204X中的每一者鍵結(例如，藉由共價鍵)到三個過渡金屬原子204M。在本文中，一層過度金屬原子204M以及兩層硫族元素原子204X互相鍵結，且可一起稱為TMC的單層204。 The two-dimensional semiconductor layer 202 can be a mono-layer or have several mono-layers. Figure 2B illustrates a single layer 204 of an exemplary TMD in accordance with some embodiments. In Figure 2B, a one molecule thick layer of TMD material includes transition metal atoms 204M and chalcogen atoms 204X. Transition metal atoms 204M may form a layer in the middle region of the one molecule thick TMD material layer, and chalcogen atoms 204X may form a first layer above the layer of transition metal atoms 204M and a second layer below the layer of transition metal atoms 204X. Transition metal atom 204M can be W atom or Mo atoms, and the chalcogen atoms 204X can be S atoms, Se atoms or Te atoms. In the example of FIG. 2, each of the transition metal atoms 204M is bonded (eg, by covalent bonds) to six chalcogen atoms 204X, and each of the chalcogen atoms 204X is bonded (eg, by covalent bonds) to three transition metal atoms 204M. Herein, one layer of transition metal atoms 204M and two layers of chalcogen atoms 204X are bonded to each other, and together may be referred to as a single layer 204 of TMC.

在一些實施例中，二維半導體層202係藉由適當的沉積技術成長在結晶基板200上。舉例來說，在二維半導體層202為TMD的實施例中，TMD層202可藉由CVD形成，其中採用MoO3及含硫氣體(例如硫蒸氣或H2S)做為製程氣體，並採用N2做為載體氣體。在一些實施例中，形成溫度可介於600℃至700℃，但更高或更低的溫度亦可被採用。這些製程條件被控制以達到目標層數的單層204。在一些其他實施例中，PECVD或其他可用的方法亦可被採用。在一些實施例中，成長在基板200上的二維半導體層202可包含晶體缺陷例如空位缺陷(vacancy defect)、間隙缺陷(interstitial defect)、及/或其他缺陷。因此，在一些實施例中，二維半導體層202亦可稱為缺陷(defective)半導體層。雖然缺陷半導體層202包含晶體缺陷，其仍具有預期的或受控的晶向，此晶向取決於下方結晶基板200的晶向。在一些實施例中，缺陷半導體層202可形成為多個缺陷二維半導體薄片、或是一連續的缺陷二維半導體膜。 In some embodiments, the two-dimensional semiconductor layer 202 is grown on the crystalline substrate 200 by suitable deposition techniques. For example, in an embodiment where the two-dimensional semiconductor layer 202 is a TMD, the TMD layer 202 can be formed by CVD, wherein MoO 3 and a sulfur-containing gas (such as sulfur vapor or H 2 S) are used as process gases, and N 2 is used as a carrier gas. In some embodiments, the forming temperature may be between 600° C. and 700° C., but higher or lower temperatures may also be used. These process conditions are controlled to achieve a target number of monolayers 204 . In some other embodiments, PECVD or other available methods may also be used. In some embodiments, the two-dimensional semiconductor layer 202 grown on the substrate 200 may contain crystal defects such as vacancy defects, interstitial defects, and/or other defects. Therefore, in some embodiments, the two-dimensional semiconductor layer 202 may also be called a defective semiconductor layer. Although the defective semiconductor layer 202 contains crystal defects, it still has a desired or controlled crystallographic orientation that depends on the crystallographic orientation of the underlying crystalline substrate 200 . In some embodiments, the defective semiconductor layer 202 can be formed as a plurality of defective two-dimensional semiconductor flakes, or a continuous defective two-dimensional semiconductor film.

缺陷半導體層202接著被轉移至晶圓W1的ILD層120上，並用於形成電晶體。第2A圖亦繪示將缺陷二維半導體層202轉移至晶圓W1的ILD層120上的準備程序。在第2A圖中，保護膜206係形成於缺陷半導體層202上。保護膜206的功能包含保護缺陷二維半導體層202以免在轉移過程中受損。在一些實施例中，保護膜206包含光阻材料，例如聚甲基丙烯酸甲酯(polymethyl methacrylate；PMMA)或其他適當材料，其為可流動的並採用如旋塗(spin coating)製程塗佈在缺陷半導體層202上。被塗佈的保護膜206經固化成固態。在一些其他實施例中，其他可提供保護的可流動且可固化的材料或者是乾燥膜亦可被採用。熱解膠(thermal release tape)208接著被覆蓋到PMMA膜206上。熱解膠208的材料可在特定的溫度條件或其他條件(例如輻射)而失去黏著性。 The defective semiconductor layer 202 is then transferred onto the ILD layer 120 of the wafer W1 and used to form transistors. FIG. 2A also shows the preparation process for transferring the defective two-dimensional semiconductor layer 202 onto the ILD layer 120 of the wafer W1. In FIG. 2A , a protective film 206 is formed on the defective semiconductor layer 202 . The function of the protection film 206 includes protecting the defective two-dimensional semiconductor layer 202 from being damaged during the transfer process. In some embodiments, the protection film 206 includes a photoresist material, such as polymethyl methacrylate (PMMA) or other suitable materials, which is flowable and coated on the defective semiconductor layer 202 by a process such as spin coating. The coated protective film 206 is cured into a solid state. In some other embodiments, other flowable and curable materials or dry films that provide protection may also be used. A thermal release tape 208 is then coated onto the PMMA film 206 . The material of the pyrolytic glue 208 may lose its adhesiveness under certain temperature conditions or other conditions such as radiation.

在缺陷二維半導體202材料被保護膜206與熱解膠208覆蓋後，缺陷二維半導體層202會被機械性或化學性地剝離自下方的結晶基板200。接著，缺陷二維半導體層202與上方的保護膜206及熱解膠208會被轉移至晶圓W1的ILD層120上，如第3A至3B圖所示。接著，熱解膠208與保護膜206會從缺陷半導體層202移除。此移除可藉由烘烤如第3B圖所示的結構，例如在溫度120℃至250℃之間，使得熱解膠208失去黏著性因而可自保護膜206上移除。此烘烤可藉由將如第3B圖所示 的結構放置在加熱板(未繪示)上。接著保護膜206會被移除，例如藉由蝕刻或溶解。在保護膜206為PMMA形成的實施例中，保護膜可藉由浸泡此結構於熱丙酮中所移除。浸泡時間例如為20分鐘至70分鐘，熱丙酮溫度可為攝氏35度至攝氏90度。 After the material of the defective two-dimensional semiconductor 202 is covered by the protective film 206 and the pyrolytic glue 208 , the defective two-dimensional semiconductor layer 202 is mechanically or chemically peeled off from the underlying crystal substrate 200 . Then, the defective two-dimensional semiconductor layer 202 and the upper protection film 206 and pyrolytic glue 208 are transferred onto the ILD layer 120 of the wafer W1 , as shown in FIGS. 3A-3B . Then, the pyrolytic glue 208 and the protection film 206 are removed from the defective semiconductor layer 202 . The removal can be performed by baking the structure shown in FIG. 3B , for example, at a temperature between 120° C. and 250° C., so that the pyrolytic glue 208 loses its adhesiveness and can be removed from the protective film 206 . This baking can be achieved by placing the The structure is placed on a heating plate (not shown). The protective film 206 is then removed, such as by etching or dissolving. In embodiments where the protective film 206 is formed of PMMA, the protective film can be removed by soaking the structure in hot acetone. The soaking time is, for example, 20 minutes to 70 minutes, and the temperature of the hot acetone can be 35 degrees Celsius to 90 degrees Celsius.

在移除保護膜206後，缺陷半導體層202留在ILD層120上。感謝的是，無論下方材料例如ILD層120的非晶材料(例如矽氧化物或氮化物)的材料或晶格結構，缺陷半導體層202都為單晶膜。這將助於成長二維材料在ILD層120的非晶材料上，因為形成單晶二維材料於非晶材料上是困難的。 After the protective film 206 is removed, the defective semiconductor layer 202 remains on the ILD layer 120 . Thankfully, the defective semiconductor layer 202 is a single crystal film regardless of the material or lattice structure of the underlying material such as the amorphous material (eg, silicon oxide or nitride) of the ILD layer 120 . This will facilitate the growth of 2D materials on the amorphous material of the ILD layer 120 because it is difficult to form single crystal 2D materials on amorphous materials.

在第4A至4B圖中，缺陷半導體層202藉由適當的微影及蝕刻技術圖案化成複數缺陷二維半導體種子210。在一些實施例中，從俯視來看，缺陷二維半導體種子210實質上等距地排成多個行與多個列，且每個種子210具有低於0.05μm3的小體積(例如，具有10μm2的表面積及0.005μm的厚度)。舉例而言，遮罩層可先形成於缺陷半導體層202上，然後被圖案化成多個種子210的圖案。接著，可採用該圖案化遮罩為蝕刻遮罩，執行蝕刻製程於缺陷二維半導體層202，因此將缺陷二維半導體層202圖案化為多個二維半導體種子210。 In Figures 4A-4B, the defective semiconductor layer 202 is patterned into a plurality of defective two-dimensional semiconductor seeds 210 by appropriate lithography and etching techniques. In some embodiments, the defective two-dimensional semiconductor seeds 210 are substantially equidistantly arranged in rows and columns when viewed from a top view, and each seed 210 has a small volume below 0.05 μm (eg, has a surface area of 10 μm and a thickness of 0.005 μm). For example, a mask layer can be formed on the defective semiconductor layer 202 first, and then patterned into a plurality of patterns of the seeds 210 . Then, the patterned mask can be used as an etching mask, and an etching process is performed on the defective two-dimensional semiconductor layer 202 , so that the defective two-dimensional semiconductor layer 202 is patterned into a plurality of two-dimensional semiconductor seeds 210 .

在一些實施例中，用於形成缺陷二維半導體種子210的圖案化遮罩層可包含有機材料，例如光阻材料，且可其形成包含先進行旋塗製程，接著採用微影技術圖案化 此光阻材料以使其具有種子210的圖案。舉例來說，光阻材料可被曝光及顯影以移除部分的光阻材料。更具體來說，光罩(未繪示)可放置於光阻材料上方，接著光阻材料可藉由輻射源曝光於輻射束，此輻射源可例如為紫外光(UV)源、深紫外光(DUV)源、極紫外光(EUV)源或X光源。舉例來說，輻射源可為具有波長約為436nm(G-line)至365nm(I-line)的範圍之間的汞燈、具有波長約為248nm之氪氟(Krypton Fluoride,KrF)准分子雷射、具有波長約為193nm之氬氟(Argon Fluorid,ArF)準分子雷射、具有波長約為157nm之氟(Fluoride,F2)準分子雷射、或是其他具有一期望之波長(例如低於約100nm)之其他光源。在其他實施例中，光源可為具有波長約為13.5nm或更短的EUV光源。 In some embodiments, the patterned mask layer for forming the defective two-dimensional semiconductor seeds 210 may include organic materials, such as photoresist materials, and may be formed by first performing a spin-coating process, followed by patterning using lithography The photoresist material is made to have a pattern of seeds 210 . For example, the photoresist can be exposed and developed to remove portions of the photoresist. More specifically, a photomask (not shown) can be placed over the photoresist material, and the photoresist material can then be exposed to a radiation beam by a radiation source, such as an ultraviolet (UV) source, deep ultraviolet (DUV) source, extreme ultraviolet (EUV) source, or X-ray source. For example, the radiation source can be a mercury lamp with a wavelength ranging from about 436nm (G-line) to 365nm (I-line), a krypton fluoride (KrF) excimer laser with a wavelength of about 248nm, an argon fluoride (ArF) excimer laser with a wavelength of about 193nm, a fluorine (Fluoride, F2) excimer laser with a wavelength of about 157nm, or others with a desired wavelength Other light sources (eg below about 100 nm). In other embodiments, the light source may be an EUV light source having a wavelength of about 13.5 nm or less.

當圖案化遮罩形成於缺陷二維半導體層202後，缺陷二維半導體層202會藉由採用圖案化遮罩為蝕刻遮罩，被圖案化成多個缺陷二維半導體種子。此圖案化製程可為任何可接受的蝕刻製程，例如活性離子蝕刻(reactive ion etch；RIE)、中性粒子束蝕刻(neutral beam etch；NBE)、相似製程、或其組合。此蝕刻可為非等向性的，因此允許缺陷二維半導體種子210具有實質上垂直的側壁。雖然第4B圖所示的缺陷二維半導體種子210具有垂直側壁，在其他實施例中，此蝕刻製程亦可能產生傾斜側壁，如虛線DL1所示。 After the patterned mask is formed on the defective two-dimensional semiconductor layer 202, the defective two-dimensional semiconductor layer 202 is patterned into a plurality of defective two-dimensional semiconductor seeds by using the patterned mask as an etching mask. The patterning process can be any acceptable etching process, such as reactive ion etch (RIE), neutral beam etch (NBE), similar processes, or combinations thereof. This etching can be anisotropic, thus allowing the defective 2D semiconductor seeds 210 to have substantially vertical sidewalls. Although the defective two-dimensional semiconductor seed 210 shown in FIG. 4B has vertical sidewalls, in other embodiments, the etching process may also produce sloped sidewalls, as shown by the dashed line DL1.

在第5A至5B圖中，介電網格212形成在晶圓 W1的ILD層120上，此步驟係在後續的自二維半導體種子的橫向成長(如第7A至7B圖所示)之前所進行的。介電網格212限位於可能在後續橫向磊晶成長製程中產生的預期晶界，因此可避免晶界形成在後續的橫向磊晶成長中。換句話說，介電網格212的圖案與二維半導體種子210的圖案是共同設計且互相關連的。此外，介電網格212的圖案與後續形成的IC元件(例如電晶體)也是共同設計且互相關連的。介電網格212具有多個網格單元212o，其與缺陷二維半導體種子210係以一對一的方式對應的。在一些實施例中，缺陷二維半導體種子210的中心實質上對齊於網格單元210o的中心。在一些實施例中，介電網格212具有沿著第一方向D1延伸的複數第一網格線2122及沿著第二方向D2延伸的複數第二網格線2124。第二方向D2垂直於第一方向D1。第二網格線2124與第一網格線2122相交。每一網格單元210o係由兩對應的第一網格線2122及兩對應的第二網格線2124所界定的。在一些實施例中，缺陷二維半導體種子210具有圓形或橢圓形的俯視輪廓，因而具有與網格單元210o不同的俯視輪廓。 In Figures 5A-5B, a dielectric grid 212 is formed on the wafer On the ILD layer 120 of W1, this step is performed prior to the subsequent lateral growth from the 2D semiconductor seed (shown in Figures 7A-7B). The dielectric grid 212 is limited to expected grain boundaries that may be generated in subsequent lateral epitaxial growth processes, thereby preventing the formation of grain boundaries in subsequent lateral epitaxial growth processes. In other words, the pattern of the dielectric grid 212 and the pattern of the two-dimensional semiconductor seed 210 are co-designed and interrelated. In addition, the pattern of the dielectric grid 212 is also co-designed and interconnected with the subsequently formed IC components (such as transistors). The dielectric grid 212 has a plurality of grid cells 212o corresponding to the defective 2D semiconductor seeds 210 in a one-to-one manner. In some embodiments, the centers of the defective two-dimensional semiconductor seeds 210 are substantially aligned with the centers of the grid cells 210o. In some embodiments, the dielectric grid 212 has a plurality of first grid lines 2122 extending along the first direction D1 and a plurality of second grid lines 2124 extending along the second direction D2. The second direction D2 is perpendicular to the first direction D1. The second gridline 2124 intersects the first gridline 2122 . Each grid unit 210o is defined by two corresponding first grid lines 2122 and two corresponding second grid lines 2124 . In some embodiments, the defective two-dimensional semiconductor seed 210 has a circular or elliptical top view profile, and thus has a different top view profile than the grid unit 210o.

在一些實施方式中，介電網格212可包含適當的介電材料，例如k值低於4.0甚至2.0的low-k介電材料。舉例來說，介電網格212可由磷矽酸鹽玻璃(phosphosilicate glass；PSG)、硼磷矽酸鹽玻璃(borophosphosilicate glass；BPSG)、氟矽酸鹽玻璃(fluorosilicate glass；FSG)、SiOxCy、旋塗 玻璃、旋塗聚合物、氧化矽、氮氧化矽、上述各者之組合等製成。介電網格212可形成包含，例如，沉積一介電層於缺陷二維半導體種子210上，接著藉由適當的微影與蝕刻劑數圖案化該介電層為介電網格。 In some embodiments, the dielectric mesh 212 may comprise a suitable dielectric material, such as a low-k dielectric material with a k value lower than 4.0 or even 2.0. For example, the dielectric grid 212 may be made of phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy , spin-on-glass, spin-on-polymer, silicon oxide, silicon oxynitride, combinations thereof, and the like. The dielectric grid 212 may be formed by, for example, depositing a dielectric layer on the defective 2D semiconductor seeds 210 and then patterning the dielectric layer into the dielectric grid by appropriate lithography and etchant quantities.

在第6A至6B圖中，退火製程AL1被執行以將缺陷二維半導體種子210轉換成實質上無缺陷的二維半導體種子214。舉例來說，退火製程AL1可使得每一二維半導體種子中的晶體缺陷(例如空位或間隙缺陷)擴散至二維半導體種子的邊緣而消散，因而將每一二維半導體種子中的晶體缺陷降低至低於一閥值，低於該閥值代表有資格做為電晶體通道、汲極及/或源極。由於二維半導體材料沒有懸鍵，故與下方ILD層120的非晶材料沒有或僅有很少的鍵結力。因此，相較於三維半導體材料(例如矽、矽鍺或相似物)，在二維半導體材料中很容易將晶體缺陷擴散。再者，由於二維半導體種子相較於大片的二維半導體層202(如第3B圖所示)具有比較小的尺寸，相較於將晶體缺陷擴散至2D半導體層202的邊緣，將晶體缺陷擴散至二維半導體種子210的邊緣是比較容易的。 In FIGS. 6A-6B , an annealing process AL1 is performed to transform the defective 2D semiconductor seeds 210 into substantially defect-free 2D semiconductor seeds 214 . For example, the annealing process AL1 can cause crystal defects (such as vacancies or interstitial defects) in each two-dimensional semiconductor seed to diffuse to the edge of the two-dimensional semiconductor seed and dissipate, thereby reducing the crystal defect in each two-dimensional semiconductor seed to below a threshold value, which means that the threshold value is qualified as a transistor channel, drain and/or source. Since the two-dimensional semiconductor material has no dangling bonds, there is little or no bonding force with the amorphous material of the underlying ILD layer 120 . Therefore, it is easier to diffuse crystal defects in two-dimensional semiconductor materials than in three-dimensional semiconductor materials such as silicon, silicon germanium or the like. Furthermore, due to the smaller size of the 2D semiconductor seed compared to the larger 2D semiconductor layer 202 (as shown in FIG. 3B ), it is easier to diffuse crystal defects to the edge of the 2D semiconductor seed 210 than to diffuse the crystal defect to the edge of the 2D semiconductor layer 202 .

在一些實施方式中，退火製程AL1的溫度自約攝氏400度至約攝氏1000度，取決於退火環境氣體。在一些實施例中，由於退火製程AL1係執行在小尺寸的二維半導體種子上，退火製程AL1的溫度可為自約攝氏300度至約攝氏600度，以避免種子縮小。如果退火溫度過高(例如高於攝氏1000度)，可能會導致二維半導體材料熔化 或氣化，或誘發與製程氣體的化學反應，導致二維半導體種子中的缺陷增加。如果退火溫度過低(例如低於約攝氏300度)，可能導致不足的結晶活化能，或者可能導致不必要的沉積現象。在一些實施例中，用於形成無缺陷二維半導體種子214的退火製程AL1的溫度為自約攝氏500度至攝氏600度，時間約為1分鐘至90分鐘，且採用H2S或H2Se做為環境氣體。 In some embodiments, the temperature of the annealing process AL1 is from about 400 degrees Celsius to about 1000 degrees Celsius, depending on the annealing ambient gas. In some embodiments, since the annealing process AL1 is performed on the small-sized two-dimensional semiconductor seeds, the temperature of the annealing process AL1 may be from about 300 degrees Celsius to about 600 degrees Celsius to avoid shrinkage of the seeds. If the annealing temperature is too high (for example, higher than 1000 degrees Celsius), it may cause the two-dimensional semiconductor material to melt or vaporize, or induce a chemical reaction with the process gas, resulting in increased defects in the two-dimensional semiconductor seed. If the annealing temperature is too low (eg, less than about 300 degrees Celsius), insufficient crystallization activation energy may result, or unwanted deposition may result. In some embodiments, the temperature of the annealing process AL1 for forming the defect-free two-dimensional semiconductor seed 214 is from about 500°C to 600°C, the time is about 1 minute to 90 minutes, and H 2 S or H 2 Se is used as the ambient gas.

在繪示的實施例中，退火製程AL1係在形成介電網格212後執行的，因此可避免無缺陷二維半導體種子214受到因為介電網格212的沉積與蝕刻製程所造成的潛在傷害。然而，在其他實施例中，退火製程AL1可在形成介電網格212之前執行。在這樣的實施例中，無缺陷二維半導體種子214係在介電網格212形成前所形成。 In the illustrated embodiment, the annealing process AL1 is performed after the dielectric grid 212 is formed, thereby avoiding potential damage to the defect-free two-dimensional semiconductor seeds 214 caused by the deposition and etching process of the dielectric grid 212 . However, in other embodiments, the annealing process AL1 may be performed before forming the dielectric grid 212 . In such an embodiment, the defect-free two-dimensional semiconductor seeds 214 are formed before the dielectric grid 212 is formed.

在第7A至7B圖中，磊晶成長製程EPI1係執行以利用無缺陷二維半導體種子214為種子而橫向成長出二維半導體膜216，使得多個二維半導體膜216分別橫向圍繞多個無缺陷二維半導體種子214。二維半導體膜216的表面積(例如頂表面積)大於無缺陷二維半導體種子214的表面積，且二維半導體膜216的厚度實質上同於無缺陷二維半導體種子214的厚度。一無缺陷二維半導體種子214與自該無缺陷二維半導體種子214橫向成長出的一對應二維半導體膜216可共同稱為一二維半導體島218，此二維半導體島218係侷限於介電網格212中的一網格單元中。從俯視來看，多個二維半導體島218係實質上等距地 排成多個列與多個行。由於二維半導體材料沒有或僅有可忽略的懸鍵在其頂表面，磊晶成長製程EPI1沒有或僅有可忽略的垂直成長速率，因此使得二維半導體膜216具有實質上平坦的表面而沒有具角度的小平面。 In FIGS. 7A to 7B , the epitaxial growth process EPI1 is performed to laterally grow a two-dimensional semiconductor film 216 using the defect-free two-dimensional semiconductor seeds 214 as seeds, so that a plurality of two-dimensional semiconductor films 216 laterally surround a plurality of defect-free two-dimensional semiconductor seeds 214 . The surface area (eg top surface area) of the two-dimensional semiconductor film 216 is greater than that of the defect-free two-dimensional semiconductor seed 214 , and the thickness of the two-dimensional semiconductor film 216 is substantially the same as that of the defect-free two-dimensional semiconductor seed 214 . A defect-free two-dimensional semiconductor seed 214 and a corresponding two-dimensional semiconductor film 216 grown laterally from the defect-free two-dimensional semiconductor seed 214 may collectively be referred to as a two-dimensional semiconductor island 218 that is localized in a grid cell in the dielectric grid 212 . From a top view, the plurality of two-dimensional semiconductor islands 218 are substantially equidistant into multiple columns and multiple rows. Since the two-dimensional semiconductor material has no or only negligible dangling bonds on its top surface, the epitaxial growth process EPI1 has no or only negligible vertical growth rate, thus making the two-dimensional semiconductor film 216 have a substantially flat surface without angled facets.

在一些實施例中，二維半導體膜216包含過渡金屬二硫族化物(transition metal dichalcogenides；TMD)、石墨烯(graphene)、層狀的III-VI硫化物、六方氮化硼(hexagonal boron nitride；h-BN)黑磷(black phosphorus)或類似物。在一些實施例中，二維半導體膜216具有與無缺陷二維半導體種子214相同的二維材料，或者是具有晶格常數(lattice constant)比種子214的晶格常數更小的其他二維材料。舉例來說，當無缺陷二維半導體種子214係由MoS2、WS2、WSe2、或MoSe2所形成時，二維半導體膜216亦係由MoS2、WS2、WSe2、或MoSe2所形成。這是因為MoS2、WS2、WSe2、及MoSe2具有相似的晶格參數(例如，自約0.3奈米至約0.35奈米)。在這樣的實施例中，每一二維半導體膜216可包含一或多層TMD的單層204，其包含如第2B圖所示的過渡金屬原子204M和硫族元素原子204X。在一些實施例中，二維半導體膜216係由沉積方法所磊晶成長的，例如CVD、low pressure CVD(LPCVD)、sub-atmospheric CVD(SACVD)、或類似製程。 In some embodiments, the two-dimensional semiconductor film 216 includes transition metal dichalcogenides (TMD), graphene, layered III-VI sulfides, hexagonal boron nitride (h-BN) black phosphorus, or the like. In some embodiments, the 2D semiconductor film 216 has the same 2D material as the defect-free 2D semiconductor seed 214 , or another 2D material with a smaller lattice constant than the seed 214 . For example, when the defect-free two-dimensional semiconductor seed 214 is formed of MoS 2 , WS 2 , WSe 2 , or MoSe 2 , the two-dimensional semiconductor film 216 is also formed of MoS 2 , WS 2 , WSe 2 , or MoSe 2 . This is because MoS 2 , WS 2 , WSe 2 , and MoSe 2 have similar lattice parameters (eg, from about 0.3 nm to about 0.35 nm). In such an embodiment, each two-dimensional semiconductor film 216 may comprise one or more TMD monolayers 204 comprising transition metal atoms 204M and chalcogen atoms 204X as shown in FIG. 2B . In some embodiments, the two-dimensional semiconductor film 216 is epitaxially grown by a deposition method, such as CVD, low pressure CVD (LPCVD), sub-atmospheric CVD (SACVD), or similar processes.

在磊晶成長EP1中，二維半導體材料從二維半導體種子214成長的速率高於從介電網格212成長的速率。 更具體地說，介電網格212係由介電材料(例如氮化矽)所形成，因此二維半導體材料在介電網格212上沒有或僅具有可忽略的成長速率。因此，此成長選擇性允許二維半導體膜216只從無缺陷二維半導體種子214成長。在一些實施例中，由於無缺陷二維半導體種子214係無缺陷的單晶種子，故從種子214成長出來的二維半導體膜216也是無缺陷的單晶膜。如果介電網格212不存在，當磊晶成長EPI1持續時，從不同種子214成長出的二維半導體膜216最終會相遇而形成晶界(grain boundary)，這些晶界並不適合做為電晶體通道、源極及/或汲極區域。然而，由於在磊晶成長製程EPI1之前，介電網格212已經形成在預期的晶界位置，故介電網格212可避免成長自不同種子的二維半導體膜216相遇而形成晶界。 In epitaxial growth EP1 , the two-dimensional semiconductor material grows at a higher rate from the two-dimensional semiconductor seed 214 than from the dielectric grid 212 . More specifically, the dielectric grid 212 is formed of a dielectric material such as silicon nitride, so the two-dimensional semiconductor material has no or only negligible growth rate on the dielectric grid 212 . Therefore, this growth selectivity allows the two-dimensional semiconductor film 216 to grow only from the defect-free two-dimensional semiconductor seed 214 . In some embodiments, since the defect-free two-dimensional semiconductor seed 214 is a defect-free single crystal seed, the two-dimensional semiconductor film 216 grown from the seed 214 is also a defect-free single crystal film. If the dielectric grid 212 is not present, as the epitaxial growth EPI1 continues, the two-dimensional semiconductor films 216 grown from different seeds 214 will eventually meet to form grain boundaries, which are not suitable as transistor channel, source and/or drain regions. However, since the dielectric grid 212 has been formed at the expected grain boundary position before the epitaxial growth process EPI1, the dielectric grid 212 can prevent the two-dimensional semiconductor films 216 grown from different seeds from meeting to form a grain boundary.

在第8圖中，當二維半導體島218形成後，就可接著形成虛設閘極結構160、閘極間隔物170SP及源極/汲極區170SD。在一些實施例中，虛設閘極結構160可包括虛設閘極介電質160GD、虛設閘極材料160GP及硬遮罩160HM。首先，可沉積虛設閘極介電材料(例如氧化矽、氮化矽等)。接下來，可在虛設閘極介電質上沉積虛設閘極材料(例如非晶矽、多晶矽等)，隨後平坦化(例如藉由CMP)。硬遮罩層(例如氮化矽、碳化矽等)可形成在虛設閘極材料上，並經圖案化成硬遮罩160HM。隨後藉由使用硬遮罩160HM作為蝕刻遮罩圖案化虛設閘極介電質及虛設閘極材料，來形成虛設閘極結構160。用於形成虛 設閘極結構160的材料可使用任何合適的方法來沉積，如CVD、PECVD、ALD、PEALD等，或者透過半導體表面的熱氧化或上述各者之組合來沉積。形成的虛設閘極結構160可延伸跨闊一或多個二維半導體島218。 In FIG. 8, after the two-dimensional semiconductor island 218 is formed, the dummy gate structure 160, the gate spacer 170 SP and the source/drain region 170 SD can be formed next. In some embodiments, the dummy gate structure 160 may include a dummy gate dielectric 160 GD , a dummy gate material 160 GP and a hard mask 160 HM . First, a dummy gate dielectric material (such as silicon oxide, silicon nitride, etc.) can be deposited. Next, a dummy gate material (eg, amorphous silicon, polysilicon, etc.) may be deposited on the dummy gate dielectric, followed by planarization (eg, by CMP). A hard mask layer (eg, silicon nitride, silicon carbide, etc.) can be formed on the dummy gate material and patterned into a hard mask 160 HM . The dummy gate structure 160 is then formed by patterning the dummy gate dielectric and dummy gate material using the hard mask 160 HM as an etch mask. The material used to form the dummy gate structure 160 may be deposited using any suitable method, such as CVD, PECVD, ALD, PEALD, etc., or by thermal oxidation of the semiconductor surface, or a combination thereof. The formed dummy gate structure 160 may extend across one or more two-dimensional semiconductor islands 218 .

如第8圖所示，源極/汲極區170SD及間隔物170SP被形成，例如，自對準於虛設閘極結構160。間隔物170SP可透過在虛設閘極圖案化完成之後執行的間隔物介電層的沉積及非等向性蝕刻來形成。間隔介電層可包括一或多種介電質，如氧化矽、氮化矽、氮氧化矽、碳化矽、碳氮化矽等，或者上述各者之組合。非等向性蝕刻製程從虛設閘極結構的頂部移除間隔物介電層，使得沿著虛設閘極結構160的側壁的間隔物170SP橫向延伸到二維半導體島218的部分表面上。 As shown in FIG. 8 , source/drain regions 170 SD and spacers 170 SP are formed, eg, self-aligned to dummy gate structure 160 . The spacers 170 SP may be formed by deposition of a spacer dielectric layer and anisotropic etching performed after dummy gate patterning is completed. The spacer dielectric layer may include one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, etc., or a combination thereof. The anisotropic etch process removes the spacer dielectric layer from the top of the dummy gate structure such that the spacers 170 SP along the sidewalls of the dummy gate structure 160 extend laterally onto a portion of the surface of the two-dimensional semiconductor island 218 .

源極/汲極區170SD是在二維半導體島218中的摻雜半導體區。在一些實施例中，源極/汲極區170SD可包括重摻雜區及相對輕摻雜的汲極延伸部，或者LDD區。大體上，使用間隔物170SP將重摻雜區與虛設閘極結構160隔開，而LDD區可在形成間隔物170SP之前形成，因此LDD區可在間隔物170SP下方延伸，並且在一些實施例中，LDD區可進一步延伸到虛設閘極結構160下方的二維半導體島218的部分中。例如，可透過使用離子佈植製程佈植n型或p型摻雜劑(例如砷、磷、硼、銦等)進入二維半導體島218的源極/汲極區域中，而無佈植入位於虛設閘極結構160正下方的二維半導體島218的通道區 域中；或者可先沉積摻雜劑來源層於二維半導體島218的源極/汲極區域上，接著藉由退火來將摻雜劑從摻雜劑來源層擴散進二維半導體島218中。 The source/drain regions 170 SD are doped semiconductor regions in the two-dimensional semiconductor island 218 . In some embodiments, the source/drain region 170 SD may include a heavily doped region and a relatively lightly doped drain extension, or an LDD region. In general, the spacers 170 SP are used to separate the heavily doped regions from the dummy gate structure 160, and the LDD regions can be formed before forming the spacers 170 SP , so the LDD regions can extend under the spacers 170 SP , and in some embodiments, the LDD regions can further extend into the portion of the two-dimensional semiconductor island 218 below the dummy gate structure 160. For example, n-type or p-type dopants (such as arsenic, phosphorus, boron, indium, etc.) can be implanted into the source/drain region of the two-dimensional semiconductor island 218 by using an ion implantation process, without implanting into the channel region of the two-dimensional semiconductor island 218 directly below the dummy gate structure 160;

在第9圖中，額外的ILD層182係形成於晶圓W1上。一旦形成源極/汲極區170SD，ILD層182沉積在源極/汲極區170SD上。可執行平坦化製程(例如，CMP)，以從虛設閘極材料160GP上方移除多餘的ILD材料及硬遮罩160HM，從而形成頂表面，其中虛設閘極材料的頂表面被曝露，並且可與ILD層180的頂表面基本共面。在一些實施例中，可在沉積ILD材料之前沉積合適介電質(例如氮化矽、碳化矽等或其組合)的接觸蝕刻停止層(contact etch stop layer；CESL)(未示出)。 In FIG. 9, an additional ILD layer 182 is formed on wafer W1. Once the source/drain regions 170 SD are formed, an ILD layer 182 is deposited on the source/drain regions 170 SD . A planarization process (eg, CMP) may be performed to remove excess ILD material and hard mask 160 HM from above dummy gate material 160 GP to form a top surface, wherein the top surface of dummy gate material is exposed and may be substantially coplanar with the top surface of ILD layer 180 . In some embodiments, a contact etch stop layer (CESL) (not shown) of a suitable dielectric (eg, silicon nitride, silicon carbide, etc., or a combination thereof) may be deposited prior to depositing the ILD material.

隨後，如第10圖所示，HKMG閘極結構170G可被形成。首先可透過使用一或多種蝕刻技術移除虛設閘極結構160從而在相應的間隔物170SP之間產生凹陷。接下來，沉積包括一或多種介電質的替換閘極介電層170GD，隨後沉積包括一或多種金屬的替換閘極金屬層170GM，以完全填充間隔物170SP之間的凹陷。閘極結構層170GD及170GM的多餘部分可使用例如CMP製程從ILD層182的頂表面上移除。所得的HKMG閘極結構170G可包括嵌入在相應間隔物170SP之間的HKMG閘極層170GD及170GM的剩餘部分。 Subsequently, as shown in FIG. 10, an HKMG gate structure 170G may be formed. Dummy gate structures 160 may first be removed by using one or more etch techniques to create recesses between corresponding spacers 170 SP . Next, a replacement gate dielectric layer 170 GD including one or more dielectrics is deposited, followed by a replacement gate metal layer 170 GM including one or more metals to completely fill the recesses between the spacers 170 SP . Excess portions of gate structure layers 170 GD and 170 GM may be removed from the top surface of ILD layer 182 using, for example, a CMP process. The resulting HKMG gate structure 170G may include remaining portions of HKMG gate layers 170GD and 170GM embedded between respective spacers 170SP .

閘極介電層170GD包括與內連接結構106下方的電晶體104中的閘極介電層104GD類似的材料。例如， 閘極介電層170GD包括高k介電材料，例如金屬的氧化物及/或矽酸鹽(例如，鉿、鋁、鋯、鑭、鎂、鋇、鈦及其他金屬的氧化物及/或矽酸鹽)、氮化矽、氧化矽等，或上述各者之組合，或上述各者之多層。在一些實施例中，閘極金屬層170GM包括與內連接結構106下方的電晶體104中的閘極金屬層104GM相似的材料。例如，閘極金屬層170GM可包括在閘極介電層170GD的頂部連續形成的阻障層、功函數層及閘極填充層。阻障層的示例材料包括TiN、TaN、鈦、鉭等，或者上述各者的多層組合。p型場效應電晶體的功函數層可包括TiN、TaN、釕、鉬、鋁，n型場效應電晶體的功函數層可包括鈦、銀、TaAl、TaAlC、TiAlN、TaC、TaCN、TaSiN、錳、鋯。填充凹槽剩餘部分的閘極填充層可包括金屬，如銅、鋁、鎢、鈷、釕等，或者上述各者之組合，或者上述各者的多層。用於形成閘極結構的材料可透過任何合適的方法沉積，該等方法例如CVD、PECVD、PVD、ALD、PEALD、ECP、無電極電鍍及/或類似方法。 Gate dielectric layer 170 GD includes a similar material to gate dielectric layer 104 GD in transistor 104 below interconnect structure 106 . For example, the gate dielectric layer 170 GD includes a high-k dielectric material, such as metal oxides and/or silicates (eg, oxides and/or silicates of hafnium, aluminum, zirconium, lanthanum, magnesium, barium, titanium, and other metals), silicon nitride, silicon oxide, etc., or a combination of the above, or multiple layers of the above. In some embodiments, gate metal layer 170 GM includes a similar material as gate metal layer 104 GM in transistor 104 below interconnect structure 106 . For example, the gate metal layer 170 GM may include a barrier layer, a work function layer, and a gate filling layer continuously formed on top of the gate dielectric layer 170 GD . Example materials for the barrier layer include TiN, TaN, titanium, tantalum, etc., or a multilayer combination of the above. The work function layer of the p-type field effect transistor can include TiN, TaN, ruthenium, molybdenum, aluminum, and the work function layer of the n-type field effect transistor can include titanium, silver, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, manganese, zirconium. The gate fill layer filling the remainder of the recess may include metals such as copper, aluminum, tungsten, cobalt, ruthenium, etc., or combinations thereof, or multiple layers thereof. Materials used to form the gate structures may be deposited by any suitable method, such as CVD, PECVD, PVD, ALD, PEALD, ECP, electroless plating, and/or the like.

在形成HKMG結構170G之後，在ILD層182上沉積另一個ILD層184。在一些實施例中，ILD層182及184的材料可類似於ILD層1100及IMD層1101至110M及1111至111M中的一或多個的材料，因此為了簡潔起見不再重複。用於形成ILD層182及184層的介電材料可使用任何合適的方法沉積，如CVD、PVD、ALD、PEALD、PECVD、SACVD、FCVD、旋塗等，或者上 述各者之組合。一旦形成ILD層184，在ILD層182及184中形成接觸窗186，以分別落在位於二維半導體島218上的閘極結構170G及位於二維半導體島218中的源極/汲極區170SD上。接觸窗186使用如前文關於接觸窗1120所述的光微影術、蝕刻及沉積技術形成，並且具有與接觸窗1120相似的材料，因此為了簡潔起見，不再重複接觸窗186的製造步驟及材料。 After forming the HKMG structure 170G , another ILD layer 184 is deposited on the ILD layer 182 . In some embodiments, the materials of ILD layers 182 and 184 may be similar to those of one or more of ILD layer 1100 and IMD layers 1101-110M and 1111-111M , and thus are not repeated for brevity. The dielectric material used to form ILD layers 182 and 184 may be deposited using any suitable method, such as CVD, PVD, ALD, PEALD, PECVD, SACVD, FCVD, spin coating, etc., or combinations thereof. Once the ILD layer 184 is formed, contact windows 186 are formed in the ILD layers 182 and 184 to respectively land on the gate structure 170 G on the two-dimensional semiconductor island 218 and the source/drain region 170 SD on the two-dimensional semiconductor island 218 . Contact 186 is formed using photolithography, etching, and deposition techniques as previously described for contact 1120 , and has similar materials to contact 1120 , so the fabrication steps and materials for contact 186 are not repeated for brevity.

在第11圖中，在形成接觸窗186後，另一內連接結構190形成在ILD層184上。此內連接結構190係採用與前文中關於內連接結構106所述的類似製程及材料所形成。舉例來說，內連接結構190電性連接一或多個在二維半導體島218上的電晶體170，且更藉由，例如，從上方內連接結構190延伸通過介電網格212及/或二維半導體島218至下方內連接結構106的一或多個深通孔(deep through via)來電性連接一或多個形成在基板102上的電晶體。內連接結構190可包含一或多個金屬化層192，其每一者包含多個介電層194、分別延伸在介電層194中的水平互連196(例如金屬線)及垂直互連198(例如金屬通孔)。 In FIG. 11, another interconnection structure 190 is formed on the ILD layer 184 after the contact opening 186 is formed. The interconnect structure 190 is formed using similar processes and materials as described above for the interconnect structure 106 . For example, interconnection structure 190 electrically connects one or more transistors 170 on two-dimensional semiconductor island 218 , and further electrically connects one or more transistors formed on substrate 102 by, for example, one or more deep through vias extending from upper interconnection structure 190 through dielectric grid 212 and/or two-dimensional semiconductor island 218 to lower interconnection structure 106 . The interconnect structure 190 may include one or more metallization layers 192 each including a plurality of dielectric layers 194 , horizontal interconnects 196 (eg, metal lines) and vertical interconnects 198 (eg, metal vias) respectively extending in the dielectric layers 194 .

HKMG結構170G、HKMG結構170G相對兩側的源極/汲極區170SD及下方的二維半導體島218的部分一起做為形成在二維半導體島218上的電晶體170。內連接結構106上方的電晶體170及內連接結構106下方的電晶體104可形成積體電路(IC)。因為積體電路包括不 同高度的電晶體(例如，比電晶體104位置更高的電晶體170)，因此其可被稱為三維(three dimensional；3D)積體電路結構。雖然在第11圖所示的電晶體170為平面電晶體(planar transistors)，在其他實施方式中，電晶體170可為形成在二維半導體島218上的非平面電晶體例如FinFETs或GAA FETs。 The HKMG structure 170 G , the source/drain regions 170 SD on opposite sides of the HKMG structure 170 G and the lower portion of the two-dimensional semiconductor island 218 together serve as the transistor 170 formed on the two-dimensional semiconductor island 218 . Transistor 170 above interconnect structure 106 and transistor 104 below interconnect structure 106 may form an integrated circuit (IC). Because the IC includes transistors of different heights (eg, transistor 170 positioned higher than transistor 104 ), it may be referred to as a three-dimensional (3D) IC structure. Although the transistors 170 shown in FIG. 11 are planar transistors, in other embodiments, the transistors 170 may be non-planar transistors such as FinFETs or GAA FETs formed on the two-dimensional semiconductor island 218 .

第12A至14圖示出了根據本揭示案的一些其他實施例的用於製造三維積體電路的各個階段的示例性立體圖剖面圖。應當理解，對於此方法的額外實施例，可在第12A至14圖所示的製程之前、期間及之後提供額外處理，並且可替換或消除下文描述的一些處理。處理/製程的順序可互換。在以下實施例中，可採用與第1A至11圖所描述的相同或相似的配置、材料、製程及/或處理，並且可省略詳細說明。 Figures 12A to 14 illustrate exemplary perspective cutaway views of various stages for fabricating a three-dimensional integrated circuit according to some other embodiments of the present disclosure. It should be understood that for additional embodiments of the method, additional processing may be provided before, during, and after the processes shown in Figures 12A-14, and that some of the processing described below may be substituted or eliminated. The order of treatments/processes can be interchanged. In the following embodiments, the same or similar configurations, materials, processes and/or processes as those described in FIGS. 1A to 11 may be used, and detailed description may be omitted.

在第12A及12B圖中，在形成缺陷二維半導體種子210(如第4A至4B圖所示的步驟)完成後，退火製程AL2被執行以將缺陷二維半導體種子轉換成無缺陷半導體種子214，而未形成介電網格於ILD層120上。換句話說，形成介電網格的步驟被跳過。此退火製程AL2係類似於前文中關於第6A-6B圖所述的退火製程AL1，故為了簡潔起見而不重複。 In FIGS. 12A and 12B, after the formation of defective two-dimensional semiconductor seeds 210 (steps shown in FIGS. 4A-4B ) is completed, an annealing process AL2 is performed to convert the defective two-dimensional semiconductor seeds into defect-free semiconductor seeds 214 without forming a dielectric grid on the ILD layer 120. In other words, the step of forming a dielectric grid is skipped. This annealing process AL2 is similar to the annealing process AL1 described above with respect to FIGS. 6A-6B , so it is not repeated for brevity.

在第13A及13B圖中，磊晶成長製程EPI2係執行以利用無缺陷二維半導體種子214為種子而橫向成長出二維半導體膜216。一無缺陷二維半導體種子214與自該 無缺陷二維半導體種子214橫向成長出的一對應二維半導體膜216可共同稱為一二維半導體島218。磊晶成長製程EPI2的磊晶條件(例如時間、溫度等等)被選擇使得在磊晶成長製程EPI2完成後，多個二維半導體島218是彼此分隔的。舉例來說，磊晶時間被控制使得二維半導體膜216在彼此碰到而形成晶界之前就停止橫向成長。二維半導體膜216的材料類似於前文關於第7A至7B圖的描述，故為了簡潔不重複。 In FIGS. 13A and 13B , the epitaxial growth process EPI2 is performed to laterally grow a two-dimensional semiconductor film 216 using the defect-free two-dimensional semiconductor seed 214 as a seed. A defect-free two-dimensional semiconductor seed 214 with the A corresponding pair of two-dimensional semiconductor films 216 grown laterally from the defect-free two-dimensional semiconductor seeds 214 may be collectively referred to as a two-dimensional semiconductor island 218 . The epitaxial conditions (such as time, temperature, etc.) of the epitaxial growth process EPI2 are selected such that the plurality of two-dimensional semiconductor islands 218 are separated from each other after the epitaxial growth process EPI2 is completed. For example, the epitaxy time is controlled so that the two-dimensional semiconductor films 216 stop growing laterally before they meet each other to form grain boundaries. The material of the two-dimensional semiconductor film 216 is similar to that described above in relation to FIGS. 7A to 7B , so it is not repeated for brevity.

接著，在第14圖中，多個電晶體170形成在二維半導體島218上，每一電晶體包含閘極結構170G及閘極結構170G相對兩側的源極/汲極區170SD。接觸窗186接著形成在閘極結構170G及源極/汲極區170SD上。上方內連接結構190接著形成在接觸窗186上。所得的結構如第14圖所示。電晶體170、接觸窗186、及內連接結構190的形成如同第8至11圖所示，故為了簡潔不重複。 Next, in FIG. 14 , a plurality of transistors 170 are formed on the two-dimensional semiconductor island 218 , and each transistor includes a gate structure 170 G and source/drain regions 170 SD on opposite sides of the gate structure 170 G. Contacts 186 are then formed on the gate structure 170G and the source/drain regions 170SD . An upper interconnection structure 190 is then formed on the contact 186 . The resulting structure is shown in Figure 14. The transistor 170, the contact window 186, and the interconnection structure 190 are formed as shown in FIGS. 8 to 11, so they are not repeated for brevity.

第15A至17圖示出了根據本揭示案的一些其他實施例的用於製造三維積體電路的各個階段的示例性立體圖及剖面圖。應當理解，對於此方法的額外實施例，可在第15A至17圖所示的製程之前、期間及之後提供額外處理，並且可替換或消除下文描述的一些處理。處理/製程的順序可互換。在以下實施例中，可採用與第1A至11圖所描述的相同或相似的配置、材料、製程及/或處理，並且可省略詳細說明。 Figures 15A-17 show exemplary perspective and cross-sectional views of various stages for fabricating a three-dimensional integrated circuit according to some other embodiments of the present disclosure. It should be understood that for additional embodiments of the method, additional processing may be provided before, during, and after the processes shown in Figures 15A-17, and that some of the processing described below may be substituted or eliminated. The order of treatments/processes can be interchanged. In the following embodiments, the same or similar configurations, materials, processes and/or processes as those described in FIGS. 1A to 11 may be used, and detailed description may be omitted.

在第15A至15B圖中，在完成形成缺陷二維半導 體種子210的圖案化製程(第4A至4B圖的步驟)後，執行退火製程AL3以將缺陷二維半導體種子轉換成無缺陷二維半導體種子214，而未形成介電網格於ILD層120上。退火製程AL3類似於前文中關於第6A至6B圖所述的退火製程AL1，故為了簡潔起見不重複。 In Figures 15A to 15B, after completing the formation of defect two-dimensional semiconductor After the patterning process of the bulk seeds 210 (steps of FIGS. 4A-4B ), an annealing process AL3 is performed to convert the defective 2D semiconductor seeds into defect-free 2D semiconductor seeds 214 without forming a dielectric grid on the ILD layer 120 . The annealing process AL3 is similar to the annealing process AL1 described above with respect to FIGS. 6A-6B , so it is not repeated for brevity.

在第16A及16B圖中，磊晶成長製程EPI3係執行以利用無缺陷二維半導體種子214為種子而橫向成長出二維半導體膜216。無缺陷二維半導體種子214與自該無缺陷二維半導體種子214橫向成長出的一對應二維半導體膜216可共同稱為一二維半導體島218。磊晶成長製程EPI3的磊晶條件(例如時間、溫度等等)被選擇使得多個二維半導體島218相遇形成晶界GB1及GB2(統稱為晶界GB)。由於二維半導體膜216係橫向成長自位於預定位置的二維半導體種子214，晶界GB1及GB2的位置是可預測且可控制的。因此，晶界GB1及GB2可藉由設計二維半導體種子214的圖案，來形成在預期的位置。舉例來說，呈多行與多列排列的二維半導體種子214允許晶界GB1及GB2一起形成網格圖案，其中晶界GB1沿著第一方向D1延伸，晶界GB2沿著與第一方向D1垂直的第二方向D2延伸，並與晶界GB1相交。由於晶界GB1及GB2的圖案係可藉由二維半導體種子214的圖案預測並控制的，電晶體佈局與內連接線的佈局可與二維半導體種子214的圖案共同設計並互相關連，從而避免形成電晶體在晶界GB1及GB2上。因此，沒有電晶體或金屬內連接線將被 形成在晶界GB1及GB2上。二維半導體膜216的材料係類似於第7A至7B圖的描述，故為了簡潔不重複。 In FIGS. 16A and 16B , the epitaxial growth process EPI3 is performed to laterally grow a two-dimensional semiconductor film 216 using the defect-free two-dimensional semiconductor seed 214 as a seed. The defect-free two-dimensional semiconductor seed 214 and a corresponding pair of two-dimensional semiconductor films 216 laterally grown from the defect-free two-dimensional semiconductor seed 214 may be collectively referred to as a two-dimensional semiconductor island 218 . The epitaxial conditions (such as time, temperature, etc.) of the epitaxial growth process EPI3 are selected such that a plurality of two-dimensional semiconductor islands 218 meet to form grain boundaries GB1 and GB2 (collectively referred to as grain boundaries GB). Since the two-dimensional semiconductor film 216 is laterally grown from the two-dimensional semiconductor seed 214 at a predetermined position, the positions of the grain boundaries GB1 and GB2 are predictable and controllable. Therefore, the grain boundaries GB1 and GB2 can be formed at desired positions by designing the pattern of the two-dimensional semiconductor seed 214 . For example, the two-dimensional semiconductor seeds 214 arranged in multiple rows and columns allow the grain boundaries GB1 and GB2 to form a grid pattern together, wherein the grain boundaries GB1 extend along the first direction D1, and the grain boundaries GB2 extend along the second direction D2 perpendicular to the first direction D1 and intersect the grain boundaries GB1. Since the patterns of the grain boundaries GB1 and GB2 can be predicted and controlled by the pattern of the two-dimensional semiconductor seeds 214, the layout of the transistors and the layout of the interconnection lines can be co-designed and interconnected with the patterns of the two-dimensional semiconductor seeds 214, thereby avoiding the formation of transistors on the grain boundaries GB1 and GB2. Therefore, no transistors or metal interconnects will be Formed on grain boundaries GB1 and GB2. The material system of the two-dimensional semiconductor film 216 is similar to that described in FIGS. 7A to 7B , so it is not repeated for brevity.

接著，在第17圖中，多個電晶體170形成在二維半導體島218上，每一電晶體包含閘極結構170G及閘極結構170G相對兩側的源極/汲極區170SD。接觸窗186接著形成在閘極結構170G及源極/汲極區170SD上。上方內連接結構190接著形成在接觸窗186上。所得的結構如第17圖所示。電晶體170、接觸窗186、及內連接結構190的形成如同第8至11圖所示，故為了簡潔不重複。 Next, in FIG. 17 , a plurality of transistors 170 are formed on the two-dimensional semiconductor island 218 , each transistor includes a gate structure 170 G and source/drain regions 170 SD on opposite sides of the gate structure 170 G. Contacts 186 are then formed on the gate structure 170G and the source/drain regions 170SD . An upper interconnection structure 190 is then formed on the contact 186 . The resulting structure is shown in Figure 17. The transistor 170, the contact window 186, and the interconnection structure 190 are formed as shown in FIGS. 8 to 11, so they are not repeated for brevity.

第18至22圖示出了根據本揭示案的一些其他實施例的用於製造三維積體電路的各個階段的示例性立體圖及剖面圖。應當理解，對於此方法的額外實施例，可在第18至22圖所示的製程之前、期間及之後提供額外處理，並且可替換或消除下文描述的一些處理。處理/製程的順序可互換。在以下實施例中，可採用與第1A至11圖所描述的相同或相似的配置、材料、製程及/或處理，並且可省略詳細說明。 Figures 18-22 illustrate exemplary perspective and cross-sectional views of various stages for fabricating a three-dimensional integrated circuit according to some other embodiments of the present disclosure. It should be understood that for additional embodiments of the method, additional processing may be provided before, during, and after the processes shown in Figures 18-22, and that some of the processing described below may be substituted or eliminated. The order of treatments/processes can be interchanged. In the following embodiments, the same or similar configurations, materials, processes and/or processes as those described in FIGS. 1A to 11 may be used, and detailed description may be omitted.

在第18圖中，在形成ILD層120(第1A至1B圖所示的步驟)後，含過渡金屬(transition metal-containing)層302藉由CVD、ALD、PVD或其他適合的沉積技術沉積於ILD層120上。在一些實施例中，含過渡金屬層302係由過渡金屬氧化物所形成，包含，例如MoOx、WOx、或其他可用於形成TMD的合適過渡金屬氧化物材料。在其他實施例中，含過渡金屬層302 係由過渡金屬所形成，例如，Mo、W、Pt、或其他可用於形成TMD的合適過渡金屬。 In FIG. 18, after forming the ILD layer 120 (the steps shown in FIGS. 1A-1B ), a transition metal-containing layer 302 is deposited on the ILD layer 120 by CVD, ALD, PVD, or other suitable deposition techniques. In some embodiments, the transition metal-containing layer 302 is formed of transition metal oxides, including, for example, MoOx , WOx , or other suitable transition metal oxide materials that can be used to form TMDs. In other embodiments, the transition metal-containing layer 302 is formed of transition metals, such as Mo, W, Pt, or other suitable transition metals that can be used to form TMDs.

在第19A及19B圖中，含過渡金屬層302藉由適當的微影及蝕刻技術圖案化成複數含過渡金屬塊310。在一些實施例中，每一含過渡金屬塊310具有低於0.05μm3的小體積(例如，具有10μm2的表面積及0.005μm的厚度)。舉例來說，遮罩層可先形成於含過渡金屬層302上並接著被圖案化成具有含過渡金屬塊的圖案。接著可採用圖案化遮罩層做為蝕刻遮罩在含過渡金屬層302上執行蝕刻製程，因而將含過渡金屬層302圖案化成含過渡金屬塊310。 In Figures 19A and 19B, the transition metal-containing layer 302 is patterned into a plurality of transition metal-containing blocks 310 by suitable lithography and etching techniques. In some embodiments, each transition metal-containing block 310 has a small volume below 0.05 μm 3 (eg, has a surface area of 10 μm 2 and a thickness of 0.005 μm). For example, a mask layer may be first formed on the transition metal-containing layer 302 and then patterned with a pattern of transition metal-containing blocks. An etching process may then be performed on the transition metal-containing layer 302 using the patterned mask layer as an etching mask, thereby patterning the transition metal-containing layer 302 into transition metal-containing blocks 310 .

在一些實施例中，用於形成含過渡金屬層302的圖案化遮罩層可包含有機材料，例如光阻材料，且可其形成包含先進行旋塗製程，接著採用微影技術圖案化此光阻材料以使其具有含過渡金屬塊310的圖案。舉例來說，光阻材料可被曝光及顯影以移除部分的光阻材料。更具體來說，光罩(未繪示)可放置於光阻材料上方，接著光阻材料可藉由輻射源曝光於輻射束，此輻射源可例如為紫外光(UV)源、深紫外光(DUV)源、極紫外光(EUV)源或X光源。舉例來說，輻射源可為具有波長約為436nm(G-line)至365nm(I-line)的範圍之間的汞燈、具有波長約為248nm之氪氟(Krypton Fluoride,KrF)準分子雷射、具有波長約為193nm之氬氟(Argon Fluorid,ArF)準分子雷射、具有波長約為157nm之氟 (Fluoride,F2)準分子雷射、或是其他具有一期望之波長(例如低於約100nm)之其他光源。在其他實施例中，光源可為具有波長約為13.5nm或更短的EUV光源。 In some embodiments, the patterned mask layer used to form the transition metal-containing layer 302 may include an organic material, such as a photoresist material, and its formation may include performing a spin-coating process first, and then patterning the photoresist material to have a pattern of transition metal-containing blocks 310 using lithography. For example, the photoresist can be exposed and developed to remove portions of the photoresist. More specifically, a photomask (not shown) can be placed over the photoresist material, and the photoresist material can then be exposed to a radiation beam by a radiation source, such as an ultraviolet (UV) source, deep ultraviolet (DUV) source, extreme ultraviolet (EUV) source, or X-ray source. For example, the radiation source can be a mercury lamp with a wavelength between about 436nm (G-line) and 365nm (I-line), a krypton fluoride (KrF) excimer laser with a wavelength of about 248nm, an argon fluoride (ArF) excimer laser with a wavelength of about 193nm, a fluorine laser with a wavelength of about 157nm (Fluoride, F2) excimer laser, or other light sources with a desired wavelength (eg, below about 100 nm). In other embodiments, the light source may be an EUV light source having a wavelength of about 13.5 nm or less.

當圖案化遮罩形成於含過渡金屬層302後，含過渡金屬層302會藉由採用圖案化遮罩為蝕刻遮罩，被圖案化成多個含過渡金屬塊310。此圖案化製程可為任何可接受的蝕刻製程，例如活性離子蝕刻(reactive ion etch；RIE)、中性粒子束蝕刻(neutral beam etch；NBE)、相似製程、或其組合。此蝕刻可為非等向性的，因此允許含過渡金屬塊310具有實質上垂直的側壁。雖然第19B圖所示的含過渡金屬塊310具有垂直側壁，在其他實施例中，此蝕刻製程亦可能產生傾斜側壁，如虛線DL2所示。 After the patterned mask is formed on the transition metal-containing layer 302, the transition metal-containing layer 302 is patterned into a plurality of transition metal-containing blocks 310 by using the patterned mask as an etching mask. The patterning process can be any acceptable etching process, such as reactive ion etch (RIE), neutral beam etch (NBE), similar processes, or combinations thereof. This etch can be anisotropic, thus allowing the transition metal-containing block 310 to have substantially vertical sidewalls. Although the transition metal-containing block 310 shown in FIG. 19B has vertical sidewalls, in other embodiments, the etching process may also produce sloped sidewalls, as shown by the dashed line DL2.

在第20A至20B圖中，介電網格212形成在晶圓W1的ILD層120上，此步驟係在後續的自二維半導體種子的橫向成長之前所進行的。介電網格212限位於可能在後續橫向磊晶成長製程中產生的預期晶界，因此可避免晶界形成在後續的橫向磊晶成長中。換句話說，介電網格212的圖案與含過渡金屬塊310的圖案是共同設計且互相關連的。介電網格212具有多個網格單元212o，其與含過渡金屬塊310係以一對一的方式對應的。在一些實施例中，含過渡金屬塊310的中心實質上對齊於網格單元210o的中心。在一些實施例中，介電網格212具有沿著第一方向D1延伸的複數第一網格線2122及沿著第二方向D2延伸的複數第二網格線2124。第二方向D2垂直於 第一方向D1。第二網格線2124與第一網格線2122相交。每一網格單元210o係由兩對應的第一網格線2122及兩對應的第二網格線2124所界定的，因此具有矩形或正方形俯視輪廓。在一些實施方式中，含過渡金屬塊310具有圓形或橢圓形的俯視輪廓，因而具有與網格單元210o不同的俯視輪廓。介電網格212的材料與製程如同前文中關於第5A至5B圖的描述，故為了簡潔起見不重複。 In FIGS. 20A-20B , a dielectric grid 212 is formed on the ILD layer 120 of wafer W1 prior to subsequent lateral growth from two-dimensional semiconductor seeds. The dielectric grid 212 is limited to expected grain boundaries that may be generated in subsequent lateral epitaxial growth processes, thereby preventing the formation of grain boundaries in subsequent lateral epitaxial growth processes. In other words, the pattern of the dielectric mesh 212 and the pattern of the transition metal-containing blocks 310 are co-designed and interrelated. The dielectric grid 212 has a plurality of grid cells 212o that correspond in a one-to-one manner with the transition metal-containing blocks 310 . In some embodiments, the center of the transition metal-containing block 310 is substantially aligned with the center of the grid cell 210o. In some embodiments, the dielectric grid 212 has a plurality of first grid lines 2122 extending along the first direction D1 and a plurality of second grid lines 2124 extending along the second direction D2. The second direction D2 is perpendicular to The first direction D1. The second gridline 2124 intersects the first gridline 2122 . Each grid unit 210o is defined by two corresponding first grid lines 2122 and two corresponding second grid lines 2124, and thus has a rectangular or square top profile. In some embodiments, the transition metal-containing block 310 has a circular or elliptical top view profile and thus has a different top view profile than the grid cell 210o. The materials and processes of the dielectric grid 212 are the same as those described above with respect to FIGS. 5A-5B , so they are not repeated for brevity.

在第21A至21B圖中，退火製程AL4被執行以將含過渡金屬塊310轉換成無缺陷二維半導體種子(亦即，TMD種子)314。舉例來說，退火製程AL4可採用含硫氣體(例如H2S)或是含硒氣體(例如H2Se)做為環境氣體，從而硫化(sulfurize)或硒化(selenize)含過渡金屬塊310成為TMD種子314。舉例來說，在含過渡金屬塊310為WOx的實施例中，採用H2S的退火製程AL4會與WOx產生硫化反應，因而形成WS2以做為TMD種子314。在含過渡金屬塊310為WOx的實施例中，採用H2Se的退火製程AL4會與WOx產生硒化反應，因而形成WSe2以做為TMD種子314。再者，退火製程AL4可使得每一二維半導體種子中的晶體缺陷(例如空位及/或間隙缺陷)擴散至二維半導體種子的邊緣而消散，因而將每一二維半導體種子中的晶體缺陷降低至低於一閥值，低於該閥值代表有資格做為電晶體通道、汲極及/或源極。 In FIGS. 21A-21B , annealing process AL4 is performed to convert transition metal-containing bulk 310 into defect-free two-dimensional semiconductor seeds (ie, TMD seeds) 314 . For example, the annealing process AL4 can use a sulfur-containing gas (such as H 2 S) or a selenium-containing gas (such as H 2 Se) as the ambient gas, so as to sulfurize or selenize the transition metal-containing block 310 to become the TMD seed 314 . For example, in the embodiment where the transition metal-containing block 310 is WO x , the annealing process AL4 using H 2 S will produce a sulfidation reaction with WO x , thus forming WS 2 as the TMD seed 314 . In the embodiment where the transition metal-containing block 310 is WO x , the annealing process AL4 using H 2 Se will generate a selenization reaction with WO x , thereby forming WSe 2 as the TMD seed 314 . Moreover, the annealing process AL4 can make the crystal defects (such as vacancies and/or interstitial defects) in each two-dimensional semiconductor seed diffuse to the edge of the two-dimensional semiconductor seed and dissipate, thereby reducing the crystal defect in each two-dimensional semiconductor seed to be lower than a threshold value, which means that the threshold value is qualified as a transistor channel, drain and/or source.

在一些實施方式中，退火製程AL4的溫度自約攝氏400度至約攝氏1000度，取決於退火環境氣體。在一 些實施例中，由於退火製程AL4係執行在小尺寸的含過渡金屬塊上，因此，退火製程AL4的溫度可為自約攝氏300度至約攝氏600度，以避免種子縮小。如果退火溫度過高(例如高於攝氏1000度)，可能會導致含過渡金屬塊熔化或氣化，或誘發與製程氣體的化學反應，導致二維半導體種子中的缺陷增加。如果退火溫度過低(例如低於約攝氏300度)，可能導致不足的結晶活化能，或者可能導致不必要的沉積現象。在一些實施例中，用於形成無缺陷二維半導體種子314的退火製程AL4的溫度為自約攝氏500度至攝氏600度，時間約為1分鐘至90分鐘，且採用H2S或H2Se做為環境氣體。 In some embodiments, the temperature of the annealing process AL4 is from about 400 degrees Celsius to about 1000 degrees Celsius, depending on the annealing ambient gas. In some embodiments, since the annealing process AL4 is performed on the small transition metal-containing block, the temperature of the annealing process AL4 may be from about 300 degrees Celsius to about 600 degrees Celsius to avoid seed shrinkage. If the annealing temperature is too high (for example, higher than 1000 degrees Celsius), it may cause the melting or gasification of the transition metal-containing bulk, or induce a chemical reaction with the process gas, resulting in increased defects in the 2D semiconductor seed. If the annealing temperature is too low (eg, less than about 300 degrees Celsius), insufficient crystallization activation energy may result, or unwanted deposition may result. In some embodiments, the temperature of the annealing process AL4 for forming the defect-free two-dimensional semiconductor seed 314 is from about 500°C to 600°C, the time is about 1 minute to 90 minutes, and H 2 S or H 2 Se is used as the ambient gas.

在第22圖中，磊晶成長製程EPI4係執行以利用無缺陷二維半導體種子314為種子而橫向成長出二維半導體膜316。一無缺陷二維半導體種子314與自該無缺陷二維半導體種子314橫向成長出的一對應二維半導體膜316可共同稱為一二維半導體島318。該二維半導體島318係侷限於介電網格212的一網格單元中。在一些實施例中，二維半導體膜316具有與無缺陷二維半導體種子314相同的二維材料，或者是具有晶格常數比種子314的晶格常數更小的其他二維材料。舉例來說，當無缺陷TMD種子314係由WS2所形成，二維半導體膜316亦可由WS2所形成，其形成方式可為以WF6及H2S做為前驅物的CVD或ALD。在這樣的狀況下，WS2膜316可由WS2種子314的邊緣橫向成長。當無缺陷TMD種子314係由WSe2所 形成，二維半導體膜316可由MoS2所形成，其形成方式可為以MoO3及硫蒸氣為前驅物的CVD。在這樣的狀況下，MoS2膜316可從WeSe2種子314的邊緣橫向成長。 In FIG. 22, the epitaxial growth process EPI4 is performed to laterally grow a two-dimensional semiconductor film 316 using a defect-free two-dimensional semiconductor seed 314 as a seed. A defect-free two-dimensional semiconductor seed 314 and a corresponding two-dimensional semiconductor film 316 grown laterally from the defect-free two-dimensional semiconductor seed 314 may be collectively referred to as a two-dimensional semiconductor island 318 . The two-dimensional semiconductor island 318 is confined within a grid cell of the dielectric grid 212 . In some embodiments, the two-dimensional semiconductor film 316 is of the same two-dimensional material as the defect-free two-dimensional semiconductor seed 314 , or another two-dimensional material with a smaller lattice constant than the seed 314 . For example, when the defect-free TMD seed 314 is formed from WS 2 , the two-dimensional semiconductor film 316 can also be formed from WS 2 by CVD or ALD with WF 6 and H 2 S as precursors. In such conditions, WS 2 film 316 may grow laterally from the edges of WS 2 seeds 314 . When the defect-free TMD seed 314 is formed by WSe 2 , the two-dimensional semiconductor film 316 can be formed by MoS 2 , and the formation method can be CVD with MoO 3 and sulfur vapor as precursors. In such conditions, the MoS 2 film 316 can grow laterally from the edge of the WeSe 2 seed 314 .

在形成二維半導體島318後，電晶體可形成在二維半導體島318上，內連接結構可形成在電晶體上，從而形成如第11圖所示的三維積體電路結構。形成電晶體與內連接結構於二維半導體島的細節如同前文中關於第8至11圖所述，故為了簡潔起見不重複。 After forming the two-dimensional semiconductor island 318, transistors can be formed on the two-dimensional semiconductor island 318, and interconnection structures can be formed on the transistors, thereby forming a three-dimensional integrated circuit structure as shown in FIG. 11 . The details of forming the transistors and interconnection structures on the two-dimensional semiconductor islands are the same as those described above with respect to FIGS. 8 to 11 , so they are not repeated for brevity.

第23至25A、26至27A及28圖示出了根據本揭示案的一些其他實施例的用於製造三維積體電路的各個階段的示例性立體圖及剖面圖。應當理解，對於此方法的額外實施例，可在第23至28圖所示的製程之前、期間及之後提供額外處理，並且可替換或消除下文描述的一些處理。處理/製程的順序可互換。在以下實施例中，可採用與第1A至11圖所描述的相同或相似的配置、材料、製程及/或處理，並且可省略詳細說明。 Figures 23-25A, 26-27A, and 28 show exemplary perspective and cross-sectional views of various stages for fabricating three-dimensional integrated circuits according to some other embodiments of the disclosure. It should be understood that for additional embodiments of the method, additional processing may be provided before, during, and after the processes shown in Figures 23-28, and that some of the processing described below may be substituted or eliminated. The order of treatments/processes can be interchanged. In the following embodiments, the same or similar configurations, materials, processes and/or processes as those described in FIGS. 1A to 11 may be used, and detailed description may be omitted.

在第23圖中，遮罩層400係形成於ILD層120上並圖案化形成開口400h。這些開口400h延伸穿過遮罩層400以暴露ILD層120的多個部分。在一些實施例中，圖案化遮罩層400可包含光阻材料，且可其形成包含先進行旋塗製程，接著採用適當的微影技術圖案化此光阻材料。舉例來說，光阻材料400可被曝光及顯影以移除部分的光阻材料。更具體來說，光罩(未繪示)可放置於光阻材料上方，接著光阻材料可藉由輻射源曝光於輻射束，此輻射 源可例如為紫外光(UV)源、深紫外光(DUV)源、極紫外光(EUV)源或X光源。舉例來說，輻射源可為具有波長約為436nm(G-line)至365nm(I-line)的範圍之間的汞燈、具有波長約為248nm之氪氟(Krypton Fluoride,KrF)準分子雷射、具有波長約為193nm之氬氟(Argon Fluorid,ArF)準分子雷射、具有波長約為157nm之氟(Fluoride,F2)準分子雷射、或是其他具有一期望之波長(例如低於約100nm)之其他光源。在其他實施例中，光源可為具有波長約為13.5nm或更短的EUV光源。 In FIG. 23, a mask layer 400 is formed on the ILD layer 120 and patterned to form an opening 400h. These openings 400h extend through mask layer 400 to expose portions of ILD layer 120 . In some embodiments, the patterned mask layer 400 may include a photoresist material, and its formation may include performing a spin-coating process first, and then patterning the photoresist material using appropriate lithography techniques. For example, the photoresist material 400 can be exposed and developed to remove a portion of the photoresist material. More specifically, a photomask (not shown) can be placed over the photoresist material, and the photoresist material can then be exposed to a radiation beam by a radiation source, the radiation The source can be, for example, an ultraviolet (UV) source, a deep ultraviolet (DUV) source, an extreme ultraviolet (EUV) source, or an X-ray source. For example, the radiation source can be a mercury lamp with a wavelength ranging from about 436nm (G-line) to 365nm (I-line), a krypton fluoride (KrF) excimer laser with a wavelength of about 248nm, an argon fluoride (ArF) excimer laser with a wavelength of about 193nm, a fluorine (Fluoride, F2) excimer laser with a wavelength of about 157nm, or others with a desired wavelength Other light sources (eg below about 100 nm). In other embodiments, the light source may be an EUV light source having a wavelength of about 13.5 nm or less.

在形成圖案化遮罩層400後，可在ILD層之暴露於圖案化遮罩層400之開口400h的暴露部分執行表面處理，以在ILD層120中形成受處理區域120t。此表面處理會對暴露在遮罩開口400h中的ILD表面斷鍵，以提升後續沉積製程中對材料的吸附能力。在一些實施例中，表面處理包含採用氧電漿或氟電漿的電漿處理、濕式表面改質製程、類似製程，或其組合。表面處理的程度(例如，表面斷鍵程度)可影響晶核成長(nucleation)位置的數量，並進而影響後續沉積的二維半導體材料的初始沉積速率，此將於下文中進一步詳述。一般來說，越多鍵結被打斷會創造出越多懸鍵(dangling bonds)，因此，越多的晶核成長位置可用於二維半導體材料的吸收及成核，因此可至少在沉積的初期提升沉積速率。因此，ILD層120的受處理區域120t具有比ILD層的未處理區域120u更多 用於二維半導體材料的晶核成長位置，因而允許在後續二維半導體材料沉積製程中產生選擇性成長的效應。 After forming the patterned mask layer 400 , surface treatment may be performed on exposed portions of the ILD layer exposed to the openings 400 h of the patterned mask layer 400 to form treated regions 120 t in the ILD layer 120 . The surface treatment will break bonds on the surface of the ILD exposed in the mask opening 400h, so as to improve the adsorption capacity of the material in the subsequent deposition process. In some embodiments, the surface treatment includes plasma treatment using oxygen plasma or fluorine plasma, a wet surface modification process, the like, or a combination thereof. The degree of surface treatment (eg, the degree of surface bond breaking) can affect the number of nucleation sites, which in turn affects the initial deposition rate of the subsequently deposited two-dimensional semiconductor material, as will be described in further detail below. In general, the more bonds are broken, the more dangling bonds will be created. Therefore, the more nucleation growth sites are available for the absorption and nucleation of the 2D semiconductor material, thereby increasing the deposition rate at least in the early stages of deposition. Therefore, the treated region 120t of the ILD layer 120 has more Nucleation growth sites for two-dimensional semiconductor materials, thus allowing selective growth effects in subsequent two-dimensional semiconductor material deposition processes.

在第24圖中，圖案化遮罩層400自ILD層120移除，例如可採用電漿灰化製程移除。在一些實施例中，電漿灰化製程的執行會使得光阻遮罩400的溫度被提升直到光阻遮罩經歷熱分解而可被移除。然而，其他適合方式例如濕式剝離亦可被採用。圖案化遮罩400的移除對受處理區域120t的懸鍵及/或斷鍵沒有或僅有可忽略的影響，因此對ILD層120的受處理區域120t及未處理區域120u的沉積選擇比沒有或僅有可忽略的影響。 In FIG. 24 , the patterned mask layer 400 is removed from the ILD layer 120 , for example, by a plasma ashing process. In some embodiments, the plasma ashing process is performed such that the temperature of the photoresist mask 400 is raised until the photoresist mask undergoes thermal decomposition and can be removed. However, other suitable methods such as wet stripping can also be used. Removal of the patterned mask 400 has no or only negligible effect on dangling and/or broken bonds in the treated region 120t, and thus has no or only negligible effect on the deposition selectivity of the treated region 120t and the untreated region 120u of the ILD layer 120.

在第25A圖中，選擇性沉積製程被執行以選擇性地形成複數缺陷二維半導體種子410於ILD層120的受處理區域120t上。第24圖所述的表面處理可增加ILD層120的受處理區域120t的晶核成長位置，因此二維半導體材料在受處理區域120t的沉積速率比在未受處理區域120u的沉積速率更快。在一些實施例中，沉積時間被控制而在二維半導體材料在未處理區域120u開始成核前終止。因此，未處理區域120u沒有二維半導體材料。 In FIG. 25A , a selective deposition process is performed to selectively form a plurality of defective two-dimensional semiconductor seeds 410 on the treated region 120 t of the ILD layer 120 . The surface treatment described in FIG. 24 can increase the nucleation growth sites in the treated region 120t of the ILD layer 120, so the deposition rate of the two-dimensional semiconductor material in the treated region 120t is faster than that in the untreated region 120u. In some embodiments, the deposition time is controlled to terminate before nucleation of the two-dimensional semiconductor material begins in the untreated region 120u. Therefore, the untreated region 120u is devoid of two-dimensional semiconductor material.

在一些實施例中，缺陷二維半導體種子410為過渡金屬二硫族化物(transition metal dichalcogenides；TMD)、石墨烯(graphene)、層狀的III-VI硫化物、六方氮化硼(hexagonal boron nitride；h-BN)黑磷(black phosphorus)或類似物。在一些實施例中，缺陷二維半導體種子為直徑為約150奈 米至250奈米(例如約200奈米)的WS2種子，其係採用含硫氣體(例如H2S氣體)及由含鎢氣體(例如WF6)所產生的電漿所沉積的。第25B圖繪示採用第23至25A圖的步驟所產生的WS2種子的拉曼光譜(Raman spectrum)圖。第25B所示的拉曼光譜可，例如，在選擇性沉積製程完成後在WS2種子上進行拉曼光譜分析來得到。如第25B圖所示，WS2在種子中的存在可藉由代表WS2的第一特徵峰E2g與第二特徵峰A1g所確認，其中主峰E2g與A1g對應面內(in-plane)原子振動與面外(out-of-plane)原子振動。在如第25B圖所示的拉曼光譜中，第一特徵峰E2g落在自約340cm-1至約360cm-1，而第二特徵峰A1g落在自約410cm-1至約430cm-1。可瞭解到，代表WS2的第一特徵峰E2g與第二特徵峰A1g可在上述範圍內些微變化，取決於選擇性沉積製程的製程參數，例如含硫氣體與含鎢氣體的流率、及選擇性沉積製程的溫度及時間。 In some embodiments, the defect 2D semiconductor seed 410 is transition metal dichalcogenides (TMD), graphene, layered III-VI sulfides, hexagonal boron nitride (h-BN) black phosphorus, or the like. In some embodiments, the defective 2D semiconductor seeds are WS2 seeds with a diameter of about 150 nm to 250 nm (eg, about 200 nm) deposited using a sulfur-containing gas (eg, H2S gas) and a plasma generated by a tungsten-containing gas (eg, WF6 ). Figure 25B shows the Raman spectrum of WS 2 seeds produced using the steps of Figures 23-25A. The Raman spectrum shown in Section 25B can be obtained, for example, by performing Raman spectroscopic analysis on the WS 2 seed after the selective deposition process is complete. As shown in Figure 25B, the existence of WS in the seeds can be confirmed by the first characteristic peak E 2g and the second characteristic peak A 1g representing WS 2 , where the main peaks E 2g and A 1g correspond to in-plane atomic vibrations and out-of-plane atomic vibrations. In the Raman spectrum shown in Fig. 25B, the first characteristic peak E 2g falls from about 340 cm −1 to about 360 cm −1 , and the second characteristic peak A 1g falls from about 410 cm −1 to about 430 cm −1 . It can be understood that the first characteristic peak E2g and the second characteristic peak A1g representing WS2 can vary slightly within the above range, depending on the process parameters of the selective deposition process, such as the flow rate of the sulfur-containing gas and the tungsten-containing gas, and the temperature and time of the selective deposition process.

在第26A至26B圖中，介電網格212形成在晶圓W1的ILD層120上，此步驟係在後續的自二維半導體種子的橫向成長之前所進行的。介電網格212限位於可能在後續橫向磊晶成長製程中產生的預期晶界，因此可避免晶界形成在後續的橫向磊晶成長中。換句話說，介電網格212的圖案與二維半導體種子410的圖案是共同設計且互相關連的。此外，由於二維半導體種子410是從ILD層120的受處理區域120t選擇性成長的，而受處理區域 120t係以圖案化遮罩層400(如第23圖所示)為遮罩所形成的，故介電網格212的圖案可與圖案化遮罩層400的圖案共同設計且相互關連。 In Figures 26A-26B, a dielectric grid 212 is formed on the ILD layer 120 of wafer W1 prior to subsequent lateral growth from two-dimensional semiconductor seeds. The dielectric grid 212 is limited to expected grain boundaries that may be generated in subsequent lateral epitaxial growth processes, thereby preventing the formation of grain boundaries in subsequent lateral epitaxial growth processes. In other words, the pattern of the dielectric grid 212 and the pattern of the two-dimensional semiconductor seed 410 are co-designed and interrelated. In addition, since the two-dimensional semiconductor seed 410 is selectively grown from the treated region 120t of the ILD layer 120, the treated region 120t is formed by using the patterned mask layer 400 (as shown in FIG. 23 ) as a mask, so the pattern of the dielectric grid 212 and the pattern of the patterned mask layer 400 can be co-designed and related to each other.

介電網格212具有多個網格單元212o，其與受處理區域120t係以一對一的方式對應的。在一些實施例中，受處理區域120t的中心實質上對齊於網格單元210o的中心。每一網格單元210o係由量兩對應第一網格線2122與兩對應第二網格線2124所界定，因此具有矩形或正方形俯視輪廓。在一些實施例中，受處理區域120t及其上方的缺陷二維半導體種子410具有圓形或橢圓形俯視輪廓，因而具有與網格單元210o不同的俯視輪廓。介電網格212的材料與製程如前文中關於第5A至5B圖所描述，故為了簡潔不重複。 The dielectric grid 212 has a plurality of grid cells 212o that correspond in a one-to-one manner with the treated area 12Ot. In some embodiments, the center of the treated area 120t is substantially aligned with the center of the grid cell 210o. Each grid unit 210o is bounded by two corresponding first grid lines 2122 and two corresponding second grid lines 2124, thus having a rectangular or square top profile. In some embodiments, the treated region 120t and the defective two-dimensional semiconductor seeds 410 above have a circular or elliptical top view profile, and thus have a different top view profile from the grid unit 210o. The materials and processes of the dielectric grid 212 are as described above with respect to FIGS. 5A-5B , so they are not repeated for brevity.

在第27A圖中，退火製程AL5被執行以將缺陷二維半導體種子410轉換為無缺陷二維半導體種子414。退火製程AL5如同前文中關於第6A至6B圖的退火製程AL1所述，故為了簡潔不重複。第27B圖繪示二維半導體種子(例如WS2 seeds種子)的光致發光光譜(photoluminescence spectra)圖，此光譜包含在H2S退火前及在H2S退火後的結果。如第27B圖所示，經歷過H2S退火的二維半導體種子比未經歷過H2S退火的二維半導體種子具有更高且更尖銳的高峰，這代表了H2S退火提升光學品質並降低二維半導體種子內的缺陷。 In FIG. 27A , an annealing process AL5 is performed to convert the defective 2D semiconductor seeds 410 into defect-free 2D semiconductor seeds 414 . The annealing process AL5 is the same as the annealing process AL1 in FIGS. 6A-6B above, so it is not repeated for brevity. FIG. 27B shows the photoluminescence spectrum of two-dimensional semiconductor seeds ( such as WS 2 seeds), which includes the results before and after H 2 S annealing. As shown in Fig. 27B, the 2D semiconductor seeds subjected to H 2 S annealing have higher and sharper peaks than the 2D semiconductor seeds not subjected to H 2 S annealing, which means that H 2 S annealing improves optical quality and reduces defects in 2D semiconductor seeds.

在第28圖中，磊晶成長製程EPI5係執行以利用 無缺陷二維半導體種子414為種子而橫向成長出二維半導體膜416。無缺陷二維半導體種子414與自該無缺陷二維半導體種子414橫向成長出的一對應二維半導體膜416可共同稱為一二維半導體島418。該二維半導體島418係侷限於介電網格212的一網格單元中。在一些實施例中，二維半導體膜416具有與無缺陷二維半導體種子414相同的二維材料，或者是具有晶格常數比種子414的晶格常數更小的其他二維材料。舉例來說，當無缺陷TMD種子414係由WS2所形成，二維半導體膜416亦可由WS2所形成，其形成方式可為以WF6及H2S做為前驅物的CVD或ALD。這樣的狀況下，WS2膜416可由WS2種子414的邊緣以同質成長的方式橫向成長。當無缺陷TMD種子414係由WSe2所形成，二維半導體膜416可由MoS2所形成，其形成方式可為以MoO3及硫蒸氣為前驅物的CVD。在這樣的狀況下，MoS2膜416可從WeSe2種子314的邊緣以異質成長的方式橫向成長。 In FIG. 28 , the epitaxial growth process EPI5 is performed to laterally grow a two-dimensional semiconductor film 416 using a defect-free two-dimensional semiconductor seed 414 as a seed. The defect-free two-dimensional semiconductor seed 414 and a corresponding pair of two-dimensional semiconductor films 416 laterally grown from the defect-free two-dimensional semiconductor seed 414 may be collectively referred to as a two-dimensional semiconductor island 418 . The two-dimensional semiconductor island 418 is confined within a grid cell of the dielectric grid 212 . In some embodiments, the two-dimensional semiconductor film 416 has the same two-dimensional material as the defect-free two-dimensional semiconductor seed 414 , or another two-dimensional material with a smaller lattice constant than the seed 414 . For example, when the defect-free TMD seed 414 is formed from WS 2 , the two-dimensional semiconductor film 416 can also be formed from WS 2 by CVD or ALD with WF 6 and H 2 S as precursors. In such a situation, the WS 2 film 416 can grow laterally from the edge of the WS 2 seed 414 in a homogenous manner. When the defect-free TMD seed 414 is formed by WSe 2 , the two-dimensional semiconductor film 416 can be formed by MoS 2 , and the formation method can be CVD with MoO 3 and sulfur vapor as precursors. Under such conditions, the MoS 2 film 416 can grow laterally from the edge of the WeSe 2 seed 314 in a heterogeneous manner.

第29至31A及32至34圖示出了根據本揭示案的一些其他實施例的用於製造三維積體電路的各個階段的示例性剖面圖。應當理解，對於此方法的額外實施例，可在第29至34圖所示的製程之前、期間及之後提供額外處理，並且可替換或消除下文描述的一些處理。處理/製程的順序可互換。在以下實施例中，可採用與第1A至11圖所描述的相同或相似的配置、材料、製程及/或處理，並且可省略詳細說明。 Figures 29-31A and 32-34 show exemplary cross-sectional views of various stages for fabricating three-dimensional integrated circuits according to some other embodiments of the present disclosure. It should be understood that for additional embodiments of the method, additional processing may be provided before, during, and after the processes shown in Figures 29-34, and that some of the processing described below may be substituted or eliminated. The order of treatments/processes can be interchanged. In the following embodiments, the same or similar configurations, materials, processes and/or processes as those described in FIGS. 1A to 11 may be used, and detailed description may be omitted.

在第29圖中，遮罩層500係形成於ILD層120上並圖案化形成開口500h。這些開口500h延伸穿過遮罩層400以暴露ILD層120的多個部分。在一些實施例中，圖案化遮罩層500可包含光阻材料，且可其形成包含先進行旋塗製程，接著採用適當的微影技術圖案化此光阻材料。舉例來說，光阻材料500可被曝光及顯影以移除部分的光阻材料。更具體來說，光罩(未繪示)可放置於光阻材料上方，接著光阻材料可藉由輻射源曝光於輻射束，此輻射源可例如為紫外光(UV)源、深紫外光(DUV)源、極紫外光(EUV)源或X光源。舉例來說，輻射源可為具有波長約為436nm(G-line)至365nm(I-line)的範圍之間的汞燈、具有波長約為248nm之氪氟(Krypton Fluoride,KrF)準分子雷射、具有波長約為193nm之氬氟(Argon Fluorid,ArF)準分子雷射、具有波長約為157nm之氟(Fluoride,F2)準分子雷射、或是其他具有一期望之波長(例如低於約100nm)之其他光源。在其他實施例中，光源可為具有波長約為13.5nm或更短的EUV光源。 In FIG. 29, a mask layer 500 is formed on the ILD layer 120 and patterned to form an opening 500h. These openings 500h extend through mask layer 400 to expose portions of ILD layer 120 . In some embodiments, the patterned mask layer 500 may include a photoresist material, and its formation may include performing a spin-coating process first, and then patterning the photoresist material using appropriate lithography techniques. For example, the photoresist material 500 can be exposed and developed to remove a portion of the photoresist material. More specifically, a photomask (not shown) can be placed over the photoresist material, and the photoresist material can then be exposed to a radiation beam by a radiation source, such as an ultraviolet (UV) source, deep ultraviolet (DUV) source, extreme ultraviolet (EUV) source, or X-ray source. For example, the radiation source can be a mercury lamp with a wavelength ranging from about 436nm (G-line) to 365nm (I-line), a krypton fluoride (KrF) excimer laser with a wavelength of about 248nm, an argon fluoride (ArF) excimer laser with a wavelength of about 193nm, a fluorine (Fluoride, F2) excimer laser with a wavelength of about 157nm, or others with a desired wavelength Other light sources (eg below about 100 nm). In other embodiments, the light source may be an EUV light source having a wavelength of about 13.5 nm or less.

在形成圖案化遮罩層500後，過渡金屬氧化物層502係毯覆式地沉積在圖案化遮罩層500上，此沉積可採用CVD、ALD、PVD或其他適合的沉積技術。藉此，過渡金屬氧化物層502可襯裹遮罩開口500h的底面及側壁。在一些實施例中，過渡金屬氧化物層502包含MoOx、WOx、或其他可用於形成TMD的合適過渡金屬氧化物材 料。 After the patterned mask layer 500 is formed, the transition metal oxide layer 502 is blanket-deposited on the patterned mask layer 500 by CVD, ALD, PVD or other suitable deposition techniques. Thereby, the transition metal oxide layer 502 can line the bottom surface and the sidewall of the mask opening 500h. In some embodiments, transition metal oxide layer 502 includes MoOx , WOx , or other suitable transition metal oxide materials that can be used to form TMDs.

在第30圖中，圖案化遮罩層500係藉由，例如，剝離成形製程(lift-off process)所移除。將圖案化遮罩層500剝離也會將其上方的過渡金屬氧化物層502移除，而留下部分的過渡金屬氧化物層502於ILD層120的局部區域。在一些實施例中，剩餘部分的過渡金屬氧化物層502可被稱為過渡金屬氧化物塊510。在一些實施例中，每一過渡金屬氧化物塊510的直徑自約450奈米至550奈米(例如，約500奈米)。 In FIG. 30, the patterned mask layer 500 is removed by, for example, a lift-off process. Lifting off the patterned mask layer 500 also removes the transition metal oxide layer 502 above it, leaving a portion of the transition metal oxide layer 502 in a local area of the ILD layer 120 . In some embodiments, the remaining portion of transition metal oxide layer 502 may be referred to as transition metal oxide bulk 510 . In some embodiments, each transition metal oxide block 510 has a diameter from about 450 nm to 550 nm (eg, about 500 nm).

在第31A圖中，硫化或硒化製程被執行以將過渡金屬氧化物塊510硫化或硒化成TMD種子512。舉例來說，在過渡金屬氧化物塊510為WOx的實施例中，過渡金屬氧化物塊510可採用H2S氣體硫化，而形成WS2以做為TMD種子512。或者，過渡金屬氧化物塊510可採用H2Se氣體硒化，從而形成WSe2以做為TMD種子512。第31B圖繪示由第29至31A圖的步驟所形成的WS2種子的拉曼光譜圖。第31B所示的拉曼光譜可，例如，在硫化製程完成後在WS2種子上進行拉曼光譜分析來得到。如第31B圖所示，WS2在種子中的存在可藉由代表WS2的第一特徵峰E2g與第二特徵峰A1g所確認，其中主峰E2g與A1g對應面內(in-plane)原子振動與面外(out-of-plane)原子振動。在如第31B圖所示的拉曼光譜中，第一特徵峰E2g落在自約340cm-1至約360cm-1，而第二特徵峰A1g落在自約410cm-1至約 430cm-1。可瞭解到，代表WS2的第一特徵峰E2g與第二特徵峰A1g可在上述範圍內些微變化，取決於硫化製程的製程參數，例如含硫氣體的流率、及硫化製程的溫度及時間。 In FIG. 31A , a sulfurization or selenization process is performed to sulfurize or selenize transition metal oxide bulk 510 into TMD seeds 512 . For example, in an embodiment where the transition metal oxide block 510 is WO x , the transition metal oxide block 510 can be sulfurized by H 2 S gas to form WS 2 as the TMD seed 512 . Alternatively, the transition metal oxide block 510 can be selenized with H 2 Se gas to form WSe 2 as the TMD seed 512 . Figure 31B shows the Raman spectra of WS 2 seeds formed by the steps of Figures 29-31A. The Raman spectrum shown in Section 31B can be obtained, for example, by performing Raman spectroscopic analysis on WS 2 seeds after the vulcanization process is completed. As shown in Fig. 31B, the existence of WS 2 in the seeds can be confirmed by the first characteristic peak E 2g and the second characteristic peak A 1g representing WS 2 , wherein the main peaks E 2g and A 1g correspond to in-plane atomic vibration and out-of-plane atomic vibration. In the Raman spectrum shown in Fig. 31B, the first characteristic peak E 2g falls from about 340 cm −1 to about 360 cm −1 , and the second characteristic peak A 1g falls from about 410 cm −1 to about 430 cm −1 . It can be understood that the first characteristic peak E 2g and the second characteristic peak A 1g representing WS 2 can vary slightly within the above range, depending on the process parameters of the vulcanization process, such as the flow rate of the sulfur-containing gas, and the temperature and time of the vulcanization process.

在第32圖中，介電網格212形成在ILD層120上，此步驟是在TMD種子512的橫向磊晶成長前執行。介電網格的細節系類似於前文中關於第5A及5B圖所載，故為了簡潔不重複。 In FIG. 32 , the dielectric grid 212 is formed on the ILD layer 120 , which is performed before the lateral epitaxial growth of the TMD seeds 512 . The details of the dielectric mesh are similar to those set forth above with respect to Figures 5A and 5B and are therefore not repeated for brevity.

在第33圖中，退火製程AL6被執行以將缺陷二維半導體種子512轉換成無缺陷二維半導體種子514。舉例來說，退火製程AL6可使得每一二維半導體種子中的晶體缺陷(例如空位或間隙缺陷)擴散至二維半導體種子的邊緣而消散，因而將每一二維半導體種子中的晶體缺陷降低至低於一閥值，低於該閥值代表有資格做為電晶體通道、汲極及/或源極。退火製程AL6係類似於前文中關於第6A至6B圖所述之退火製程AL1，故為了簡潔不重複。 In FIG. 33 , an annealing process AL6 is performed to convert the defective 2D semiconductor seeds 512 into defect-free 2D semiconductor seeds 514 . For example, the annealing process AL6 can cause crystal defects (such as vacancies or interstitial defects) in each two-dimensional semiconductor seed to diffuse to the edge of the two-dimensional semiconductor seed and dissipate, thereby reducing the crystal defect in each two-dimensional semiconductor seed to below a threshold value, which means that the threshold value is qualified as a transistor channel, drain and/or source. The annealing process AL6 is similar to the annealing process AL1 described above with respect to FIGS. 6A-6B , so it is not repeated for brevity.

在第34圖中，磊晶成長製程EPI6係執行以利用無缺陷二維半導體種子514為種子而橫向成長出二維半導體膜516。無缺陷二維半導體種子514與自該無缺陷二維半導體種子514橫向成長出的一對應二維半導體膜516可共同稱為一二維半導體島518。該二維半導體島518係侷限於介電網格212的一網格單元中。在一些實施例中，二維半導體膜516具有與無缺陷二維半導體種子514相同的二維材料，或者是具有晶格常數比種子514的晶格常數更 小的其他二維材料。舉例來說，當無缺陷TMD種子514係由WS2所形成，二維半導體膜516亦可由WS2所形成，其形成方式可為以WF6及H2S做為前驅物的CVD或ALD。這樣的狀況下，WS2膜516可由WS2種子514的邊緣以同質成長的方式橫向成長。當無缺陷TMD種子514係由WSe2所形成，二維半導體膜516可由MoS2所形成，其形成方式可為以MoO3及硫蒸氣為前驅物的CVD。在這樣的狀況下，MoS2膜516可從WeSe2種子514的邊緣以異質成長的方式橫向成長。 In FIG. 34 , the epitaxial growth process EPI6 is performed to laterally grow a two-dimensional semiconductor film 516 using a defect-free two-dimensional semiconductor seed 514 as a seed. The defect-free two-dimensional semiconductor seed 514 and a corresponding pair of two-dimensional semiconductor films 516 laterally grown from the defect-free two-dimensional semiconductor seed 514 may be collectively referred to as a two-dimensional semiconductor island 518 . The two-dimensional semiconductor island 518 is confined within a grid cell of the dielectric grid 212 . In some embodiments, the two-dimensional semiconductor film 516 has the same two-dimensional material as the defect-free two-dimensional semiconductor seed 514 , or another two-dimensional material with a smaller lattice constant than the seed 514 . For example, when the defect-free TMD seed 514 is formed from WS 2 , the two-dimensional semiconductor film 516 can also be formed from WS 2 by CVD or ALD with WF 6 and H 2 S as precursors. Under such conditions, the WS 2 film 516 can grow laterally from the edge of the WS 2 seed 514 in a homogenous manner. When the defect-free TMD seed 514 is formed by WSe 2 , the two-dimensional semiconductor film 516 can be formed by MoS 2 , and the formation method can be CVD with MoO 3 and sulfur vapor as precursors. Under such conditions, the MoS 2 film 516 can grow laterally from the edge of the WeSe 2 seed 514 in a heterogeneous manner.

基於以上論述，可見本揭露提供多項優點。然而，應理解，其他實施例亦可提供額外優點，且本案不一定揭示所有優點，且並無特定優點是所有實施例均必需的。一個優點是「IC品質」(亦即，沒有或僅有可忽略的晶體缺陷)的二維半導體島可形成在層間介電(ILD)材料或金屬間介電(IMD)材料的非晶表面上。另一優點是形成在層間介電材料或金屬間介電材料上的IC品質二維半導體島可做為電晶體的主動區域，因此可形成3D積體電路，此3D積體電路具有較低位置的較低電晶體(例如，低於內連接結構)及較高位置的較高電晶體(例如，高於內連接結構)。 Based on the above discussion, it can be seen that the present disclosure provides several advantages. However, it should be understood that other embodiments may also provide additional advantages, and this application does not necessarily disclose all advantages, and no specific advantage is required for all embodiments. One advantage is that "IC quality" (ie, no or only negligible crystal defects) two-dimensional semiconductor islands can be formed on amorphous surfaces of interlayer dielectric (ILD) or intermetal dielectric (IMD) materials. Another advantage is that IC-quality two-dimensional semiconductor islands formed on ILD or IMD can serve as active regions for transistors, thereby forming 3D integrated circuits with lower transistors at lower positions (e.g., below interconnect structures) and higher transistors at higher positions (e.g., above interconnect structures).

在一些實施例中，一種積體電路結構包含一第一電晶體、一第一內連接結構、一介電層、複數二維半導體島、及複數第二電晶體。第一電晶體形成在一基板上。第一內連接結構在該第一電晶體上。介電層在該內連接結構 上。該些二維半導體島在該介電層上。該些第二電晶體形成在該些二維半導體島上。在一些實施例中，該些二維半導體島之每一者包含一二維半導體種子以及一二維半導體膜橫向圍繞該二維半導體種子。在一些實施例中，該二維半導體膜與該二維半導體種子係由相同材料形成。在一些實施例中，該二維半導體膜與該二維半導體種子係由不同材料形成。在一些實施例中，該二維半導體膜的表面積比該二維半導體種子的表面積大。在一些實施例中，該二維半導體膜的厚度實質上同於該二維半導體種子的厚度。在一些實施例中，從俯視觀看，該些二維半導體島係呈多行與多列排列。在一些實施例中，該些二維半導體島彼此分隔。在一些實施例中，積體電路結構更包含一介電網格，在該介電層上，該些二維半導體島係以一對一的形式設置在該介電網格的複數網格單元中。在一些實施例中，該些二維半導體島的相鄰兩者形成一晶界。在一些實施例中，積體電路結構更包含一第二內連接結構，在該些第二電晶體上。 In some embodiments, an integrated circuit structure includes a first transistor, a first interconnection structure, a dielectric layer, a plurality of two-dimensional semiconductor islands, and a plurality of second transistors. The first transistor is formed on a substrate. A first interconnect structure is on the first transistor. The dielectric layer connects the structure within the superior. The two-dimensional semiconductor islands are on the dielectric layer. The second transistors are formed on the two-dimensional semiconductor islands. In some embodiments, each of the two-dimensional semiconductor islands includes a two-dimensional semiconductor seed and a two-dimensional semiconductor film laterally surrounding the two-dimensional semiconductor seed. In some embodiments, the two-dimensional semiconductor film and the two-dimensional semiconductor seed are formed of the same material. In some embodiments, the two-dimensional semiconductor film and the two-dimensional semiconductor seed are formed of different materials. In some embodiments, the surface area of the two-dimensional semiconductor film is greater than the surface area of the two-dimensional semiconductor seed. In some embodiments, the thickness of the two-dimensional semiconductor film is substantially the same as the thickness of the two-dimensional semiconductor seed. In some embodiments, viewed from a top view, the two-dimensional semiconductor islands are arranged in multiple rows and columns. In some embodiments, the two-dimensional semiconductor islands are separated from each other. In some embodiments, the integrated circuit structure further includes a dielectric grid, and on the dielectric layer, the two-dimensional semiconductor islands are arranged one-to-one in plural grid units of the dielectric grid. In some embodiments, two adjacent two-dimensional semiconductor islands form a grain boundary. In some embodiments, the integrated circuit structure further includes a second interconnect structure on the second transistors.

在一些實施例中，一種積體電路結構包含一內連接結構、一介電層、複數二維半導體種子、複數二維半導體膜、以及複數電晶體。該內連接結構在一基板上，並包含縱向延伸於該基板上的一導電通孔及橫向延伸於該導電通孔上的一導電線。介電層在該內連接結構上。該些二維半導體種子呈多行及多列地排列於該介電層上。該些二維半導體膜分別橫向地圍繞該些二維半導體種子。該些電晶體 在該些二維半導體膜上。在一些實施例中，該些二維半導體種子係由過渡金屬二硫族化物(transition metal dichalcogenides；TMD)、石墨烯(graphene)、層狀的III-VI硫化物、六方氮化硼(hexagonal boron nitride；h-BN)、或黑磷(black phosphorus)所形成。在一些實施例中，該些二維半導體膜係由過渡金屬二硫族化物(transition metal dichalcogenides；TMD)、石墨烯(graphene)、層狀的III-VI硫化物、六方氮化硼(hexagonal boron nitride；h-BN)、或黑磷(black phosphorus)所形成。在一些實施例中，該些二維半導體種子與該些二維半導體膜係由相同的過渡金屬二硫族化物(TMD)所形成的。在一些實施例中，該些二維半導體種子係由第一TMD材料形成的，該些二維半導體膜係由與該第一TMD材料不同的一第二TMD材料形成的。 In some embodiments, an integrated circuit structure includes an interconnection structure, a dielectric layer, a plurality of two-dimensional semiconductor seeds, a plurality of two-dimensional semiconductor films, and a plurality of transistors. The internal connection structure is on a substrate, and includes a conductive via hole extending longitudinally on the substrate and a conductive line extending laterally on the conductive via hole. A dielectric layer is on the interconnect structure. The two-dimensional semiconductor seeds are arranged on the dielectric layer in rows and columns. The two-dimensional semiconductor films laterally surround the two-dimensional semiconductor seeds respectively. The transistors on these two-dimensional semiconductor films. In some embodiments, the two-dimensional semiconductor seeds are formed of transition metal dichalcogenides (TMD), graphene, layered III-VI sulfides, hexagonal boron nitride (h-BN), or black phosphorus. In some embodiments, the two-dimensional semiconductor films are formed of transition metal dichalcogenides (TMD), graphene, layered III-VI sulfides, hexagonal boron nitride (h-BN), or black phosphorus. In some embodiments, the two-dimensional semiconductor seeds and the two-dimensional semiconductor films are formed of the same transition metal dichalcogenide (TMD). In some embodiments, the two-dimensional semiconductor seeds are formed of a first TMD material, and the two-dimensional semiconductor films are formed of a second TMD material different from the first TMD material.

在一些實施例中，一種方法包含形成複數第一電晶體於一基板上；形成一內連接結構於該些第一電晶體上；形成一介電層於該內連接結構上；形成複數二維半導體種子於該介電層上；對該些二維半導體種子退火；在對該些二維半導體種子退火後，進行一磊晶製程以從該些二維半導體種子分別橫向成長複數二維半導體膜；及形成複數第二電晶體於該些二維半導體膜上。在一些實施例中，形成該些二維半導體種子包含沉積一二維半導體層在一結晶基板上；將該二維半導體層自該結晶基板轉移至該介電層上； 及圖案化該二維半導體層成該些二維半導體種子。在一些實施例中，形成該些二維半導體種子包含沉積一含過渡金屬層在該介電層上；圖案化該含過渡金屬層成複數含過渡金屬塊；及硫化或硒化該些含過渡金屬塊以形成該些二維半導體種子。 In some embodiments, a method includes forming a plurality of first transistors on a substrate; forming an interconnection structure on the first transistors; forming a dielectric layer on the interconnection structure; forming a plurality of two-dimensional semiconductor seeds on the dielectric layer; annealing the two-dimensional semiconductor seeds; In some embodiments, forming the two-dimensional semiconductor seeds includes depositing a two-dimensional semiconductor layer on a crystalline substrate; transferring the two-dimensional semiconductor layer from the crystalline substrate to the dielectric layer; and patterning the two-dimensional semiconductor layer into the two-dimensional semiconductor seeds. In some embodiments, forming the two-dimensional semiconductor seeds includes depositing a transition metal-containing layer on the dielectric layer; patterning the transition metal-containing layer into a plurality of transition metal-containing blocks; and sulfiding or selenizing the transition metal-containing blocks to form the two-dimensional semiconductor seeds.

前述內容介紹數個實施例之特徵，以使得熟習此技術者可理解本揭露之態樣。彼等熟習此技術者應理解，其可將本揭露用作設計或修飾其他製程與結構的基礎，以實現與本案介紹的實施例相同的目的及/或獲得相同的優勢。彼等熟習此技術者亦應認識到，此種同等構成不脫離本揭露的精神與範疇，且此等構成可在本案中進行各種變更、替換，及改動，而不脫離本揭露的精神及範疇。 The foregoing description introduces features of several embodiments so that those skilled in the art can understand aspects of the present disclosure. Those skilled in the art should understand that they can use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and/or obtain the same advantages as the embodiments described herein. Those skilled in the art should also realize that such equivalent configurations do not depart from the spirit and scope of this disclosure, and that these configurations can be subject to various changes, substitutions, and changes in this case without departing from the spirit and scope of this disclosure.

102:基板 102: Substrate

103:鰭 103: Fins

104:元件 104: Elements

104G:閘極結構 104 G : gate structure

104GD:替換閘極介電層 104 GD : Replacement gate dielectric layer

104GM:閘極金屬層 104 GM : gate metal layer

104SD:源極/汲極區 104 SD : source/drain region

104SP:間隔物 104 SP : spacer

105:STI區 105: STI area

106:內連接結構 106: Internal connection structure

1081:金屬化層 108 1 : metallization layer

108M-1:金屬化層 108 M-1 : metallization layer

108M:金屬化層 108 M : metallization layer

1100:ILD層 110 0 : ILD layer

1101:IMD層 110 1 : IMD layer

110M-1:IMD層 110 M-1 : IMD layer

110M:IMD層 110 M : IMD layer

1111:IMD層 111 1 : IMD layer

111M-1:IMD層 111 M-1 : IMD layer

111M:IMD層 111 M : IMD layer

1120:接觸窗 112 0 : contact window

1141:導線 114 1 : Wire

114M-1:導線 114 M-1 : Wire

114M:導線 114 M : Wire

1161:導電通孔 116 1 : Conductive via

116M-1:導電通孔 116 M-1 : Conductive vias

116M:導電通孔 116 M : Conductive Via

120:ILD層 120: ILD layer

160:虛設閘極結構 160:Dummy gate structure

170G:閘極結構 170 G : gate structure

170GD:替換閘極介電層 170 GD : Replacement gate dielectric

170GM:替換閘極金屬層 170 GM : Replacement gate metal layer

170SD:源極/汲極區 170 SD : source/drain region

170SP:間隔物 170 SP : spacer

182:ILD層 182: ILD layer

184:ILD層 184: ILD layer

186:接觸窗 186: contact window

190:內連接結構 190: Internal connection structure

192:金屬化層 192: metallization layer

194:介電層 194: dielectric layer

196:金屬線 196: metal wire

198:金屬通孔 198: metal through hole

212:介電網格 212:Dielectric mesh

214:二維半導體種子 214: Two-dimensional semiconductor seeds

216:二維半導體膜 216: Two-dimensional semiconductor film

218:二維半導體島 218: Two-dimensional semiconductor island

W1:晶圓 W1: Wafer

Claims (10)

一種積體電路結構，包含：一第一電晶體，形成在一基板上；一第一內連接結構，在該第一電晶體上；一介電層，在該內連接結構上；複數二維半導體島，在該介電層上，其中該些二維半導體島之每一者包含一二維半導體種子以及一二維半導體膜橫向圍繞該二維半導體種子；及複數第二電晶體，形成在該些二維半導體島上。 An integrated circuit structure comprising: a first transistor formed on a substrate; a first interconnection structure on the first transistor; a dielectric layer on the interconnection structure; a plurality of two-dimensional semiconductor islands on the dielectric layer, wherein each of the two-dimensional semiconductor islands includes a two-dimensional semiconductor seed and a two-dimensional semiconductor film laterally surrounding the two-dimensional semiconductor seed; and a plurality of second transistors formed on the two-dimensional semiconductor islands. 如請求項1所述之積體電路結構，其中該二維半導體膜的表面積比該二維半導體種子的表面積大。 The integrated circuit structure as claimed in claim 1, wherein the surface area of the two-dimensional semiconductor film is larger than the surface area of the two-dimensional semiconductor seed. 如請求項1所述之積體電路結構，其中從俯視觀看，該些二維半導體島係呈多行與多列排列。 The integrated circuit structure according to claim 1, wherein the two-dimensional semiconductor islands are arranged in multiple rows and columns when viewed from a top view. 如請求項1所述之積體電路結構，其中該些二維半導體島彼此分隔。 The integrated circuit structure as claimed in claim 1, wherein the two-dimensional semiconductor islands are separated from each other. 如請求項1所述之積體電路結構，更包含：一介電網格，在該介電層上，該些二維半導體島係以一對一的形式設置在該介電網格的複數網格單元中。 The integrated circuit structure as claimed in Claim 1 further includes: a dielectric grid, on the dielectric layer, the two-dimensional semiconductor islands are arranged in a plurality of grid units of the dielectric grid in a one-to-one manner. 一種積體電路結構，包含： 一內連接結構，在一基板上，並包含縱向延伸於該基板上的一導電通孔及橫向延伸於該導電通孔上的一導電線；一介電層，在該內連接結構上；複數二維半導體種子，呈多行及多列地排列於該介電層上；複數二維半導體膜，分別橫向地圍繞該些二維半導體種子；以及複數電晶體，在該些二維半導體膜上。 An integrated circuit structure comprising: An internal connection structure on a substrate, including a conductive via hole extending longitudinally on the substrate and a conductive line extending laterally on the conductive via hole; a dielectric layer, on the internal connection structure; a plurality of two-dimensional semiconductor seeds arranged in multiple rows and columns on the dielectric layer; a plurality of two-dimensional semiconductor films, respectively laterally surrounding the two-dimensional semiconductor seeds; and a plurality of transistors, on the two-dimensional semiconductor films. 如請求項6所述之積體電路結構，其中該些二維半導體種子與該些二維半導體膜係由相同的過渡金屬二硫族化物(TMD)所形成的。 The integrated circuit structure as claimed in claim 6, wherein the two-dimensional semiconductor seeds and the two-dimensional semiconductor films are formed of the same transition metal dichalcogenide (TMD). 如請求項6所述之積體電路結構，其中該些二維半導體種子係由第一TMD材料形成的，該些二維半導體膜係由與該第一TMD材料不同的一第二TMD材料形成的。 The integrated circuit structure as claimed in claim 6, wherein the two-dimensional semiconductor seeds are formed of a first TMD material, and the two-dimensional semiconductor films are formed of a second TMD material different from the first TMD material. 一種積體電路之製造方法，包含：形成複數第一電晶體於一基板上；形成一內連接結構於該些第一電晶體上；形成一介電層於該內連接結構上；形成複數二維半導體種子於該介電層上；對該些二維半導體種子退火； 在對該些二維半導體種子退火後，進行一磊晶製程以從該些二維半導體種子分別橫向成長複數二維半導體膜；及形成複數第二電晶體於該些二維半導體膜上。 A method for manufacturing an integrated circuit, comprising: forming a plurality of first transistors on a substrate; forming an interconnection structure on the first transistors; forming a dielectric layer on the interconnection structure; forming a plurality of two-dimensional semiconductor seeds on the dielectric layer; and annealing the two-dimensional semiconductor seeds; After the two-dimensional semiconductor seeds are annealed, an epitaxy process is performed to laterally grow a plurality of two-dimensional semiconductor films from the two-dimensional semiconductor seeds; and a plurality of second transistors are formed on the two-dimensional semiconductor films. 如請求項9所述之積體電路之製造方法，其中形成該些二維半導體種子包含：沉積一二維半導體層在一結晶基板上；將該二維半導體層自該結晶基板轉移至該介電層上；及圖案化該二維半導體層成該些二維半導體種子。 The manufacturing method of an integrated circuit as described in Claim 9, wherein forming the two-dimensional semiconductor seeds comprises: depositing a two-dimensional semiconductor layer on a crystalline substrate; transferring the two-dimensional semiconductor layer from the crystalline substrate to the dielectric layer; and patterning the two-dimensional semiconductor layer into the two-dimensional semiconductor seeds.
TW111108054A 2021-03-30 2022-03-04 Three dimensional integrated circuit and fabrication thereof TWI807667B (en)

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