TWI806816B - 半導體裝置和其製造之方法 - Google Patents
半導體裝置和其製造之方法 Download PDFInfo
- Publication number
- TWI806816B TWI806816B TW105117136A TW105117136A TWI806816B TW I806816 B TWI806816 B TW I806816B TW 105117136 A TW105117136 A TW 105117136A TW 105117136 A TW105117136 A TW 105117136A TW I806816 B TWI806816 B TW I806816B
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- electronic device
- dielectric layer
- redistribution structure
- conductive
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 88
- 238000000034 method Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 127
- 239000008393 encapsulating agent Substances 0.000 claims abstract description 20
- 239000003990 capacitor Substances 0.000 claims abstract description 5
- 230000008878 coupling Effects 0.000 claims description 26
- 238000010168 coupling process Methods 0.000 claims description 26
- 238000005859 coupling reaction Methods 0.000 claims description 26
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 22
- 229910000679 solder Inorganic materials 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 239000007787 solid Substances 0.000 claims description 5
- 230000000149 penetrating effect Effects 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 description 31
- 239000002184 metal Substances 0.000 description 31
- 239000010949 copper Substances 0.000 description 23
- 239000003989 dielectric material Substances 0.000 description 20
- 229910052802 copper Inorganic materials 0.000 description 16
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 16
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 11
- 239000000463 material Substances 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 239000004020 conductor Substances 0.000 description 8
- 229920000642 polymer Polymers 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 239000011651 chromium Substances 0.000 description 7
- 239000003822 epoxy resin Substances 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 7
- 229920000647 polyepoxide Polymers 0.000 description 7
- -1 polysiloxane Polymers 0.000 description 7
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 239000000945 filler Substances 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910052804 chromium Inorganic materials 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 229910052763 palladium Inorganic materials 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- 229910052709 silver Inorganic materials 0.000 description 5
- 239000004332 silver Substances 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 4
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 4
- 239000012778 molding material Substances 0.000 description 4
- 229920002577 polybenzoxazole Polymers 0.000 description 4
- 229920001296 polysiloxane Polymers 0.000 description 4
- 238000007639 printing Methods 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 239000003566 sealing material Substances 0.000 description 4
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 4
- 229910004541 SiN Inorganic materials 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 229910052742 iron Inorganic materials 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 2
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000002679 ablation Methods 0.000 description 2
- 150000001252 acrylic acid derivatives Chemical class 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000005011 phenolic resin Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229920003192 poly(bis maleimide) Polymers 0.000 description 2
- 229920000058 polyacrylate Polymers 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910001080 W alloy Inorganic materials 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- ZTXONRUJVYXVTJ-UHFFFAOYSA-N chromium copper Chemical compound [Cr][Cu][Cr] ZTXONRUJVYXVTJ-UHFFFAOYSA-N 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
- H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13199—Material of the matrix
- H01L2224/1329—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13298—Fillers
- H01L2224/13299—Base material
- H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
- H01L2224/301—Disposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/8122—Applying energy for connecting with energy being in the form of electromagnetic radiation
- H01L2224/81224—Applying energy for connecting with energy being in the form of electromagnetic radiation using a laser
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/81439—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/81444—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/81455—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/81464—Palladium [Pd] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/81471—Chromium [Cr] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Abstract
一種具有用於嵌入式裝置的蝕刻的溝槽的半導體裝置被揭示,並且例如可以包含基板,其包括頂表面以及底表面;溝槽,其是從所述底表面延伸到所述基板中;以及在所述基板中的重分佈結構,其是在所述基板的所述頂表面與所述底表面之間。半導體晶粒例如可以是耦接至所述基板的所述頂表面。電子裝置例如可以是至少部分地在所述溝槽之內,並且電耦接至所述重分佈結構。導電墊例如可以是在所述基板的所述底表面上。導電凸塊例如可以是在所述導電墊上。在所述溝槽中的所述電子裝置例如可以延伸超出所述基板的所述底表面一段距離,所述距離小於所述導電凸塊從所述基板的所述底表面起算的高度。囊封劑例如可以封入所述半導體晶粒以及所述基板的所述頂表面。所述電子裝置例如可以包括電容器。
Description
本揭露內容的某些範例實施例是有關於半導體裝置封裝。更明確地說,本揭露內容的某些範例實施例是有關於一種具有用於嵌入式裝置的蝕刻的溝槽的半導體裝置。
相關的申請案的交互參照
本申請案是參考2016年1月6日申請的韓國專利申請案號10-2016-0001657,主張其優先權並且主張其益處,所述韓國專利申請案的內容是藉此將其整體納入在此作為參考。
儘管產品封裝持續傾向小型化,但是對於被納入到此種產品內的半導體裝置而言,具有增進的功能及/或縮小的尺寸是所期望的。此外,為了縮減半導體裝置的尺寸,所述半導體裝置的面積及/或厚度可被減低。
習知及傳統的方式的進一步限制及缺點對於具有此項技術的技能者而言,透過此種系統與如同在本申請案的其餘部分中參考圖式所闡述的本揭露內容的比較將會變成是明顯的。
此揭露內容的各種特點提供一種具有用於嵌入式裝置的蝕
刻的溝槽的半導體裝置,其實質如同在圖式的至少一圖中所示且/或相關該圖敘述的,即如同更完整地在所述請求項中闡述的。
本揭露內容的各種優點、特點以及新穎的特徵、以及各種支持實施例的所描繪的例子的細節從以下的說明及圖式將會更完整地瞭解。
10:載體基板
11:矽氧化物層
20:電子裝置區域墊
100:基板
110:導電墊
111:凸塊墊
112:金屬墊
120:第一介電層
120a:電子裝置溝槽
121:介電層
130:第一重分佈結構
131:電子裝置耦接結構
140:第二介電層
150:第二重分佈結構
160:第三介電層
170:第三重分佈結構
180:第四介電層
190:導電圖案
200:半導體晶粒
210:微凸塊
230:凸塊下金屬
300:囊封劑
400:電子裝置
500:導電凸塊
S1:形成一導電墊
S2:形成一第一介電層
S3:形成一重分佈結構
S4:形成一第二介電層
S5:耦接一半導體晶粒
S6:封入
S7:移除一載體基板
S8:選擇性的蝕刻
S9:連接一電子裝置
OP1:第一開口
OP2:第二開口
圖1是根據本揭露內容的一實施例的一種半導體裝置的橫截面圖。
圖2是描繪根據本揭露內容的一實施例的一種製造一半導體裝置的方法的流程圖。
圖3至圖9是描繪在圖2中所示的一半導體裝置的製造方法的各種的步驟。
本揭露內容的某些特點可見於一種具有用於嵌入式裝置的蝕刻的溝槽的半導體裝置中。本揭露內容的範例特點可包括一基板,其包括一頂表面以及一底表面;在所述基板中的一重分佈(redistribution)結構,其是在所述基板的所述頂表面與所述基板的所述底表面之間;以及一蝕刻區域或是溝槽,其是從所述底表面至所述第一重分佈結構地延伸到所述基板中。一半導體晶粒例如可以是耦接至所述基板的所述頂表面,並且一電子裝置可以是至少部分地在所述蝕刻區域之內,並且電耦接至所述第一重分佈結構。一導電墊例如可以是在所述基板的所述底表面上。一導電凸塊例如可以是在所述導電墊上。在所述蝕刻區域中的所述電子裝置例如可以延伸超出所述基板的所述底表面一段小於所述導電凸塊從所述基板的所述底
表面起算的一高度的距離。一囊封劑(encapsulant)例如可以封入所述半導體晶粒以及所述基板的所述頂表面。所述電子裝置例如可以包括一電容器。所述第一重分佈結構例如可以是電耦接至一在所述基板中的第二重分佈結構。所述半導體晶粒例如可以是電耦接至所述第二重分佈結構。
此揭露內容是提供支持本揭露內容的範例實施例。本揭露內容的範疇並不限於這些範例實施例。例如是在結構、尺寸、材料的類型、以及製程上的變化的許多變化,不論是明確由所述說明書提供的、或是由所述說明書所意涵的,都可以由熟習此項技術者鑒於此揭露內容下加以實施。
圖1是根據本揭露內容的一實施例的一種半導體裝置的橫截面圖。
參照圖1,根據本揭露內容的一實施例的半導體裝置可包含一基板100、一半導體晶粒200、一囊封劑300、一電子裝置400、以及一導電凸塊500。
所述基板100例如可包括一中介體,儘管本揭露內容並非限於此的,並且可包括任何具有絕緣及導電區域的支撐結構。所述基板100可包括被形成在例如是聚醯亞胺上的各種導電層。在另一範例情節中,所述基板100可包括各種堆疊在一矽晶圓或玻璃上的導電層及介電層。所述基板100可包括一在所述基板100的一底表面的導電墊110、一覆蓋除了所述導電墊110的一底表面之外的區域的第一介電層120、以及一第一重分佈結構130(例如,一第一導電層、等等),其是電連接至所述導電墊110並且被形成在所述第一介電層120的一頂表面處。
所述基板100亦可包括一覆蓋所述第一重分佈結構130的一部分的第二介電層140、一沿著所述第二介電層140的一頂表面所形成的第二重分佈結構150(例如,一導電層、等等)、一圍繞所述第二重分佈結構150的一部分的第三介電層160、一被形成在所述第三介電層160的一頂表面的第三重分佈結構170(例如,一導電層、等等)、一覆蓋所述第三重分佈結構170的一頂表面的一部分的第四介電層180、以及一電連接至所述第三重分佈結構170的一露出區域的導電圖案190(例如,線路、墊、焊盤、等等)。
在此,根據所需的複雜度,根據本揭露內容的一實施例的半導體裝置可以在無所述第二重分佈結構150至所述導電圖案190下、或是在額外的介電層以及重分佈結構下加以形成。例如,所述第一重分佈結構130或是所述第二重分佈結構150的頂表面可被露出以作用為一導電圖案(例如,作為所述導電圖案190)。
所述導電墊110可以透過所述基板100的底表面(例如,透過所述第一介電層120的底表面、等等)而被露出。所述範例的導電墊110是包含一金屬墊112以及一被設置在所述金屬墊112之下的凸塊墊111(例如,其包括凸塊下金屬化(under bump metallization)、等等)。
所述凸塊墊111可以耦接至所述金屬墊112的一表面。所述凸塊墊111可以具有和所述金屬墊112實質相同的寬度,並且可被形成以增加在所述金屬墊112與所述導電凸塊500之間的黏著性。所述凸塊墊111例如可包括鎳金(Ni/Au),但是本揭露內容並非限於此的。由於在一銅墊與一焊料凸塊之間的黏著性可能是弱的,因此被設置在所述金屬墊112與所述導電凸塊500之間的凸塊墊111可以增進所述黏著性。
所述金屬墊112例如可包括銅(Cu),因為銅是呈現極佳的導電度,其可以是有利於透過所述金屬墊112的信號傳輸。然而,所述金屬墊112可包括任何適當的導電層,以用於接收一至所述基板100的電性接點。
所述第一介電層120可被形成以圍繞所述導電墊110。如同在以下敘述的,所述第一介電層120可被形成在所述基板100的具有所述導電墊110被形成於其上的表面上,同時其圍繞所述導電墊110。在此例中,由於被形成在所述金屬墊112上的凸塊墊111是接觸所述基板100,因此所述凸塊墊111的一底表面可以在一移除所述基板100的部分的後續的步驟中,透過在所述第一介電層120中的開口而被露出。
所述第一介電層120(如同在此論述的任一個或是所有的介電層)可包括一或多層的各種介電材料的任一種,例如是無機介電材料(例如,Si3N4、SiO2、SiON、SiN、氧化物、氮化物、上述組合、其等同物、等等)及/或有機介電材料(例如,一聚合物、聚醯亞胺(PI)、苯環丁烯(BCB)、聚苯並噁唑(PBO)、雙馬來醯亞胺三嗪(BT)、一模製材料、一苯酚樹脂、一環氧樹脂、聚矽氧烷、丙烯酸酯聚合物、上述組合、其等同物、等等),但是本揭露內容的範疇並不限於此。
此外,所述第一介電層120可包括一被形成在所述第一介電層120中的電子裝置溝槽120a(或凹處)以露出所述第一重分佈結構130,以用於電性接觸至所述第一重分佈結構130。所述電子裝置溝槽120a可被形成到所述第一介電層120的一預設的深度,藉此露出所述第一重分佈結構130的一電子裝置耦接結構131(或區域)。注意到的是,在各種的範例實施方式中,所述溝槽120a可以延伸穿過多個介電層(例如,兩個介電層、三個
介電層、等等)以露出一所選的重分佈結構,以用於電連接至所選的重分佈結構。
根據將被設置於其中的電子裝置的形狀,所述溝槽120a(或凹處)可以用各種的形狀來加以形成。例如,所述溝槽120a可包括一用於直線結構的長且薄的通道、或是一方形或圓形開口以用於類似形狀的裝置,其中所述溝槽120a包括之開口可例如為圖1及圖4所示的第一開口OP1。根據圖1所示的實施例,所述第一開口OP1延伸穿過所述第一介電層120的底側而到所述第一重分佈結構130以及到所述基板100中的一深度。又根據圖1及圖4所示,所述第一介電層120包括第二開口OP2,所述第二開口OP2延伸至所述第一介電層120的頂側並且部分穿透所述第一介電層120。所述第一開口OP1部分穿過所述第一介電層120而到所述第二開口OP2並且曝露所述第一重分佈結構130的底側部,其中所述第一開口OP1的寬度大於所述第二開口OP2的寬度;以及所述電子裝置400電耦接到藉由所述第一開口OP1和所述第二開口OP2所曝露的所述第一重分佈結構130的所述底側部。於是,所述電子裝置400可以在所述基板100的一底部部分耦接至所述基板100,並且電連接至所述電子裝置耦接結構131(或區域)。由於所述電子裝置400可被設置在介於所述基板與一被耦接至所述基板110的底部部分的外部的電路板(未顯示)之間的基板100的溝槽中,因此避免或防止所述半導體裝置的整體厚度增加是可能的,甚至在相當大的裝置被設置於其中也是如此。此外,由於所述電子裝置400的厚度是等於或小於所述電子裝置溝槽120a的一深度以及所述導電凸塊500的一高度的總和,因此所述較大的可利用的高度是在選擇所述電子裝置400上提供一較大的自由度。
此外,所述第一介電層120的底部區域可以被一介電層121所覆蓋。所述介電層121例如可包括一矽氧化物層,其可以藉由製備或利用由一矽材料所做成的一載體基板來加以提供,其是在以下加以描述。在移除所述載體基板的一後續的步驟中,所述載體基板可被形成使得其只有保留在所述第一介電層120的一除了所述導電墊110以及電子裝置溝槽120a之外的區域中。所述介電層121可以電性隔離(或是進一步電性隔離)所述基板100的底表面,藉此增進電性可靠度。於是,在一種其中一額外的介電層是所要的範例的實施方式中,一用以形成此種層的額外的製程步驟並不需要加以執行。
所述第一重分佈結構130(例如,一或多個導電層、等等)可以沿著所述第一介電層120的一頂表面來加以形成。所述第一重分佈結構130(如同在此論述的所有的重分佈結構、導電層、互連結構、與類似者)可包括各種材料(例如,銅、鋁、鎳、鐵、銀、金、鈦、鉻、鎢、鈀、上述組合、其合金、或是類似的材料、等等)的任一種,但是本揭露內容的範疇並不限於此。所述第一重分佈結構130可以填入一在所述第一介電層120中的貫孔(via),以便於電連接至所述導電墊110。所述第一重分佈結構130例如可以像是所述導電墊110的金屬墊112而包括銅,但是本揭露內容的特點並不限於此。由於所述第一重分佈結構130可以垂直地耦接至所述導電墊110,並且水平地從所述導電墊110延伸,因此一導電圖案可被形成,而不論耦接至所述導電墊110的導電凸塊500的間距或高度為何。因此,根據本揭露內容,所述第一重分佈結構130可以在設計所述半導體裝置上增加一自由度。
此外,用於耦接所述電子裝置400至所述基板100的電子裝置耦接結構131可以利用和所述第一重分佈結構130相同的一或多層的導電層來加以形成。所述電子裝置耦接結構131可以在和所述第一重分佈結構130相同的製程中加以形成,並且可以在不連接至一個別的導電墊之下,透過所述第一介電層120而被露出。
所述第二介電層140可以覆蓋所述第一重分佈結構130。例如,所述第二介電層140可被形成以露出所述第一重分佈結構130的一區域以用於電連接至所述區域,同時其覆蓋所述第一重分佈結構130的其餘部分。所述第二介電層140可包括在此相關所述第一介電層120論述的介電材料中的任一種或是多種。所述第二介電層140例如可以包括和所述第一介電層120相同的介電材料、或是可包括不同的介電材料。
所述第二重分佈結構150(例如,一或多個導電層、等等)可以沿著所述第二介電層140的一頂表面來加以形成。所述第二重分佈結構150例如可以包括在此相關所述第一重分佈結構130論述的導電材料中的任一種或是多種。所述第二重分佈結構150例如可以包括和所述第一重分佈結構130相同的導電材料、或是可包括不同的導電材料。所述第二重分佈結構150可以透過一在所述第二介電層140中的貫孔來電連接至所述第一重分佈結構130。
所述第三介電層160可以覆蓋所述第二重分佈結構150。例如,所述第三介電層160可被形成以露出所述第二重分佈結構150的一區域以用於電連接至所述區域,同時覆蓋所述第二重分佈結構150的其餘部分。所述第三介電層160可包括在此相關所述第一介電層120論述的介電材料中
的任一種或是多種。所述第三介電層160例如可以包括和所述第一介電層120及/或所述第二介電層140相同的介電材料、或是可包括不同的介電材料。
所述第三重分佈結構170(例如,一或多個導電層、等等)可以沿著所述第三介電層160的一頂表面來加以形成。所述第三重分佈結構170可被形成以沿著所述第三介電層160延伸而向上到達一耦接至所述半導體晶粒200的區域。所述第三重分佈結構170例如可以包括在此相關所述第一重分佈結構130論述的導電材料中的任一種或是多種。所述第三重分佈結構例如可以包括和所述第一重分佈結構130及/或所述第二重分佈結構150相同的導電材料、或是可包括不同的導電材料。所述第三重分佈結構170可以透過一在所述第三介電層160中的貫孔來電連接至所述第二重分佈結構150。
所述第四介電層180可以覆蓋所述第三重分佈結構170。所述第四介電層180例如可以覆蓋除了所述第三重分佈結構170的將被耦接至所述半導體晶粒200的一區域之外的大部分的第三重分佈結構170。所述第四介電層180可包括在此相關所述第一介電層120論述的介電材料中的任一種或是多種。所述第四介電層180例如可以包括和所述第一介電層120、第二介電層140、及/或第三介電層160相同的介電材料、或是可包括不同的介電材料。如本發明圖9所揭示之實施例,所述第一介電層120的厚度大於第二介電層140、第三介電層160以及第四介電層180任一者的厚度。
所述導電圖案190(例如,一線路、墊、焊盤、等等)可以電
連接至所述第三重分佈結構170的一露出區域。所述導電圖案190可包括在此相關所述第一重分佈結構130論述的導電材料中的任一種或是多種。所述導電圖案190例如可以通過一在所述第四介電層180中的貫孔,以電耦接至所述第三重分佈結構170。所述導電圖案190可被露出以耦接至所述半導體晶粒200。
所述半導體晶粒200可以電連接至所述基板100的導電圖案190。所述半導體晶粒200可以藉由例如是質量回焊、熱壓縮、雷射接合、導電的黏著劑接合、等等來電連接至所述基板100的導電圖案190,但是此揭露內容的範疇並不限於此。儘管只有一半導體晶粒200被展示,但是可以有任意數目的半導體晶粒(或是其它電子構件)。在一包含複數個半導體晶粒的範例的實施方式中,此種實施方式可包括複數個被配置在水平及/或垂直的方向上的半導體晶粒。
再者,所述半導體晶粒200可包括從一半導體晶圓分開的積體電路晶片。此外,所述半導體晶粒200例如可包括像是中央處理單元(CPU)、數位信號處理器(DSP)、網路處理器、電源管理單元、音訊處理器、RF電路、無線基頻系統單晶片(SoC)處理器、感測器以及特殊應用積體電路(ASIC)的電路。
所述半導體晶粒200可以是在主動側向下,透過微凸塊210或是各種類型的互連結構的任一種而被接合至所述基板100的導電圖案190。所述半導體晶粒200的微凸塊210(或互連結構)可包括一例如是焊料凸塊或球體的導電凸塊或球體、一例如是銅柱或柱體的導電柱或柱體、及/或一具有一被形成在其上的焊料蓋的導電柱或柱體、等等。為了增加在所述
半導體晶粒200的微凸塊210與所述基板100的導電圖案190之間的黏著力,一個別的凸塊下金屬230可被利用。所述凸塊下金屬230例如可以包括鉻(Cr)、鎳(Ni)、鈀(Pd)、金(Au)、銀(Ag)、其合金、以及類似的材料中的一或多種,但是本揭露內容的特點並不限於此。
所述囊封劑300(或是密封的材料)可被形成在所述基板100的頂表面上,以封入所述半導體晶粒200。所述囊封劑300可包括各種密封或模製材料(例如,樹脂、聚合物、聚合物複合材料、具有填充物的聚合物、環氧樹脂、具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯、聚矽氧烷樹脂、上述組合、其等同物、等等)的任一種。所述囊封劑300例如可以有助於維持在所述基板100與半導體晶粒200之間的電性互連,並且藉由防止撞擊直接被轉移至所述半導體晶粒200來保護所述半導體晶粒200。
所述電子裝置400可以在所述基板100的一底部側(或是表面)處被耦接至所述基板100。所述電子裝置400可以與所述半導體晶粒200分開地運作,並且例如可包含主動或是被動元件,例如像是一通訊模組、振盪器、時脈、例如是電容器或電感器的晶片外的電抗元件、及/或晶片外的電阻器。
所述電子裝置400可以電連接至被形成在所述基板100之內的電子裝置耦接結構131。如上所述,由於所述電子裝置耦接結構131是藉由被形成在所述基板100的第一介電層120中的電子裝置溝槽120a(或是凹處或孔)而被露出,因此所述電子裝置400可以連接至所述電子裝置耦接結構131,使得所述電子裝置400的至少一部分被***到所述電子裝置溝槽120a中。因此,所述電子裝置400可以耦接至所述基板100,使得所述電子
裝置400的至少一部分是被嵌入在所述基板100之內。此外,在一範例的實施方式中,所述電子裝置400的一高度並不超過所述基板100的電子裝置溝槽120a的深度以及所述導電凸塊500的一高度的總和。如圖9所示的實施例中,所述電子裝置溝槽120a沒有延伸至所述第一介電層120的頂側。在一範例的實施方式中,所述電子裝置400的高度是小於所述電子裝置溝槽120a的深度以及所述導電凸塊500(例如,在所述導電凸塊500被回焊以將所述半導體裝置附接至另一基板之前及/或之後)的高度的總和。在一範例的實施方式中,所述電子裝置400可以作為在所述電子裝置與所述電子裝置例如是在所述導電凸塊500被回焊時將被附接到的一基板之間的一間隔。在一範例的實施方式中,所述導電凸塊500可包括一固體的核心(例如,一銅核心、等等),以確保在所述導電凸塊500的回焊以將所述半導體裝置附接至一基板之際,在所述電子裝置400與此種基板之間有一間隙。
所述電子裝置400例如可以與所述半導體晶粒200的位置無關地加以設置(例如,在所述半導體晶粒200的覆蓋區之內或是之外、等等),並且所述電子裝置400的至少一部分可被嵌入或是***到所述基板100中,藉此降低所述半導體裝置的整體厚度。此外,由於所述導電凸塊500的高度被最小化(例如,相對於一種其中所述電子裝置400並未被內嵌的實施方式、等等),因此一細微的間距可加以實施。
所述導電凸塊500(或是其它互連結構)可被設置在所述基板100之下。所述導電凸塊500可包括各種特徵的任一種。例如,所述導電凸塊500(或是其它互連結構)可包括一導電凸塊或球體(例如,一焊料凸塊或球體、一金屬或銅核心焊料凸塊或球體、等等)、一金屬柱或柱體(例如,一銅
柱或柱體、一焊料封頂的金屬柱或柱體、等等)、等等。如圖所示,所述導電凸塊500例如可以具有一實質球狀的形狀,儘管其它的形狀及材料也是可能的。所述導電凸塊500可以耦接至在所述基板100的導電墊110上的凸塊墊111。因此,根據本揭露內容的一實施例的半導體裝置可以輸入/輸出一電性信號往/返所述晶粒200,透過所述導電凸塊500以往/返一外部的電路(未顯示)。
如上所述,在根據本揭露內容的一實施例的半導體裝置中,所述電子裝置溝槽120a可被形成在所述基板100的一區域中,以露出所述第一重分佈結構130(或是其它重分佈結構或層)的電子裝置耦接結構131,並且所述電子裝置400可以電連接至所述電子裝置耦接結構131,其中所述電子裝置400的至少一部分是被***到所述電子裝置溝槽120a中,藉此降低所述電子裝置400的整體厚度。此外,由於所述電子裝置400的至少一部分可被***或是內嵌在所述電子裝置溝槽120a中,因此一細微的間距可以藉由維持所述導電凸塊500的厚度在一最小位準來加以實施。
根據本揭露內容的一實施例的一種製造所述半導體裝置的方法是在以下加以描述。
圖2是描繪根據本揭露內容的一實施例的一種製造一半導體裝置的方法的流程圖,並且圖3至圖9是描繪在圖2中所示的製造一半導體裝置的方法的各種步驟。
首先參考圖2,根據本揭露內容的一實施例的製造所述半導體裝置的方法可包括形成一導電墊(S1)、形成一第一介電層(S2)、形成一重分佈結構(S3)、形成一第二介電層(S4)、耦接一半導體晶粒(S5)、封入(S6)、
移除一載體基板(S7)、選擇性的蝕刻(S8)、以及連接一電子裝置(S9)。在圖2中所示的製造所述半導體裝置的方法的各種步驟是參考圖3至9來加以描述。
參照圖2及圖3,在形成所述導電墊(步驟S1)中,一載體基板10是被設置有一在其頂表面上的矽氧化物層11(或是其它介電層)、以及在所述矽氧化物層11的一頂表面上的一導電墊110以及一電子裝置區域墊20。
所述載體基板10例如可以是有核心的、或是無核心的。所述載體基板10可包括一或多層的各種介電材料的任一種,例如是無機介電材料(例如,Si3N4、SiO2、SiON、SiN、氧化物、氮化物、等等)及/或有機介電材料(例如,一聚合物、聚醯亞胺(PI)、苯環丁烯(BCB)、聚苯並噁唑(PBO)、雙馬來醯亞胺三嗪(BT)、一模製材料、一苯酚樹脂、一環氧樹脂、等等),但是本揭露內容的範疇並不限於此。所述載體基板10例如可以包括矽或是各種半導體材料的任一種。再者,所述載體基板10例如可以包括一玻璃或是金屬板(或晶圓)。所述載體基板10可以是具有各種配置的任一種。例如,所述載體基板10可以是晶圓或面板形式。再者,所述載體基板10例如可以是具有經切割或單粒化的形式。所述基板亦可被稱為一中介體。
所述介電層11例如可以包括在此論述的介電層的任一個的特徵。在一範例的實施方式中,所述介電層11可包括一矽氧化物層或是其它無機介電層。
如上所述,所述導電墊110可包括一凸塊墊111以及一金屬墊112。所述凸塊墊111例如可以包括一凸塊下金屬化結構。步驟S1可包
括用各種方式的任一種來形成所述凸塊墊111,其非限制性的例子是在此加以提供。在一範例的實施方式中,所述凸塊下金屬化("UBM")結構(其亦可被稱為一凸塊下金屬結構)例如可以包括一層鈦-鎢(TiW),其可被稱為一層或是晶種層。此種層例如可以是藉由濺鍍來加以形成。同樣例如的是,所述UBM結構可包括在所述TiW層上的一層銅(Cu)。再者,此種層例如可以是藉由濺鍍來加以形成。在另一範例的實施方式中,形成一UBM結構可包括藉由濺鍍來形成一層鈦(Ti)或是鈦-鎢(TiW)、(ii)在所述鈦或是鈦-鎢層上藉由濺鍍以形成一層銅(Cu)、以及(iii)在所述銅層上藉由電鍍以形成一層鎳(Ni)。然而,注意到的是所述UBM結構及/或被利用以形成所述UBM結構的製程並不限於所給出的例子。例如,所述UBM結構可包括鉻/鉻-銅合金/銅(Cr/Cr-Cu/Cu)、鈦-鎢合金/銅(Ti-W/Cu)、鋁/鎳/銅(Al/Ni/Cu)、其等同物、等等的一種多層的結構。再者,所述UBM結構例如可以包括鋁、鈀、金、銀、其合金、等等。注意到的是,在各種的範例實施方式中,所述凸塊墊111(或是UBM結構)並不需要加以形成。
所述金屬墊112可包括各種材料(例如,銅、鋁、鎳、鐵、銀、金、鈦、鉻、鎢、鈀、上述組合、其合金、其等同物、等等)的任一種,但是本揭露內容的範疇並不限於此。步驟S1可包括用各種方式的任一種以形成所述金屬墊112,其非限制性的例子是在此加以提供。所述金屬墊112可以利用各種製程(例如,電解的電鍍、無電的電鍍、化學氣相沉積(CVD)、濺鍍或物理氣相沉積(PVD)、原子層沉積(ALD)、電漿氣相沉積、印刷、網版印刷、微影、等等)中的任一種或是多種來加以形成或是沉積,但是本揭露內容的範疇並不限於此。此外,步驟S1可包括例如是用所述金屬墊112
被形成所用的相同的方式(例如,在一相同的製程步驟中)來形成所述電子裝置區域墊20。在一範例的實施方式中,相對於所述導電墊110,所述電子裝置區域墊20可以不包含所述凸塊墊111(或類似者),例如其被直接形成在所述矽氧化物上,而不是一種被形成在所述矽氧化物上的UBM結構。
參照圖2及圖4,在形成所述第一介電層(步驟S2)中,所述第一介電層120可被形成在所述載體基板10的一頂表面上。所述第一介電層120例如可被形成以覆蓋所述導電墊110以及電子裝置區域墊20的區域,同時露出所述導電墊110以及電子裝置區域墊20的部分,以用於電連接至所述部分。
所述第一介電層120可包括一或多層的各種介電材料的任一種,例如是無機介電材料(例如,Si3N4、SiO2、SiON、SiN、氧化物、氮化物、上述組合、其等同物、等等)及/或有機介電材料(例如,一聚合物、聚醯亞胺(PI)、苯環丁烯(BCB)、聚苯並噁唑(PBO)、雙馬來醯亞胺三嗪(BT)、一模製材料、一苯酚樹脂、一環氧樹脂、聚矽氧烷、丙烯酸酯聚合物、上述組合、其等同物、等等),但是本揭露內容的範疇並不限於此。
步驟S2可包括用各種方式的任一種以形成所述第一介電層120。例如,所述第一介電層120可以利用各種製程(例如,旋轉塗覆、噴霧塗覆、印刷、燒結、熱氧化、物理氣相沉積(PVD)、化學氣相沉積(CVD)、金屬有機化學氣相沉積(MOCVD)、原子層沉積(ALD)、低壓化學氣相沉積(LPCVD)、電漿輔助化學氣相沉積(PECVD)、電漿氣相沉積(PVD)、片疊層、蒸鍍、等等)中的任一種或是多種來加以形成,但是本揭露內容的範疇並不限於此。
參照圖2及圖5,在形成所述重分佈層(步驟S3)中,一第一重分佈結構130(例如,一或多個導電層、等等)可以藉由在所述第一介電層120的一頂表面上形成由一種導電材料所做成的一圖案來加以形成。所述第一重分佈結構130可以電連接至所述露出的導電墊110以及所述露出的電子裝置區域墊20,並且可以沿著所述第一介電層120的頂表面延伸。此外,所述電子裝置耦接結構131可被形成在所述電子裝置區域墊20上,藉此將所述電子裝置耦接結構131電耦接至所述電子裝置區域墊20。
所述第一重分佈結構130以及電子裝置耦接結構131(如同在此論述的所有的重分佈結構、導電層、互連結構、與類似者)可包括各種材料(例如,銅、鋁、鎳、鐵、銀、金、鈦、鉻、鎢、鈀、上述組合、其合金、其等同物、等等)的任一種,但是本揭露內容的範疇並不限於此。步驟S3可包括利用各種製程(例如,電解的電鍍、無電的電鍍、化學氣相沉積(CVD)、濺鍍或物理氣相沉積(PVD)、原子層沉積(ALD)、電漿氣相沉積、印刷、網版印刷、微影、等等)中的任一種或是多種來形成所述第一重分佈結構130以及電子裝置耦接結構131,但是本揭露內容的範疇並不限於此。
參照圖2及圖5,在形成所述第二介電層(步驟S4)中,除了所述第一重分佈結構130的一被露出用於電連接至其的部分之外,一第二介電層140可被形成在所述第一重分佈結構130上。所述第二介電層140可包括在此相關所述第一介電層120論述的介電材料中的任一種或是多種。所述第二介電層140例如可以包括和所述第一介電層120相同的介電材料、或是可包括不同的介電材料。步驟S4例如可以包括用在此相關所述第一介電層120(例如,相關步驟S2、等等)論述的方式的任一種來形成第二介電層
140。
此外,如同在圖5中所繪的,在形成所述第二介電層140之後,一第二重分佈結構150、一第三介電層160、一第三重分佈結構170、一第四介電層180以及一導電圖案190接著可被形成。包含所述第二介電層140、第二重分佈結構150、第三介電層160、第三重分佈結構170、第四介電層180、以及導電圖案190的層的形成可以根據所要的互連複雜度而被簡化或消除。例如,此種介電層及/或其形成的任一個都可以與在此論述的第一及/或第二介電層120及140及/或其形成共用任一個或是所有的特徵。同樣例如的是,此種重分佈結構及/或其形成的任一個都可以與在此論述的第一重分佈層130及/或其形成共用任一個或是所有的特徵。
參照圖2及圖6,在耦接所述半導體晶粒(步驟S5)中,所述半導體晶粒200可以耦接至所述導電圖案190的一頂端部分。步驟S5可包括利用各種類型的互連結構(例如,導電球體或凸塊、焊料球體或凸塊、金屬柱或柱體、銅柱或柱體、焊料封頂的柱或柱體、焊料膏、導電的黏著劑、等等)的任一種,來附接(或是安裝)所述半導體晶粒200至所述基板100(或是其導電圖案190)。步驟S5可包括利用各種接合技術(例如,熱壓接合、質量回焊、雷射回焊、黏著劑附接、等等)的任一種,來安裝所述半導體晶粒200(及/或其它電子構件)至所述基板。在一如同在此論述的範例的實施方式中,所述半導體晶粒200可以在主動側向下地被接合,透過所述微凸塊210以耦接至所述導電圖案190,並且所述凸塊下金屬230可被形成(例如,如同在此論述的)在所述半導體晶粒200與所述導電圖案190之間,以增進所述晶粒200至所述基板100的黏著性。
參照圖2及圖7,在封入所述封裝(步驟S6)中,一囊封劑300可被形成在所述基板100上,以封入所述半導體晶粒200。此外,儘管未個別地加以描繪,所述囊封劑300可被形成以將所述半導體晶粒200的一頂表面露出至其頂表面以用於散熱。在另一範例情節中,所述囊封劑300可被向下研磨到所述半導體晶粒200的頂表面。
所述囊封劑300(或是密封的材料)可被形成在所述基板100的頂表面上,以封入所述半導體晶粒200。所述囊封劑300可包括各種密封或模製材料(例如,樹脂、聚合物、聚合物複合材料、具有填充物的聚合物、環氧樹脂、具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯、聚矽氧烷樹脂、上述組合、其等同物、等等)的任一種。步驟S6可包括用各種方式(例如,壓縮模製、轉移模製、液體囊封劑模製、真空疊層、膏印刷、膜輔助的模製、等等)的任一種來形成所述囊封劑300。
參照圖2及圖8,在移除所述載體基板(S7)中,所述載體基板10可以例如是藉由研磨、剝離、蝕刻、等等來和所述基板100(例如,全體或是部分的)分開。當所述載體基板10被移除時,所述介電層121可以留下。此外,所述導電墊110的金屬墊111以及所述電子裝置區域墊20可以藉由部分地蝕刻所述介電層121而被露出。
參照圖2及圖9,對於選擇性的蝕刻(步驟S8)而言,所述電子裝置區域墊20可以選擇性地被蝕刻,並且從所述露出的金屬墊111以及所述露出的電子裝置區域墊20加以移除。步驟S8可包括用各種方式的任一種來形成所述電子裝置溝槽120a(或是凹處或孔)。例如,由於所述電子裝置區域墊20以及所述金屬墊111包括不同的材料,因此選擇性的乾式或濕
式蝕刻可以利用在所述電子裝置區域墊20以及所述金屬墊111的蝕刻速率之間的差異來加以執行。於是,所述電子裝置溝槽120a可被形成在所述基板100上,並且所述第一重分佈結構130的電子裝置耦接結構131可以透過所述電子裝置溝槽120a而被露出。同樣例如的是,步驟S8可包括利用機械式剝蝕、雷射剝蝕、電漿剝蝕、等等以形成所述電子裝置溝槽120a,並且露出所述電子裝置耦接結構131。
參照圖2及圖9,在連接所述電子裝置(S9)中,所述電子裝置400的至少一部分可被***到所述電子裝置溝槽120a中,以電連接至所述電子裝置耦接結構131。所述電子裝置400的連接例如可以利用各種接合技術(例如,熱壓接合、質量回焊、雷射回焊、黏著劑附接、等等)的任一種來加以執行。此外,如同在圖9中所繪,所述導電凸塊500(或是各種互連結構的任一種,其例子是在此被提供)可以利用一焊料材料而被形成在所述金屬墊111上。
所述電子裝置400可以連接至所述電子裝置耦接結構131,使得所述電子裝置400的至少一部分是被***到所述電子裝置溝槽120a中。因此,所述電子裝置400可以耦接至所述基板100,以使得所述電子裝置400的至少一部分是被嵌入在所述基板100之內。此外,在一範例的實施方式中,所述電子裝置400的一高度並不超過所述基板100的電子裝置溝槽120a的深度以及所述導電凸塊500的一高度的總和。在一範例的實施方式中,所述電子裝置400的高度是小於所述電子裝置溝槽120a的深度以及所述導電凸塊500(例如,在所述導電凸塊500被回焊以將所述半導體裝置附接至另一基板之前及/或之後)的高度的總和。在一範例的實施方式中,所述電
子裝置400可以作為在所述電子裝置以及所述電子裝置例如在所述導電凸塊500被回焊時被附接到的一基板之間的一間隔。在一範例的實施方式中,所述導電凸塊500可包括一固體的核心(例如,一銅核心、等等),以確保在所述導電凸塊500的回焊以將所述半導體裝置附接至一基板之際,在所述電子裝置400與此種基板之間有一間隙。
在本揭露內容的一範例實施例中,一種具有用於嵌入式裝置的蝕刻的溝槽的半導體裝置包括一基板,其包括一頂表面以及一底表面;一溝槽,其是從所述底表面延伸到所述基板中;以及在所述基板中的一重分佈結構,其是在所述基板的所述頂表面與所述基板的所述底表面之間。一半導體晶粒可以耦接至所述基板的所述頂表面。一電子裝置可以至少部分地在所述溝槽之內,並且電耦接至所述重分佈結構。一導電墊可以是在所述基板的所述底表面上。一導電凸塊可以是在所述導電墊上。在所述溝槽中的所述電子裝置可以延伸超出所述基板的所述底表面一段小於所述導電凸塊從所述基板的所述底表面起算的一高度的距離。一囊封劑可以封入所述半導體晶粒以及所述基板的所述頂表面。所述電子裝置可包括一電容器。所述重分佈結構可以電耦接至一在所述基板中的第二重分佈結構。所述半導體晶粒可以電耦接至所述第二重分佈結構。
儘管各種支持本揭露內容的特點已經參考某些範例實施例來加以敘述,但是熟習此項技術者將會理解到可以做成各種的改變,並且等同物可加以取代,而不脫離本揭露內容的範疇。此外,可以做成許多修改以將一特定的情況或材料調適至本揭露內容的教示,而不脫離其範疇。因此,所欲的是本揭露內容並不受限於所揭露之特定的範例實施例,而是
本揭露內容將會包含所有落入所附的請求項的範疇內的實施例。
100:基板
110:導電墊
111:凸塊墊
112:金屬墊
120:第一介電層
120a:電子裝置溝槽
121:介電層
130:第一重分佈結構
131:電子裝置耦接結構
140:第二介電層
150:第二重分佈結構
160:第三介電層
170:第三重分佈結構
180:第四介電層
190:導電圖案
200:半導體晶粒
210:微凸塊
230:凸塊下金屬
300:囊封劑
400:電子裝置
500:導電凸塊
Claims (11)
- 一種半導體裝置,其包括:基板,其包括:頂表面以及底表面;第一介電層,其在所述基板的所述頂表面與所述基板的所述底表面之間;第一重分佈結構,其在所述第一介電層的頂側上;第二介電層,其在所述第一重分佈結構的頂側上;以及第一開口,其延伸穿過所述第一介電層的底側而到所述第一重分佈結構以及到所述基板中的一深度;半導體晶粒,其是耦接至所述基板的所述頂表面;電子裝置,其經由所述第一開口電耦接至所述第一重分佈結構;以及焊料凸塊,其耦接至所述基板的所述底表面;其中所述焊料凸塊包括固體銅核心;其中所述電子裝置的垂直高度大於所述基板的所述第一開口的所述深度;並且其中所述第一介電層的厚度大於所述第二介電層的厚度;其中所述固體銅核心確保在所述電子裝置經由所述焊料凸塊的焊料回焊而附接到另一裝置之後,在所述電子裝置的底部和另一裝置之間有一間隙;其中所述第一介電層包括第二開口,所述第二開口延伸至所述第一介電層的頂側並且部分穿透所述第一介電層; 其中所述第一開口部分穿過所述第一介電層而到所述第二開口並且曝露所述第一重分佈結構的底側部,其中所述第一開口的寬度大於所述第二開口的寬度;並且其中所述電子裝置電耦接到藉由所述第一開口和所述第二開口所曝露的所述第一重分佈結構的所述底側部。
- 如請求項1的半導體裝置,其包括:導電墊,所述導電墊在所述基板的所述底表面上;並且其中所述焊料凸塊耦接到所述導電墊。
- 如請求項2的半導體裝置,其中所述固體銅核心確保所述第一開口的所述深度與所述焊料凸塊的回焊高度的總和大於所述電子裝置的所述高度。
- 如請求項1的半導體裝置,其包括將所述半導體晶粒以及所述基板的所述頂表面封入的囊封劑,其中所述囊封劑接觸所述基板的所述頂表面。
- 如請求項1的半導體裝置,其中所述電子裝置包括電容器。
- 如請求項1的半導體裝置,其中所述基板包括第二重分佈結構,其電耦接至所述第一重分佈結構。
- 如請求項6的半導體裝置,其中所述半導體晶粒是電耦接至所述第二重分佈結構。
- 一種製造半導體裝置的方法,所述方法包括:形成基板,形成所述基板包括:形成電子裝置區域墊於載體上;將第一介電層覆蓋所述電子裝置區域墊的頂表面; 曝露所述電子裝置區域墊的所述頂表面;以及在所述第一介電層上方形成第一重分佈結構,使得所述第一重分佈結構耦接到所述電子裝置區域墊的所述頂表面;耦接半導體晶粒至所述基板的所述頂表面;從所述基板處移除所述載體;從所述基板的底表面選擇性蝕刻所述電子裝置區域墊的金屬以形成溝槽,所述溝槽延伸穿過所述基板的所述底表面且進入所述第一介電層並且曝露所述第一重分佈結構的底表面區域;以及經由所述溝槽將電子裝置耦接至所述第一重分佈結構,所述電子裝置的高度大於所述溝槽的深度,以使得所述電子裝置部分地定位在所述溝槽之中並且延伸超過所述基板的所述底表面。
- 如請求項8的方法,其包括利用囊封劑來封入所述半導體晶粒以及所述基板的所述頂表面,所述囊封劑接觸所述基板的所述頂表面。
- 如請求項8的方法,其包括在所述基板的所述底表面處將焊料凸塊耦接至導電墊。
- 如請求項10的方法,其中所述焊料凸塊包括固體銅核心,所述固體銅核心確保從所述基板的所述底表面算起的所述焊料凸塊的回焊高度大於所述電子裝置從所述基板的所述底表面延伸的距離。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020160001657A KR101761502B1 (ko) | 2016-01-06 | 2016-01-06 | 반도체 디바이스 및 그 제조 방법 |
KR10-2016-0001657 | 2016-01-06 | ||
US15/149,436 US20170194239A1 (en) | 2016-01-06 | 2016-05-09 | A semiconductor package having an etched groove for an embedded device formed on bottom surface of a support substrate and a method for fabricating the same |
US15/149,436 | 2016-05-09 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201725671A TW201725671A (zh) | 2017-07-16 |
TWI806816B true TWI806816B (zh) | 2023-07-01 |
Family
ID=59226668
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW111130237A TW202308067A (zh) | 2016-01-06 | 2016-06-01 | 半導體裝置和其製造之方法 |
TW105117136A TWI806816B (zh) | 2016-01-06 | 2016-06-01 | 半導體裝置和其製造之方法 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW111130237A TW202308067A (zh) | 2016-01-06 | 2016-06-01 | 半導體裝置和其製造之方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20170194239A1 (zh) |
KR (1) | KR101761502B1 (zh) |
CN (1) | CN106952878B (zh) |
TW (2) | TW202308067A (zh) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10573590B2 (en) * | 2016-10-20 | 2020-02-25 | UTAC Headquarters Pte. Ltd. | Multi-layer leadless semiconductor package and method of manufacturing the same |
US20220028770A1 (en) * | 2020-07-24 | 2022-01-27 | Texas Instruments Incorporated | Semiconductor device with a power converter module |
US20240222345A1 (en) * | 2022-12-29 | 2024-07-04 | Intel Corporation | Die attach in glass core package through organic-to-organic bonding |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201532234A (zh) * | 2014-02-13 | 2015-08-16 | Taiwan Semiconductor Mfg Co Ltd | 具有嵌入式表面配裝裝置的半導體封裝與其形成方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5939782A (en) * | 1998-03-03 | 1999-08-17 | Sun Microsystems, Inc. | Package construction for integrated circuit chip with bypass capacitor |
JP2003060523A (ja) * | 2001-08-09 | 2003-02-28 | Tdk Corp | 無線通信モジュール |
US20040022038A1 (en) * | 2002-07-31 | 2004-02-05 | Intel Corporation | Electronic package with back side, cavity mounted capacitors and method of fabrication therefor |
JP2004079736A (ja) * | 2002-08-15 | 2004-03-11 | Sony Corp | チップ内蔵基板装置及びその製造方法 |
KR100840788B1 (ko) * | 2006-12-05 | 2008-06-23 | 삼성전자주식회사 | 칩 적층 패키지 및 그 제조 방법 |
KR101025520B1 (ko) * | 2008-11-26 | 2011-04-04 | 삼성전기주식회사 | 다층 인쇄회로기판 제조방법 |
CN206022346U (zh) * | 2016-01-06 | 2017-03-15 | 艾马克科技公司 | 具有用于嵌入式装置的蚀刻沟槽的半导体装置 |
-
2016
- 2016-01-06 KR KR1020160001657A patent/KR101761502B1/ko active IP Right Grant
- 2016-05-09 US US15/149,436 patent/US20170194239A1/en not_active Abandoned
- 2016-06-01 TW TW111130237A patent/TW202308067A/zh unknown
- 2016-06-01 TW TW105117136A patent/TWI806816B/zh active
- 2016-06-29 CN CN201610495703.5A patent/CN106952878B/zh active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201532234A (zh) * | 2014-02-13 | 2015-08-16 | Taiwan Semiconductor Mfg Co Ltd | 具有嵌入式表面配裝裝置的半導體封裝與其形成方法 |
Also Published As
Publication number | Publication date |
---|---|
KR20170082359A (ko) | 2017-07-14 |
KR101761502B1 (ko) | 2017-07-25 |
US20170194239A1 (en) | 2017-07-06 |
CN106952878A (zh) | 2017-07-14 |
TW201725671A (zh) | 2017-07-16 |
CN106952878B (zh) | 2023-03-14 |
TW202308067A (zh) | 2023-02-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20210082848A1 (en) | Methods and Apparatus for Transmission Lines in Packages | |
TWI749005B (zh) | 半導體裝置及其製造方法 | |
KR102436836B1 (ko) | 반도체 장치 및 그 제조 방법 | |
US10074553B2 (en) | Wafer level package integration and method | |
US10079157B2 (en) | Semiconductor device and manufacturing method thereof | |
US9478474B2 (en) | Methods and apparatus for forming package-on-packages | |
KR102642327B1 (ko) | 반도체 디바이스 및 그 제조 방법 | |
JP2019096873A (ja) | パッケージ構造体及びパッケージ構造体の製造方法 | |
CN107275229B (zh) | 半导体封装及其制造方法 | |
TWI806816B (zh) | 半導體裝置和其製造之方法 | |
US10141270B2 (en) | Semiconductor device and method of manufacturing thereof |