TWI805203B

TWI805203B - Three-dimensional memory device and method of forming the same

Info

Publication number: TWI805203B
Application number: TW111103239A
Authority: TW
Inventors: 曾碧山
Original assignee: 旺宏電子股份有限公司
Priority date: 2022-01-26
Filing date: 2022-01-26
Publication date: 2023-06-11
Also published as: TW202332018A

Abstract

Provided is a three-dimensional (3D) memory device including: a substrate, a stack structure, and a plurality of barrier structures. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of gate layers stacked alternately. The plurality of barrier structures respectively wrap surfaces of the plurality of gate layers. Each barrier structure includes a first barrier layer and a second barrier layer. The first barrier layer continuously covers a top surface, a bottom surface and a first sidewall of a corresponding gate layer. The second barrier layer covers a second sidewall of the corresponding gate layer opposite to the first sidewall, and connects the first barrier layer. The second barrier layer has a thickness greater than a thickness of the first barrier layer. A method of forming a 3D memory device is also provided.

Description

三維記憶體元件及其形成方法Three-dimensional memory element and method of forming the same

本發明是有關於一種半導體元件及其形成方法，且特別是有關於一種三維記憶體元件及其形成方法。The present invention relates to a semiconductor element and its forming method, and in particular to a three-dimensional memory element and its forming method.

非揮發性記憶體（例如快閃記憶體）由於具有使存入的資料在斷電後也不會消失的優點，因此成為個人電腦和其他電子設備所廣泛採用的一種記憶體。Non-volatile memory (such as flash memory) has the advantage that the stored data will not disappear after power failure, so it has become a type of memory widely used in personal computers and other electronic devices.

目前業界較常使用的三維快閃記憶體包括反或式（NOR）快閃記憶體以及反及式（NAND）快閃記憶體。此外，另一種三維快閃記憶體為及式（AND）快閃記憶體，其可應用在多維度的快閃記憶體陣列中而具有高積集度與高面積利用率，且具有操作速度快的優點。因此，三維快閃記憶體的發展已逐漸成為目前的趨勢。Currently, the 3D flash memory commonly used in the industry includes a negative-or (NOR) flash memory and a negative-and-type (NAND) flash memory. In addition, another type of 3D flash memory is AND flash memory, which can be applied in a multi-dimensional flash memory array and has high integration and high area utilization, and has fast operation speed. The advantages. Therefore, the development of 3D flash memory has gradually become the current trend.

本發明提供一種三維記憶體元件，其利用阻障結構完全包圍閘極層的所有表面，以防止氟逸氣問題發生，進而提升元件的可靠度。The invention provides a three-dimensional memory device, which completely surrounds all surfaces of the gate layer with a barrier structure to prevent fluorine outgassing, thereby improving the reliability of the device.

本發明提供一種三維記憶體元件包括：基底、堆疊結構以及多個阻障結構。堆疊結構配置在基底上。堆疊結構包括交替堆疊的多個介電層與多個閘極層。多個阻障結構分別包圍多個閘極層的表面。每一個阻障結構包括：第一阻障層與第二阻障層。第一阻障層連續覆蓋在相應的閘極層的頂面、底面以及第一側壁上。第二阻障層覆蓋在相應的閘極層的相對於第一側壁的第二側壁上，且與第一阻障層連接。第二阻障層的厚度大於第一阻障層的厚度。The invention provides a three-dimensional memory element including: a base, a stack structure and a plurality of barrier structures. The stack structure is configured on the base. The stack structure includes a plurality of dielectric layers and a plurality of gate layers stacked alternately. The multiple barrier structures respectively surround the surfaces of the multiple gate layers. Each barrier structure includes: a first barrier layer and a second barrier layer. The first barrier layer continuously covers the top surface, the bottom surface and the first sidewall of the corresponding gate layer. The second barrier layer covers the second sidewall of the corresponding gate layer opposite to the first sidewall, and is connected with the first barrier layer. The thickness of the second barrier layer is greater than the thickness of the first barrier layer.

在本發明的一實施例中，上述的基底包括陣列區，且陣列區包括通道柱區與狹縫區。In an embodiment of the present invention, the above-mentioned substrate includes an array area, and the array area includes a channel column area and a slit area.

在本發明的一實施例中，上述的三維記憶體元件，更包括：多個垂直通道柱，貫穿堆疊結構且配置在通道柱區上且與第一側壁相鄰；以及狹縫填充結構，貫穿堆疊結構且配置在狹縫區上，且與第二側壁相鄰，其中第二阻障層物理分隔狹縫填充結構與相應的閘極層。In an embodiment of the present invention, the above-mentioned three-dimensional memory device further includes: a plurality of vertical channel pillars penetrating through the stack structure and disposed on the channel pillar area and adjacent to the first sidewall; and a slit filling structure penetrating through The stacked structure is disposed on the slit area and adjacent to the second sidewall, wherein the second barrier layer physically separates the slit filling structure from the corresponding gate layer.

在本發明的一實施例中，上述的狹縫填充結構包括：氧化物層，覆蓋在堆疊結構的側壁上；導體層，配置在氧化物層上；以及第三阻障層，配置在氧化物層與導體層之間。In an embodiment of the present invention, the above-mentioned slot-filling structure includes: an oxide layer covering the sidewall of the stack structure; a conductor layer disposed on the oxide layer; and a third barrier layer disposed on the oxide layer. layer and conductor layer.

在本發明的一實施例中，上述的多個閘極層的寬度小於多個介電層的寬度，第二側壁與相鄰的介電層共同形成凹槽，氧化物層部分延伸至凹槽中並與第二阻障層相連接。In an embodiment of the present invention, the width of the plurality of gate layers is smaller than the width of the plurality of dielectric layers, the second sidewall and the adjacent dielectric layer jointly form a groove, and the oxide layer partially extends to the groove and connected to the second barrier layer.

在本發明的一實施例中，上述的三維記憶體元件，更包括：緩衝層，共形地延伸在多個介電層與多個閘極層之間以及多個垂直通道柱與多個閘極層之間。In an embodiment of the present invention, the above-mentioned three-dimensional memory device further includes: a buffer layer extending conformally between the plurality of dielectric layers and the plurality of gate layers, and the plurality of vertical channel pillars and the plurality of gate layers between polar layers.

在本發明的一實施例中，上述的第二阻障層覆蓋第二側壁與相鄰的緩衝層的一部分，第二阻障層與緩衝層共同形成凹口，凹口具有第一垂直深度與第二垂直深度，第一垂直深度大於第二垂直深度。In an embodiment of the present invention, the above-mentioned second barrier layer covers a part of the second sidewall and the adjacent buffer layer, the second barrier layer and the buffer layer jointly form a notch, and the notch has a first vertical depth and The second vertical depth, the first vertical depth is greater than the second vertical depth.

在本發明的一實施例中，上述的第一阻障層配置在緩衝層與相應的閘極層之間。In an embodiment of the present invention, the above-mentioned first barrier layer is disposed between the buffer layer and the corresponding gate layer.

在本發明的一實施例中，每一個阻障結構完全包圍相應的閘極層的所有表面。In an embodiment of the invention, each barrier structure completely surrounds all surfaces of the corresponding gate layer.

在本發明的一實施例中，上述的三維記憶體元件包括三維及式（AND）快閃記憶體、三維反及式（NAND）快閃記憶體、三維反或式（NOR）快閃記憶體或其組合。In an embodiment of the present invention, the above-mentioned three-dimensional memory element includes three-dimensional AND (AND) flash memory, three-dimensional inverse and (NAND) flash memory, three-dimensional inverse-OR (NOR) flash memory or a combination thereof.

本發明提供一種三維記憶體元件的形成方法，包括：提供具有第一區與第二區的基底；在基底上形成包括有交替堆疊的多個介電層與多個犧牲層的堆疊結構；在第二區的堆疊結構中形成狹縫；通過狹縫進行第一蝕刻製程，移除多個犧牲層以在多個介電層之間形成多個間隙；在多個間隙中形成多個閘極層與多個第一阻障層，其中多個第一阻障層環繞多個閘極層的部分表面且暴露出多個閘極層的側壁；以及形成多個第二阻障層，以覆蓋多個閘極層的側壁，其中多個第二阻障層分別與多個第一阻障層連接以形成多個阻障結構。The present invention provides a method for forming a three-dimensional memory element, comprising: providing a substrate having a first region and a second region; forming a stacked structure including a plurality of dielectric layers and a plurality of sacrificial layers alternately stacked on the substrate; Forming slits in the stacked structure of the second region; performing a first etching process through the slits, removing a plurality of sacrificial layers to form a plurality of gaps between a plurality of dielectric layers; forming a plurality of gates in the plurality of gaps layer and a plurality of first barrier layers, wherein the plurality of first barrier layers surround partial surfaces of the plurality of gate layers and expose sidewalls of the plurality of gate layers; and form a plurality of second barrier layers to cover The side walls of the plurality of gate layers, wherein the plurality of second barrier layers are respectively connected with the plurality of first barrier layers to form a plurality of barrier structures.

在本發明的一實施例中，在形成多個第二阻障層之後，上述的方法更包括：在狹縫中形成狹縫填充結構。In an embodiment of the present invention, after forming the plurality of second barrier layers, the above method further includes: forming a slot-filling structure in the slot.

在本發明的一實施例中，在形成狹縫之前，上述的方法更包括：在第一區的堆疊結構中形成多個垂直通道柱。In an embodiment of the present invention, before forming the slit, the above method further includes: forming a plurality of vertical channel pillars in the stacked structure in the first region.

在本發明的一實施例中，在多個間隙中形成多個閘極層與多個第一阻障層的步驟包括：形成第一阻障材料層與導體材料層以填入多個間隙中；以及進行第二蝕刻製程，移除多個介電層的側壁上的第一阻障材料層與導體材料層，以在多個間隙中形成多個閘極層與多個第一阻障層。In an embodiment of the present invention, the step of forming a plurality of gate layers and a plurality of first barrier layers in the plurality of gaps includes: forming a first barrier material layer and a conductive material layer to fill the plurality of gaps and performing a second etching process to remove the first barrier material layer and the conductive material layer on the sidewalls of the plurality of dielectric layers, so as to form a plurality of gate layers and a plurality of first barrier layers in the plurality of gaps .

在本發明的一實施例中，上述的第一阻障材料層的材料可包括鈦（Ti）、氮化鈦（TiN）、鉭（Ta）、氮化鉭（TaN）或其組合。In an embodiment of the present invention, the material of the above-mentioned first barrier material layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof.

在本發明的一實施例中，在進行上述的第二蝕刻製程之後，多個閘極層的側壁內凹於多個介電層的側壁，以形成多個凹槽。In an embodiment of the present invention, after the above-mentioned second etching process is performed, the sidewalls of the plurality of gate layers are recessed into the sidewalls of the plurality of dielectric layers to form a plurality of grooves.

在本發明的一實施例中，形成多個第二阻障層的步驟包括：形成第二阻障材料層，以共形覆蓋多個介電層的側壁與多個凹槽的表面；以及進行第三蝕刻製程，移除多個介電層的側壁上的第二阻障材料層，以在多個凹槽中形成多個第二阻障層，其中每一個第二阻障層形成為C字型結構。In an embodiment of the present invention, the step of forming a plurality of second barrier layers includes: forming a second barrier material layer to conformally cover the sidewalls of the plurality of dielectric layers and the surfaces of the plurality of grooves; and performing A third etching process, removing the second barrier material layer on the sidewalls of the plurality of dielectric layers to form a plurality of second barrier layers in the plurality of grooves, wherein each second barrier layer is formed as C font structure.

在本發明的一實施例中，上述的第一阻障材料層與第二阻障材料層具有相同材料。In an embodiment of the present invention, the above-mentioned first barrier material layer and the second barrier material layer have the same material.

基於上述，本發明利用額外的阻障層覆蓋閘極層的側壁，並與環繞閘極層的阻障層連接，進而形成完全包圍閘極層的所有表面的阻障結構。因此，本發明的阻障結構可有效地防止氟逸氣問題發生，進而提升三維記憶體元件的可靠度。此外，本發明之阻障結構的形成步驟相容於現行的三維記憶體元件的製程中，進而可應用在各種三維記憶體元件中。Based on the above, the present invention utilizes an additional barrier layer to cover the sidewall of the gate layer, and is connected to the barrier layer surrounding the gate layer to form a barrier structure completely surrounding all surfaces of the gate layer. Therefore, the barrier structure of the present invention can effectively prevent the fluorine outgassing problem, thereby improving the reliability of the three-dimensional memory device. In addition, the forming steps of the barrier structure of the present invention are compatible with the current manufacturing process of three-dimensional memory devices, and can be applied in various three-dimensional memory devices.

參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。圖式中的層與區域的厚度會為了清楚起見而放大。相同或相似之元件標號表示相同或相似之元件，以下段落將不再一一贅述。The present invention will be described more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. The same or similar component numbers represent the same or similar components, and the following paragraphs will not repeat them one by one.

圖1A是依照本發明一實施例的一種三維記憶體元件的剖面示意圖。圖1B是圖1A的平面示意圖。FIG. 1A is a schematic cross-sectional view of a three-dimensional memory device according to an embodiment of the invention. FIG. 1B is a schematic plan view of FIG. 1A .

請參照圖1A與圖1B，本發明實施例的三維記憶體元件可包括基底100、停止層102、堆疊結構110、頂蓋層116以及垂直通道柱130。在一些實施例中，基底100例如為半導體基底、半導體化合物基底或是絕緣層上有半導體基底（Semiconductor Over Insulator, SOI）。半導體例如是IVA族的原子，例如矽或鍺。半導體化合物例如是IVA族的原子所形成之半導體化合物，例如是碳化矽或是矽化鍺，或是IIIA族原子與VA族原子所形成之半導體化合物，例如是砷化鎵。在本實施例中，基底100可為介電基底。介電基底可包括形成在矽基板上的介電層，例如是氧化矽層。也就是說，基底100的下方可具有周邊電路。另外，基底100可包括陣列區R，陣列區R可包括第一區R1與第二區R2。在一實施例中，第一區R1可以是通道柱區，而第二區R2可以是狹縫（slit）區。也就是說，鄰近通道柱區R1處可具有一或多個狹縫（slit），如圖1B所示。Referring to FIG. 1A and FIG. 1B , the three-dimensional memory device of the embodiment of the present invention may include a substrate 100 , a stopper layer 102 , a stack structure 110 , a capping layer 116 and vertical channel pillars 130 . In some embodiments, the substrate 100 is, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor over insulator (SOI) substrate. Semiconductors are, for example, atoms of group IVA, such as silicon or germanium. The semiconductor compound is, for example, a semiconductor compound formed of atoms of group IVA, such as silicon carbide or germanium silicide, or a semiconductor compound formed of atoms of group IIIA and group VA, such as gallium arsenide. In this embodiment, the substrate 100 may be a dielectric substrate. The dielectric substrate may include a dielectric layer, such as a silicon oxide layer, formed on a silicon substrate. That is to say, there may be peripheral circuits under the substrate 100 . In addition, the substrate 100 may include an array region R, and the array region R may include a first region R1 and a second region R2. In an embodiment, the first region R1 may be a channel column region, and the second region R2 may be a slit region. That is, there may be one or more slits adjacent to the channel column region R1 , as shown in FIG. 1B .

停止層102可形成在基底100上。在一實施例中，停止層102的材料包括導體材料，例如是多晶矽、III-V族化合物半導體或其組合。當該三維記憶體元件為三維反及式（NAND）快閃記憶體的實施例時，此停止層102可用以當作源極線（source line）。當該三維記憶體元件為三維反或式（NOR）快閃記憶體的實施例時，此停止層102可用以當作虛擬字元線（dummy word line）。雖然圖1A所繪示的停止層102為單層結構，但本發明不以此為限。在替代實施例中，停止層102亦可以是多層結構。此多層結構可包括交替堆疊的多個介電層（例如氧化矽層）與多個導體層（例如多晶矽層）。The stop layer 102 may be formed on the substrate 100 . In one embodiment, the material of the stop layer 102 includes a conductive material, such as polysilicon, III-V compound semiconductor or a combination thereof. When the three-dimensional memory device is an embodiment of a three-dimensional NAND flash memory, the stop layer 102 can be used as a source line. When the 3D memory device is an embodiment of 3D NOR flash memory, the stop layer 102 can be used as a dummy word line. Although the stop layer 102 shown in FIG. 1A is a single-layer structure, the present invention is not limited thereto. In alternative embodiments, the stop layer 102 may also be a multi-layer structure. The multi-layer structure may include a plurality of dielectric layers (such as silicon oxide layers) and a plurality of conductive layers (such as polysilicon layers) stacked alternately.

堆疊結構110可形成在停止層102上，以使停止層102配置在基底100與堆疊結構110之間。在一實施例中，堆疊結構110可包括交替堆疊的多個介電層112與多個犧牲層114。在一實施例中，介電層112與犧牲層114可以是不同材料，或是具有不同蝕刻速率的材料。舉例來說，介電層112可以是氧化矽層；犧牲層114可以是氮化矽層、多晶矽層或金屬鎢層。介電層112與犧牲層114的數量可以依據需求來調整，本發明不以此為限。The stack structure 110 can be formed on the stop layer 102 such that the stop layer 102 is disposed between the substrate 100 and the stack structure 110 . In one embodiment, the stack structure 110 may include a plurality of dielectric layers 112 and a plurality of sacrificial layers 114 stacked alternately. In one embodiment, the dielectric layer 112 and the sacrificial layer 114 may be made of different materials or have different etch rates. For example, the dielectric layer 112 can be a silicon oxide layer; the sacrificial layer 114 can be a silicon nitride layer, a polysilicon layer or a metal tungsten layer. The quantities of the dielectric layer 112 and the sacrificial layer 114 can be adjusted according to requirements, and the present invention is not limited thereto.

頂蓋層116可形成在堆疊結構110上，以使堆疊結構110配置在停止層102與頂蓋層116之間。在一實施例中，頂蓋層116的材料可包括介電材料，例如是氧化矽。The cap layer 116 can be formed on the stack structure 110 such that the stack structure 110 is disposed between the stop layer 102 and the cap layer 116 . In an embodiment, the material of the cap layer 116 may include a dielectric material, such as silicon oxide.

垂直通道柱130可形成在第一區R1中的堆疊結構110與停止層102中。如圖1A所示，垂直通道柱130可貫穿堆疊結構110、停止層102且部分延伸至基底100中。值得注意的是，在形成可容納垂直通道柱130的開口115時，停止層102不僅可用以當作蝕刻停止層，還可用以防止在電漿蝕刻時所產生的電弧效應（arcing effect），進而改善元件的可靠度。在此實施例中，停止層102可視為放電層（discharging layer），其通常會接地至矽基板，以降低上述電漿蝕刻所累積的電荷，進而避免元件的損壞。因此，在進行高深寬比的蝕刻製程時，通常會將停止層102接地至矽基板，以避免電弧放電發生。The vertical channel pillar 130 may be formed in the stack structure 110 and the stop layer 102 in the first region R1. As shown in FIG. 1A , the vertical channel pillar 130 may penetrate through the stack structure 110 , the stop layer 102 and partially extend into the substrate 100 . It should be noted that when forming the opening 115 for accommodating the vertical channel column 130, the stop layer 102 can not only be used as an etch stop layer, but also can be used to prevent arcing effect (arcing effect) generated during plasma etching, and further Improve component reliability. In this embodiment, the stop layer 102 can be regarded as a discharging layer, which is usually grounded to the silicon substrate, so as to reduce the charge accumulated by the above-mentioned plasma etching, thereby avoiding damage to the device. Therefore, when performing an etching process with a high aspect ratio, the stop layer 102 is usually grounded to the silicon substrate to avoid arc discharge.

基本上，根據三維記憶體元件的不同形式，垂直通道柱130可具有不同態樣，詳細說明如下所述。Basically, according to different forms of the three-dimensional memory device, the vertical channel pillars 130 may have different shapes, which will be described in detail as follows.

圖2A、圖3A以及圖4A繪示出依照本發明各種實施例的垂直通道柱的剖面示意圖。圖2B、圖3B以及圖4B分別是圖2A、圖3A以及圖4A的平面示意圖。2A , 3A and 4A illustrate schematic cross-sectional views of vertical channel columns according to various embodiments of the present invention. FIG. 2B , FIG. 3B and FIG. 4B are schematic plan views of FIG. 2A , FIG. 3A and FIG. 4A , respectively.

請參照圖2A與圖2B，當該三維記憶體元件為三維及式（AND）快閃記憶體，垂直通道柱130A可包括電荷儲存結構132、通道層134、介電材料136、第一源極/汲極柱133以及第二源極/汲極柱135。如圖2A所示，第一源極/汲極柱133與第二源極/汲極柱135可貫穿頂蓋層116、堆疊結構110以及停止層102，並部分延伸至基底100中。在一實施例中，第一源極/汲極柱133與第二源極/汲極柱135可具有相同的導體材料，例如是N型摻雜（N+）多晶矽材料。介電材料136可配置在第一源極/汲極柱133與第二源極/汲極柱135之間，以分隔第一源極/汲極柱133與第二源極/汲極柱135。另外，如圖2B所示，通道層134可橫向環繞介電材料136、第一源極/汲極柱133以及第二源極/汲極柱135。第一源極/汲極柱133與第二源極/汲極柱135分別物理接觸通道層134的一部分。電荷儲存結構132可橫向環繞通道層134。在一實施例中，電荷儲存結構132可以是由穿隧層、電荷儲存層以及阻擋層所構成的複合層。穿隧層、電荷儲存層以及阻擋層可分別被視為氧化物/氮化物/氧化物（ONO）。在另一實施例中，穿隧層可以是氧化物/氮化物/氧化物（ONO）的複合層或是其他合適的材料。在替代實施例中，電荷儲存層可以是氧化物/氮化物/氧化物（ONO）的複合層或是其他合適的材料。在其他實施例中，阻擋層可以是氧化物/氮化物/氧化物（ONO）的複合層或是其他合適的材料。通道層134可包括摻雜多晶矽層或是未摻雜多晶矽層。介電材料136可包括氧化矽、氮化矽、氮氧化矽或其組合。Please refer to FIG. 2A and FIG. 2B. When the three-dimensional memory device is a three-dimensional AND (AND) flash memory, the vertical channel column 130A may include a charge storage structure 132, a channel layer 134, a dielectric material 136, and a first source. /drain post 133 and a second source/drain post 135 . As shown in FIG. 2A , the first source/drain column 133 and the second source/drain column 135 can penetrate the cap layer 116 , the stack structure 110 and the stop layer 102 , and partially extend into the substrate 100 . In one embodiment, the first source/drain column 133 and the second source/drain column 135 may have the same conductor material, such as N-type doped (N+) polysilicon material. A dielectric material 136 may be disposed between the first source/drain column 133 and the second source/drain column 135 to separate the first source/drain column 133 from the second source/drain column 135 . In addition, as shown in FIG. 2B , the channel layer 134 may laterally surround the dielectric material 136 , the first source/drain pillar 133 and the second source/drain pillar 135 . The first source/drain stud 133 and the second source/drain stud 135 physically contact a part of the channel layer 134 respectively. The charge storage structure 132 may laterally surround the channel layer 134 . In an embodiment, the charge storage structure 132 may be a composite layer composed of a tunneling layer, a charge storage layer and a blocking layer. The tunneling layer, charge storage layer and blocking layer can be regarded as oxide/nitride/oxide (ONO), respectively. In another embodiment, the tunneling layer may be a composite layer of oxide/nitride/oxide (ONO) or other suitable materials. In alternative embodiments, the charge storage layer may be a composite layer of oxide/nitride/oxide (ONO) or other suitable materials. In other embodiments, the barrier layer may be a composite layer of oxide/nitride/oxide (ONO) or other suitable materials. The channel layer 134 may include a doped polysilicon layer or an undoped polysilicon layer. The dielectric material 136 may include silicon oxide, silicon nitride, silicon oxynitride or combinations thereof.

請參照圖3A與圖3B，當該三維記憶體元件為第一類型的三維反及式（NAND）快閃記憶體，垂直通道柱130B可包括電荷儲存結構132、通道結構234以及介電柱236。如圖3A所示，介電柱236可貫穿頂蓋層116、堆疊結構110以及停止層102。通道結構234可包括襯層234A與插塞234B。襯層234A可覆蓋介電柱236的側壁與底面，而插塞234B可密封介電柱236的頂面。在此情況下，通道結構234可完整包覆介電柱236的所有表面。電荷儲存結構132可配置在通道結構234與頂蓋層116之間，以及通道結構234與堆疊結構110之間。通道結構234與停止層102之間的電荷儲存結構132則是被移除，以使通道結構234直接接觸停止層102。從平面圖3B的角度來看，電荷儲存結構132可橫向環繞通道結構234與介電柱236。電荷儲存結構132、通道結構234以及介電柱236的材料分別與電荷儲存結構132、通道層134以及介電材料136的材料相同，且已在上述段落詳述過，於此便不再贅述。Referring to FIGS. 3A and 3B , when the 3D memory device is a first type 3D NAND flash memory, the vertical channel pillar 130B may include a charge storage structure 132 , a channel structure 234 and a dielectric pillar 236 . As shown in FIG. 3A , the dielectric pillar 236 may penetrate through the cap layer 116 , the stack structure 110 and the stop layer 102 . The channel structure 234 may include a liner 234A and a plug 234B. The liner 234A can cover the sidewalls and the bottom surface of the dielectric pillar 236 , and the plug 234B can seal the top surface of the dielectric pillar 236 . In this case, the channel structure 234 can completely cover all surfaces of the dielectric pillar 236 . The charge storage structure 132 can be disposed between the channel structure 234 and the cap layer 116 , and between the channel structure 234 and the stack structure 110 . The charge storage structure 132 between the channel structure 234 and the stop layer 102 is removed so that the channel structure 234 directly contacts the stop layer 102 . From the perspective of the plan view of FIG. 3B , the charge storage structure 132 may laterally surround the channel structure 234 and the dielectric pillar 236 . The materials of the charge storage structure 132 , the channel structure 234 and the dielectric pillar 236 are the same as those of the charge storage structure 132 , the channel layer 134 and the dielectric material 136 respectively, and have been described in detail in the above paragraphs, and will not be repeated here.

請參照圖4A與圖4B，當該三維記憶體元件為第二類型的三維反及式（NAND）快閃記憶體，垂直通道柱130C可包括電荷儲存結構132以及通道柱334。如圖4A所示，通道柱334可貫穿頂蓋層116、堆疊結構110以及停止層102。電荷儲存結構132可配置在通道柱334與頂蓋層116之間，以及通道柱334與堆疊結構110之間。通道柱334與停止層102之間的電荷儲存結構132則是被移除，以使通道柱334直接接觸停止層102。從平面圖4B的角度來看，電荷儲存結構132可橫向環繞通道柱334。電荷儲存結構132與通道柱334的材料分別與電荷儲存結構132與通道層134的材料相同，且已在上述段落詳述過，於此便不再贅述。Referring to FIGS. 4A and 4B , when the 3D memory device is a second type of 3D NAND flash memory, the vertical channel column 130C may include a charge storage structure 132 and a channel column 334 . As shown in FIG. 4A , the channel post 334 can penetrate through the cap layer 116 , the stack structure 110 and the stop layer 102 . The charge storage structure 132 can be disposed between the channel pillar 334 and the cap layer 116 , and between the channel pillar 334 and the stack structure 110 . The charge storage structure 132 between the channel pillar 334 and the stop layer 102 is removed so that the channel pillar 334 directly contacts the stop layer 102 . From the perspective of the plan view of FIG. 4B , the charge storage structure 132 may laterally surround the channel pillar 334 . The materials of the charge storage structure 132 and the channel pillar 334 are the same as those of the charge storage structure 132 and the channel layer 134 respectively, and have been described in detail in the above paragraphs, and will not be repeated here.

請回頭參照圖1A，在形成垂直通道柱130之後，可進行閘極替換製程，以將堆疊結構110中的犧牲層114替換成閘極層154，如圖5至圖11所示，其中圖5至圖11為圖1A的區域10的放大圖。具體來說，首先，如圖1A所示，在第二區R2的堆疊結構110中形成狹縫15。狹縫15貫穿頂蓋層116與堆疊結構110，以暴露出停止層102的一部分。雖然圖1A所繪示的狹縫15的底面與停止層102的頂面齊平，但本發明不以此為限。在其他實施例中，狹縫15的底面亦可低於停止層102的頂面。另外，如平面圖1B所示，狹縫15可沿著水平方向延伸，且配置在相鄰兩個第一區R1的垂直通道柱130之間。也就是說，狹縫15可以垂直於圖1A的紙面方向延伸，以形成溝渠。Referring back to FIG. 1A, after forming the vertical channel column 130, a gate replacement process can be performed to replace the sacrificial layer 114 in the stack structure 110 with a gate layer 154, as shown in FIGS. FIG. 11 is an enlarged view of the region 10 in FIG. 1A . Specifically, first, as shown in FIG. 1A , a slit 15 is formed in the stacked structure 110 of the second region R2. The slit 15 penetrates through the top cover layer 116 and the stack structure 110 to expose a part of the stop layer 102 . Although the bottom surface of the slit 15 shown in FIG. 1A is flush with the top surface of the stop layer 102 , the invention is not limited thereto. In other embodiments, the bottom surface of the slit 15 may also be lower than the top surface of the stop layer 102 . In addition, as shown in the plan view of FIG. 1B , the slit 15 may extend along the horizontal direction and be disposed between the vertical channel pillars 130 of two adjacent first regions R1 . That is, the slit 15 may extend perpendicular to the paper direction of FIG. 1A to form a ditch.

接著，請參照圖5，進行第一蝕刻製程，移除犧牲層114，以在介電層112之間形成多個間隙14。間隙14橫向暴露出垂直通道柱130。也就是說，間隙14是由介電層112與垂直通道柱130所定義的。在一實施例中，上述的第一蝕刻製程可以是濕式蝕刻製程。舉例來說，當犧牲層114為氮化矽時，所述第一蝕刻製程可以是使用含有磷酸的蝕刻液，並將所述蝕刻液倒入狹縫15中，從而移除犧牲層114。由於所述蝕刻液對於犧牲層114具有高蝕刻選擇性，因此，犧牲層114可被完全移除，而介電層112未被移除或僅少量移除。Next, referring to FIG. 5 , a first etching process is performed to remove the sacrificial layer 114 to form a plurality of gaps 14 between the dielectric layers 112 . Gap 14 laterally exposes vertical channel posts 130 . That is, the gap 14 is defined by the dielectric layer 112 and the vertical via pillars 130 . In an embodiment, the above-mentioned first etching process may be a wet etching process. For example, when the sacrificial layer 114 is silicon nitride, the first etching process may be to use an etchant containing phosphoric acid and pour the etchant into the slit 15 to remove the sacrificial layer 114 . Since the etchant has a high etching selectivity for the sacrificial layer 114 , the sacrificial layer 114 can be completely removed while the dielectric layer 112 is not removed or only slightly removed.

請參照圖5與圖6，依序形成緩衝層120、阻障材料層122以及導體材料層124。具體來說，緩衝層120與阻障材料層122可共形地覆蓋圖5所示結構的表面並填入間隙14中；而導體材料層124則可填滿間隙14並橫向延伸至狹縫15中。在一實施例中，緩衝層120的材料包括介電常數大於7的高介電常數材料，例如氧化鋁（Al ₂O ₃）、氧化鉿（HfO ₂）、氧化鑭（La ₂O ₅）、過渡金屬氧化物、鑭系元素氧化物或其組合。阻障材料層122的材料可包括鈦（Ti）、氮化鈦（TiN）、鉭（Ta）、氮化鉭（TaN）或其組合。導體材料層124的材料可包括多晶矽、非晶矽、鎢（W）、鈷（Co）、鋁（Al）、矽化鎢（WSi _x）或矽化鈷（CoSi _x）。 Referring to FIG. 5 and FIG. 6 , the buffer layer 120 , the barrier material layer 122 and the conductor material layer 124 are sequentially formed. Specifically, the buffer layer 120 and the barrier material layer 122 can conformally cover the surface of the structure shown in FIG. middle. In one embodiment, the material of the buffer layer 120 includes a high dielectric constant material with a dielectric constant greater than 7, such as aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), lanthanum oxide (La ₂ O ₅ ), transition metal oxides, lanthanide oxides, or combinations thereof. The material of the barrier material layer 122 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof. The material of the conductive material layer 124 may include polysilicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide ( _WSix ) or cobalt silicide ( _CoSix ).

請參照圖6與圖7，進行第二蝕刻製程，移除介電層112的側壁上的阻障材料層122與導體材料層124，以在間隙14中形成閘極層154與環繞閘極層154的阻障層152。值得注意的是，為了使介電層112的側壁上的導體材料層124被完全移除以形成彼此分隔的閘極層154，因此，在進行所述第二蝕刻製程時會移除間隙14中的部分導體材料層124。在此情況下，如圖7所示，所形成的閘極層154的側壁會內凹於介電層112的側壁，以形成多個凹槽24。在一實施例中，上述的第二蝕刻製程可以是濕式蝕刻製程、乾式蝕刻製程或其組合。Referring to FIG. 6 and FIG. 7, a second etching process is performed to remove the barrier material layer 122 and the conductive material layer 124 on the sidewall of the dielectric layer 112 to form the gate layer 154 and the surrounding gate layer in the gap 14. 154 of the barrier layer 152 . It should be noted that, in order to completely remove the conductive material layer 124 on the sidewall of the dielectric layer 112 to form the gate layer 154 separated from each other, therefore, the gap 14 will be removed during the second etching process. part of the conductive material layer 124 . In this case, as shown in FIG. 7 , the formed sidewalls of the gate layer 154 are recessed from the sidewalls of the dielectric layer 112 to form a plurality of grooves 24 . In an embodiment, the above-mentioned second etching process may be a wet etching process, a dry etching process or a combination thereof.

請參照圖8，形成阻障材料層142，以共形覆蓋緩衝層120的表面、阻障層152的表面以及閘極層154的表面（亦即凹槽24的表面）。在一實施例中，阻障材料層142的材料可包括鈦（Ti）、氮化鈦（TiN）、鉭（Ta）、氮化鉭（TaN）或其組合。Referring to FIG. 8 , the barrier material layer 142 is formed to conformally cover the surface of the buffer layer 120 , the surface of the barrier layer 152 and the surface of the gate layer 154 (ie, the surface of the groove 24 ). In an embodiment, the material of the barrier material layer 142 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof.

請參照圖8與圖9，進行第三蝕刻製程，移除介電層112的側壁上的阻障材料層142，以在凹槽24中形成阻障層162。在此情況下，如圖9所示，阻障層152與阻障層162彼此相連以形成阻障結構160，而此阻障結構160可完全包圍閘極層154的所有表面。在一些實施例中，阻障層152、162可具有相同材料，例如TiN。在替代實施例中，阻障層152、162可具有不同材料，舉例來說，阻障層152為TiN層，而阻障層162為TaN層。Referring to FIGS. 8 and 9 , a third etching process is performed to remove the barrier material layer 142 on the sidewall of the dielectric layer 112 to form a barrier layer 162 in the groove 24 . In this case, as shown in FIG. 9 , the barrier layer 152 and the barrier layer 162 are connected to each other to form a barrier structure 160 , and the barrier structure 160 can completely surround all surfaces of the gate layer 154 . In some embodiments, barrier layers 152, 162 may be of the same material, such as TiN. In alternative embodiments, the barrier layers 152, 162 may be of different materials, for example, the barrier layer 152 is a TiN layer and the barrier layer 162 is a TaN layer.

在一實施例中，阻障層152的厚度T1可小於或等於阻障層162的厚度T2。阻障層152的厚度T1可介於30 Å至100 Å之間，而阻障層162的厚度T2可介於50 Å至150 Å之間。值得注意的是，較薄的厚度T1可使得阻障層152易於填入間隙14中，且不會影響後續閘極層154的形成。較厚的厚度T2則可使阻障層162完整地覆蓋閘極層154的側壁，以有效地防止氟逸氣問題（Fluorine outgassing issue）發生。也就是說，倘若沒有將阻障層162形成在閘極層154的側壁上，在進行後續熱處理製程時，閘極層154中殘留的氟會逸出且破壞後續沉積在閘極層154的側壁上的的氧化物層170（如圖10所示）並產生空洞（void），進而導致閘極層154與狹縫15中的導體層174（如圖11所示）電性連接（橋接）。因此，本發明之阻障層162可有效地防止氟逸氣問題，進而提升元件的可靠度。In one embodiment, the thickness T1 of the barrier layer 152 may be less than or equal to the thickness T2 of the barrier layer 162 . The thickness T1 of the barrier layer 152 may be between 30 Å and 100 Å, and the thickness T2 of the barrier layer 162 may be between 50 Å and 150 Å. It is worth noting that the thinner thickness T1 can make the barrier layer 152 easy to fill in the gap 14 without affecting the subsequent formation of the gate layer 154 . The thicker thickness T2 can make the barrier layer 162 completely cover the sidewall of the gate layer 154 to effectively prevent the occurrence of fluorine outgassing issue. That is to say, if the barrier layer 162 is not formed on the sidewall of the gate layer 154 , the residual fluorine in the gate layer 154 will escape and damage the sidewall of the gate layer 154 subsequently deposited during the subsequent heat treatment process. The oxide layer 170 (as shown in FIG. 10 ) on the upper surface creates a void, which leads to the electrical connection (bridge) between the gate layer 154 and the conductor layer 174 (as shown in FIG. 11 ) in the slit 15 . Therefore, the barrier layer 162 of the present invention can effectively prevent the problem of fluorine outgassing, thereby improving the reliability of the device.

在一實施例中，為了使介電層112的側壁上的阻障材料層142被完全移除以形成彼此分隔的阻障層162，因此，在進行所述第三蝕刻製程時會移除凹槽24中的部分阻障材料層142。在此情況下，如圖9所示，阻障層162可形成C字型結構。具體來說，阻障層162覆蓋閘極層154的側壁（即，第二側壁）與相鄰的緩衝層120的一部分，使得阻障層162與緩衝層120共同形成凹口26。如圖9所示，凹口26具有第一垂直深度V1與第二垂直深度V2。在本實施例中，第一垂直深度V1大於第二垂直深度V2。第一垂直深度V1可介於15 nm至25 nm之間，而第二垂直深度V2可介於10 nm至20 nm之間。為了確保介電層112的側壁上沒有阻障材料的殘留，會進一步移除閘極層154的側壁上的阻障材料，以避免相鄰閘極層154之間的橋接（亦即字元線橋接）。因此，當第二垂直深度V2介於10 nm至20 nm之間時，便可確保介電層112的側壁上沒有阻障材料的殘留。另一方面，在本實施例中，阻障層162的外側壁與緩衝層120的側壁之間的寬度W1可介於10 nm至20 nm之間，而阻障層162的內側壁與緩衝層120的側壁之間的寬度W2可介於20 nm至30 nm之間。但本發明不以此為限，在其他實施例中，阻障層162亦可形成直線型結構。In one embodiment, in order to completely remove the barrier material layer 142 on the sidewall of the dielectric layer 112 to form the barrier layer 162 separated from each other, the recesses are removed during the third etching process. A portion of barrier material layer 142 in trench 24 . In this case, as shown in FIG. 9 , the barrier layer 162 may form a C-shaped structure. Specifically, the barrier layer 162 covers the sidewall (ie, the second sidewall) of the gate layer 154 and a part of the adjacent buffer layer 120 , so that the barrier layer 162 and the buffer layer 120 jointly form the notch 26 . As shown in FIG. 9 , the notch 26 has a first vertical depth V1 and a second vertical depth V2 . In this embodiment, the first vertical depth V1 is greater than the second vertical depth V2. The first vertical depth V1 may be between 15 nm and 25 nm, and the second vertical depth V2 may be between 10 nm and 20 nm. In order to ensure that there is no barrier material remaining on the sidewall of the dielectric layer 112, the barrier material on the sidewall of the gate layer 154 will be further removed to avoid bridging between adjacent gate layers 154 (that is, the word line bridging). Therefore, when the second vertical depth V2 is between 10 nm and 20 nm, it can ensure that there is no barrier material remaining on the sidewall of the dielectric layer 112 . On the other hand, in this embodiment, the width W1 between the outer sidewall of the barrier layer 162 and the sidewall of the buffer layer 120 may be between 10 nm and 20 nm, while the inner sidewall of the barrier layer 162 and the buffer layer The width W2 between the sidewalls of 120 may be between 20 nm and 30 nm. However, the present invention is not limited thereto. In other embodiments, the barrier layer 162 may also form a linear structure.

請參照圖10，形成氧化物層170，以覆蓋緩衝層120與阻障層162的表面（亦即堆疊結構的側壁）。具體來說，氧化物層170可部分延伸至圖9的凹槽24中，並與阻障層162相連。在一實施例中，氧化物層170可以低溫氧化製程（Low Temperature Oxidation process），在250°C至350°C的低溫下通過反應氣體，從而在狹縫15的側壁與底部上形成氧化物層170。在此情況下，氧化物層170亦可稱為低溫氧化物（Low Temperature Oxide，LTO）層。在形成氧化物層170之後，可進行熱處理製程以使氧化物層170更為緻密。在一實施例中，熱處理製程的溫度可介於800°C至900°C，例如850°C。在替代實施例中，氧化物層170亦可以是高品質氧化物（High Quality Oxide，HQO）層。值得注意的是，本發明之阻障層162可有效地阻擋閘極層154中殘留的氟因上述熱處理製程而逸出，以使氧化物層170免受破壞，進而提升元件的可靠度。Referring to FIG. 10 , an oxide layer 170 is formed to cover the surfaces of the buffer layer 120 and the barrier layer 162 (ie, sidewalls of the stacked structure). Specifically, the oxide layer 170 may partially extend into the groove 24 of FIG. 9 and be connected to the barrier layer 162 . In one embodiment, the oxide layer 170 can be formed by a low temperature oxidation process (Low Temperature Oxidation process) by passing a reactive gas at a low temperature of 250° C. to 350° C., thereby forming an oxide layer on the sidewall and bottom of the slit 15 . 170. In this case, the oxide layer 170 may also be called a low temperature oxide (Low Temperature Oxide, LTO) layer. After the oxide layer 170 is formed, a heat treatment process may be performed to make the oxide layer 170 denser. In one embodiment, the temperature of the heat treatment process may be 800°C to 900°C, for example, 850°C. In an alternative embodiment, the oxide layer 170 may also be a high quality oxide (HQO) layer. It is worth noting that the barrier layer 162 of the present invention can effectively block the residual fluorine in the gate layer 154 from escaping due to the above-mentioned heat treatment process, so as to prevent the oxide layer 170 from being damaged, thereby improving the reliability of the device.

請參照圖11，在氧化物層170上依序形成阻障層172與導體層174，進而形成狹縫填充結構175。在一實施例中，阻障層172的材料可包括鈦（Ti）、氮化鈦（TiN）、鉭（Ta）、氮化鉭（TaN）或其組合。導體層174的材料可包括多晶矽、非晶矽、鎢（W）或其組合。Referring to FIG. 11 , a barrier layer 172 and a conductive layer 174 are sequentially formed on the oxide layer 170 to form a slot-filling structure 175 . In one embodiment, the material of the barrier layer 172 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof. The material of the conductive layer 174 may include polysilicon, amorphous silicon, tungsten (W) or a combination thereof.

如圖11所示，本實施例之三維記憶體元件至少包括：堆疊結構210、垂直通道柱130、多個阻障結構160以及狹縫填充結構175。堆疊結構210包括交替堆疊的多個介電層112與多個閘極層154。多個阻障結構160分別包圍多個閘極層154的表面。每一個阻障結構160包括：第一阻障層152與第二阻障層162。第一阻障層152連續覆蓋在相應的閘極層154的頂面、底面以及第一側壁上。第二阻障層162覆蓋在相應的閘極層154的相對於第一側壁的第二側壁上，且與第一阻障層152連接。狹縫填充結構175貫穿堆疊結構210。第二阻障層162可物理分隔狹縫填充結構175與閘極層154，以有效地阻擋閘極層154中殘留的氟逸出，並避免導體層174與閘極層154橋接，進而提升元件的可靠度。As shown in FIG. 11 , the three-dimensional memory device of this embodiment at least includes: a stack structure 210 , a vertical channel pillar 130 , a plurality of barrier structures 160 and a slot-filling structure 175 . The stack structure 210 includes a plurality of dielectric layers 112 and a plurality of gate layers 154 stacked alternately. The plurality of barrier structures 160 respectively surround the surfaces of the plurality of gate layers 154 . Each barrier structure 160 includes: a first barrier layer 152 and a second barrier layer 162 . The first barrier layer 152 continuously covers the top surface, the bottom surface and the first sidewall of the corresponding gate layer 154 . The second barrier layer 162 covers the second sidewall of the corresponding gate layer 154 opposite to the first sidewall, and is connected to the first barrier layer 152 . The slot-filling structure 175 penetrates through the stacked structure 210 . The second barrier layer 162 can physically separate the slit-filling structure 175 and the gate layer 154, so as to effectively block the fluorine remaining in the gate layer 154 from escaping, and prevent the conductor layer 174 from bridging with the gate layer 154, thereby improving the device. reliability.

圖12A與圖12B以及圖12C分別是依照本發明一實施例的一種三維及式（AND）快閃記憶體1的立體示意圖、平面示意圖以及電路示意圖。FIG. 12A , FIG. 12B and FIG. 12C are respectively a perspective view, a plan view and a circuit view of a three-dimensional AND (AND) flash memory 1 according to an embodiment of the present invention.

請參照圖12A，本實施例之3D AND快閃記憶體1具有多個記憶胞150。詳細地說，如圖12A所示，多個閘極層154沿著垂直方向交替排列，且分別環繞垂直通道柱130。被閘極層154環繞的垂直通道柱130的一部分可構成一個記憶胞150。在本實施例中，單一個垂直通道柱130可定義有彼此堆疊的3個記憶胞150。但本發明不以此為限，在其他實施例中，記憶胞150的數量可隨著堆疊結構210中的閘極層154的數量來調整。更進一步地說，記憶胞150形成在閘極層154與垂直通道柱130的交叉點處。因此，垂直堆疊的閘極層154的數量愈多，則記憶串中的記憶胞150的數量也愈多。另外，雖然圖12A僅繪示出兩個垂直通道柱130，但本發明不以此為限。在替代實施例中，3D AND快閃記憶體1可包括多個垂直通道柱130，且這些垂直通道柱130可在上視角度中以陣列的方式排列，如圖1B所示。Referring to FIG. 12A , the 3D AND flash memory 1 of this embodiment has a plurality of memory cells 150 . In detail, as shown in FIG. 12A , a plurality of gate layers 154 are arranged alternately along the vertical direction and respectively surround the vertical channel pillars 130 . A portion of the vertical channel pillar 130 surrounded by the gate layer 154 can constitute a memory cell 150 . In this embodiment, a single vertical channel column 130 may define three memory cells 150 stacked on top of each other. But the present invention is not limited thereto. In other embodiments, the number of memory cells 150 can be adjusted along with the number of gate layers 154 in the stacked structure 210 . Furthermore, the memory cell 150 is formed at the intersection of the gate layer 154 and the vertical channel pillar 130 . Therefore, the more the number of vertically stacked gate layers 154 is, the more the number of memory cells 150 in the memory string is. In addition, although FIG. 12A only shows two vertical channel columns 130 , the present invention is not limited thereto. In an alternative embodiment, the 3D AND flash memory 1 may include a plurality of vertical channel pillars 130 , and these vertical channel pillars 130 may be arranged in an array in a top view, as shown in FIG. 1B .

為了對3D AND快閃記憶體1進行操作，在製造3D AND快閃記憶體1之後，會在3D AND快閃記憶體1上方形成導電線以電性連接至3D AND快閃記憶體1。在本實施例中，如圖12A所示，在作為源極的第一源極/汲極柱133上方形成一些導電線以作為源極線SL，在作為汲極的第二源極/汲極柱135上方形成其他導電線以作為位元線BL，且這些源極線SL與位元線BL彼此平行排列而彼此不接觸。In order to operate the 3D AND flash memory 1 , after manufacturing the 3D AND flash memory 1 , conductive wires are formed above the 3D AND flash memory 1 to be electrically connected to the 3D AND flash memory 1 . In this embodiment, as shown in FIG. 12A, some conductive lines are formed above the first source/drain column 133 as the source as the source line SL, and some conductive lines are formed on the second source/drain as the drain. Other conductive lines are formed above the pillars 135 as the bit lines BL, and the source lines SL and the bit lines BL are arranged parallel to each other without contacting each other.

以下對3D AND快閃記憶體1中的記憶胞150的操作進行說明。The operation of the memory cell 150 in the 3D AND flash memory 1 will be described below.

如圖12B所示，對於3D AND快閃記憶體1來說，可個別地對每一個記憶胞150進行操作。可對記憶胞150的第一源極/汲極柱133、第二源極/汲極柱135與對應的閘極層154（可視為閘極或字元線）施加操作電壓，來進行寫入（程式化）操作、讀取操作或抹除操作。在對第一源極/汲極柱133與第二源極/汲極柱135施加寫入電壓時，由於第一源極/汲極柱133與第二源極/汲極柱135與通道層134連接，因此電子可沿著第一電路徑E1與第二電路徑E2（例如是雙面（double sides）電路徑）傳送並儲存在整個電荷儲存結構132中。As shown in FIG. 12B , for the 3D AND flash memory 1 , each memory cell 150 can be operated individually. An operating voltage can be applied to the first source/drain column 133, the second source/drain column 135, and the corresponding gate layer 154 (which can be regarded as a gate or a word line) of the memory cell 150 to perform writing. (programming) operations, read operations, or erase operations. When a writing voltage is applied to the first source/drain column 133 and the second source/drain column 135, since the first source/drain column 133, the second source/drain column 135 and the channel layer 134 , so electrons can be transferred along the first electrical path E1 and the second electrical path E2 (eg, double sides electrical path) and stored in the entire charge storage structure 132 .

另外，請參照圖12C，本實施例之記憶胞150可排列成多個行與多個列，以形成3D AND快閃記憶體陣列。每一個記憶胞150可包括電性連接至字元線WL（即WLm、WLm+1）的閘極G、電性連接至源極線SL（即SLn、SLn+1）的源極S以及電性連接至位元線BL（即BLn、BLn+1）的汲極D。值得注意的是，在本實施例之3D AND快閃記憶體陣列中，沿著源極/汲極柱133、135的延伸方向D1的多個記憶胞150可彼此並聯連接。具體來說，如圖12C所示，上記憶胞150a與下記憶胞150b通過共同源極/汲極柱133、135以共享同一源極線SLn+1以及同一位元線BLn+1，上記憶胞150a的閘極電性連接至上字元線WLm+1，且下記憶胞150b的閘極電性連接至下字元線WLm。在此情況下，本實施例之3D AND快閃記憶體陣列的架構與操作方法是不同於習知的三維反及式（3D NAND）快閃記憶體陣列的架構與操作方法，其中習知的3D NAND快閃記憶體陣列包括彼此串聯連接的多個記憶胞。In addition, referring to FIG. 12C , the memory cells 150 of this embodiment can be arranged in multiple rows and multiple columns to form a 3D AND flash memory array. Each memory cell 150 may include a gate G electrically connected to the word line WL (ie, WLm, WLm+1), a source S electrically connected to the source line SL (ie, SLn, SLn+1), and an electrical is connected to the drain D of the bit line BL (ie, BLn, BLn+1). It should be noted that, in the 3D AND flash memory array of this embodiment, a plurality of memory cells 150 along the extending direction D1 of the source/drain columns 133 and 135 can be connected in parallel. Specifically, as shown in FIG. 12C, the upper memory cell 150a and the lower memory cell 150b share the same source line SLn+1 and the same bit line BLn+1 through common source/drain poles 133, 135, the upper memory The gate of the cell 150a is electrically connected to the upper word line WLm+1, and the gate of the lower memory cell 150b is electrically connected to the lower word line WLm. In this case, the structure and operation method of the 3D AND flash memory array of this embodiment are different from the structure and operation method of the conventional three-dimensional inverse and (3D NAND) flash memory array, wherein the conventional A 3D NAND flash memory array includes a plurality of memory cells connected to each other in series.

此外，圖11的三維記憶體元件是以氧化物/氮化物/氧化物優先（ONO first）製程來形成電荷儲存結構132。但本發明不以此為限，其他實施例亦可以ONO最後（ONO last）製程來形成電荷儲存結構，詳細結構請參照以下段落。In addition, the three-dimensional memory device in FIG. 11 uses an oxide/nitride/oxide first (ONO first) process to form the charge storage structure 132 . However, the present invention is not limited thereto. In other embodiments, the charge storage structure can also be formed by an ONO last (ONO last) process. For the detailed structure, please refer to the following paragraphs.

圖13是依照本發明替代實施例的一種三維記憶體元件的剖面示意圖。FIG. 13 is a schematic cross-sectional view of a three-dimensional memory device according to an alternative embodiment of the present invention.

圖13的三維記憶體元件與圖11的三維記憶體元件相似，相同或相似的構件則以相同或相似的元件標號來表示，於此便不再贅述。上述兩者主要不同之處在於：圖13的三維記憶體元件的電荷儲存結構132是配置在緩衝層120與介電層112之間，且環繞阻障結構160與閘極層154，而不包括在垂直通道柱130中。The 3D memory device in FIG. 13 is similar to the 3D memory device in FIG. 11 , and the same or similar components are denoted by the same or similar component numbers, which will not be repeated here. The main difference between the above two is that the charge storage structure 132 of the three-dimensional memory device in FIG. In the vertical channel column 130 .

具體來說，電荷儲存結構132的形成方法可包括：在進行閘極替換製程中的移除犧牲層114之後，將電荷儲存結構132共形覆蓋間隙14；接著依序形成緩衝層120、阻障材料層122以及導體材料層124，如圖6所示；然後進行第二蝕刻製程，移除介電層112的側壁上的阻障材料層122與導體材料層124，以暴露出緩衝層120；以及形成阻障層162以覆蓋閘極層154的側壁。在此情況下，如圖13所示，電荷儲存結構132可配置在緩衝層120與介電層112之間，且環繞阻障結構160與閘極層154。在本實施例中，阻障層162亦可有效地阻擋閘極層154中殘留的氟因熱處理製程而逸出，以使氧化物層170免受破壞，進而提升元件的可靠度。Specifically, the method for forming the charge storage structure 132 may include: after removing the sacrificial layer 114 in the gate replacement process, conformally covering the gap 14 with the charge storage structure 132 ; The material layer 122 and the conductive material layer 124, as shown in FIG. 6 ; then a second etching process is performed to remove the barrier material layer 122 and the conductive material layer 124 on the sidewall of the dielectric layer 112 to expose the buffer layer 120; And a barrier layer 162 is formed to cover the sidewall of the gate layer 154 . In this case, as shown in FIG. 13 , the charge storage structure 132 may be disposed between the buffer layer 120 and the dielectric layer 112 and surround the barrier structure 160 and the gate layer 154 . In this embodiment, the barrier layer 162 can also effectively block the remaining fluorine in the gate layer 154 from escaping due to the heat treatment process, so as to prevent the oxide layer 170 from being damaged, thereby improving the reliability of the device.

綜上所述，本發明利用額外的阻障層覆蓋閘極層的側壁，並與環繞閘極層的阻障層連接，進而形成完全包圍閘極層的所有表面的阻障結構。因此，本發明的阻障結構可有效地防止氟逸氣問題發生，進而提升三維記憶體元件的可靠度。此外，本發明之阻障結構的形成步驟相容於現行的三維記憶體元件的製程中，進而可應用在各種三維記憶體元件中。In summary, the present invention utilizes an additional barrier layer to cover the sidewall of the gate layer, and is connected to the barrier layer surrounding the gate layer, thereby forming a barrier structure completely surrounding all surfaces of the gate layer. Therefore, the barrier structure of the present invention can effectively prevent the fluorine outgassing problem, thereby improving the reliability of the three-dimensional memory device. In addition, the forming steps of the barrier structure of the present invention are compatible with the current manufacturing process of three-dimensional memory devices, and can be applied in various three-dimensional memory devices.

1:三維及式（AND）快閃記憶體1: Three-dimensional and type (AND) flash memory

10:區域10: area

14:間隙14: Gap

15:狹縫15: Slit

24:凹槽24: Groove

26:凹口26: notch

100:基底100: base

102:停止層102: stop layer

110、210:堆疊結構110, 210: stack structure

112:介電層112: dielectric layer

114:犧牲層114: sacrificial layer

115:開口115: opening

116:蓋層116: cover layer

120:緩衝層120: buffer layer

122、142:阻障材料層122, 142: barrier material layer

124:導體材料層124: conductor material layer

130、130A、130B、130C:垂直通道柱130, 130A, 130B, 130C: vertical channel column

132:電荷儲存結構132:Charge storage structure

133:第一源極/汲極柱133: The first source/drain column

134:通道層134: Channel layer

135:第二源極/汲極柱135: Second source/drain column

136:介電材料136: Dielectric material

150、150a、150b:記憶胞150, 150a, 150b: memory cells

152、162、172:阻障層152, 162, 172: barrier layer

154:閘極層154: gate layer

160:阻障結構160: Barrier structure

170:氧化物層170: oxide layer

174:導體層174: conductor layer

175:狹縫填充結構175:Slit filling structure

234:通道結構234: Channel structure

234A:襯層234A: lining

234B:插塞234B: plug

236:介電柱236: Dielectric column

334:通道柱334: channel column

BL、BLn、BLn+1:位元線BL, BLn, BLn+1: bit lines

D:汲極D: drain

D1、D2:距離D1, D2: distance

E1:第一電路徑E1: the first electrical path

E2:第二電路徑E2: Second electrical path

G:閘極G: gate

S:源極S: source

SL、SLn、SLn+1:源極線SL, SLn, SLn+1: source line

WL、WLm、WLm+1:字元線WL, WLm, WLm+1: word line

R:陣列區R: array area

R1:第一區R1: Region 1

R2:第二區R2: second area

T1、T2:厚度T1, T2: Thickness

圖1A是依照本發明一實施例的一種三維記憶體元件的剖面示意圖。圖1B是圖1A的平面示意圖。圖2A、圖3A以及圖4A繪示出依照本發明各種實施例的垂直通道柱的剖面示意圖。圖2B、圖3B以及圖4B分別是圖2A、圖3A以及圖4A的平面示意圖。圖5至圖11是依照本發明一實施例的一種三維記憶體元件的製造流程的剖面示意圖。圖12A與圖12B以及圖12C分別是依照本發明一實施例的一種三維及式（AND）快閃記憶體的立體示意圖、平面示意圖以及電路示意圖。圖13是依照本發明替代實施例的一種三維記憶體元件的剖面示意圖。 FIG. 1A is a schematic cross-sectional view of a three-dimensional memory device according to an embodiment of the invention. FIG. 1B is a schematic plan view of FIG. 1A . 2A , 3A and 4A illustrate schematic cross-sectional views of vertical channel columns according to various embodiments of the present invention. FIG. 2B , FIG. 3B and FIG. 4B are schematic plan views of FIG. 2A , FIG. 3A and FIG. 4A , respectively. 5 to 11 are schematic cross-sectional views of a manufacturing process of a three-dimensional memory device according to an embodiment of the present invention. FIG. 12A , FIG. 12B and FIG. 12C are a three-dimensional AND type (AND) flash memory according to an embodiment of the present invention, respectively, a schematic perspective view, a schematic plan view, and a schematic circuit diagram. FIG. 13 is a schematic cross-sectional view of a three-dimensional memory device according to an alternative embodiment of the present invention.

112:介電層 112: dielectric layer

120:緩衝層 120: buffer layer

130:垂直通道柱 130: vertical channel column

132:電荷儲存結構 132:Charge storage structure

152、162、172:阻障層 152, 162, 172: barrier layer

154:閘極層 154: gate layer

160:阻障結構 160: Barrier structure

170:氧化物層 170: oxide layer

174:導體層 174: conductor layer

175:狹縫填充結構 175:Slit filling structure

210:堆疊結構 210:Stack structure

Claims

一種三維記憶體元件，包括：基底；堆疊結構，配置在所述基底上，其中所述堆疊結構包括交替堆疊的多個介電層與多個閘極層；以及多個阻障結構，分別包圍所述多個閘極層的表面，其中每一個阻障結構包括：第一阻障層，連續覆蓋在相應的閘極層的頂面、底面以及第一側壁上；以及第二阻障層，覆蓋在所述相應的閘極層的相對於所述第一側壁的第二側壁上，且與所述第一阻障層連接，其中所述第二阻障層為C字型結構。 A three-dimensional memory element, comprising: a substrate; a stack structure configured on the substrate, wherein the stack structure includes a plurality of dielectric layers and a plurality of gate layers stacked alternately; and a plurality of barrier structures respectively surrounding The surface of the plurality of gate layers, wherein each barrier structure includes: a first barrier layer continuously covering the top surface, bottom surface and first sidewall of the corresponding gate layer; and a second barrier layer, covering on the second sidewall of the corresponding gate layer opposite to the first sidewall and connected to the first barrier layer, wherein the second barrier layer is a C-shaped structure.

如請求項1所述的三維記憶體元件，其中所述基底包括陣列區，且所述陣列區包括通道柱區與狹縫區。 The three-dimensional memory device as claimed in claim 1, wherein the substrate includes an array area, and the array area includes a channel column area and a slit area.

如請求項2所述的三維記憶體元件，更包括：多個垂直通道柱，貫穿所述堆疊結構且配置在所述通道柱區上且與所述第一側壁相鄰；以及狹縫填充結構，貫穿所述堆疊結構且配置在所述狹縫區上，且與所述第二側壁相鄰，其中所述第二阻障層物理分隔所述狹縫填充結構與所述相應的閘極層。 The three-dimensional memory device according to claim 2, further comprising: a plurality of vertical channel pillars passing through the stack structure and disposed on the channel pillar region and adjacent to the first sidewall; and a slit-filling structure , passing through the stack structure and disposed on the slit region, and adjacent to the second sidewall, wherein the second barrier layer physically separates the slit-filling structure from the corresponding gate layer .

如請求項3所述的三維記憶體元件，其中所述狹縫填充結構包括：氧化物層，覆蓋在所述堆疊結構的側壁上；導體層，配置在所述氧化物層上；以及第三阻障層，配置在所述氧化物層與所述導體層之間。 The three-dimensional memory element as claimed in item 3, wherein the slit-filling structure comprises: an oxide layer covering the sidewall of the stack structure; a conductor layer configured on the oxide layer; and a third barrier layer configured between the oxide layer and the conductor layer.

如請求項4所述的三維記憶體元件，其中所述多個閘極層的寬度小於所述多個介電層的寬度，以使所述第二側壁與相鄰的介電層共同形成凹槽，所述氧化物層部分延伸至所述凹槽中並與所述第二阻障層相連接。 The three-dimensional memory element according to claim 4, wherein the width of the plurality of gate layers is smaller than the width of the plurality of dielectric layers, so that the second sidewall and the adjacent dielectric layer jointly form a concave a groove, the oxide layer partially extends into the groove and is connected to the second barrier layer.

如請求項3所述的三維記憶體元件，更包括：緩衝層，共形地延伸在所述多個介電層與所述多個閘極層之間以及所述多個垂直通道柱與所述多個閘極層之間。 The three-dimensional memory device according to claim 3, further comprising: a buffer layer conformally extending between the plurality of dielectric layers and the plurality of gate layers and the plurality of vertical channel pillars and the plurality of gate layers between the multiple gate layers.

如請求項6所述的三維記憶體元件，其中所述第二阻障層覆蓋所述第二側壁與相鄰的緩衝層的一部分，所述第二阻障層與所述緩衝層共同形成凹口，所述凹口具有第一垂直深度與第二垂直深度，所述第一垂直深度大於所述第二垂直深度。 The three-dimensional memory element according to claim 6, wherein the second barrier layer covers a part of the second side wall and the adjacent buffer layer, and the second barrier layer and the buffer layer jointly form a concave The notch has a first vertical depth and a second vertical depth, and the first vertical depth is greater than the second vertical depth.

如請求項6所述的三維記憶體元件，其中所述第一阻障層配置在所述緩衝層與所述相應的閘極層之間。 The three-dimensional memory device according to claim 6, wherein the first barrier layer is disposed between the buffer layer and the corresponding gate layer.

如請求項1所述的三維記憶體元件，其中每一個阻障結構完全包圍相應的閘極層的所有表面。 The three-dimensional memory device according to claim 1, wherein each barrier structure completely surrounds all surfaces of the corresponding gate layer.

如請求項1所述的三維記憶體元件，其中所述三維記憶體元件包括三維及式(AND)快閃記憶體、三維反及式(NAND)快閃記憶體、三維反或式(NOR)快閃記憶體或其組合。 The three-dimensional memory element as claimed in claim 1, wherein the three-dimensional memory element comprises three-dimensional AND (AND) flash memory, three-dimensional inverse and (NAND) flash memory, three-dimensional inverse-or (NOR) flash memory or a combination thereof.

如請求項1所述的三維記憶體元件，其中所述第二阻障層的厚度大於所述第一阻障層的厚度。 The three-dimensional memory device according to claim 1, wherein the thickness of the second barrier layer is greater than the thickness of the first barrier layer.

如請求項1所述的三維記憶體元件，其中所述第二阻障層的厚度介於50Å至150Å之間。 The three-dimensional memory element according to claim 1, wherein the thickness of the second barrier layer is between 50Å and 150Å.

一種三維記憶體元件的形成方法，包括：提供具有第一區與第二區的基底；在所述基底上形成包括有交替堆疊的多個介電層與多個犧牲層的堆疊結構；在所述第二區的所述堆疊結構中形成狹縫；通過所述狹縫進行第一蝕刻製程，移除所述多個犧牲層以在所述多個介電層之間形成多個間隙；在所述多個間隙中形成多個閘極層與多個第一阻障層，其中所述多個第一阻障層環繞所述多個閘極層的部分表面且暴露出所述多個閘極層的側壁；以及形成多個第二阻障層，以覆蓋所述多個閘極層的所述側壁，其中所述多個第二阻障層分別與所述多個第一阻障層連接以形成多個阻障結構，且每一個第二阻障層形成為C字型結構。 A method for forming a three-dimensional memory element, comprising: providing a substrate having a first region and a second region; forming a stack structure including a plurality of dielectric layers and a plurality of sacrificial layers alternately stacked on the substrate; forming a slit in the stacked structure of the second region; performing a first etching process through the slit to remove the plurality of sacrificial layers to form a plurality of gaps between the plurality of dielectric layers; A plurality of gate layers and a plurality of first barrier layers are formed in the plurality of gaps, wherein the plurality of first barrier layers surround parts of the surfaces of the plurality of gate layers and expose the plurality of gates sidewalls of the electrode layer; and forming a plurality of second barrier layers to cover the sidewalls of the plurality of gate layers, wherein the plurality of second barrier layers are respectively connected to the plurality of first barrier layers connected to form a plurality of barrier structures, and each second barrier layer is formed into a C-shaped structure.

如請求項13所述的三維記憶體元件的形成方法，其中在形成所述多個第二阻障層之後，所述方法更包括：在所述狹縫中形成狹縫填充結構。 The method for forming a three-dimensional memory device according to claim 13, after forming the plurality of second barrier layers, the method further includes: forming a slot-filling structure in the slot.

如請求項13所述的三維記憶體元件的形成方法，其中在形成所述狹縫之前，所述方法更包括：在所述第一區的所述堆疊結構中形成多個垂直通道柱。 The method for forming a three-dimensional memory device according to claim 13, wherein before forming the slit, the method further includes: forming a plurality of vertical channel pillars in the stacked structure in the first region.

如請求項13所述的三維記憶體元件的形成方法，其中在所述多個間隙中形成所述多個閘極層與所述多個第一阻障層的步驟包括：形成第一阻障材料層與導體材料層以填入所述多個間隙中；以及進行第二蝕刻製程，移除所述多個介電層的側壁上的所述第一阻障材料層與所述導體材料層，以在所述多個間隙中形成所述多個閘極層與所述多個第一阻障層。 The method for forming a three-dimensional memory element according to claim 13, wherein the step of forming the plurality of gate layers and the plurality of first barrier layers in the plurality of gaps comprises: forming a first barrier a material layer and a conductive material layer to fill the plurality of gaps; and performing a second etching process to remove the first barrier material layer and the conductive material layer on the sidewalls of the plurality of dielectric layers , to form the plurality of gate layers and the plurality of first barrier layers in the plurality of gaps.

如請求項16所述的三維記憶體元件的形成方法，其中所述第一阻障材料層的材料包括鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)或其組合。 The method for forming a three-dimensional memory element according to claim 16, wherein the material of the first barrier material layer includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof.

如請求項16所述的三維記憶體元件的形成方法，其中在進行所述第二蝕刻製程之後，所述多個閘極層的所述側壁內凹於所述多個介電層的所述側壁，以形成多個凹槽。 The method for forming a three-dimensional memory element according to claim 16, wherein after performing the second etching process, the sidewalls of the plurality of gate layers are recessed in the sidewalls of the plurality of dielectric layers sidewalls to form a plurality of grooves.

如請求項18所述的三維記憶體元件的形成方法，其中形成所述多個第二阻障層的步驟包括：形成第二阻障材料層，以共形覆蓋所述多個介電層的所述側壁與所述多個凹槽的表面；以及進行第三蝕刻製程，移除所述多個介電層的所述側壁上的所述第二阻障材料層，以在所述多個凹槽中形成所述多個第二阻障層。 The method for forming a three-dimensional memory element according to claim 18, wherein the step of forming the plurality of second barrier layers includes: forming a second barrier material layer to conformally cover the plurality of dielectric layers Surfaces of the sidewalls and the plurality of grooves; and performing a third etching process to remove all of the sidewalls of the plurality of dielectric layers The second barrier material layer is formed to form the plurality of second barrier layers in the plurality of grooves.

如請求項19所述的三維記憶體元件的形成方法，其中所述第一阻障材料層與所述第二阻障材料層具有相同材料。The method for forming a three-dimensional memory device according to claim 19, wherein the first barrier material layer and the second barrier material layer are made of the same material.