TWI803995B - 一種半導體裝置及其形成方法 - Google Patents
一種半導體裝置及其形成方法 Download PDFInfo
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- TWI803995B TWI803995B TW110136682A TW110136682A TWI803995B TW I803995 B TWI803995 B TW I803995B TW 110136682 A TW110136682 A TW 110136682A TW 110136682 A TW110136682 A TW 110136682A TW I803995 B TWI803995 B TW I803995B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 73
- 238000000034 method Methods 0.000 title claims description 212
- 238000002955 isolation Methods 0.000 claims abstract description 69
- 238000005530 etching Methods 0.000 claims abstract description 40
- 238000000151 deposition Methods 0.000 claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims description 48
- 239000002184 metal Substances 0.000 claims description 48
- 239000003989 dielectric material Substances 0.000 claims description 38
- 239000000463 material Substances 0.000 claims description 28
- 238000007789 sealing Methods 0.000 claims description 24
- 239000000203 mixture Substances 0.000 claims description 22
- 125000006850 spacer group Chemical group 0.000 claims description 21
- 239000000758 substrate Substances 0.000 abstract description 24
- 238000004519 manufacturing process Methods 0.000 abstract description 10
- 239000010410 layer Substances 0.000 description 421
- 230000008569 process Effects 0.000 description 137
- 229910052710 silicon Inorganic materials 0.000 description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 29
- 239000010703 silicon Substances 0.000 description 29
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 27
- 238000005253 cladding Methods 0.000 description 17
- 239000007789 gas Substances 0.000 description 17
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 15
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 15
- 238000000231 atomic layer deposition Methods 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 229910052814 silicon oxide Inorganic materials 0.000 description 14
- 229910052581 Si3N4 Inorganic materials 0.000 description 13
- 238000001312 dry etching Methods 0.000 description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 11
- 239000010936 titanium Substances 0.000 description 11
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 10
- 230000008021 deposition Effects 0.000 description 10
- 229910052732 germanium Inorganic materials 0.000 description 10
- 238000001039 wet etching Methods 0.000 description 10
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 9
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 9
- 230000003071 parasitic effect Effects 0.000 description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 9
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 9
- 229910010271 silicon carbide Inorganic materials 0.000 description 9
- 239000000126 substance Substances 0.000 description 9
- 229910021332 silicide Inorganic materials 0.000 description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 7
- 238000001451 molecular beam epitaxy Methods 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 7
- 238000001020 plasma etching Methods 0.000 description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 7
- 229910052721 tungsten Inorganic materials 0.000 description 7
- 239000010937 tungsten Substances 0.000 description 7
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 239000010941 cobalt Substances 0.000 description 6
- 229910017052 cobalt Inorganic materials 0.000 description 6
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 150000002739 metals Chemical class 0.000 description 6
- 239000002135 nanosheet Substances 0.000 description 6
- 230000036961 partial effect Effects 0.000 description 6
- 238000000059 patterning Methods 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 6
- 238000000927 vapour-phase epitaxy Methods 0.000 description 6
- -1 InAlAs Inorganic materials 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 230000005669 field effect Effects 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 5
- 239000011295 pitch Substances 0.000 description 5
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 4
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 4
- 239000000908 ammonium hydroxide Substances 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 4
- 239000000460 chlorine Substances 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 229910052731 fluorine Inorganic materials 0.000 description 4
- 239000011737 fluorine Substances 0.000 description 4
- 239000005350 fused silica glass Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 229910052707 ruthenium Inorganic materials 0.000 description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 239000011800 void material Substances 0.000 description 4
- 229910052726 zirconium Inorganic materials 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- 230000002829 reductive effect Effects 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- 229910052691 Erbium Inorganic materials 0.000 description 2
- 229910005540 GaP Inorganic materials 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 229910052769 Ytterbium Inorganic materials 0.000 description 2
- OQNXPQOQCWVVHP-UHFFFAOYSA-N [Si].O=[Ge] Chemical compound [Si].O=[Ge] OQNXPQOQCWVVHP-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- RVSGESPTHDDNTH-UHFFFAOYSA-N alumane;tantalum Chemical compound [AlH3].[Ta] RVSGESPTHDDNTH-UHFFFAOYSA-N 0.000 description 2
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910002113 barium titanate Inorganic materials 0.000 description 2
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 2
- 229910052794 bromium Inorganic materials 0.000 description 2
- 230000005465 channeling Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 description 2
- 230000009969 flowable effect Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- TXFYZJQDQJUDED-UHFFFAOYSA-N germanium nickel Chemical compound [Ni].[Ge] TXFYZJQDQJUDED-UHFFFAOYSA-N 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- KUVFGOLWQIXGBP-UHFFFAOYSA-N hafnium(4+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Hf+4] KUVFGOLWQIXGBP-UHFFFAOYSA-N 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 229910052740 iodine Inorganic materials 0.000 description 2
- 239000011630 iodine Substances 0.000 description 2
- 229910052741 iridium Inorganic materials 0.000 description 2
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 229910003468 tantalcarbide Inorganic materials 0.000 description 2
- NAWDYIZEMPQZHO-UHFFFAOYSA-N ytterbium Chemical compound [Yb] NAWDYIZEMPQZHO-UHFFFAOYSA-N 0.000 description 2
- ZVWKZXLXHLZXLS-UHFFFAOYSA-N zirconium nitride Chemical compound [Zr]#N ZVWKZXLXHLZXLS-UHFFFAOYSA-N 0.000 description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- 229910019311 (Ba,Sr)TiO Inorganic materials 0.000 description 1
- ITWBWJFEJCHKSN-UHFFFAOYSA-N 1,4,7-triazonane Chemical compound C1CNCCNCCN1 ITWBWJFEJCHKSN-UHFFFAOYSA-N 0.000 description 1
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- 229910017109 AlON Inorganic materials 0.000 description 1
- 229910017121 AlSiO Inorganic materials 0.000 description 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 229910005542 GaSb Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910021193 La 2 O 3 Inorganic materials 0.000 description 1
- 229910017855 NH 4 F Inorganic materials 0.000 description 1
- 229910018503 SF6 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 229910008322 ZrN Inorganic materials 0.000 description 1
- 229910006249 ZrSi Inorganic materials 0.000 description 1
- 229910006501 ZrSiO Inorganic materials 0.000 description 1
- ZGUQGPFMMTZGBQ-UHFFFAOYSA-N [Al].[Al].[Zr] Chemical compound [Al].[Al].[Zr] ZGUQGPFMMTZGBQ-UHFFFAOYSA-N 0.000 description 1
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 1
- HLFWJMSINGUMDQ-UHFFFAOYSA-N [Ge].[Pt].[Ni] Chemical compound [Ge].[Pt].[Ni] HLFWJMSINGUMDQ-UHFFFAOYSA-N 0.000 description 1
- OBZUDFAHIZFVHI-UHFFFAOYSA-N [La].[Si]=O Chemical compound [La].[Si]=O OBZUDFAHIZFVHI-UHFFFAOYSA-N 0.000 description 1
- DBOSVWZVMLOAEU-UHFFFAOYSA-N [O-2].[Hf+4].[La+3] Chemical compound [O-2].[Hf+4].[La+3] DBOSVWZVMLOAEU-UHFFFAOYSA-N 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 1
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 description 1
- HVXCTUSYKCFNMG-UHFFFAOYSA-N aluminum oxygen(2-) zirconium(4+) Chemical compound [O-2].[Zr+4].[Al+3] HVXCTUSYKCFNMG-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- ZDZIJHSDFUXADX-UHFFFAOYSA-N azanium hydrogen peroxide hydroxide hydrate Chemical compound O.OO.[OH-].[NH4+] ZDZIJHSDFUXADX-UHFFFAOYSA-N 0.000 description 1
- MKTJTLRLXTUJCM-UHFFFAOYSA-N azanium;hydrogen peroxide;hydroxide Chemical compound [NH4+].[OH-].OO MKTJTLRLXTUJCM-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- ONRPGGOGHKMHDT-UHFFFAOYSA-N benzene-1,2-diol;ethane-1,2-diamine Chemical compound NCCN.OC1=CC=CC=C1O ONRPGGOGHKMHDT-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000011066 ex-situ storage Methods 0.000 description 1
- ZQXQADNTSSMHJI-UHFFFAOYSA-N hafnium(4+) oxygen(2-) tantalum(5+) Chemical compound [O-2].[Ta+5].[Hf+4] ZQXQADNTSSMHJI-UHFFFAOYSA-N 0.000 description 1
- KQHQLIAOAVMAOW-UHFFFAOYSA-N hafnium(4+) oxygen(2-) zirconium(4+) Chemical compound [O--].[O--].[O--].[O--].[Zr+4].[Hf+4] KQHQLIAOAVMAOW-UHFFFAOYSA-N 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- PCLURTMBFDTLSK-UHFFFAOYSA-N nickel platinum Chemical compound [Ni].[Pt] PCLURTMBFDTLSK-UHFFFAOYSA-N 0.000 description 1
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 229910021339 platinum silicide Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000007652 sheet-forming process Methods 0.000 description 1
- HWEYZGSCHQNNEH-UHFFFAOYSA-N silicon tantalum Chemical compound [Si].[Ta] HWEYZGSCHQNNEH-UHFFFAOYSA-N 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- KVVXFICVLMKMGS-UHFFFAOYSA-N tetrachloro silicate Chemical compound ClO[Si](OCl)(OCl)OCl KVVXFICVLMKMGS-UHFFFAOYSA-N 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- XLOMVQKBTHCTTD-UHFFFAOYSA-N zinc oxide Inorganic materials [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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Abstract
本文揭露了半導體裝置及其形成方法。一種示例性的形成方法包括:提供工件,包括前側及背側,工件包含遮罩、位於遮罩上的隔離部件、從遮罩突出並穿過隔離部件的第一鰭形結構,以及從遮罩突出並穿過隔離部件的第二鰭形結構,其中遮罩位於工件的背側,並且第一及第二鰭形結構位於工件的前側;在第一及第二鰭形結構之間形成介電鰭片;分別在第一及第二鰭形結構上形成第一及第二閘極結構。此示例性的形成方法也包括:從工件的背側蝕刻隔離部件,以形成溝槽,露出介電鰭片;從工件的背側蝕刻介電鰭片,從而形成延伸溝槽;及在延伸溝槽上沉積密封層,其中密封層覆蓋第一和第二閘極結構之間的氣隙。
Description
本揭露實施例是關於半導體裝置,特別是關於具有閘極隔離結構之半導體裝置及其形成方法。
半導體積體電路(integrated circuit;IC)產業經歷了快速成長。IC材料和設計上的技術進步產生了一代又一代的IC,每一代都比上一代的電路更小、更複雜。積體電路演進期間,功能密度(亦即,單位晶片面積的互連裝置數目)通常會增加,而幾何尺寸(亦即,即可使用製程生產的最小元件(或線))卻減少。此微縮化的製程通常會以增加生產效率與降低相關成本而提供助益。這種微縮化也增加了積體電路結構(如三維電晶體)和加工的複雜性。
例如,隨著IC技術向更小的技術節點發展,已導入多閘極金屬氧化物半導體場效電晶體(多閘極金屬氧化物半導體場效電晶體(metal-oxide-semiconductor field-effect transistor;MOSFET),或多閘極裝置),以透過增加閘極-通道耦合(gate-channel coupling)、降低截止狀態電流(off-state current)和減少短通道效應(short-channel effects;SCE)來改善閘控。多閘極裝置一般是指具有閘極結構(也稱為閘極堆疊)或其部分的裝置設置在通道區的
一個以上的側面。鰭式場效電晶體(fin-like field effect transistors;FinFET)和多橋通道(multi-bridge-channel;MBC)電晶體是多閘極裝置的例子,已成為在高性能和低洩漏(leakage)應用中受歡迎且有潛力的候選裝置。FinFET具有由多於一側的閘極結構包繞的高架通道(例如,閘極包繞從基板延伸出來的半導體材料"鰭片"的頂部和側壁)。MBC電晶體的閘極結構可以部分地或全部地圍繞通道區延伸,以便在兩側或更多側上提供對通道區的通路。由於其閘極結構包圍通道區,MBC電晶體也可稱為環繞式閘極電晶體(surrounding gate transistor;SGT)或全繞式閘極(gate-all-around;GAA)電晶體。
為了繼續在更小的技術節點中提供MBC電晶體所需的尺寸和增加的密度,已引入了介電鰭片(也稱為混合介電鰭片或混合鰭片)來提供閘極結構之間的隔離。隨著閘極臨界尺寸(critical dimension;CD)進一步減小,即便使用低k介電材料製成的介電鰭片,閘極結構之間的寄生電容可能會降低裝置的性能,如電路速度和串音耦合(cross-talk coupling)。改善MBC電晶體閘極結構之間的隔離的措施可能面臨在進一步降低寄生電容的同時形成隔離結構的挑戰。雖然現有的半導體裝置通常足以滿足其預期的目的,但其並非在所有面向都令人滿意。
本發明實施例提供一種半導體裝置的形成方法,包括:提供工件,包括前側及背側,工件包含遮罩、位於遮罩上的隔離部件、從遮罩突出並穿過隔離部件的第一鰭形結構,以及從遮罩突出並穿過隔離部件的第二鰭形結構,其中遮罩位於工件的背側,並且第一及第二鰭形結構位於工件的前側;在
第一及第二鰭形結構之間形成介電鰭片;分別在第一及第二鰭形結構上形成第一及第二閘極結構;從工件的背側蝕刻隔離部件,以形成溝槽,露出介電鰭片;從工件的背側蝕刻介電鰭片,從而形成延伸溝槽;及在延伸溝槽上沉積密封層,其中密封層覆蓋第一和第二閘極結構之間的氣隙。
本發明實施例提供一種半導體裝置的形成方法,包括:在遮罩上形成複數個通道構件,這些通道構件垂直地堆疊;形成與這些通道構件的側端毗鄰的介電鰭片;形成與每個通道構件嚙合(engage)嚙合的閘極結構;移除遮罩,從而露出介電鰭片的底表面;移除介電鰭片,從而形成溝槽,溝槽露出閘極結構的側壁;以及在溝槽上沉積介電層,介電層將孔隙封閉在溝槽中。
本發明實施例提供一種半導體裝置,包括:複數個第一通道構件,垂直地堆疊;複數個第二通道構件,垂直地堆疊;第一閘極結構,與第一複數個通道構件嚙合;第二閘極結構,與第二複數個通道構件嚙合;第一金屬導線層,位於半導體裝置的前側;第二金屬導線層,位於半導體裝置的背側,其中第一及第二閘極結構垂直地堆疊於第一及第二金屬導線層之間;以及隔離結構,垂直地堆疊於第一及第二金屬導線層之間,其中隔離結構包含在第一及第二閘極結構之間橫向地堆疊的氣隙。
100:方法
132-158:方框
200:工件
202:基板
204:堆疊
206:犧牲層
206T:頂部犧牲層
206B:底部犧牲層
208:通道層
208B:上方的半導體層
210:鰭狀結構
210A:鰭狀結構
210B:鰭狀結構
210C:鰭狀結構
210Top:頂部部分
210Base:底部部分
212:鰭片溝槽
212A:鰭片溝槽
212B:鰭片溝槽
214:硬遮罩層
216:隔離部件
218:第一介電鰭片
220:第一介電層
222:第二介電層
224:第二介電鰭片
226:披覆層
228:第三介電層
230:第四介電層
240:虛設閘極堆疊
242:虛設介電層
244:虛設電極
246:閘極頂部硬遮罩
248:氮化矽遮罩層
250:氧化矽遮罩層
252:閘極間隔物
254:源極/汲極凹槽
254S:深源極/汲極凹槽
256:內間隔部件
258:源極/汲極部件
258B:延伸的底部部分
260:孔隙
262:接觸蝕刻停止層
264:層間介電層
266:閘極溝槽
270:閘極結構
272:閘極介電層
274:閘極電極層
276:金屬蓋層
278:自對準蓋層
280:閘極切割部件
282:源極/汲極接觸件
284:源極/汲極接觸導孔
286:閘極接觸件
288:閘極接觸導孔
290:附加層間介電層
291:金屬間介電層
292:載體
294:黏合層
296:溝槽
298:密封層
300:氣隙
302:溝槽
304:介電層
306:背側自對準源極/汲極接觸件
308:背側互連層
310:背側動力軌
312:背側金屬線
314:背側第一層級金屬軌道
316:金屬接觸插塞
318:源極/汲極接觸導孔
W1:第一寬度
W2:第二寬度
S1:第一間距
S2:第二間
T-1:MBC電晶體
T-2:MBC電晶體
T-3:MBC電晶體
由以下的詳細敘述配合所附圖式,可最好地理解本發明實施例。應注意的是,依據在業界的標準做法,各種特徵並未按照比例繪製。事實上,可任意地放大或縮小各種元件的尺寸,以清楚地表現出本發明實施例之特徵。
第1A、1B圖是根據本揭露的一個或多個面向,繪示出形成半導體裝置的示
例方法之流程圖。
第2A、2B、2C、3A、3B、3C、4A、4B、4C、5A、5B、5C、6A、6B、6C、7A、7B、7C、8A、8B、8C、9A、9B、9C、10A、10B、10C、11A、11B、11C、12A、12B、12C、13A、13B、13C、14A、14B、14C、15A、15B、15C、16A、16B、16C、17A、17B、17C、18A、18B、18C、19A、19B、19C、20A、20B、20C、21A、21B、21C、22A、22B、22C、23A、23B、23C、24A、24B、24C、25A、25B、25C、26A、26B、26C、27A、27B、27C、28A、28B、28C、29A、29B、29C、30A、30B、30C、31A、31B、31C、32A、32B、32C圖是根據本揭露的一個或多個面向,繪示出第1圖和第2圖的方法中,工件在各個製造階段期間之局部剖面圖。
以下揭露提供了許多不同的實施例或示例,用於實現本揭露的不同部件。下文描述部件及配置的具體示例以簡化本揭露。當然,這些僅是示例而不是限制性的。例如,在以下描述中在第二部件之上或上方形成第一部件可括包含第一和第二部件直接接觸形成的實施例,並且還可以包括可在第一部件和第二部件之間形成附加部件的實施例,使第一和第二部件可以不直接接觸。此外,本揭露可以在各種示例中重複引用數字及/或字母。這種重複性是以簡單和清楚為目的,其本身並不對所討論的各種實施例及/或配置之間的關係進行規定。
此外,本揭露可以在各種示例中重複引用數字及/或字母。這種重複是以簡單和清楚為目的,其本身並不對所討論的各種實施例及/或配置之間的
關係進行規定。另外,在隨後的本揭露中,在另一部件上、連接到及/或耦合到另一部件之一個部件的形成可包括部件透過直接接觸而形成的實施例,並且還可以包括形成***於部件的附加部件的實施例,使部件可不直接接觸。此外,空間相對術語,例如「較低的」、「較高的」、「水平的」、「垂直的」、「上方」、「在...之上」、「下方」、「在...之下」、「上」、「下」、「頂部」、「底部」等及其衍生詞(例如,「水平地」、「向下地」、「向上地」等)用於簡化本揭露的一個部件與另一部件的關係。空間相對術語旨在涵蓋包括多個部件的裝置的不同方向。更進一步地,當使用「大約」、「大概」等來描述數字或數字範圍時,此術語旨在涵蓋包括所述的數字在內的合理範圍內的數字,例如在+/-內所述的數字或所屬技術領域具有通常知識者所理解的其它值的10%。例如,「約5nm」的術語涵蓋從4.5nm到5.5nm的尺寸範圍。
本揭露內容通常與半導體裝置及其製造有關,特別是與一種含氣隙的隔離結構有關,以降低寄生電容來改善在閘極結構之間的隔離。
為了提高驅動電流以滿足設計需要,MBC電晶體可包含薄且寬的奈米級通道構件。這樣的MBC電晶體也可以稱為奈米片電晶體。雖然奈米片電晶體能提供令人滿意的驅動電流和通道控制,但其寬大的奈米片通道構件可使減少單元尺寸成為挑戰。在一些示例結構中,可以實施魚骨式結構或叉片(fork-sheet)式結構來減少單元尺寸。在魚骨式結構或叉片式結構中,鄰近的通道構件堆疊可被介電鰭片(也稱為混合介電鰭片或混合鰭片)分割。不管是魚骨式結構還是叉片式結構,通道構件之間的緊鄰(close proximity)導致與相應的通道構件嚙合的閘極結構(也稱為閘極堆疊)之間的緊鄰,因此閘極結構之間的寄生電容很高。
即使已經引入了低k介電材料或極低k介電材料來形成作為閘極隔離結構的介電鰭片,隨著閘極CD的進一步減少,寄生電容仍然對進一步的裝置性能,如電路速度和串音耦合構成挑戰。除了使用低k或極低k的介電材料,另一種方法是實施氣隙,以含有氣隙的閘極隔離結構的形式提供。即使在金屬部件附近有一個小的氣隙,也可能導致整體有效介電常數(k)的顯著改善;例如,在鄰近的金屬部件之間有一個體積約為35%至約40%的氣隙,可減少約15%的寄生電容。如本文所用,術語「氣隙」用於描述由周圍的實質性部件所定義的孔隙,其中孔隙可包含空氣、氮氣、環境氣體、製造過程中使用的氣體化學品或其組合。
現將參照圖示來更詳細地描述本揭露的各種面向。第1A圖和第1B圖共同繪示了半導體裝置的形成方法100的流程圖。上述方法100僅為一示例,並不旨在將本揭露內容限制在方法100中明確說明的內容。在方法100之前、期間和之後可以提供額外的步驟,而且可以替換、取消或移動所述的一些步驟,以用於上述方法的額外實施例。為簡單起見,這裡沒有詳述所有的步驟。下文結合第2A-32C圖來描述方法100,圖中說明了根據方法100的實施例,在不同製造階段的工件200的局部剖面圖。由於半導體裝置將由工件200形成,工件200可根據上下文所需稱為半導體裝置200或裝置200。為了更佳地繪示本揭露內容的各種面向,以大寫字母A結尾的各圖繪示了將要形成的電晶體的源極/汲極區(即,在源極區或汲極區的Y-Z平面內的切面,其垂直於通道構件的長度方向)的局部剖面圖,以大寫字母B結尾的各圖繪示了通道區的局部剖面圖(即,在通道區的Y-Z平面內,沿著閘極結構的長度方向並垂直於通道構件的長度方向的切口),以及每個以大寫字母C結尾的數字說明了沿通道構件的長度方向(即,在
X-Z平面內沿通道構件的長度方向並穿過通道區和毗鄰的源極/汲極區的切口)的局部剖面圖。在整個第2A-32C圖中,X方向、Y方向和Z方向是相互垂直的,且其使用為一致的。此外,在本揭露中,類似的引用數字用於表示相似的部件。儘管圖中說明了包括魚骨或叉片式電晶體的實施例,但本揭露內容並不限於此,可應用於其它多閘極裝置,如其它類型的MBC電晶體或FinFET。
參照第2A-2C圖,方法100包括方框102,接收工件200(第1A圖)。工件200包含基板202和設置在基板202上的堆疊204。在一實施例中,基板202可以是矽(Si)基板。在一些其它實施例中,基板202可包含其它半導體材料,如鍺(Ge)、矽鍺(SiGe),或III-V半導體材料。示例性的III-V族半導體材料可包含砷化鎵(GaAs)、磷化銦(InP)、磷化鎵(GaP)、氮化鎵(GaN)、磷化砷化鎵(gallium arsenide phosphide;GaAsP)、砷化銦鋁(aluminum indium arsenide;AlInAs)、砷化鎵鋁(aluminum gallium arsenide;AlGaAs)、磷化銦鎵(gallium indium phosphide;GaInP)和砷化鎵銦(indium gallium arsenide;InGaAs)。基板202可包含多個n型井區和多個p型井區。p型井區可以摻入p型摻雜物(即硼(B))。n型井區可以摻入n型摻雜物(即磷(P)或砷(As))。
在第2A-2C圖中所示的一些實施例中,堆疊204可包含在基板202上的底部犧牲層206B、在底部犧牲層206B上的上方的半導體層208B、在底部犧牲層206B上的交替通道層208和犧牲層206,以及在犧牲層206和通道層208上的頂部犧牲層206T。底部犧牲層206B、上方的半導體層208B、頂部犧牲層206T、犧牲層206和通道層208可以使用磊晶製程進行沉積。示例的磊晶製程可包括氣相磊晶(vapor-phase epitaxy;VPE)、超高真空CVD(ultra-high vacuum CVD;UHV-CVD))、分子束磊晶(molecular beam epitaxy;MBE)及/或其它合適的
製程。通道層208和犧牲層206可具有不同的半導體組成。在一些實施例中,通道層208由矽(Si)形成,犧牲層206由矽鍺(SiGe)形成。犧牲層206中額外的鍺(Ge)含量允許選擇性地移除或凹蝕犧牲層206而不對通道層208造成實質性損壞。犧牲層206和通道層208交替地設置,使犧牲層206與通道層208交錯(interleave)。第2A-2C圖說明了兩(2)層犧牲層206和兩(2)層通道層208交替地且垂直地排列,這僅用於說明的目的,並不旨在限制請求項中具體陳述的內容。層數取決於半導體裝置200所需的通道構件的數量。在一些實施例中,通道層208的數量在1至6之間。
底部犧牲層206B可以由矽鍺(SiGe)形成。在一實施例中,底部犧牲層206B的鍺含量可以與犧牲層206的鍺含量相同。在另一實施例中,與犧牲層206不同,底部犧牲層206B的鍺含量可以小於犧牲層206的鍺含量。例如,犧牲層206的鍺含量的莫耳比可以在大約20%和大約30%之間,並且底部犧牲層206B的鍺含量可以是犧牲層206的鍺含量的約80%至約90%。在某些情況下,底部犧牲層206B的鍺含量的莫耳比可在約16%至約27%之間。底部犧牲層206B可以比沿Z方向的每個犧牲層206厚。在某些情況下,每個犧牲層206的厚度可在約4奈米和約15奈米之間,而底部犧牲層206B的厚度可在約8和約30奈米之間。如下文所述,底部犧牲層206B在稍後的裝置背側薄化製程(device backside thinning process)中作為蝕刻停止層或機械研磨停止層發揮作用。
上方的半導體層208B和基板202都可包含塊材單晶矽(Si)。或者,上方的半導體層208B和基板202可包含相同或不同的半導體組成,其中每個組成可包含但不限於Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、InP或者其組合。
與犧牲層206一樣,頂部犧牲層206T可以由矽鍺(SiGe)形成。在一些情況下,犧牲層206和頂部犧牲層206T的組成大抵上相同。頂部犧牲層206T可以比犧牲層206厚,其功能為保護堆疊204在製造過程中不受損壞。在某些情況下,頂部犧牲層206T的厚度可在約20奈米和約40奈米之間,而犧牲層206的厚度可在約4奈米和約15奈米之間。
參照第3A-3C圖,方法100包括方框104(第1A圖),將堆疊204和基板202圖案化以形成由鰭片溝槽212分隔的鰭狀結構210。為了將堆疊204和基板202圖案化,在頂部犧牲層206T上沉積了硬遮罩層214。然後,將硬遮罩層214圖案化,作為蝕刻遮罩來圖案化頂部犧牲層206T、堆疊204和基板202的頂部部分。在一些實施例中,硬遮罩層214可以使用CVD、電漿增強CVD(plasma-enhanced CVD;PECVD)、原子層沉積(atomic layer deposition;ALD)、電漿增強ALD(plasma-enhanced ALD;PEALD)或合適的沉積方法進行沉積。硬遮罩層214可以是單層或多層。當硬遮罩層214為多層時,硬遮罩層214可包含氧化墊和氮化墊層。在另一實施例中,硬遮罩層214可包含矽(Si)。鰭狀結構210可以使用合適的製程來進行圖案化,包括雙重圖案化(double-patterning)或多重圖案化(multi-patterning)製程。一般來說,雙重圖案化或多重圖案化製程結合了微影和自對準製程,創建出具有如間距比使用單一、直接的微影製程可獲得的還小的圖案。例如,在一實施例中,材料層在基板上形成,並使用微影製程來形成圖案。使用自對準製程來將間隔物形成於圖案化的材料層旁邊。接著將材料層移除,剩餘的間隔物或心軸可用於圖案化硬遮罩層214,然後圖案化的硬遮罩層214可用作蝕刻遮罩,以蝕刻堆疊204和基板202,形成鰭狀結構210。蝕刻製程可包含乾式蝕刻、濕式蝕刻、反應性離子蝕刻(reactive ion etching;RIE)
及/或其它合適的製程。
如第3A-3C圖所示,鰭狀結構210中的每一個包含從基板202的一部分形成的底部部分210Base和從堆疊204形成的頂部部分210Top。頂部部分210Top設置在底部部分210Base上。鰭狀結構210沿X方向縱向延伸,並沿Z方向從基板202垂直延伸。沿著Y方向,鰭狀結構210由鰭片溝槽212隔開。每個鰭片溝槽212(如所繪示的實施例中的鰭片溝槽212A和212B)可以在鄰近的鰭狀結構210之間定義相同或不同的間距。在所繪示的實施例中,鰭片溝槽212A沿Y方向比鰭片溝槽212B寬,以提供較大的間距。如第3A和3B圖所示,鰭片溝槽212A定義第一間距S1,鰭片溝槽212B定義第二間距S2。第一間距S1大於第二間距S2。在一些情況下,第一間距S1在約25奈米和約40奈米之間,第二間距S2在約10奈米和約25奈米之間。在各種實施例中,S1和S2(S1-S2)之間的差值至少為8奈米,這有利於形成魚骨式或叉片式的結構。同樣地,每個鰭狀結構210(如所繪示的實施例中的鰭狀結構210A、210B和210C)可以具有相同或不同的寬度。如第3A和3B圖所示,鰭狀結構210A具有第一寬度W1,鰭狀結構210B/210C具有第二寬度W2。第一寬度W1大於第二寬度W2。在某些情況下,第一寬度W1在約10奈米和約100奈米之間,第二寬度W2在約10奈米和約40奈米之間。如下文所述,較窄的鰭片溝槽212B和較窄的鰭狀結構210B/210C共同允許形成魚骨式結構或叉片式結構中具有通道構件堆疊的MBC電晶體,而較寬的鰭片溝槽212A和較寬的鰭狀結構210A共同允許形成具有奈米片通道構件的MBC電晶體。
參照第4A-4C圖和第5A-5C圖,方法100包括方框106(第1A圖),在鰭片溝槽212中形成隔離部件216。隔離部件216可以稱為淺溝隔離(shallow trench isolation;STI)部件216。在形成隔離部件216的示例製程中,在工件200
上沉積介電材料,用介電材料填充鰭片溝槽212。在一些實施例中,介電材料可包含四氯矽酸鹽(tetraethylorthosilicate;TEOS)氧化物、未摻雜的矽玻璃、或摻雜的矽氧化物,如硼磷矽玻璃(borophosphosilicate glass;BPSG)、熔矽石玻璃(fused silica glass;FSG)、磷矽玻璃(phosphosilicate glass;PSG)、摻硼矽玻璃(boron doped silicon glass;BSG)及/或其它合適的介電材料。各種示例中,在方框106中,介電材料可以透過可流動的CVD(flowable CVD;FCVD)、旋塗及/或其它合適的製程進行沉積。然後,將沉積的介電材料稀釋和平坦化,例如透過化學機械拋光(chemical mechanical polishing;CMP)製程,直到暴露出硬遮罩層214,如第4A-4C圖所示。在平坦化之後,在回蝕製程中將沉積的介電材料進行凹蝕,直到鰭狀結構210的頂部部分210Top,特別是犧牲層206和通道層208,突出於隔離部件216之上。硬遮罩層214也可在回蝕製程中移除。在所繪示的實施例中,如第5A-5C圖所示,上方的半導體層208B的頂部部分也可以突出於隔離部件216之上。此時,底部部分210Base、底部犧牲層206B和上方的半導體層208B的底部部分被隔離部件216所包圍。隔離部件216減少了鰭片溝槽212的深度。
參照第6A-6C圖和第7A-7C圖,方法100包括方框108(第1A圖),形成第一介電鰭片218。在所繪示的實施例中,在方框108中,第一介電鰭片218形成於較窄的鰭片溝槽212B中。形成第一介電鰭片218的示例製程包含依序在工件200上共形沉積第一介電層220和第二介電層222,包含在較寬的鰭片溝槽212A中。第二介電層222被第一介電層220包圍。第一介電層220可以使用CVD、ALD或合適的方法進行共形沉積。第一介電層220將較寬的鰭片溝槽的側壁和底表面212A和212B進行排列。接著使用CVD、高密度電漿CVD(high density plasma CVD;HDPCVD)及/或其它合適的製程在第一介電層220上共形沉積第二介電層
222。在某些情況下,第二介電層222的介電常數比第一介電層220的介電常數小。第一介電層220可包含矽、氮化矽、碳化矽、碳氧化矽(silicon oxycarbonitride)、氧化鋁、氮化鋁、氮氧化鋁(aluminum oxynitride)、氧化鋯、氮化鋯、氧化鋯鋁(zirconium aluminum oxide)、氧化鉿,或合適的介電材料。在一實施例中,第一介電層220包含氧化鋁。第二介電層222可包含氧化矽、碳化矽、氮氧化矽(silicon oxynitride)、碳氧化矽,或合適的介電材料。在一實施例中,第二介電層222包含氧化矽。在第6A-6C圖所示的一些實施例中,由於鰭片溝槽212之間的寬度差異,第二介電層222完全地填充較窄的鰭片溝槽212B,但不完全地填充較寬的鰭片溝槽212A。隨後,示例製程將共形沉積的介電層220和222進行回蝕,以暴露出頂部的犧牲層206T,並從較寬的鰭片溝槽212A中移除介電層220和222。在一些實施例中,可在乾式蝕刻製程中將介電層220和222回蝕,上述製程使用氧氣、氮氣、含氟氣體(例如CF4、SF6、CH2F2、CHF3及/或C2F6)、含氯氣體(例如。Cl2、CHCl3、CCl4及/或BCl3)、含溴氣體(例如HBr及/或CHBr3)、含碘氣體、其它合適的氣體及/或電漿,及/或其組合。在一些實施例中,回蝕可包含針對第二介電層222的第一階段和針對第一介電層220的第二階段。與完全由介電層220和222填充的較窄的鰭片溝槽212B不同,較寬的鰭片溝槽212A允許蝕刻劑從溝槽內將介電層220和222的側壁和底表面進行蝕刻,使得介電層220和222從較寬的鰭片溝槽212A移除的速度比從較窄的鰭片溝槽212B移除的速度快。如第7A-7C圖所示,方框108結束時,介電層220和222從較寬的鰭片溝槽212A移除,而介電層220和222一起在較窄的鰭片溝槽212B中定義第一介電鰭片218。
參照第8A-8C圖和第9A-9C圖,方法100包括方框110(第1A圖),形成第二介電鰭片224。在所繪示的實施例中,在方框110中,第二介電鰭片224
形成於較寬的鰭片溝槽212A中。形成第二介電鰭片224的示例製程包含,在方框108結束時暴露出較寬的鰭片溝槽212A,在工件200上沉積披覆層226,包含在較寬的鰭片溝槽212A的側壁上。在一些實施例中,披覆層226可以具有與犧牲層206或頂部犧牲層206T相似的組成。在一示例中,披覆層226可以由矽鍺(SiGe)形成。它們的共同組成允許在後續的蝕刻製程中選擇性地且同時地移除犧牲層206和披覆層226。在一些實施例中,披覆層226可以使用氣相磊晶(VPE)或分子束磊晶(MBE)進行共形和磊晶生長。如第8A-8C圖所示,將披覆層226選擇性地設置在較寬的鰭片溝槽212A中露出的側壁表面上。根據披覆層226的選擇性生長的程度,可以進行回蝕製程以暴露出隔離部件216。隨後,如第9A-9B圖所示,此示例製程將第三介電層228和第四介電層230共形沉積至鰭片溝槽212A中。第四介電層230被第三介電層228所包圍。第三介電層228的組成和形成可以與第一介電層220相同或大抵上相似,而第四介電層230的組成和形成可以與第二介電層222相同或大抵上相似。或者,第三介電層228的組成和形成可以與第一介電層220的不同,而第四介電層230的組成和形成可以與第二介電層222的不同。在一些實施例中,第三介電層228可以使用CVD、HDPCVD或可流動CVD(FCVD)進行沉積,第四介電層230可以使用FCVD進行沉積。在沉積介電層228和230後,使用化學機械拋光(CMP)製程對工件200進行平坦化,以暴露出頂部的犧牲層206T。如第9A-9C圖所示,在CMP製程結束後,介電層228和230共同定義較寬的鰭片溝槽212A中的第二介電鰭片224。在各種實施例中,第二介電鰭片224的寬度可以與第一介電鰭片218的寬度相同或更寬。
參照第10A-10C圖,方法100包括方框112(第1A圖),將鰭狀結構210中的頂部犧牲層206T移除。在方框112中,將工件200進行蝕刻,以選擇性
地移除頂部犧牲層206T和披覆層226的一部分,以暴露出最頂部的通道層208,而非實質性的損壞介電鰭片218和224。在某些情況下,由於頂部犧牲層206T和披覆層226是由矽鍺(SiGe)形成的,方框112的蝕刻製程可以對矽鍺(SiGe)有選擇性。例如,披覆層226和頂部犧牲層206T可以使用選擇性濕式蝕刻製程,包含氫氧化銨(NH4OH)、氟化氫(HF)、過氧化氫(H2O2),或其組合。在移除頂部犧牲層206T和部分披覆層226後,介電鰭片218和224在最頂層通道層208上方浮現。
參照第11A-11C圖,方法100包括方框114(第1A圖),在鰭狀結構210的通道區上形成虛設閘極堆疊240。在一些實施例中,採用了閘極替代製程(或閘極後置製程),其中虛設閘極堆疊240作為功能性閘極結構(functional gate structure)的預留位置。其它製程和配置是可能的。在所繪示的實施例中,虛設閘極堆疊240包含虛設介電層242和設置在虛設介電層242上的虛設電極244。以圖案化為目的,在虛設閘極堆疊240上沉積閘極頂部硬遮罩246。閘極頂部硬遮罩246可以是多層的,包含氮化矽遮罩層248和在氮化矽遮罩層248上的氧化矽遮罩層250。鰭狀結構210在虛設閘極堆疊240下方的區域可稱為通道區。鰭狀結構210中的每一個通道區都被夾在兩個源極/汲極區之間以形成源極/汲極。在一示例製程中,透過CVD將虛設介電層242毯覆沉積(blanketly deposited)在工件200上。接著將用於虛設電極244的材料層毯覆沉積在虛設介電層242上。然後用微影製程對虛設介電層242和用於虛設電極244的材料層進行圖案化,以形成虛設閘極堆疊240。在一些實施例中,虛設介電層242可包含氧化矽,虛設電極244可包含多晶矽。
參照第12A-12C圖,方法100包括方框116(第1A圖),沿虛設閘極
堆疊240的側壁形成閘極間隔物252。閘極間隔物252可包含兩個或更多的閘極間隔物。可以選擇用於閘極間隔物252的介電材料,以允許選擇性地移除虛設閘極堆疊240。合適的介電材料可包含氮化矽、碳氧化矽、碳化矽、氧化矽、碳氧化矽、碳化矽、氮氧化矽及/或其組合。在一示例中,可以用CVD、次常壓CVD(subatmospheric CVD;SACVD)或ALD在工件200上共形沉積閘極間隔物252,然後進行異向性蝕刻以移除水平部分,而閘極間隔物252的垂直部分留在虛設閘極堆疊240的側壁上。
繼續參照第12A-12C圖,方法100包括方框118(第1A圖),其中將鰭狀結構210的源極/汲極區凹蝕以形成源極凹槽和汲極凹槽,統稱為源極/汲極凹槽254(或源極/汲極溝槽)。以虛設閘極堆疊240和閘極間隔物252作為蝕刻遮罩,對工件200進行異向性蝕刻,以在鰭狀結構210的源極/汲極區上形成源極/汲極凹槽254。在所繪示的實施例中,方框118的操作將犧牲層206、通道層208、披覆層226以及上方的半導體層208B的頂部部分從源極/汲極區移除,從而暴露出隔離部件216。在一些實施例中,源極/汲極凹槽254可以延伸至上方的半導體層208B中,並位於隔離部件216的頂表面下方。方框118的異向性蝕刻可包含乾式蝕刻製程。例如,乾式蝕刻製程可以使用氫氣、含氟氣體(例如CF4、SF6、CH2F2、CHF3及/或C2F6)、含氯氣體(例如Cl2、CHCl3、CCl4及/或BCl3)、含溴氣體(例如HBr及/或CHBr3)、含碘氣體、其它合適的氣體及/或電漿,及/或其組合。
參照第13A-13C圖,方法100包括方框120,透過蝕刻製程將源極區中的源極/汲極凹槽254進一步延伸至上方的半導體層208B中以形成深源極/汲極凹槽254S。在所繪示的實施例中,深源極/汲極凹槽254S位於介電鰭片218和224之間。在方框120的蝕刻製程之前,可以形成圖案化遮罩(未顯示),以限制源
極區的蝕刻製程。在其它實施例中,方框120的操作可以替代地在汲極區、或源極區與汲極區兩者中延伸(多個)源極/汲極凹槽。在本揭露中,源極和汲極可互換使用。方框120的蝕刻可以使用乾式蝕刻製程(傾向於異向性)或濕式蝕刻製程(傾向於等向性)來進行。選擇性濕式蝕刻製程的示例可包含使用乙二胺焦油(ethylenediamine pyrocatechol;EDP)、四甲基氫氧化銨(tetramethylammonium hydroxide;TMAH)、硝酸(HNO3)、氫氟酸(HF)、氨(NH3)、氟化銨(NH4F)或合適的濕式蝕刻劑。選擇性乾式蝕刻製程的示例可包含六氟化硫(SF6)、氫氣(H2)、氨氣(NH3)、氟化氫(HF)、四氟化碳(CF4)、氬氣(Ar),或其混合物。在所繪示的實施例中,深源極/汲極凹槽254S設置於底部犧牲層206B以上的層級。在一些替代性實施例中,底部犧牲層206B在方框120的蝕刻製程中作為蝕刻停止層,而深源極/汲極凹槽254S暴露出底部犧牲層206B的頂表面。又如第13A圖所示,由於第一介電鰭片218的側壁和下方的隔離部件216大抵上是齊平(flushed)的,深源極/汲極凹槽254S在第一介電鰭片218的一側具有直側壁,在第二介電鰭片224的一側具有階梯側壁。
繼續參照第13A-13C圖,方法100包括方框122,形成內間隔部件256。在一些實施例中,在方框122中,暴露在源極/汲極凹槽254和深源極/汲極凹槽254S中的犧牲層206首先被選擇性地且部分地凹蝕以形成內間隔凹槽,而暴露出的通道層208大抵上沒有被蝕刻。因為披覆層226和犧牲層206有相似的組成,也可以在方框122將披覆層226凹蝕。在一實施例中,通道層208基本上由矽(Si)組成,犧牲層206基本上由矽鍺(SiGe)組成,而披覆層226基本上由矽鍺(SiGe)組成,犧牲層206和披覆層226的選擇性和部分凹蝕可以包括一個SiGe氧化製程,然後移除SiGe氧化物。在該實施例中,SiGe氧化製程可包含使用臭氧。在
一些其它實施例中,部分凹蝕可包含選擇性蝕刻製程(例如,選擇性乾式蝕刻製程或選擇性濕蝕刻製程),犧牲層206和披覆層226凹蝕的程度由蝕刻製程的持續時間控制。選擇性乾式蝕刻製程可包含使用一種或多種氟基蝕刻劑,如氟氣或氫氟碳化物。選擇性濕式蝕刻製程可包含氫氧化銨(NH4OH)、氟化氫(HF)、過氧化氫(H2O2),或其組合(例如,包含氫氧化銨-過氧化氫-水混合物的APM蝕刻)。在形成內間隔凹槽後,接著使用CVD或ALD在工件200上共形沉積內間隔材料層,包含在內間隔凹槽上方和進入內間隔凹槽以及由披覆層226的移除部分留下的空間。內間隔材料可包含氮化矽、碳氧化矽、碳化矽、氧化矽、碳氧化矽、碳化矽或氮氧化矽。在沉積內間隔材料層後,將內間隔材料層回蝕,形成內間隔部件256,如第13A-13C圖所示。
參照第14A-14C圖,方法100包括方框124,形成源極/汲極部件258。源極/汲極部件258選擇性且磊晶沉積在通道層208的暴露半導體表面上和源極/汲極凹槽254和深源極/汲極凹槽254S中的上方的半導體層208B上。源極/汲極部件258可使用磊晶製程沉積,例如氣相磊晶(vapor-phase epitaxy;VPE)、超高真空化學氣相沉積(ultra-high vacuum CVD;UHV-CVD)、分子束磊晶(molecular beam epitaxy;MBE)及/或其它合適的製程。根據工件200的設計,源極/汲極部件258可以是n型或p型。當源極/汲極部件258是n型時,其可包含摻有n型摻雜物的矽(Si)、如磷(P)或砷(As)。當源極/汲極部件258是p型時,其可包含摻有p型摻雜物的矽(SiGe)、如硼(B)或鎵(Ga)。源極/汲極部件258的摻雜可以透過沉積在原位(in situ)進行,或使用植入製程在異位(ex situ)進行,如接面植入製程(junction implant process)。在深源極/汲極凹槽254S中形成的源極/汲極部件258具有延伸底部部分258B,延伸底部部分258B比形成在源極/汲極凹槽254中
的其他源極/汲極部件258更深入地延伸至工件200的背側。延伸底部部分258B保留了用於後續製造過程中形成背側自對準源極/汲極接觸件的空間。如上所述,在第14A圖所示的說明性實施例中,具有延伸底部部分258B的源極/汲極部件258是形成於源極區的源極部件,而其兩側的其它兩個源極/汲極部件258是形成於汲極區的汲極部件。然而,另一種情況為,具有延伸底部部分258B的源極/汲極部件258可以是汲極部件,而其兩側的另外兩個源極/汲極部件258可以是源極部件。在本揭露中,源極和汲極是可以互換使用的。又如第14A圖所示,在源極/汲極凹槽254的側壁和深源極/汲極凹槽254S的臺階區(step region),源極/汲極部件258的切面(facet)可以將孔隙260封閉在源極/汲極部件258和介電部件,如第二介電鰭片224和隔離部件216之間。作為比較,由於源極/汲極凹槽254的直側壁和第一介電鰭片218一側上的深源極/汲極凹槽254S,孔隙260可能不會如所繪示的實施例所示在直側壁上形成。
繼續參照第14A-14C圖,方法100包括方框126(第1A圖),其中在工件200的前側上沉積接觸蝕刻停止層(contact etch stop layer;CESL)262和層間介電(interlayer dielectric;ILD)264層。在一示例中,CESL 262首先在工件200上共形沉積,然後ILD層264在CESL 262上毯覆沉積。CESL 262可包含氮化矽、氧化矽、氮氧化矽及/或本領域內已知的其它材料。CESL 262可以使用ALD、電漿增強化學氣相沉積(plasma-enhanced chemical vapor deposition;PECVD)製程及/或其它合適的沉積或氧化製程進行沉積。在一些實施例中,ILD層264包含如四氯矽酸鹽(tetraethylorthosilicate;TEOS)氧化物、未摻雜的矽玻璃或摻雜的氧化矽,如硼磷矽玻璃(BPSG)、熔矽石玻璃(FSG)、磷矽玻璃(PSG)、硼摻雜矽玻璃(BSG)及/或其它合適的介電材料。ILD層264可以透
過旋塗、FCVD製程或其它合適的沉積技術進行沉積。在一些實施例中,在形成ILD層264後,可對工件200進行退火以改善ILD層264的完整性。為了移除多餘的材料(包含閘極頂部硬遮罩246)並暴露出虛設閘極堆疊240的虛設電極244的頂表面,可對工件200進行平坦化製程(例如CMP製程),以提供平坦化的頂表面。虛設電極244的頂表面暴露在平坦的頂表面上。
參照第15A-15C圖,方法100包括方框128(第1A圖),選擇性地移除虛設閘極堆疊240和犧牲層206。在方框126結束時暴露出的虛設閘極堆疊240透過選擇性蝕刻製程從工件200上移除。選擇性蝕刻製程可以是選擇性濕式蝕刻製程、選擇性乾式蝕刻製程,或其組合。在所述的實施例中,選擇性蝕刻製程選擇性地移除虛設介電層242和虛設電極244,而不對通道層208和閘極間隔物252造成實質性損壞。移除虛設閘極堆疊240,使閘極溝槽266位於通道區上。在移除虛設閘極堆疊240後,通道區的通道層208、犧牲層206和披覆層226暴露在閘極溝槽266中。隨後,方框128的操作選擇性地將犧牲層206和披覆層226從閘極溝槽266中移除,以釋出通道層208。方框128結束時釋出的通道層208也被示為通道構件208。在所述的實施例中,通道構件208類似於片材或奈米片,通道構件釋出製程(release process)也可稱為片材形成製程。通道構件208沿Z方向垂直地堆疊。所有的通道構件208都與第二介電鰭片224間隔開,而一些與第一介電鰭片218毗鄰的通道構件208則從第一介電鰭片218的側壁橫向地延伸。犧牲層206和披覆層226的選擇性移除可以透過選擇性乾式蝕刻、選擇性濕式蝕刻或其它選擇性蝕刻製程來實現。在一些實施例中,選擇性濕式蝕刻包含氫氧化銨(NH4OH)、氟化氫(HF)、過氧化氫(H2O2),或其組合(例如,包括氫氧化銨-過氧化氫-水混合物的APM蝕刻)。在一些替代性的實施例中,選擇性移除
包含矽鍺氧化(silicon germanium oxidation),然後再移除矽鍺氧化物(silicon germanium oxide)。例如,可以透過臭氧清潔提供氧化,然後透過蝕刻劑(如NH4OH)移除矽鍺氧化物。隨著犧牲層206和披覆層226從通道區移除,介電鰭片218和224、通道構件208、上方的半導體層208B的頂表面、內間隔部件258和隔離部件216暴露在閘極溝槽266中。
參照第16A-16C圖,方法100包括方框130(第1A圖),第一介電鰭片218和第二介電鰭片224透過選擇性地移除外介電層--第一介電層220和第三介電層228而減薄寬度。介電鰭片218和224的薄化提供了較大的閘極溝槽體積,進而促進即將形成的功能性閘極結構中各種介電和金屬層的沉積。暴露在閘極溝槽266中的介電層220和228透過選擇性蝕刻製程從通道區移除。選擇性蝕刻製程可以是選擇性濕式蝕刻製程、選擇性乾式蝕刻製程,或其組合。在所述的實施例中,選擇性蝕刻製程可以選擇性地移除介電層220和228,而不對介電層222和230造成實質性損壞。如上所述,介電層220和228可包含相同或相似的組成,而選擇性蝕刻製程可以在一個階段內移除兩個介電層;或者,介電層220和228可包含不同的組成,而選擇性蝕刻製程可包含針對介電層220和228中的一個的第一階段和針對另一個的第二階段。如第16B圖所示,由於暴露於蝕刻劑的面積較小,相應地蝕刻率也較小,因此夾在通道構件208和第二介電層222之間的第一介電層220的一些部分,以及堆疊在第二介電層222和隔離部件216之間的第一介電層220的一些部分可以留下。同樣地,堆疊在第四介電層230和隔離部件216之間的第三介電層228的一些部分可以留下。此外,由於與第一介電鰭片218毗鄰的上述通道構件208的遮罩作用,堆疊在第二介電層222和隔離部件216之間的第一介電層220的部分可能具有比第二介電層222較大的寬度,並且可能完全覆
蓋下方的隔離部件216。作為比較,堆疊在第四介電層230和隔離部件216之間的第三介電層228的部分可以具有與第四介電層230相同或比其更小的寬度,並且暴露出下方的隔離部件216。雖然沒有顯示,但在一些替代實施例中,選擇性蝕刻製程可以從閘極溝槽266完全移除介電層220和228,從而使通道構件208與第一介電鰭片218和第二介電鰭片224間隔開。
參照第17A-17C圖,方法100包括方框132(第1B圖),閘極結構270(也稱為功能性閘極結構或金屬閘極結構)在閘極溝槽266中形成以與通道構件208中的每一個嚙合。每個閘極結構270包含設置在通道構件208上的閘極介電層272和閘極介電層272上的閘極電極層274。在一些實施例中,閘極介電層272包含介面層和高k介電層。介面層可包含氧化矽,氧化矽的形成為預清潔製程的結果。預清潔製程的示例可包含使用RCA SC-1(氨、過氧化氫和水)及/或RCA SC-2(鹽酸、過氧化氫和水)。預清潔處使通道構件208所暴露出的表面氧化,以形成介面層。然後使用ALD、CVD及/或其它合適的方法將高k介電層沉積在介面層上。高k介電層包含高k介電材料。在一實施例中,高k介電層可包含氧化鉿。或者,高k介電層可包含其它高k介電材料,如氧化鈦(TiO2)、氧化鋯鉿(hafnium zirconium oxide;HfZrO)、氧化鉭(tantalum oxide;Ta2O5)。氧化鉿矽(hafnium silicon oxide;HfSiO4),氧化鋯(ZrO2),氧化鋯矽(zirconium silicon oxide;ZrSiO2),氧化鑭(La2O3),氧化鋁(Al2O3),氧化鋯(ZrO)。氧化釔(yttrium oxide;Y2O3)、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、氧化鑭鉿(hafnium lanthanum oxide;HfLaO)、氧化鑭矽(lanthanum silicon oxide;LaSiO)、氧化鋁矽(aluminum silicon oxide;AlSiO)、鉿鉭氧化物(hafnium tantalum oxide;HfTaO)、鉿鈦氧化物(hafnium titanium oxide;HfTiO)、(Ba,Sr)TiO3(BST)、
氮化矽(SiN)、氮氧化矽(SiON)、其組合或其它合適的材料。在形成閘極介電層272之後,閘極電極層274沉積在閘極介電層272上。閘極電極層274可以是多層結構,包含至少一個功函數層和一個金屬填充層。舉例來說,至少一個功函數層可包含氮化鈦(TiN)、鈦鋁(TiAl)、氮化鈦鋁(titanium aluminum nitride;TiAlN)、氮化鉭(TaN)、鉭鋁(TaAl)、氮化鉭鋁(tantalum aluminum nitride;TaAlN)、碳化鉭鋁(tantalum aluminum carbide;TaAlC)或碳化鉭(TaC)。金屬填充層可包含鋁(Al)、鎢(W)、鎳(Ni)、鈦(Ti)、釕(Ru)、鈷(Co)、鉑(Pt)、鉭氮化矽(tantalum silicon nitride;TaSiN)、銅(Cu)、其它耐火金屬(refractory metals)、或其它合適的金屬材料或其組合。在各實施例中,閘極電極層274可以透過ALD、PVD、CVD、電子束蒸鍍(e-beam evaporation)或其它合適的製程形成。雖然在圖中沒有明示,但閘極結構270被沉積為聯合閘極結構(joint gate structure),然後被回蝕直到介電鰭片218和224將聯合閘極結構分離成彼此分開的閘極結構270。介質鰭片218和224也在相鄰的閘極結構270之間提供電性隔離。閘極結構270的回蝕可包含使用硝酸、鹽酸、硫酸、氫氧化銨、過氧化氫或其組合的選擇性濕式蝕刻製程。如第17B圖所示,閘極結構270不在第一介電層218和毗鄰的通道構件208之間延伸,因為剩餘的第一介電層220填充了兩者之間的孔隙。另外,如上方與方框130的操作有關的討論,若在某些情況下將介電層220和228從閘極溝槽266中完全移除,通道構件208中的每一個則會因此被各自的閘極結構270所包繞。
參照第18A-18C圖,方法100包括方框134(圖1B),在工件200的前側上形成金屬蓋層(metal cap layer)276、自對準蓋(self-aligned cap;SAC)層278和閘極切割部件280。在一些實施例中,金屬蓋層276可包含鈦(Ti)、氮
化鈦(TiN)、氮化鉭(TaN)、鎢(W)、釕(Ru)、鈷(Co)或鎳(Ni),並且可以使用PVD、CVD或金屬有機化學氣相沉積(metal organic chemical vapor deposition;MOCVD)進行沉積。在一實施例中,金屬蓋層276包含鎢(W),如無氟鎢(fluorine-free tungsten;FFW),並透過PVD沉積。在一些替代性的實施例中,金屬蓋層276是透過MOCVD沉積的,金屬蓋層276的沉積可以選擇性地沉積在閘極結構270上。在金屬蓋層276沉積後,SAC層278透過CVD、PECVD或合適的沉積製程沉積在工件200上。SAC層278可包含氧化矽、氮化矽、碳化矽、氮氧化矽、碳氧化矽、氧化鋁、氮化鋁、氮氧化鋁、氧化鋯、氮化鋯、氧化鋯鋁、氧化鉿、或合適的介電材料。接著進行微影製程和蝕刻製程,對沉積的SAC層278進行蝕刻,形成閘極切割開口(gate cut opening),以暴露出介電鰭片的頂表面,例如所繪示的實施例中的第一介電鰭片218。此後,透過CMP製程沉積並平坦化介電材料,以在閘極切割開口處形成閘極切割部件280。用於閘極切割部件280的介電材料可以使用HDPCVD、CVD、ALD或合適的沉積技術進行沉積。在某些情況下,閘極切割部件280可包含氧化矽、氮化矽、碳化矽、氮氧化矽、碳氧化矽、氧化鋁、氮化鋁、氮氧化鋁、氧化鋯、氮化鋯、氧化鋯鋁、氧化鉿,或合適的介電材料。在一些實施例中,閘極切割部件280和SAC層278可以具有不同的組成,以引入蝕刻選擇性。
參照第19A-19C圖,方法100包括方框136(第1B圖),進行一個或多個前側的產線中段(middle-end-of-line;MEOL)和前側的產線後段(back-end-of-line;BEOL)製程,以形成一個或多個具有埋置於介電層中的接觸件、導孔和金屬線(也稱為金屬導線層)的互連層。在一些實施例中,方框136的操作包含形成源極/汲極接觸件282、源極/汲極接觸導孔284、閘極接觸件286、
閘極接觸導孔288、附加層間介電(ILD)層290、金屬間介電(intermetal dielectric;IMD)層291、IMD層291的介電層中的金屬線、接觸墊等。工件200可進一步包含建立在工件200前側的鈍化層及/或其它層。這些層和一個或多個互連層連接各種電晶體的閘極、源極和汲極電極,以及工件200中的其它電路,以形成部分或整體的積體電路。
參考第19A-19C圖,方法100包括方框138(第1B圖),其中載體292附接到工件200的前側。在一些實施例中,載體292可以是矽晶圓。方框138的操作可以使用任何合適的附接製程(attaching processes),例如直接接合(direct bonding)、混合接合(hybrid bonding)、使用黏合劑或其他接合方法。在所繪示的實施例中,在工件200的前側上形成黏合層294,並將載體292與工件200的前側相接。方框138的操作可以進一步包含校準(alignment)、退火及/或其它製程。連接載體292後,可以將工件200倒置。這使得可以從工件200的背面接近工件200,以便於進一步的加工。需要注意的是,在下方的圖中,即第20A-32C圖中,工件200為倒置的。
參照第20A-20C圖,方法100包括方框140(第1B圖),將工件200從背側薄化,直到上方的半導體層208B和隔離部件216從工件200的背側暴露出。示例性的薄化製程可包含在第一階段移除基板202,在第二階段移除底部犧牲層206B。在一些實施例中,薄化製程的第一階段包含機械研磨製程(mechanical grinding process),以完全移除基板202,而底部犧牲層206B則作為機械研磨停止層(mechanical grinding stop layer)。在一些實施例中,薄化製程的第一階段包含機械研磨製程和化學薄化製程。在機械研磨製程中,大量的基板202可以被移除。之後,化學薄化製程可將蝕刻化學品應用於工件的背側,以完全移除基板
202,而底部犧牲層206B可作為蝕刻停止層。同樣地,在一些實施例中,薄化製程的第二階段包含機械研磨製程,以完全移除底部犧牲層206B,而上方的半導體層208B(及/或隔離部件216)作為機械研磨停止層。在一些實施例中,薄化製程的第二階段包含機械研磨製程和化學薄化製程。在機械研磨製程中,大量的底部犧牲層206B可以被移除。之後,化學薄化製程可將蝕刻化學品應用於工件的背側,以完全移除底部犧牲層206B,而上方的半導體層208B和隔離部件216可作為蝕刻停止層。
參照第21A-21C圖,方法100包括方框142(第1B圖),將隔離部件216進行選擇性地蝕刻以在工件200的背側形成溝槽296。溝槽296暴露出介電鰭片218和224-特別是第一介電層220和第三介電層228-以及源極/汲極部件258的切面,此切面在源極/汲極區將孔隙260封閉,並且還暴露出介電鰭片218和224以及通道區中的閘極結構270的閘極介電層272。在一些實施例中,方框142的操作運用蝕刻製程,將此製程調整為對隔離部件216中的介電材料有選擇性,而對上方的半導體層208B、源極/汲極部件258、介電鰭片218和224以及閘極介電層272沒有進行蝕刻(或進行最少的蝕刻)。選擇性蝕刻製程可以是乾式蝕刻、濕式蝕刻、反應性離子蝕刻或其它合適的蝕刻方法。
參照第22A-22C圖,方法100包括方框144(第1B圖),將第一介電層220和第三介電層228的暴露部分從溝槽296中進行選擇性地蝕刻。如上所述,第一介電層220和第二介電層222,以及第三介電層228和第四介電層230包含不同的材料組成(例如介電層220和228的高介電材料,介電層222和230的低介電材料)以實現蝕刻的選擇性。方框144的操作運用蝕刻製程,將此製程調整為對第一介電層220和第三介電層228的材料(例如,高k介電材料)有選擇性,而對第
二介電層222和第四介電層230沒有進行蝕刻(或進行最少的蝕刻)。此外,在所繪示的實施例中,共同或類似的組成(如高k介電材料)允許在同一選擇性蝕刻製程中,選擇性且同時移除閘極介電層272的暴露部分以及介電層220和228的溝槽296。選擇性蝕刻製程可以是乾式蝕刻、濕式蝕刻、反應性離子蝕刻或其它合適的蝕刻方法。如第22A圖和第22B圖所示,從溝槽296中移除介電層220和228後,暴露出第二介電層222、第四介電層230和閘極電極層274。
參照第23A-23C圖,方法100包括方框146(第1B圖),透過從溝槽296將第二介電層222和第四介電層230進行選擇性地蝕刻以延伸溝槽296。從溝槽296中移除介電層222和230,暴露出源極/汲極區中的第三介電層228和CESL 262,並暴露出通道區的閘極介電層272、金屬蓋層276和閘極切割部件280。方框146的操作運用蝕刻製程,將此製程調整為對第二介電層222和第四介電層230的材料(例如,低k介電材料)具有選擇性,對第三介電層228和閘極介電層272沒有進行蝕刻(或進行最少的蝕刻)。選擇性蝕刻製程可以是乾式蝕刻、濕式蝕刻、反應性離子蝕刻或其它合適的蝕刻方法。然而在一些替代性的實施例中,第三介電層228和閘極介電層272也可以在選擇性蝕刻製程的額外階段中的方框146被移除,以便進一步放大溝槽296的體積。
參照第24A-24C圖,方法100包括方框148(第1B圖),在工件200的背側沉積密封層298,並蓋住溝槽296中的氣隙300。密封層298的沉積也稱為封蓋製程(capping process)。在一些實施例中,密封層298的沉積材料包含SiN、SiOCN、SiOC、SiCN、其組合或其它合適的材料。密封層298可以透過CVD、PVD、PE-CVD、塗佈製程或其它合適的沉積技術進行沉積。在一實施例中,密封層298是透過PE-CVD製程沉積的,這更容易使沉積的介電材料合併在狹窄的
開口頂部。PE-CVD製程中的參數(例如,壓力、溫度和氣體黏度)以這樣的方式進行調整,即沉積介電材料的間隙填充行為可以保留氣隙300而不完全地填充溝槽296。在本實施例中,PE-CVD製程採用了壓力小於約0.75托和溫度高於約75℃的設置。因此,密封層298的介電材料可以包封(enclose)溝槽296的開口,而不會大量沉積在溝槽296的下部,並保留氣隙300。氣隙300可以從通道區連續延伸到毗鄰的源極/汲極區,在鄰近的閘極結構270之間以及鄰近的源極/汲極部件258之間提供隔離。氣體可位於氣隙300中,例如在沉積密封層298的介電材料期間使用的(多種)氣體或可擴散至氣隙3300中的任何其它種類的氣體。方框148的操作可包含對密封層298進行平坦化製程,例如CMP製程,以從工件200的背側移除過多的介電材料,並暴露出上方的半導體層208B。含氣隙的密封層298與第一介電層220的剩餘部分(與一些通道構件208的側端毗鄰)共同定義鄰近閘極結構270之間橫向地堆疊的隔離結構以提供隔離。此隔離結構也可稱為閘極隔離結構或混合鰭片。
在第24A-24C圖所示的一實施例中,氣隙300停留在閘極結構270的底表面(定義為靠近工件200背側的表面)下方。在第25A-25C圖所示的另一實施例中,氣隙300可以延伸到閘極結構270的底表面之外。將氣隙300延伸到閘極結構270的底表面之外有助於改善閘極結構270之間的隔離。在如第26A-26C圖所示的另一個實施例中,代替在一個溝槽296中的細長的連續氣隙,方框148的封蓋製程可以產生一系列垂直地堆疊於一個溝槽296中的較小氣隙300。最底層的較小氣隙300可以延伸到閘極結構270的底表面之外。在第27A-27C所示的另一實施例中,如上文與方框146相關的討論,可在沉積密封層298之前將第三介電層228和閘極介電層272從溝槽296中移除。透過移除第三介電層228和閘極介電
層272,將密封層298沉積在源極/汲極區中的源極/汲極部件258的側壁上和通道區的閘極電極層274的側壁上。移除第三介電層228和閘極介電層272的一個優點是,溝槽296可以沿Y方向擴展,允許形成具有較大體積的氣隙,進而進一步改善隔離,並減少寄生電容。
參照第28A-28C圖,方法100包括方框150(第1B圖),將上方的半導體層208B進行選擇性地蝕刻以在閘極結構270和源極/汲極部件258的背側上形成溝槽302。溝槽302從工件200的背側暴露出源極/汲極部件258的表面。在一個示例製程中,方框150的操作運用蝕刻製程,將此製程調整為對上方的半導體層208B中的半導體材料(例如矽)具有選擇性,並且對閘極結構270和源極/汲極部件258沒有進行蝕刻(或進行最少的蝕刻)。蝕刻製程可以是乾式蝕刻、濕式蝕刻、反應性離子蝕刻或其它蝕刻方法。
參照第29A-29C圖,方法100包括方框152(第1B圖),介電層304以一種或多種介電材料來填充溝槽302。在一些實施例中,介電層304可包含La2O3、Al2O3、SiOCN、SiOC、SiCN、SiO2、SiC、ZnO、ZrN、Zr2Al3O9、TiO2、TaO2、ZrO2、HfO2、Si3N4、Y2O3、AlON、TaCN、ZrSi或其它合適的材料中的一種或多種,並且可以透過PECVD、FCVD或其它合適的方法形成。方框152的操作還包含對介電層304進行平坦化製程,例如CMP製程,以從工件200的背側移除過多的介電材料,並暴露出源極部件的延伸底部部分258B。
參照第30A-30C圖,方法100包括方框154(第1B圖),透過用導電組成來替換源極部件的延伸底部部分258B,以形成背側自對準源極/汲極接觸件306。形成背側自對準源極/汲極接觸306的示例製程包含在選擇性蝕刻製程中凹蝕延伸底部部分258B,此製程將延伸底部部分258B的磊晶半導體材料調整為對
密封層298和介電層304沒有進行蝕刻(或進行最少的蝕刻),從而形成源極/汲極接觸孔。選擇性蝕刻製程可以是乾式蝕刻、濕式蝕刻、反應性離子蝕刻或其它合適的蝕刻方法。選擇性蝕刻製程還可將暴露源極/汲極接觸孔中的源極部件凹蝕至等於或低於被介電層304覆蓋的其它源極/汲極部件258的程度,以便為後續的矽化物(silicide)形成騰出空間。在一實施例中,方框154的操作在源極部件和背側自對準源極/汲極接觸306之間形成矽化物部件(未顯示),以進一步降低接觸電阻。在一示例中,將一種或多種金屬沉積到源極/汲極接觸孔中,然後對工件200進行退火製程,以造成一種或多種金屬與源極部件之間的反應,從而產生矽化物部件。一種或多種金屬可包含鈦(Ti)、鉭(Ta)、鎢(W)、鎳(Ni)、鉑(Pt)、鐿(Yb)、銥(Ir)、鉺(Er)、鈷(Co)或其組合(例如,兩種或多種金屬的合金),並可使用CVD、PVD、ALD或其它合適的方法進行沉積。矽化物部件可包含矽化鈦(TiSi)、矽化鎳(NiSi)、矽化鎢(WSi)、矽化鎳鉑(nickel-platinum silicide;NiPtSi)、矽化鎳鉑鍺(nickel-platinum-germanium silicide;NiPtGeSi)、鎳鍺矽化物(nickel-germanium silicide;NiGeSi)、矽化鐿(YbSi)、矽化鉑(PtSi)、矽化銥(IrSi)、矽化鉺(ErSi)、矽化鈷(CoSi)、其組合,或其它合適的化合物。或者,可以跳過矽化物的形成,背側自對準源極/汲極接觸件306直接接觸源極部件。背側自對準源極/汲極接觸件306可包含鎢(W)、鈷(Co)、鉬(Mo)、釕(Ru)、銅(Cu)、鎳(Ni)、鈦(Ti)、鉭(Ta)、氮化鈦(TiN)、氮化鉭(TaN),或其它金屬,並可以透過CVD、PVD、ALD、電鍍,或其它合適的製程形成。背側自對準源極/汲極接觸件306被密封層298所包圍。
參照第31A-31B圖,方法100包括方框156(第1B圖),進行一個
或多個背側產線中段(MEOL)和產線後段(BEOL)製程,以形成一個或多個具有埋置於介電層中的接觸件、導孔和金屬線(也稱為金屬導線層)的互連層。在一些實施例中,方框156的操作包含形成一個或多個背側互連層308,其背側動力軌(backside power rail)310埋置於工件200背側上的介電層中。背側動力軌310可包含接觸件、導孔、金屬線及/或其它導電部件。在所繪示的實施例中,背側動力軌310的上部透過作為背側第一層級金屬(M0)軌道(backside first level metal(M0)track)314一部分的背側金屬線312來與背側自對準源極/汲極接觸件306電性連接。在一實施例中,背側動力軌310可以使用鑲嵌製程、雙鑲嵌製程、金屬圖案製程或其它合適的製程形成。背側動力軌可包含鎢(W)、鈷(Co)、鉬(Mo)、釕(Ru)、銅(Cu)、鎳(Ni)、鈦(Ti)、鉭(Ta)、氮化鈦(TiN)、氮化鉭(TaN)或其它金屬,並可透過CVD、PVD、ALD、電鍍或其它合適的製程進行沉積。具有背側動力軌有利於增加工件200中可用的金屬軌帶(metal track)的數量,以直接連接到源極/汲極接觸件和導孔,包含背側自對準源極/汲極接觸件306。背側動力軌可具有比工件200前側上的第一層級金屬(M0)軌帶更寬的尺寸,這有利於減少背側動力軌的阻力。需要注意的是,儘管如第31C圖所示的所產生的結構沒有顯示其它汲極接觸件(或接觸插塞)來電性連接到源極部件兩側上的兩個汲極部件,這種導電部件可以在各種其它實施例中的工件200的前側形成,例如第32A-32C圖所示的金屬接觸插塞316和源極/汲極接觸導孔318,其提供與其它不被背側動力軌偏壓(biased)的源極/汲極部件的電性耦合(electrical coupling)。如上文與方框136相關的討論,金屬接觸插塞316和源極/汲極接觸導孔318可以在一個或多個前側MEOL或BEOL製程中形成。
在方框158中,方法100(第1B圖)對工件200進行進一步的製造
過程。例如,其可以在工件200的背側上形成更多的互連層,在工件200的背側形成鈍化層,進行其它BEOL製程,並移除載體292。
參照第32B圖。在方法100結束後,所繪示的Y-Z平面的剖面圖中,形成由氣隙300分隔的三個MBC電晶體T-1、T-2和T-3。每個MBC電晶體包含與一個或多個通道構件嚙合的閘極結構270。在MBC電晶體T-1中,閘極結構270包繞每個通道構件所有的四個側面。MBC電晶體T-1可以稱為奈米片電晶體。作為比較,由於MBC電晶體T-2和T-3中的通道構件與包含含氣隙的密封層298的混合鰭片的側壁接觸,閘極結構270從另外三個側面與這些通道構件接觸。MBC電晶體T-2和T-3可以稱為叉片式電晶體或魚骨式電晶體。或者,這些MBC電晶體可以稱為具有魚骨/叉片式結構的MBC電晶體。不論是魚骨式(fish-bone)或叉片式(fork-sheet)結構,通道構件之間的緊鄰造成嚙合這些通道構件的閘極結構之間的緊鄰,同時,即使使用低k介電材料作為隔離結構,仍導致閘極結構之間的高寄生電容。透過在鄰近的閘極結構之間實施含有氣隙的混合鰭片作為隔離結構,進一步降低隔離結構的整體有效介電常數,進而導致更少的寄生電容和更佳的隔離。此外,在本揭露的實施例中,氣隙從通道區連續延伸至毗鄰的源極/汲極區中,也為相鄰的源極/汲極區部件提供隔離。
在一個示例性面向,本揭露內容涉及一種方法。上述方法包括:提供工件,包括前側及背側,工件包含遮罩、位於遮罩上的隔離部件、從遮罩突出並穿過隔離部件的第一鰭形結構,以及從遮罩突出並穿過隔離部件的第二鰭形結構,其中遮罩位於工件的背側,並且第一及第二鰭形結構位於工件的前側;在第一及第二鰭形結構之間形成介電鰭片;分別在第一及第二鰭形結構上形成第一及第二閘極結構;從工件的背側蝕刻隔離部件,以形成溝槽,露出介
電鰭片;從工件的背側蝕刻介電鰭片,從而形成延伸溝槽;及在延伸溝槽上沉積密封層,其中密封層覆蓋第一和第二閘極結構之間的氣隙。
在一實施例中,介電鰭片毗鄰(abut)第一及第二鰭狀結構。在一實施例中,溝槽更露出第一及第二閘極結構的一部分。在一實施例中,延伸溝槽露出第一及第二閘極結構的多個閘極介電層。在一實施例中,半導體裝置的形成方法更包括蝕刻這些閘極介電層,以放大延伸溝槽的體積。工件更包含第一源極/汲極部件毗鄰第一鰭狀結構、以及第二源極/汲極部件毗鄰第二鰭狀結構,且其中氣隙連續延伸至夾在第一及第二源極/汲極部件之間的位置。
在一實施例中,介電鰭片的形成包含:在第一及第二鰭狀結構之間的溝槽中沉積第一介電層;並且在溝槽中沉積第二介電層並且被第一介電層包圍,其中第一及第二介電層包含不同材料組成。在一實施例中,在形成第一及第二閘極結構之前,部分地移除第一介電層。在一實施例中,在蝕刻隔離部件之前,從工件的背側薄化遮罩,以露出隔離部件。在一實施例中,在工件的背側形成源極/汲極接觸件,其中源極/汲極接觸件被密封層包圍。
在另一個示例性面向,本揭露內容涉及一種半導體裝置的形成方法。上述方法包括:在遮罩上形成複數個通道構件,這些通道構件垂直地堆疊;形成與這些通道構件的側端毗鄰的介電鰭片;形成與每個通道構件嚙合(engage)嚙合的閘極結構;移除遮罩,從而露出介電鰭片的底表面;移除介電鰭片,從而形成溝槽,溝槽露出閘極結構的側壁;以及在溝槽上沉積介電層,介電層將孔隙封閉在溝槽中。
在一實施例中,在形成閘極結構之前,部分地移除介電鰭片的一外層,其中留下堆疊於遮罩及介電鰭片的內層之間的外層的一部分。在一實施
例中,外層包含介電常數高於內層的介電材料。在一實施例中,孔隙延伸超過閘極結構的底表面。在一實施例中,閘極結構包含閘極介電層及閘極電極層,且方法更包括:從溝槽部分地移除閘極介電層,從而露出溝槽中的閘極電極層。在一實施例中,半導體裝置的形成方法,更包括:形成與這些通道構件毗鄰的源極/汲極部件,其中源極/汲極部件包含被介電層包圍的延伸部分;凹蝕源極/汲極部件的延伸部分,從而形成被介電層包圍的源極/汲極接觸孔;以及在源極/汲極接觸孔中沉積導電部件。
在另一個示例性面向,本揭露涉及一種半導體裝置。”上述半導體裝置包括:複數個第一通道構件,垂直地堆疊;複數個第二通道構件,垂直地堆疊;第一閘極結構,與第一複數個通道構件嚙合;第二閘極結構,與第二複數個通道構件嚙合;第一金屬導線層,位於半導體裝置的前側;第二金屬導線層,位於半導體裝置的背側,其中第一及第二閘極結構垂直地堆疊於第一及第二金屬導線層之間;以及隔離結構,垂直地堆疊於第一及第二金屬導線層之間,其中隔離結構包含在第一及第二閘極結構之間橫向地堆疊的氣隙。
在一實施例中,半導體裝置更包括:第一源極/汲極部件鄰接(adjoin)這些第一通道構件;以及第二源極/汲極部件鄰接這些第二通道構件,其中氣隙連續延伸至在第一及第二源極/汲極部件之間橫向地堆疊的一位置。在一實施例中,氣隙延伸超過第一及第二閘極結構的底表面。在一實施例中,隔離結構包含包圍氣隙的第一介電層,以與這些第一及第二通道構件的側端毗鄰的第二介電層。
以上概述數個實施例之特徵,以使本發明所屬技術領域中具有通常知識者可以更加理解本發明實施例的觀點。本發明所屬技術領域中具有通常
知識者應理解,可輕易地以本發明實施例為基礎,設計或修改其它製程和結構,以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解,此類等效的結構並無悖離本發明的精神與範圍,且可在不違背本發明之精神和範圍下,做各式各樣的改變、取代和替換。因此,本發明之保護範圍當視後附之申請專利範圍所界定為準。
100:方法
132-158:方框
Claims (15)
- 一種半導體裝置的形成方法,包括:提供一工件,包括一前側及一背側,該工件包含一遮罩、位於該遮罩上的一隔離部件、從該遮罩突出並穿過該隔離部件的一第一鰭形結構,以及從該遮罩突出並穿過該隔離部件的一第二鰭形結構,其中該遮罩位於該工件的該背側,並且該第一及該第二鰭形結構位於該工件的該前側;在該第一及該第二鰭形結構之間形成一介電鰭片;分別在該第一及該第二鰭形結構上形成第一及第二閘極結構;從該工件的該背側蝕刻該隔離部件,以形成一溝槽,露出該介電鰭片;從該工件的該背側蝕刻該介電鰭片,從而形成一延伸溝槽;及在該延伸溝槽上沉積一密封層,其中該密封層覆蓋該第一和第二閘極結構之間的一氣隙。
- 如請求項1之半導體裝置的形成方法,其中該介電鰭片毗鄰(abut)該第一及該第二鰭狀結構。
- 如請求項1之半導體裝置的形成方法,其中:該溝槽更露出該第一及該第二閘極結構的一部分;以及該延伸溝槽露出該第一及該第二閘極結構的多個閘極介電層。
- 如請求項3之半導體裝置的形成方法,更包括:蝕刻該些閘極介電層,以放大該延伸溝槽的體積。
- 如請求項1之半導體裝置的形成方法,其中該工件更包含一第一源極/汲極部件毗鄰該第一鰭狀結構、以及一第二源極/汲極部件毗鄰該第二鰭狀結構,且其中該氣隙連續延伸至夾在該第一及該第二源極/汲極部件之間的一位 置。
- 如請求項1之半導體裝置的形成方法,其中該介電鰭片的形成包含:在該第一及該第二鰭狀結構之間的一溝槽中沉積一第一介電層;並且在該溝槽中沉積一第二介電層並且被第一介電層包圍,其中該第一及該第二介電層包含不同材料組成。
- 如請求項6之半導體裝置的形成方法,更包括:在形成該第一及該第二閘極結構之前,部分地移除該第一介電層;在蝕刻該隔離部件之前,從該工件的該背側薄化該遮罩,以露出該隔離部件;以及在該工件的該背側形成一源極/汲極接觸件,其中該源極/汲極接觸件被該密封層包圍。
- 一種半導體裝置的形成方法,包括:在一遮罩上形成複數個通道構件,該些通道構件垂直地堆疊;形成與該些通道構件的側端毗鄰的一介電鰭片;形成與每個通道構件嚙合(engage)嚙合的一閘極結構;移除該遮罩,從而露出該介電鰭片的一底表面;移除該介電鰭片,從而形成一溝槽,該溝槽露出該閘極結構的一側壁;以及在該溝槽上沉積一介電層,該介電層將一孔隙封閉在該溝槽中。
- 如請求項8之半導體裝置的形成方法,更包括:在形成該閘極結構之前,部分地移除該介電鰭片的一外層,其中留下堆疊於該遮罩及該介電鰭片的一內層之間的該外層的一部分;其中 該外層包含介電常數高於該內層的一介電材料。
- 如請求項8之半導體裝置的形成方法,其中該孔隙延伸超過該閘極結構的一底表面。
- 如請求項8之半導體裝置的形成方法,其中該閘極結構包含一閘極介電層及一閘極電極層,且該方法更包括:從該溝槽部分地移除該閘極介電層,從而露出溝槽中的該閘極電極層。
- 如請求項8之半導體裝置的形成方法,更包括:形成與該些通道構件毗鄰的一源極/汲極部件,其中該源極/汲極部件包含被該介電層包圍的一延伸部分;凹蝕該源極/汲極部件的該延伸部分,從而形成被該介電層包圍的一源極/汲極接觸孔;以及在該源極/汲極接觸孔中沉積一導電部件。
- 一種半導體裝置,包括:複數個第一通道構件,垂直地堆疊;複數個第二通道構件,垂直地堆疊;一第一閘極結構,與該第一複數個通道構件嚙合;一第二閘極結構,與該第二複數個通道構件嚙合;一第一金屬導線層,位於該半導體裝置的一前側;一第二金屬導線層,位於該半導體裝置的一背側,其中該第一及該第二閘極結構垂直地堆疊於該第一及該第二金屬導線層之間;以及一隔離結構,垂直地堆疊於該第一及該第二金屬導線層之間,其中該隔離結構包含在該第一及該第二閘極結構之間橫向地堆疊的一氣隙。
- 如請求項13之半導體裝置,更包括:一第一源極/汲極部件鄰接(adjoin)該些第一通道構件;以及一第二源極/汲極部件鄰接該些第二通道構件,其中:該氣隙連續延伸至在該第一及該第二源極/汲極部件之間橫向地堆疊的一位置;以及該氣隙延伸超過該第一及該第二閘極結構的底表面。
- 如請求項13之半導體裝置,其中該隔離結構包含包圍該氣隙的一第一介電層,以與該些第一及第二通道構件的側端毗鄰的一第二介電層。
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