TWI803312B - Semiconductor device with multi-stacking carrier structure - Google Patents

Semiconductor device with multi-stacking carrier structure Download PDF

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TWI803312B
TWI803312B TW111117362A TW111117362A TWI803312B TW I803312 B TWI803312 B TW I803312B TW 111117362 A TW111117362 A TW 111117362A TW 111117362 A TW111117362 A TW 111117362A TW I803312 B TWI803312 B TW I803312B
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layer
insulating layer
via hole
passivation layer
semiconductor device
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TW202327049A (en
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李維中
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南亞科技股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings

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Abstract

The present application discloses a semiconductor device. The semiconductor device includes an inter-dielectric layer on a substrate; a conductive pad in the inter-dielectric layer; and a multi-stacking carrier structure including a first tier on the inter-dielectric layer, a second tier on the first tier, and a third tier on the second tier.

Description

具有多堆疊載體結構之半導體元件Semiconductor element with multi-stacked carrier structure

本申請案主張美國第17/561,151及17/560,548號專利申請案之優先權(即優先權日為「2021年12月23日」)，其內容以全文引用之方式併入本文中。 This application claims priority to US Patent Application Nos. 17/561,151 and 17/560,548 (ie, the priority date is "December 23, 2021"), the contents of which are incorporated herein by reference in their entirety.

本揭露係關於一種半導體元件。特別是關於一種具有多堆疊載體結構之半導體元件。 The present disclosure relates to a semiconductor device. In particular, it relates to a semiconductor element with a multi-stacked carrier structure.

半導體元件已運用在各種電子應用上，像是個人電腦、手機、數位相機以及其他的電子設備。半導體元件的尺寸不斷微縮化，以滿足對不斷增長的計算能力之需求。但是，在微縮化的製程期間會出現各種問題，而且這些問題還在不斷增加。因此，在達到提高品質、產率、性能、和可靠性以及降低複雜度方面仍然存在挑戰。 Semiconductor devices have been used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor devices continues to shrink to meet the ever-increasing demand for computing power. However, various problems arise during the miniaturization process, and these problems are still increasing. Accordingly, challenges remain in achieving improvements in quality, yield, performance, and reliability, as well as reductions in complexity.

上文之「先前技術」說明僅係提供背景技術，並未承認上文之「先前技術」說明揭示本揭露之標的，不形成本揭露之先前技術，且上文之「先前技術」之任何說明均不應做為本案之任一部分。 The above "prior art" description is only to provide background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not form the prior art of this disclosure, and any description of the above "prior art" shall not form any part of this case.

本揭露之一方面提供一種半導體元件，包括：一基板；一 中間介電層，位於該基板上；一導電襯墊，位於該中間介電層中；以及一多堆疊載體結構。該多堆疊載體結構包括：一第一層，包括位於該中間介電層上的一第一鈍化層、位於該第一鈍化層上的一第一絕緣層、以及一第一通孔，其中該第一通孔沿著該第一鈍化層和該第一絕緣層設置且電性連接至該導電襯墊；一第二層，位於該第一層上且包括位於該第一絕緣層上的一第二鈍化層、位於該第二鈍化層上的一第二絕緣層、以及一第二通孔，其中該第二通孔沿著該第二鈍化層和該第二絕緣層設置且電性連接至該第一通孔；以及一第三層，位於該第二層上且包括位於該第二絕緣層上的一第三鈍化層、位於該第三鈍化層上的一第三絕緣層、以及一第三通孔，其中該第三通孔沿著該第三鈍化層和該第三絕緣層設置且電性連接至該第二通孔。 One aspect of the present disclosure provides a semiconductor device, including: a substrate; a An intermediate dielectric layer is located on the substrate; a conductive pad is located in the intermediate dielectric layer; and a multi-stacked carrier structure. The multi-stack carrier structure includes: a first layer including a first passivation layer on the intermediate dielectric layer, a first insulating layer on the first passivation layer, and a first via hole, wherein the A first through hole is arranged along the first passivation layer and the first insulating layer and is electrically connected to the conductive pad; a second layer is located on the first layer and includes a layer located on the first insulating layer A second passivation layer, a second insulating layer on the second passivation layer, and a second through hole, wherein the second through hole is arranged along the second passivation layer and the second insulating layer and is electrically connected to the first via hole; and a third layer on the second layer and including a third passivation layer on the second insulating layer, a third insulating layer on the third passivation layer, and A third through hole, wherein the third through hole is disposed along the third passivation layer and the third insulating layer and is electrically connected to the second through hole.

本揭露之另一方面提供一種多堆疊載體結構，包括：一蝕刻停止層；一第一層，包括位於該蝕刻停止層上的一第一鈍化層、位於該第一鈍化層上的一第一絕緣層、以及一第一通孔，其中該第一通孔沿著該第一鈍化層和該第一絕緣層設置；一第二層，位於該第一層上且包括位於該第一絕緣層上的一第二鈍化層、位於該第二鈍化層上的一第二絕緣層、以及一第二通孔，其中該第二通孔沿著該第二鈍化層和該第二絕緣層設置且電性連接至該第一通孔；以及一第三層，位於該第二層上且包括位於該第二絕緣層上的一第三鈍化層、位於該第三鈍化層上的一第三絕緣層、以及一第三通孔，其中該第三通孔沿著該第三鈍化層和該第三絕緣層設置且電性連接至該第二通孔。 Another aspect of the present disclosure provides a multi-stack carrier structure, including: an etch stop layer; a first layer including a first passivation layer on the etch stop layer, a first passivation layer on the first passivation layer an insulating layer, and a first through hole, wherein the first through hole is arranged along the first passivation layer and the first insulating layer; a second layer, located on the first layer and including the first insulating layer a second passivation layer on the second passivation layer, a second insulating layer on the second passivation layer, and a second via hole, wherein the second via hole is arranged along the second passivation layer and the second insulating layer and electrically connected to the first through hole; and a third layer on the second layer and including a third passivation layer on the second insulating layer, a third insulating layer on the third passivation layer layer, and a third via hole, wherein the third via hole is disposed along the third passivation layer and the third insulating layer and is electrically connected to the second via hole.

本揭露之另一方面提供一種半導體元件的製備方法，包括：提供一基板；形成一中間介電層於該基板上；形成一導電襯墊於該中 間介電層中；形成一第一層於該中間介電層上，其中該第一層包括位於該中間介電層上的一第一鈍化層、位於該第一鈍化層上的一第一絕緣層、以及一第一通孔，其中該第一通孔沿著該第一鈍化層和該第一絕緣層設置且電性連接至該導電襯墊；形成一第二層於該第一層上，其中該第二層包括位於該第一絕緣層上的一第二鈍化層、位於該第二鈍化層上的一第二絕緣層、以及一第二通孔，其中該第二通孔沿著該第二鈍化層和該第二絕緣層設置且電性連接至該第一通孔；以及形成一第三層於該第二層上，其中該第三層包括位於該第二絕緣層上的一第三鈍化層、位於該第三鈍化層上的一第三絕緣層、以及一第三通孔，其中該第三通孔沿著該第三鈍化層和該第三絕緣層設置且電性連接至該第二通孔。該第一層、該第二層、和該第三層一起構成一多堆疊載體結構。 Another aspect of the present disclosure provides a method of manufacturing a semiconductor device, including: providing a substrate; forming an intermediate dielectric layer on the substrate; forming a conductive pad in the In the dielectric layer; form a first layer on the dielectric layer, wherein the first layer includes a first passivation layer on the dielectric layer, a first passivation layer on the first passivation layer an insulating layer, and a first via hole, wherein the first via hole is arranged along the first passivation layer and the first insulating layer and is electrically connected to the conductive pad; forming a second layer on the first layer , wherein the second layer includes a second passivation layer located on the first insulating layer, a second insulating layer located on the second passivation layer, and a second via hole, wherein the second via hole is along the disposed along the second passivation layer and the second insulating layer and electrically connected to the first through hole; and forming a third layer on the second layer, wherein the third layer includes a a third passivation layer, a third insulating layer on the third passivation layer, and a third via hole, wherein the third via hole is arranged along the third passivation layer and the third insulating layer and electrically connected to the second via. The first layer, the second layer, and the third layer together form a multi-stack carrier structure.

本揭露之另一方面提供一種半導體元件的製備方法，包括：提供一犧牲載體；暫時附接一蝕刻停止層於該犧牲載體上；形成一多堆疊載體結構於該蝕刻停止層上，其中該多堆疊載體結構包括：一第一層，位於該蝕刻停止層上；一第二層，位於該第一層上；以及一第三層，位於該第二層上；提供一基板；形成一中間介電層於該基板上；形成一導電襯墊於該中間介電層中；翻轉該多堆疊載體結構並接合該多堆疊載體結構至該中間介電層上；從該蝕刻停止層分離該犧牲載體；以及薄化該基板。 Another aspect of the present disclosure provides a method for fabricating a semiconductor device, including: providing a sacrificial carrier; temporarily attaching an etch stop layer on the sacrificial carrier; forming a multi-stacked carrier structure on the etch stop layer, wherein the multiple The stacked carrier structure includes: a first layer located on the etch stop layer; a second layer located on the first layer; and a third layer located on the second layer; providing a substrate; forming an interposer an electrical layer on the substrate; forming a conductive pad in the intermediate dielectric layer; flipping the multi-stacked carrier structure and bonding the multi-stacked carrier structure to the intermediate dielectric layer; separating the sacrificial carrier from the etch stop layer ; and thinning the substrate.

由於本揭露之半導體元件的設計，多堆疊載體結構可以用作暫時載體以輔助基板的薄化製程。因此，在基板的薄化製程期間不需要載體。其結果，可以降低半導體元件的製造成本。此外，在薄化製程之後，多堆疊載體結構可以提供連接到半導體元件的元件構件的電性路徑。 因此，在多堆疊載體結構存在的情況下，可以容易地分析半導體元件的性能。 Due to the design of the semiconductor device of the present disclosure, the multi-stacked carrier structure can be used as a temporary carrier to assist in the thinning process of the substrate. Therefore, no carrier is required during the thinning process of the substrate. As a result, the manufacturing cost of the semiconductor element can be reduced. Furthermore, after the thinning process, the multi-stacked carrier structure can provide electrical paths connected to the device components of the semiconductor device. Therefore, the performance of semiconductor elements can be easily analyzed in the presence of multi-stacked carrier structures.

上文已相當廣泛地概述本揭露之技術特徵及優點，俾使下文之本揭露詳細描述得以獲得較佳瞭解。形成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解，可相當容易地利用下文揭示之概念與特定實施例可做為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解，這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。 The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages forming the subject of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.

1A:半導體元件 1A: Semiconductor components

1B:半導體元件 1B: Semiconductor components

1C:半導體元件 1C: Semiconductor components

1D:半導體元件 1D: Semiconductor components

10:方法 10: method

20:方法 20: method

101:基板 101: Substrate

103:中間介電層 103:Intermediate dielectric layer

105:導電襯墊 105: Conductive gasket

200:多堆疊載體結構 200: Multi-stack carrier structure

203:頂部鈍化層 203: Top passivation layer

203O:第一頂部開口 203O: first top opening

205:重分佈層 205: Redistribution layer

207:蝕刻停止層 207: etch stop layer

207O:第二頂部開口 207O: second top opening

210:第一層 210: first floor

211:第一鈍化層 211: the first passivation layer

213:第一絕緣層 213: The first insulating layer

215:第一通孔 215: the first through hole

215BS:底表面 215BS: bottom surface

215O:第一通孔開口 215O: First through-hole opening

215SW:側壁 215SW: side wall

215TS:頂表面 215TS: Top surface

220:第二層 220: second floor

221:第二鈍化層 221: Second passivation layer

223:第二絕緣層 223: Second insulating layer

225:第二通孔 225: Second through hole

225O:第二通孔開口 225O: Second through-hole opening

225TS:頂表面 225TS: top surface

230:第三層 230: third floor

231:第三鈍化層 231: The third passivation layer

233:第三絕緣層 233: The third insulating layer

235:第三通孔 235: The third through hole

235O:第三通孔開口 235O: Third through-hole opening

235TS:頂表面 235TS: top surface

240:第四層 240: fourth floor

241:第四鈍化層 241: The fourth passivation layer

243:第四絕緣層 243: The fourth insulating layer

245:第四通孔 245: The fourth through hole

245TS:頂表面 245TS: top surface

250:第五層 250: fifth floor

251:第五鈍化層 251: The fifth passivation layer

253:第五絕緣層 253: fifth insulating layer

255:第五通孔 255: Fifth through hole

255TS:頂表面 255TS: top surface

401:犧牲載體 401: sacrificial carrier

510:第一罩幕層 510: The first mask layer

510O:第一圖案化開口 510O: first patterned opening

520:第二罩幕層 520:Second mask layer

520O:第二圖案化開口 520O: second patterned opening

530:第三罩幕層 530: The third mask layer

530O:第三圖案化開口 530O: third patterned opening

AL:黏附層 AL: Adhesion layer

BL:障壁層 BL: barrier layer

FL:填料層 FL: filler layer

IL:隔離層 IL: isolation layer

SL:種子層 SL: seed layer

S11:步驟 S11: step

S13:步驟 S13: step

S15:步驟 S15: step

S21:步驟 S21: step

S23:步驟 S23: step

S25:步驟 S25: step

T0:厚度 T0: Thickness

T1:厚度 T1: Thickness

T2:厚度 T2: Thickness

TL:厚度 TL: Thickness

W0:寬度 W0: width

W1:寬度 W1: width

W2:寬度 W2: width

W3:寬度 W3: width

W4:寬度 W4: width

W5:寬度 W5: width

W6:寬度 W6: width

W7:寬度 W7: width

W8:寬度 W8: width

W9:寬度 W9: width

W10:寬度 W10: width

WC:寬度 WC: width

Z:方向 Z: Direction

本揭露各方面可配合以下圖式及詳細說明閱讀以便了解。要強調的是，依照工業上的標準慣例，各個部件(feature)並未按照比例繪製。事實上，為了清楚之討論，可能任意的放大或縮小各個部件的尺寸。 Various aspects of this disclosure can be read in conjunction with the following diagrams and detailed descriptions for understanding. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily expanded or reduced for clarity of discussion.

圖1根據本揭露一實施例顯示半導體元件的剖面示意圖。 FIG. 1 shows a schematic cross-sectional view of a semiconductor device according to an embodiment of the disclosure.

圖2根據本揭露一實施例顯示製備半導體元件的第一通孔的特寫剖面示意圖。 FIG. 2 is a schematic cross-sectional view showing a close-up of a first through hole for fabricating a semiconductor device according to an embodiment of the present disclosure.

圖3到圖5根據本揭露一些實施例顯示半導體元件的剖面示意圖。 3 to 5 illustrate schematic cross-sectional views of semiconductor devices according to some embodiments of the present disclosure.

圖6根據本揭露一實施例以流程圖的形式顯示半導體元件的製備方法。 FIG. 6 shows a method for fabricating a semiconductor device in the form of a flow chart according to an embodiment of the present disclosure.

圖7到圖21根據本揭露一實施例顯示半導體元件之製備流程的剖面示意圖。 7 to 21 are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment of the present disclosure.

圖22根據本揭露另一實施例顯示半導體元件之製備流程的剖面示意 圖。 FIG. 22 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to another embodiment of the present disclosure picture.

圖23根據本揭露另一實施例以流程圖的形式顯示半導體元件的製備方法。 FIG. 23 shows a method for fabricating a semiconductor device in the form of a flow chart according to another embodiment of the present disclosure.

圖24到圖32根據本揭露另一實施例顯示半導體元件之製備流程的剖面示意圖。 24 to 32 are cross-sectional schematic diagrams showing a manufacturing process of a semiconductor device according to another embodiment of the present disclosure.

圖33根據本揭露另一實施例顯示半導體元件之製備流程的剖面示意圖。 FIG. 33 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to another embodiment of the present disclosure.

以下揭示提供許多不同的實施例或是例子來實行本揭露實施例之不同部件。以下描述具體的元件及其排列的例子以簡化本揭露實施例。當然這些僅是例子且不該以此限定本揭露實施例的範圍。例如，在描述中提及第一個部件形成於第二個部件“之上”或“上”時，其可能包括第一個部件與第二個部件直接接觸的實施例，也可能包括兩者之間有其他部件形成而沒有直接接觸的實施例。此外，本揭露可能在不同實施例中重複參照符號及/或標記。這些重複係為了簡化與清晰的目的，並非用以限定所討論的不同實施例及/或結構之間的關係。 The following disclosure provides many different embodiments or examples for implementing different elements of the disclosed embodiments. Examples of specific components and their arrangement are described below to simplify the embodiments of the present disclosure. Of course, these are just examples and should not limit the scope of the embodiments of the present disclosure. For example, when the description refers to a first component being formed "on" or "on" a second component, it may include embodiments where the first component is in direct contact with the second component, or both. An embodiment in which other components are formed without direct contact between them. In addition, the present disclosure may repeat reference symbols and/or labels in different embodiments. These repetitions are for simplicity and clarity and are not intended to limit the relationship between the different embodiments and/or structures discussed.

此外，本文用到與空間相關的用詞，例如：“在...下方”、“下方”、“較低的”、“之上”、“較高的”、及其類似的用詞係為了便於描述圖式中所示的一個元件或部件與另一個元件或部件之間的關係。這些空間關係詞係用以涵蓋圖式所描繪的方位之外的使用中或操作中的元件之不同方位。裝置可能被轉向不同方位(旋轉90度或其他方位)，則其中使用的空間相關形容詞也可相同地照著解釋。 In addition, the text uses terms related to space, such as: "below", "beneath", "lower", "above", "higher", and similar terms In order to facilitate description of the relationship between one element or component and another element or component shown in the drawings. These spatial relative terms are intended to encompass different orientations of the element in use or operation than that depicted in the drawings. The device may be turned in different orientations (rotated 90 degrees or otherwise) and the spatially relative adjectives used therein may be interpreted similarly.

應理解的是，當一個元件或層被稱為“連接至”或“耦合 至”另一個元件或層時，它可以是直接連接或耦合到另一個元件或層，或者可能存在中間元件或層。 It should be understood that when an element or layer is referred to as being "connected to" or "coupled When "to" another element or layer, it may be directly connected or coupled to the other element or layer, or intervening elements or layers may be present.

應理解的是，儘管本文可以使用第一、第二等用詞來描述各種元件，但是這些元件不應受到這些用詞的限制。除非另有說明，否則這些用詞僅用於區分一個元件與另一個元件。因此，例如，在不脫離本揭露的教示的情況下，以下討論的第一元件、第一組件或第一部分可以被稱為第二元件、第二組件或第二部分 It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. Unless stated otherwise, these terms are only used to distinguish one element from another. Thus, for example, a first element, a first component or a first section discussed below could be termed a second element, a second component or a second section without departing from the teachings of the present disclosure.

除非上下文另外指出，否則本文在提及方位、佈局、位置、形狀、尺寸、數量或其他量度時所使用像是“相同”、“相等”、“平面”、或“共平面”的用詞不一定表示完全相同的方位、佈局、位置、形狀、尺寸、數量或其他量度，而是旨在涵蓋在例如由於製造製程而產生的在可接受變化範圍內幾乎相同的方位、佈局、位置、形狀、尺寸、數量或其他量度。本文中可以使用用詞“實質上(substantially)”來反映此含義。舉例而言，被描述為“實質上相同”、“實質上相等”、或“實質上平面”的項目可以正好相同、相等或平面，或者在例如由於製造製程而產生的在可接受變化範圍內可相同、相等或平面。 Unless the context dictates otherwise, terms such as "same", "equal", "planar", or "coplanar" when used herein to refer to orientation, arrangement, position, shape, size, quantity, or other measure do not necessarily denote exactly the same orientation, arrangement, position, shape, size, quantity or other measure, but are intended to cover nearly the same orientation, arrangement, position, shape, size, quantity or other measure. The term "substantially" may be used herein to reflect this meaning. For example, items described as "substantially the same", "substantially equal", or "substantially planar" may be exactly the same, equal or planar, or within acceptable variations, such as due to manufacturing processes Can be same, equal or flat.

在本揭露中，半導體元件通常是指可以透過利用半導體特性來發揮功用的元件，並且電光元件、發光顯示元件、半導體電路、和電子元件都包括在半導體元件的類別中。 In the present disclosure, a semiconductor element generally refers to an element that can function by utilizing semiconductor properties, and electro-optical elements, light-emitting display elements, semiconductor circuits, and electronic elements are all included in the category of semiconductor elements.

應注意的是，在本揭露的描述中，上方(above)或上(up)對應於方向Z的箭頭方向，下方(below)或下(down)對應相反於方向Z的箭頭方向。 It should be noted that in the description of the present disclosure, above or up corresponds to the arrow direction of the direction Z, and below or down corresponds to the arrow direction opposite to the direction Z.

圖1根據本揭露一實施例顯示半導體元件1A的剖面示意 圖。圖2根據本揭露一實施例顯示製備半導體元件1A的第一通孔215的特寫剖面示意圖。圖3到圖5根據本揭露一些實施例顯示半導體元件1B、1C、和1D的剖面示意圖。 FIG. 1 shows a schematic cross-sectional view of a semiconductor device 1A according to an embodiment of the present disclosure. picture. FIG. 2 shows a close-up cross-sectional view of the first through hole 215 of the semiconductor device 1A according to an embodiment of the present disclosure. 3 to 5 show schematic cross-sectional views of semiconductor devices 1B, 1C, and 1D according to some embodiments of the present disclosure.

參照圖1，半導體元件1A可以包括基板101、複數個元件構件(device elements)(為了清楚起見並未顯示)、中間介電層(inter-dielectric layer)103、複數個導電部件、和多堆疊載體結構200。 Referring to FIG. 1, a semiconductor device 1A may include a substrate 101, a plurality of device elements (device elements) (not shown for clarity), an inter-dielectric layer 103, a plurality of conductive components, and multiple stacks. Carrier structure 200 .

參照圖1，基板101可以包括完全由至少一種半導體材料構成的塊狀半導體基板。塊狀半導體基板可以包括例如元素半導體，像是矽或鍺；化合物半導體，像是矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、銻化銦、或其他第III-V族化合物半導體或第II-VI族化合物半導體、或前述之組合。 Referring to FIG. 1 , the substrate 101 may include a bulk semiconductor substrate entirely composed of at least one semiconductor material. The bulk semiconductor substrate may include, for example, elemental semiconductors such as silicon or germanium; compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other Group III-V compound semiconductors or Group II-VI compound semiconductors, or combinations thereof.

在一些實施例中，基板101的厚度T0可以小於約200μm、小於約50μm、或小於約10μm。例如，基板101的厚度T0可為大約3μm。 In some embodiments, the thickness T0 of the substrate 101 may be less than about 200 μm, less than about 50 μm, or less than about 10 μm. For example, the thickness T0 of the substrate 101 may be about 3 μm.

參照圖1，可以形成該些元件構件於塊狀半導體基板上。該些元件構件的一些部分可以形成於塊狀半導體基板中。該些元件構件可以是電晶體，像是互補式金氧半電晶體(complementary metal-oxide-semiconductor transistors)、金氧半場效電晶體(metal-oxide-semiconductor field-effect transistors)、鰭狀場效電晶體(fin field-effect-transistors)、其類似物、或前述之組合。 Referring to FIG. 1, the element components may be formed on a bulk semiconductor substrate. Some parts of these element components may be formed in a bulk semiconductor substrate. These element components can be transistors, such as complementary metal-oxide-semiconductor transistors, metal-oxide-semiconductor field-effect transistors, fin field effect Transistors (fin field-effect-transistors), their analogs, or combinations thereof.

參照圖1，中間介電層103可以設置在基板101上。在一些實施例中，中間介電層103可以是一疊層結構。中間介電層103可以包括複數個絕緣子層。該些絕緣子層中的每一個可以具有介於大約0.5微米至 大約3.0微米之間的厚度。該些絕緣子層可以包括例如氧化矽、硼磷矽酸鹽玻璃、未經摻雜的矽酸鹽玻璃、氟化矽酸鹽玻璃、低介電常數(low-k)介電材料、其類似材料、或前述之組合。該些絕緣子層可以包括不同的材料，但不限於此。低介電常數介電材料可以具有小於3.0或甚至小於2.5的介電常數。在一些實施例中，低介電常數介電材料可以具有小於2.0的介電常數。該些介電層的製作技術可以包括像是化學氣相沉積(chemical vapor deposition)、電漿輔助化學氣相沉積(plasma-enhanced chemical vapor deposition)、或其類似技術。可以在沉積製程之後進行平坦化製程以移除多餘的材料並為後續處理步驟提供實質上平坦的表面。 Referring to FIG. 1 , an intermediate dielectric layer 103 may be disposed on a substrate 101 . In some embodiments, the interlayer dielectric layer 103 may be a stacked structure. The intermediate dielectric layer 103 may include a plurality of insulating sublayers. Each of these insulator layers may have a thickness between about 0.5 microns to thickness between approximately 3.0 microns. The insulator layers may include, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, and the like. , or a combination of the foregoing. The insulator layers may include different materials, but are not limited thereto. Low-k dielectric materials may have a dielectric constant of less than 3.0 or even less than 2.5. In some embodiments, the low-k dielectric material may have a dielectric constant less than 2.0. The fabrication techniques of the dielectric layers may include, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or similar techniques. A planarization process may be performed after the deposition process to remove excess material and provide a substantially planar surface for subsequent processing steps.

應注意的是，在本揭露的描述中，修飾本揭露所採用的成分、組分、或反應物之用量的用詞“大約”是指例如透過用於製備濃縮液或溶液的典型測量和液體處理程序可能產生的數量變化。此外，可能由於測量程序的疏忽錯誤、製造組合物或實施方法所使用成分的製造、來源或純度上的差異而產生變化。一方面，用詞“大約”是指在報告數值的10%以內。另一方面，用詞“大約”是指在報告數值的5%以內。又，另一方面，用詞“大約”是指在報告數值的10、9、8、7、6、5、4、3、2、或1%之內。 It should be noted that in the description of the present disclosure, the term "about" used to modify the amount of an ingredient, component, or reactant used in the present disclosure means, for example, by typical measurements and liquids used to prepare a concentrate or solution. The number of changes a handler may produce. In addition, variations may arise from inadvertent errors in measurement procedures, differences in the manufacture, source or purity of ingredients used in making the compositions or performing the methods. In one aspect, the word "about" means within 10% of the reported value. On the other hand, the word "about" means within 5% of the reported value. In yet another aspect, the word "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

參照圖1，該些導電部件可以設置在中間介電層103中。該些導電部件可以包括內連線層(interconnect layer)(為了清楚起見並未顯示)、導電通孔(conductive vias)(為了清楚起見並未顯示)、和複數個導電襯墊105。內連線層可以彼此分離並且可以沿著方向Z水平地設置在該些介電層中。在本實施例中，最頂部的內連線層可以被指定為導電 襯墊105。該些導電襯墊105的頂表面和中間介電層103的頂表面可以是實質上共平面的。導電通孔可以連接沿方向Z相鄰的內連線層、相鄰的元件構件和內連線層、以及相鄰的導電襯墊105和內連線層。在一些實施例中，導電通孔可以改善散熱並且可以提供結構支撐。在一些實施例中，該些導電部件可以包括例如鎢、鈷、鋯、鉭、鈦、鋁、釕、銅、金屬碳化物(例如，碳化鉭、碳化鈦、碳化鉭鎂)、金屬氮化物(例如，氮化鈦)、過渡金屬鋁化物、或前述之組合。可以在形成該些介電層期間形成該些導電部件。 Referring to FIG. 1 , the conductive members may be disposed in the intermediate dielectric layer 103 . The conductive components may include an interconnect layer (not shown for clarity), conductive vias (not shown for clarity), and a plurality of conductive pads 105 . The interconnection layers may be separated from each other and may be arranged horizontally along the direction Z in the dielectric layers. In this embodiment, the topmost interconnect layer can be designated as conductive Liner 105. The top surfaces of the conductive pads 105 and the top surface of the interlayer dielectric layer 103 may be substantially coplanar. The conductive vias may connect adjacent interconnection layers in direction Z, adjacent component members and interconnection layers, and adjacent conductive pads 105 and interconnection layers. In some embodiments, conductive vias can improve heat dissipation and can provide structural support. In some embodiments, the conductive components may include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (eg, tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides ( For example, titanium nitride), transition metal aluminides, or combinations thereof. The conductive features may be formed during the formation of the dielectric layers.

在一些實施例中，該些元件構件和該些導電部件可以一起構成半導體元件1A的功能單元。在本揭露的描述中，功能單元通常是指為了功能目的而被劃分為不同單元的功能相關電路。在一些實施例中，功能單元通常可以是高度複雜的電路，像是處理器核心或加速器單元。在一些其他實施例中，功能單元的複雜性和功能性可以更加複雜或較不複雜。 In some embodiments, the element components and the conductive components may together constitute a functional unit of the semiconductor element 1A. In the description of the present disclosure, functional units generally refer to functionally related circuits that are divided into different units for functional purposes. In some embodiments, a functional unit may typically be a highly complex circuit, like a processor core or an accelerator unit. In some other embodiments, the complexity and functionality of the functional units may be more or less complex.

參照圖1，多堆疊載體結構200可以設置在中間介電層103上。多堆疊載體結構200可以包括第一層(tier)210、第二層220、第三層230、第四層240、第五層250、和頂部鈍化層203。在一些實施例中，多堆疊載體結構200的厚度TL可以大於約500微米。在一些實施例中，多堆疊載體結構200的厚度TL與基板101的厚度T0的厚度比可以介於大約180：1至大約50：1之間。 Referring to FIG. 1 , a multi-stack carrier structure 200 may be disposed on the intermediate dielectric layer 103 . The multi-stack carrier structure 200 may include a first tier 210 , a second tier 220 , a third tier 230 , a fourth tier 240 , a fifth tier 250 , and a top passivation layer 203 . In some embodiments, the thickness TL of the multi-stack carrier structure 200 may be greater than about 500 microns. In some embodiments, the thickness ratio of the thickness TL of the multi-stack carrier structure 200 to the thickness T0 of the substrate 101 may be between about 180:1 and about 50:1.

參照圖1，第一層210可以設置在中間介電層103上。第一層210可以包括第一鈍化層211、第一絕緣層213、和複數個第一通孔(vias)215。 Referring to FIG. 1 , a first layer 210 may be disposed on the intermediate dielectric layer 103 . The first layer 210 may include a first passivation layer 211 , a first insulating layer 213 , and a plurality of first vias 215 .

參照圖1，第一鈍化層211可以設置在中間介電層103上。 在一些實施例中，第一鈍化層211可以包括例如氧化物材料。在一些實施例中，第一鈍化層211可以包括例如氧化矽、硼磷矽酸鹽玻璃(borophosphosilicate glass)、未經摻雜的矽酸鹽玻璃(undoped silicate glass)、氟化矽酸鹽玻璃(fluorinated silicate glass)、其類似材料、或前述之組合。在一些實施例中，第一鈍化層211的厚度T1可以介於大約1μm至大約2μm之間。 Referring to FIG. 1 , a first passivation layer 211 may be disposed on the interlayer dielectric layer 103 . In some embodiments, the first passivation layer 211 may include, for example, an oxide material. In some embodiments, the first passivation layer 211 may include, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass ( fluorinated silicate glass), its similar materials, or a combination of the foregoing. In some embodiments, the thickness T1 of the first passivation layer 211 may be between about 1 μm and about 2 μm.

參照圖1，第一絕緣層213可以設置在第一鈍化層211上。在一些實施例中，第一絕緣層213可以包括例如氧化物材料。在一些實施例中，第一絕緣層213可以包括與第一鈍化層211相同的材料。在一些實施例中，第一絕緣層213可以包括例如氧化矽、硼磷矽酸鹽玻璃、未經摻雜的矽酸鹽玻璃、氟化矽酸鹽玻璃、其類似材料、或前述之組合。在一些實施例中，第一絕緣層213的厚度T2可以小於約200μm。例如，第一絕緣層213的厚度T2可以介於大約150μm至大約190μm之間。 Referring to FIG. 1 , a first insulating layer 213 may be disposed on the first passivation layer 211 . In some embodiments, the first insulating layer 213 may include, for example, an oxide material. In some embodiments, the first insulating layer 213 may include the same material as the first passivation layer 211 . In some embodiments, the first insulating layer 213 may include, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, similar materials, or combinations thereof. In some embodiments, the thickness T2 of the first insulating layer 213 may be less than about 200 μm. For example, the thickness T2 of the first insulating layer 213 may be between about 150 μm and about 190 μm.

參照圖1和圖2，在一些實施例中，該些第一通孔215可以沿著第一絕緣層213和第一鈍化層211設置、設置在該些導電襯墊105上、且分別並對應地電性連接至該些導電襯墊105。 Referring to FIG. 1 and FIG. 2, in some embodiments, the first via holes 215 may be disposed along the first insulating layer 213 and the first passivation layer 211, disposed on the conductive pads 105, and respectively and correspondingly The ground is electrically connected to the conductive pads 105 .

為了簡潔、清楚和方便描述，僅描述一個第一通孔215。 For brevity, clarity and convenience of description, only one first through hole 215 is described.

在一些實施例中，第一通孔215的側壁215SW可以是漸縮的(tapered)。第一通孔215的底表面215BS的寬度W0可以小於第一通孔215的頂表面215TS的寬度W1。在一些實施例中，第一通孔215可以包括填料層FL、種子層SL、黏附層AL、障壁層BL、和隔離層IL。 In some embodiments, the sidewall 215SW of the first through hole 215 may be tapered. The width W0 of the bottom surface 215BS of the first through hole 215 may be smaller than the width W1 of the top surface 215TS of the first through hole 215 . In some embodiments, the first via hole 215 may include a filler layer FL, a seed layer SL, an adhesion layer AL, a barrier layer BL, and an isolation layer IL.

應注意的是，在本揭露的描述中，元件(或部件)位於沿著方向Z之最高垂直水平(vertical level)的表面被稱為該元件(或部 件)的頂表面。元件(或部件)位於沿著方向Z之最低垂直水平的表面被稱為元件(或部件)的底表面。 It should be noted that in the description of the present disclosure, the surface of an element (or part) located at the highest vertical level (vertical level) along the direction Z is referred to as the element (or part) pieces) top surface. The surface of the element (or component) located at the lowest vertical level along the direction Z is referred to as the bottom surface of the element (or component).

應注意的是，在本揭露的描述中，“寬度”是指在剖面透視圖中從元件(例如，層、插塞、溝槽、孔、開口等)的一側表面測量到一相對表面的元件尺寸。在指明處，用詞“厚度”可以代替“寬度”。 It should be noted that in the description of the present disclosure, "width" refers to the distance measured from one side surface of an element (e.g., layer, plug, groove, hole, opening, etc.) to an opposite surface in a cross-sectional perspective view. Component size. Where indicated, the word "thickness" may be used instead of "width".

填料層FL可以沿著第一絕緣層213和第一鈍化層211設置，並且設置在導電襯墊105上。在一些實施例中，填料層FL可以具有介於大約1：2至大約1：35之間或介於大約1：10至大約1：25之間的深寬比。填料層FL可以包括例如經摻雜的多晶矽、鎢、銅、碳奈米管、或銲錫合金。 The filler layer FL may be disposed along the first insulating layer 213 and the first passivation layer 211 , and disposed on the conductive pad 105 . In some embodiments, the filler layer FL may have an aspect ratio between about 1:2 to about 1:35 or between about 1:10 to about 1:25. The filler layer FL may include, for example, doped polysilicon, tungsten, copper, carbon nanotubes, or solder alloy.

參照圖2，在一些實施例中，種子層SL可以具有U形剖面輪廓。種子層SL可以設置在填料層FL和第一絕緣層213之間、填料層FL和第一鈍化層211之間、以及填料層FL和導電襯墊105之間。在一些實施例中，種子層SL可以具有介於大約10nm至大約40nm之間的厚度。在一些實施例中，種子層SL可以包括例如銅。種子層SL可以在填料層FL的形成期間降低開口的電阻率。 Referring to FIG. 2 , in some embodiments, the seed layer SL may have a U-shaped cross-sectional profile. The seed layer SL may be disposed between the filler layer FL and the first insulating layer 213 , between the filler layer FL and the first passivation layer 211 , and between the filler layer FL and the conductive pad 105 . In some embodiments, the seed layer SL may have a thickness between about 10 nm and about 40 nm. In some embodiments, the seed layer SL may include copper, for example. The seed layer SL may reduce the resistivity of the opening during the formation of the filler layer FL.

在一些實施例中，黏附層AL可以具有U形剖面輪廓。黏附層AL可以設置在種子層SL和第一絕緣層213之間、種子層SL和第一鈍化層211之間、以及種子層SL和導電襯墊105之間。種子層SL可以包括例如鈦、鉭、鈦、鎢、或氮化錳。黏附層AL可以提高種子層SL和障壁層BL之間的黏附性。 In some embodiments, the adhesive layer AL may have a U-shaped cross-sectional profile. The adhesion layer AL may be disposed between the seed layer SL and the first insulating layer 213 , between the seed layer SL and the first passivation layer 211 , and between the seed layer SL and the conductive pad 105 . The seed layer SL may include, for example, titanium, tantalum, titanium, tungsten, or manganese nitride. The adhesion layer AL can improve the adhesion between the seed layer SL and the barrier layer BL.

在一些實施例中，障壁層BL可以具有U形剖面輪廓。障壁層BL可以位於黏附層AL和第一絕緣層213之間、黏附層AL和第一鈍化層 211之間、以及黏附層AL和導電襯墊105之間。障壁層BL可以包括例如鉭、氮化鉭、鈦、氮化鈦、錸、硼化鎳、或氮化鉭/鉭雙層。障壁層BL可以抑制填料層FL的導電材料擴散至第一絕緣層213、第一鈍化層211、或中間介電層103中。 In some embodiments, the barrier layer BL may have a U-shaped cross-sectional profile. The barrier layer BL may be located between the adhesion layer AL and the first insulating layer 213, the adhesion layer AL and the first passivation layer 211, and between the adhesive layer AL and the conductive pad 105. The barrier layer BL may include, for example, tantalum, tantalum nitride, titanium, titanium nitride, rhenium, nickel boride, or a tantalum nitride/tantalum bilayer. The barrier layer BL can inhibit the conductive material of the filler layer FL from diffusing into the first insulating layer 213 , the first passivation layer 211 , or the interlayer dielectric layer 103 .

在一些實施例中，隔離層IL可以設置在障壁層BL和第一絕緣層213之間、以及障壁層BL和第一鈍化層211之間。在一些實施例中，隔離層IL可以包括例如氧化矽、氮化矽、氧氮化矽、或四乙氧基矽烷(tetra-ethyl ortho-silicate)。隔離層IL可以具有介於大約50nm至大約200nm之間的厚度。在一些實施例中，隔離層IL可以包括例如聚對二甲苯(parylene)、環氧樹脂、或聚(對二甲苯)(poly(p-xylene))。隔離層IL可以具有介於大約1μm至大約5μm之間的厚度。隔離層IL可以保證填料層FL在第一絕緣層213和第一鈍化層211中電性隔離。 In some embodiments, the isolation layer IL may be disposed between the barrier layer BL and the first insulating layer 213 , and between the barrier layer BL and the first passivation layer 211 . In some embodiments, the isolation layer IL may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or tetra-ethyl ortho-silicate. The isolation layer IL may have a thickness between about 50 nm and about 200 nm. In some embodiments, the isolation layer IL may include, for example, parylene, epoxy resin, or poly(p-xylene). The isolation layer IL may have a thickness between about 1 μm to about 5 μm. The isolation layer IL can ensure that the filler layer FL is electrically isolated in the first insulating layer 213 and the first passivation layer 211 .

參照圖1，第二層220可以設置在第一層210上。第二層220可以包括第二鈍化層221、第二絕緣層223、和複數個第二通孔225。第二鈍化層221可以設置在第一絕緣層213上。第二絕緣層223可以設置在第二鈍化層221上。該些第二通孔225可以沿著第二絕緣層223和第二鈍化層221設置、設置在該些第一通孔215上、且分別並對應地電性連接至該些第一通孔215。第二鈍化層221、第二絕緣層223、和該些第二通孔225可以分別並對應地包括與第一鈍化層211、第一絕緣層213、和該些第一通孔215相同的材料，在此不再重複其描述。 Referring to FIG. 1 , the second layer 220 may be disposed on the first layer 210 . The second layer 220 may include a second passivation layer 221 , a second insulating layer 223 , and a plurality of second via holes 225 . The second passivation layer 221 may be disposed on the first insulating layer 213 . The second insulating layer 223 may be disposed on the second passivation layer 221 . The second through holes 225 may be disposed along the second insulating layer 223 and the second passivation layer 221, disposed on the first through holes 215, and electrically connected to the first through holes 215 respectively and correspondingly. . The second passivation layer 221, the second insulating layer 223, and the second through holes 225 may respectively and correspondingly comprise the same materials as the first passivation layer 211, the first insulating layer 213, and the first through holes 215. , and its description will not be repeated here.

參照圖1，第二通孔225的頂表面225TS的寬度W2可以大於第一通孔215的頂表面215TS的寬度W1。 Referring to FIG. 1 , the width W2 of the top surface 225TS of the second through hole 225 may be greater than the width W1 of the top surface 215TS of the first through hole 215 .

參照圖1，第三層230可以設置在第二層220上。第三層230 可以包括第三鈍化層231、第三絕緣層233、和複數個第三通孔235。第三鈍化層231可以設置在第二絕緣層223上。第三絕緣層233可以設置在第三鈍化層231上。該些第三通孔235可以沿著第三絕緣層233和第三鈍化層231設置、設置在該些第二通孔225上、且分別並對應地電性連接至該些第二通孔225。第三鈍化層231、第三絕緣層233、和該些第三通孔235可以分別並對應地包括與第一鈍化層211、第一絕緣層213、和該些第一通孔215相同的材料，在此不再重複其描述。 Referring to FIG. 1 , a third layer 230 may be disposed on the second layer 220 . The third floor 230 A third passivation layer 231 , a third insulating layer 233 , and a plurality of third via holes 235 may be included. The third passivation layer 231 may be disposed on the second insulating layer 223 . A third insulating layer 233 may be disposed on the third passivation layer 231 . The third through holes 235 may be disposed along the third insulating layer 233 and the third passivation layer 231 , disposed on the second through holes 225 , and electrically connected to the second through holes 225 respectively and correspondingly. . The third passivation layer 231, the third insulating layer 233, and the third through holes 235 may respectively and correspondingly comprise the same materials as the first passivation layer 211, the first insulating layer 213, and the first through holes 215. , and its description will not be repeated here.

參照圖1，第三通孔235的頂表面235TS的寬度W3可以大於第二通孔225的頂表面225TS的寬度W2。 Referring to FIG. 1 , a width W3 of a top surface 235TS of the third through hole 235 may be greater than a width W2 of a top surface 225TS of the second through hole 225 .

參照圖1，第四層240可以設置在第三層230上。第四層240可以包括第四鈍化層241、第四絕緣層243、和複數個第四通孔245。第四鈍化層241可以設置在第三絕緣層233上。第四絕緣層243可以設置在第四鈍化層241上。該些第四通孔245可以沿著第四絕緣層243和第四鈍化層241設置、設置在該些第三通孔上235上、且分別並對應地電性連接至該些第三通孔235。第四鈍化層241、第四絕緣層243、和該些第四通孔245可以分別並對應地包括與第一鈍化層211、第一絕緣層213、和該些第一通孔215相同的材料，在此不再重複其描述。 Referring to FIG. 1 , a fourth layer 240 may be disposed on the third layer 230 . The fourth layer 240 may include a fourth passivation layer 241 , a fourth insulating layer 243 , and a plurality of fourth via holes 245 . A fourth passivation layer 241 may be disposed on the third insulating layer 233 . A fourth insulating layer 243 may be disposed on the fourth passivation layer 241 . The fourth through holes 245 may be disposed along the fourth insulating layer 243 and the fourth passivation layer 241, disposed on the third through holes 235, and electrically connected to the third through holes respectively and correspondingly. 235. The fourth passivation layer 241, the fourth insulating layer 243, and the fourth through holes 245 may respectively and correspondingly comprise the same materials as the first passivation layer 211, the first insulating layer 213, and the first through holes 215. , and its description will not be repeated here.

參照圖1，第四通孔245的頂表面245TS的寬度W4可以大於第三通孔235的頂表面235TS的寬度W3。 Referring to FIG. 1 , a width W4 of a top surface 245TS of the fourth through hole 245 may be greater than a width W3 of a top surface 235TS of the third through hole 235 .

參照圖1，第五層250可以設置在第四層240上。第五層250可以包括第五鈍化層251、第五絕緣層253、和複數個第五通孔255。第五鈍化層251可以設置在第四絕緣層243上。第五絕緣層253可以設置在第五鈍化層251上。該些第五通孔255可以沿著第五絕緣層253和第五鈍化層 251設置、設置在該些第四通孔上245上、且分別並對應地電性連接至該些第四通孔245。第五鈍化層251、第五絕緣層253、和該些第五通孔255可以分別並對應地包括與第一鈍化層211、第一絕緣層213、和該些第一通孔215相同的材料，在此不再重複其描述。 Referring to FIG. 1 , a fifth layer 250 may be disposed on the fourth layer 240 . The fifth layer 250 may include a fifth passivation layer 251 , a fifth insulating layer 253 , and a plurality of fifth via holes 255 . A fifth passivation layer 251 may be disposed on the fourth insulating layer 243 . A fifth insulating layer 253 may be disposed on the fifth passivation layer 251 . The fifth via holes 255 can be formed along the fifth insulating layer 253 and the fifth passivation layer 251 is disposed on, disposed on the fourth through holes 245 , and electrically connected to the fourth through holes 245 respectively and correspondingly. The fifth passivation layer 251, the fifth insulating layer 253, and the fifth through holes 255 may respectively and correspondingly comprise the same materials as the first passivation layer 211, the first insulating layer 213, and the first through holes 215. , and its description will not be repeated here.

參照圖1，第五通孔255的頂表面255TS的寬度W5可以大於第四通孔245的頂表面245TS的寬度W4。 Referring to FIG. 1 , a width W5 of a top surface 255TS of the fifth through hole 255 may be greater than a width W4 of a top surface 245TS of the fourth through hole 245 .

應注意的是，在本揭露的描述中，多堆疊載體結構200的層數僅用於說明目的。換句話說，多堆疊載體結構200的層數可以多於或少於五層。 It should be noted that in the description of the present disclosure, the number of layers of the multi-stacked carrier structure 200 is for illustrative purposes only. In other words, the multi-stack carrier structure 200 may have more or less than five layers.

參照圖1，頂部鈍化層203可以設置在最頂部絕緣層(亦即，第五層250的第五絕緣層253)上。頂部鈍化層203可以是單層結構或多層結構。在一些實施例中，頂部鈍化層203可以包括聚苯並噁唑、聚醯亞胺、苯並環丁烯、味之素增建膜(ajinomoto buildup film)、銲錫光阻膜(solder resist film)、或其類似材料、或前述之組合。在一些其他實施例中，頂部鈍化層203可以是介電層。介電層可以包括像是氮化矽的氮化物、像是氧化矽的氧化物、像是氮氧化矽的氮氧化物、氧化氮化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、經硼摻雜的磷矽酸鹽玻璃、其類似材料、或前述之組合。 Referring to FIG. 1 , a top passivation layer 203 may be disposed on the topmost insulating layer (ie, the fifth insulating layer 253 of the fifth layer 250 ). The top passivation layer 203 may be a single-layer structure or a multi-layer structure. In some embodiments, the top passivation layer 203 may include polybenzoxazole, polyimide, benzocyclobutene, ajinomoto buildup film, solder resist film , or similar materials, or a combination of the foregoing. In some other embodiments, the top passivation layer 203 may be a dielectric layer. Dielectric layers may include nitrides such as silicon nitride, oxides such as silicon oxide, oxynitrides such as silicon oxynitride, silicon oxynitride, phosphosilicate glass, borosilicate glass, Boron-doped phosphosilicate glass, similar materials, or combinations thereof.

應注意的是，在本揭露的描述中，氮氧化矽是指包含矽、氮和氧並且其中氧的比例大於氮的比例的物質。氧化氮化矽是指含有矽、氧和氮並且其中氮的比例大於氧的比例的物質。 It should be noted that in the description of the present disclosure, silicon oxynitride refers to a substance including silicon, nitrogen and oxygen, wherein the proportion of oxygen is greater than that of nitrogen. Silicon oxynitride refers to a substance that contains silicon, oxygen and nitrogen and wherein the proportion of nitrogen is greater than that of oxygen.

參照圖1，複數個第一頂部開口203O可以沿著頂部鈍化層203設置以分別並對應地暴露出該些第五通孔255。暴露的第五通孔255可 以電性耦合至用於電特性測試的探針。 Referring to FIG. 1 , a plurality of first top openings 203O may be disposed along the top passivation layer 203 to respectively and correspondingly expose the fifth via holes 255 . The exposed fifth via hole 255 can be Electrically coupled to probes for electrical characteristic testing.

在基板101的薄化製程期間，多堆疊載體結構200可以作為暫時載體。在多堆疊載體結構200的輔助下，可以分析包括小於10μm的基板101之半導體元件1A的性能。相反地，包括小於10μm的基板之傳統半導體元件被載體覆蓋，所以無法容易地分析其性能。 During the thinning process of the substrate 101, the multi-stacked carrier structure 200 may serve as a temporary carrier. With the aid of the multi-stack carrier structure 200, the performance of the semiconductor device 1A comprising the substrate 101 smaller than 10 μm can be analyzed. In contrast, a conventional semiconductor element including a substrate smaller than 10 μm is covered by a carrier, so its performance cannot be easily analyzed.

參照圖3，半導體元件1B的結構可以與圖1所示的結構相似。圖3中與圖1相同或相似的元件，已以類似的參照符號標記並且省略重複的描述。 Referring to FIG. 3 , the structure of the semiconductor element 1B may be similar to that shown in FIG. 1 . Components in FIG. 3 that are the same as or similar to those in FIG. 1 have been marked with similar reference symbols and repeated descriptions are omitted.

參照圖3，複數個重分佈層205可以沿著頂部鈍化層203設置、設置在該些第五通孔255上、且分別並對應地電性連接至該些第五通孔255。該些重分佈層205可以重新佈線(re-route)該些第五通孔255以提供更彈性的配置和更多用於電特性測試的接觸面積。該些重分佈層205可以包括例如鎢、鈦、錫、鎳、銅、金、鋁、鉑、鈷、或前述之組合。 Referring to FIG. 3 , a plurality of redistribution layers 205 may be disposed along the top passivation layer 203 , disposed on the fifth through holes 255 , and electrically connected to the fifth through holes 255 respectively and correspondingly. The redistribution layers 205 can re-route the fifth vias 255 to provide a more flexible configuration and more contact area for electrical characteristic testing. The redistribution layers 205 may include, for example, tungsten, titanium, tin, nickel, copper, gold, aluminum, platinum, cobalt, or combinations thereof.

參照圖4，半導體元件1C的結構可以與圖1所示的結構相似。圖4中與圖1相同或相似的元件，已以類似的參照符號標記並且省略重複的描述。 Referring to FIG. 4 , the structure of the semiconductor element 1C may be similar to that shown in FIG. 1 . Components in FIG. 4 that are the same as or similar to those in FIG. 1 have been marked with similar reference symbols and repeated descriptions are omitted.

參照圖4，第五層250、第四層240、第三層230、第二層220、和第一層210可以依照與圖1所示的多堆疊載體結構200相反的順序設置在中間介電層103上。例如，第五絕緣層253設置在中間介電層103上、第五鈍化層251設置在第五絕緣層253上、第四絕緣層243設置在第五鈍化層251上、以及第四鈍化層241設置在第四絕緣層243上。 Referring to FIG. 4, the fifth layer 250, the fourth layer 240, the third layer 230, the second layer 220, and the first layer 210 may be disposed on the intermediate dielectric in the reverse order of the multi-stack carrier structure 200 shown in FIG. layer 103. For example, the fifth insulating layer 253 is disposed on the intermediate dielectric layer 103, the fifth passivation layer 251 is disposed on the fifth insulating layer 253, the fourth insulating layer 243 is disposed on the fifth passivation layer 251, and the fourth passivation layer 241 disposed on the fourth insulating layer 243 .

參照圖4，在一些實施例中，第一通孔215的側壁215SW可以是漸縮的。第一通孔215的底表面215BS的寬度W7可以大於第一通孔 215的頂表面215TS的寬度W6。 Referring to FIG. 4 , in some embodiments, the sidewall 215SW of the first through hole 215 may be tapered. The width W7 of the bottom surface 215BS of the first through hole 215 may be greater than that of the first through hole. The width W6 of the top surface 215TS of 215 .

參照圖4，在一些實施例中，一蝕刻停止層207可以設置在第一層210的第一絕緣層213上。在一些實施例中，蝕刻停止層207可以優選地包括蝕刻選擇性與相鄰層的蝕刻選擇性不同的介電材料。例如，蝕刻停止層207可以包括氮化矽、碳氮化矽、碳氧化矽、其類似材料、或前述之組合。複數個第二頂部開口207O可以沿著蝕刻停止層207設置以暴露出該些第一通孔215。暴露的第一通孔215可以電性耦合至用於電特性測試的探針。 Referring to FIG. 4 , in some embodiments, an etch stop layer 207 may be disposed on the first insulating layer 213 of the first layer 210 . In some embodiments, etch stop layer 207 may preferably include a dielectric material having an etch selectivity different from that of adjacent layers. For example, the etch stop layer 207 may include silicon nitride, silicon carbonitride, silicon oxycarbide, similar materials, or combinations thereof. A plurality of second top openings 207O can be disposed along the etch stop layer 207 to expose the first through holes 215 . The exposed first via hole 215 can be electrically coupled to a probe for electrical characteristic testing.

參照圖5，半導體元件1D的結構可以與圖4所示的結構相似。圖5中與圖4相同或相似的元件，已以類似的參照符號標記並且省略重複的描述。 Referring to FIG. 5 , the structure of the semiconductor element 1D may be similar to that shown in FIG. 4 . Components in FIG. 5 that are the same as or similar to those in FIG. 4 have been marked with similar reference symbols and repeated descriptions are omitted.

參照圖5，頂部鈍化層203可以設置在第一層210的第一絕緣層213上。頂部鈍化層203可以是單層結構或多層結構。在一些實施例中，頂部鈍化層203可以包括聚苯並噁唑、聚醯亞胺、苯並環丁烯、味之素增建膜、銲錫光阻膜、或其類似材料、或前述之組合。在一些其他實施例中，頂部鈍化層203可以是介電層。介電層可以包括像是氮化矽的氮化物、像是氧化矽的氧化物、像是氮氧化矽的氮氧化物、氧化氮化化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、經硼摻雜的磷矽酸鹽玻璃、其類似材料、或前述之組合。 Referring to FIG. 5 , a top passivation layer 203 may be disposed on the first insulating layer 213 of the first layer 210 . The top passivation layer 203 may be a single-layer structure or a multi-layer structure. In some embodiments, the top passivation layer 203 may include polybenzoxazole, polyimide, benzocyclobutene, Ajinomoto build-up film, solder photoresist film, or similar materials, or combinations thereof. . In some other embodiments, the top passivation layer 203 may be a dielectric layer. Dielectric layers may include nitrides such as silicon nitride, oxides such as silicon oxide, oxynitrides such as silicon oxynitride, silicon oxynitride, phosphosilicate glass, borosilicate glass, Boron-doped phosphosilicate glass, similar materials, or combinations thereof.

參照圖5，該些重分佈層205可以沿著頂部鈍化層203設置、設置在該些第一通孔215上、且分別並對應地電性連接至該些第一通孔215。該些重分佈層205可以重新佈線該些第一通孔215以提供更彈性的配置和更多用於電特性測試的接觸面積。該些重分佈層205可以包括例如 鎢、鈦、錫、鎳、銅、金、鋁、鉑、鈷、或前述之組合。 Referring to FIG. 5 , the redistribution layers 205 may be disposed along the top passivation layer 203 , disposed on the first through holes 215 , and electrically connected to the first through holes 215 respectively and correspondingly. The redistribution layers 205 can rewire the first vias 215 to provide a more flexible configuration and more contact area for electrical characteristic testing. These redistribution layers 205 may include, for example Tungsten, titanium, tin, nickel, copper, gold, aluminum, platinum, cobalt, or combinations thereof.

應注意的是，用詞“形成(forming)”、“形成(formed)”、和“形式(form)”可以表示並且包括創造、構建(building)、圖案化、植入、或沉積元件、摻雜物、或材料的任何方法。形成方法的示例可以包括但不限於原子層沉積(atomic layer deposition)、化學氣相沉積(chemical vapor deposition)、物理氣相沉積(physical vapor deposition)、濺鍍(sputtering)、共濺鍍(co-sputtering)、旋塗(spin coating)、擴散、沉積、生長、植入(implantation)、微影(photolithography)、乾蝕刻、和濕蝕刻。 It should be noted that the terms "forming," "formed," and "form" can mean and include creating, building, patterning, implanting, or depositing elements, doping debris, or material in any way. Examples of formation methods may include, but are not limited to, atomic layer deposition (atomic layer deposition), chemical vapor deposition (chemical vapor deposition), physical vapor deposition (physical vapor deposition), sputtering (sputtering), co-sputtering (co- sputtering, spin coating, diffusion, deposition, growth, implantation, photolithography, dry etching, and wet etching.

應注意的是，在本揭露的描述中，在此提及的功能或步驟可以按照與圖式中提及的順序不同的順序出現。例如，根據所涉及的功能或步驟，連續顯示的兩個圖式實際上實質上可以同時進行或者有時可以依相反的順序進行。 It should be noted that, in the description of the present disclosure, the functions or steps mentioned herein may appear in an order different from that mentioned in the drawings. For example, two figures shown in succession may, in fact, be executed substantially concurrently or may sometimes be executed in the reverse order, depending upon the functions or steps involved.

圖6根據本揭露一實施例以流程圖的形式顯示半導體元件1A的製備方法10。圖7到圖21根據本揭露一實施例顯示半導體元件1A之製備流程的剖面示意圖。 FIG. 6 shows a method 10 for manufacturing the semiconductor device 1A in the form of a flowchart according to an embodiment of the present disclosure. 7 to 21 are schematic cross-sectional views showing the fabrication process of the semiconductor device 1A according to an embodiment of the present disclosure.

參照圖6和圖7，在步驟S11，可以提供一基板101，且可以形成一中間介電層103於基板101上。 Referring to FIG. 6 and FIG. 7 , in step S11 , a substrate 101 may be provided, and an intermediate dielectric layer 103 may be formed on the substrate 101 .

參照圖7，基板101的材料如圖1所示，在此不再重複其描述。在一些實施例中，基板101可以包括絕緣體上半導體結構，其從底部到頂部包括處理基板、絕緣層、和最頂部的半導體材料層。處理基板和最頂部的半導體材料層可以包括與上述塊狀半導體基板相同的材料。絕緣層可以是結晶或非結晶介電材料，像是氧化物及/或氮化物。例如，絕緣層 可以是介電氧化物，像是氧化矽。又例如，絕緣層可以是介電氮化物，像是氮化矽或氮化硼。再例如，絕緣層可以包括介電氧化物和介電氮化物的堆疊，像是氧化矽和氮化矽或氮化硼之任何順序的堆疊。絕緣層可以具有介於大約10nm至大約200nm之間的厚度。應注意的是，在此階段，基板101的厚度T0可以大於700μm或大於500μm。 Referring to FIG. 7 , the material of the substrate 101 is as shown in FIG. 1 , and its description will not be repeated here. In some embodiments, substrate 101 may include a semiconductor-on-insulator structure that includes, from bottom to top, a handle substrate, an insulating layer, and a topmost semiconductor material layer. The handle substrate and the topmost layer of semiconductor material may comprise the same materials as described above for the bulk semiconductor substrate. The insulating layer can be crystalline or amorphous dielectric material, such as oxide and/or nitride. For example, insulation It may be a dielectric oxide, such as silicon oxide. As another example, the insulating layer can be a dielectric nitride, such as silicon nitride or boron nitride. As another example, the insulating layer may include a stack of dielectric oxide and dielectric nitride, such as a stack of silicon oxide and silicon nitride or boron nitride in any order. The insulating layer may have a thickness between about 10 nm to about 200 nm. It should be noted that at this stage, the thickness T0 of the substrate 101 may be greater than 700 μm or greater than 500 μm.

參照圖7，形成中間介電層103於基板101上的製作技術可以包括像是化學氣相沉積的沉積製程。可以進行像是化學機械研磨(chemical mechanical polishing)的平坦化製程以為後續製程步驟提供實質上平坦的表面。可以在形成中間介電層103期間形成元件構件(為了清楚起見並未顯示)和導電部件(為了清楚起見並未顯示)。形成該些導電襯墊105於中間介電層103中的製作技術可以包括例如鑲嵌製程。該些導電襯墊105的頂表面和中間介電層103的頂表面可以實質上共平面。 Referring to FIG. 7 , the fabrication technique for forming the interlayer dielectric layer 103 on the substrate 101 may include a deposition process such as chemical vapor deposition. Planarization processes such as chemical mechanical polishing may be performed to provide a substantially planar surface for subsequent processing steps. Element components (not shown for clarity) and conductive features (not shown for clarity) may be formed during formation of the interlayer dielectric layer 103 . The fabrication technique for forming the conductive pads 105 in the interlayer dielectric layer 103 may include, for example, a damascene process. The top surfaces of the conductive pads 105 and the top surface of the interlayer dielectric layer 103 may be substantially coplanar.

參照圖6和圖8到圖19，在步驟S13，可以形成一多堆疊載體結構200於中間介電層103上。 Referring to FIG. 6 and FIG. 8 to FIG. 19 , in step S13 , a multi-stack carrier structure 200 may be formed on the intermediate dielectric layer 103 .

參照圖8，可以形成第一鈍化層211於中間介電層103上，且第三鈍化層231的製作技術可以包括例如化學氣相沉積、電漿輔助化學氣相沉積、或其他可應用的沉積製程。在一些實施例中，可以進行氧化物接合製程以形成第一絕緣層213於第一鈍化層211上。第一鈍化層211的材料如圖1所示，在此不再重複其描述。 Referring to FIG. 8, the first passivation layer 211 can be formed on the intermediate dielectric layer 103, and the fabrication technique of the third passivation layer 231 can include, for example, chemical vapor deposition, plasma-assisted chemical vapor deposition, or other applicable deposition techniques. Process. In some embodiments, an oxide bonding process may be performed to form the first insulating layer 213 on the first passivation layer 211 . The material of the first passivation layer 211 is as shown in FIG. 1 , and its description will not be repeated here.

參照圖9，可以形成一第一罩幕層510於第一絕緣層213上。第一罩幕層510可以包括複數個第一圖案化開口510O，其定義了該些第一通孔215的位置。第一圖案化開口510O可以具有寬度W8。第一圖案化開口510O的寬度W8可以大於導電襯墊105的寬度WC。 Referring to FIG. 9 , a first mask layer 510 may be formed on the first insulating layer 213 . The first mask layer 510 may include a plurality of first patterned openings 510O, which define the positions of the first through holes 215 . The first patterned opening 510O may have a width W8. The width W8 of the first patterned opening 510O may be greater than the width WC of the conductive pad 105 .

參照圖10，可以使用第一罩幕層510作為圖案引導來進行氧化物蝕刻製程以移除第一絕緣層213的一部分和第一鈍化層211的一部分，並同時形成複數個第一通孔開口215O。在一些實施例中，該些第一通孔開口215O的側壁可以是漸縮的。在氧化物蝕刻製程之後，可以移除第一罩幕層510。 Referring to FIG. 10, an oxide etching process may be performed using the first mask layer 510 as a pattern guide to remove a portion of the first insulating layer 213 and a portion of the first passivation layer 211, and simultaneously form a plurality of first via openings. 215O. In some embodiments, the sidewalls of the first via openings 215O may be tapered. After the oxide etch process, the first mask layer 510 may be removed.

參照圖11，形成該些第一通孔215於該些第一通孔開口215O中的製作技術可以包括例如化學氣相沉積、物理氣相沉積、蒸發、濺射、電鍍、或前述之組合。可以進行像是化學機械研磨的平坦化製程以移除多餘的材料並為後續處理步驟提供實質上平坦的表面。該些第一通孔215的材料和結構如圖1和圖2所示，在此不再重複其描述。第一鈍化層211、第一絕緣層213、和該些第一通孔215一起構成第一層210。 Referring to FIG. 11 , the fabrication techniques for forming the first via holes 215 in the first via hole openings 215O may include, for example, chemical vapor deposition, physical vapor deposition, evaporation, sputtering, electroplating, or combinations thereof. A planarization process such as chemical mechanical polishing may be performed to remove excess material and provide a substantially planar surface for subsequent processing steps. The materials and structures of the first through holes 215 are shown in FIGS. 1 and 2 , and the description thereof will not be repeated here. The first passivation layer 211 , the first insulating layer 213 , and the first through holes 215 together constitute the first layer 210 .

參照圖12，可以形成第二鈍化層221於第一絕緣層213上，可以形成第二絕緣層223於第二鈍化層221上，並且可以形成第二罩幕層520於第二絕緣層223上。第二鈍化層221的材料和第二絕緣層223的材料如圖1所示，在此不再重複其描述。可以透過與圖8到圖11所示的第一層210類似的步驟形成第二鈍化層221、第二絕緣層223、和第二罩幕層520，在此不再重複其描述。第二罩幕層520可以包括複數個第二圖案化開口520O，其定義了該些第二通孔225的位置。第二圖案化開口520O的寬度W9可以大於第一圖案化開口510O的寬度W8。 12, a second passivation layer 221 can be formed on the first insulating layer 213, a second insulating layer 223 can be formed on the second passivation layer 221, and a second mask layer 520 can be formed on the second insulating layer 223. . The material of the second passivation layer 221 and the material of the second insulating layer 223 are as shown in FIG. 1 , and the description thereof will not be repeated here. The second passivation layer 221 , the second insulating layer 223 , and the second mask layer 520 may be formed through steps similar to those of the first layer 210 shown in FIGS. 8 to 11 , and the description thereof will not be repeated here. The second mask layer 520 may include a plurality of second patterned openings 520O, which define the positions of the second through holes 225 . The width W9 of the second patterned opening 520O may be greater than the width W8 of the first patterned opening 510O.

參照圖13，可以使用第二罩幕層520作為圖案引導來進行氧化物蝕刻製程以移除第二絕緣層223的一部分和第二鈍化層221的一部分，並同時形成複數個第二通孔開口225O。在一些實施例中，該些第二通孔開口225O的側壁可以是漸縮的。在氧化物蝕刻製程之後，可以移除 第二罩幕層520。 Referring to FIG. 13, an oxide etching process may be performed using the second mask layer 520 as a pattern guide to remove a portion of the second insulating layer 223 and a portion of the second passivation layer 221, and simultaneously form a plurality of second via openings. 225O. In some embodiments, the sidewalls of the second via openings 225O may be tapered. After the oxide etch process, it can be removed The second mask layer 520 .

參照圖14，可以透過與該些第一通孔215類似的製程形成該些第二通孔225於該些第二通孔開口225O中，在此不再重複其描述。可以進行像是化學機械研磨的平坦化製程以移除多餘的材料並為後續處理步驟提供實質上平坦的表面。第二鈍化層221、第二絕緣層223、和該些第二通孔225一起構成第二層220。 Referring to FIG. 14 , the second through holes 225 can be formed in the second through hole openings 225O through a process similar to that of the first through holes 215 , and the description thereof will not be repeated here. A planarization process such as chemical mechanical polishing may be performed to remove excess material and provide a substantially planar surface for subsequent processing steps. The second passivation layer 221 , the second insulating layer 223 , and the second through holes 225 together constitute the second layer 220 .

第二圖案化開口520O的更大寬度可以轉移到第二通孔開口225O，然後由第二通孔225繼承。第二通孔225的更大寬度可以為後續微影製程(例如，第三通孔235的微影製程)提供更大的容差窗口(tolerance window)。其結果，可以提高半導體元件1A的產率。 The larger width of the second patterned opening 520O may be transferred to the second via opening 225O and then inherited by the second via 225 . The larger width of the second via hole 225 may provide a larger tolerance window for subsequent lithography processes (eg, the lithography process of the third via hole 235 ). As a result, the yield of the semiconductor element 1A can be improved.

參照圖15，可以形成第三鈍化層231於第二絕緣層223上，可以形成第三絕緣層233於第三鈍化層231上，以及可以形成第三罩幕層530於第三絕緣層233上。第三鈍化層231的材料和第三絕緣層233的材料如圖1所示，在此不再重複其描述。可以透過與圖8到圖11所示的第一層210類似的步驟形成第三鈍化層231、第三絕緣層233、和第三罩幕層530，在此不再重複其描述。第三罩幕層530可以包括複數個第三圖案化開口530O，其定義了該些第三通孔235的位置。第三圖案化開口530O的寬度W10可以大於第二圖案化開口520O的寬度W9。 15, a third passivation layer 231 can be formed on the second insulating layer 223, a third insulating layer 233 can be formed on the third passivation layer 231, and a third mask layer 530 can be formed on the third insulating layer 233. . The material of the third passivation layer 231 and the material of the third insulating layer 233 are as shown in FIG. 1 , and the description thereof will not be repeated here. The third passivation layer 231 , the third insulating layer 233 , and the third mask layer 530 may be formed through steps similar to those of the first layer 210 shown in FIGS. 8 to 11 , and the description thereof will not be repeated here. The third mask layer 530 may include a plurality of third patterned openings 530O, which define the positions of the third through holes 235 . The width W10 of the third patterned opening 530O may be greater than the width W9 of the second patterned opening 520O.

參照圖16，可以使用第三罩幕層530作為圖案引導來進行氧化物蝕刻製程以移除第三絕緣層233的一部分和第三鈍化層231的一部分，並同時形成複數個第三通孔開口235O。在一些實施例中，該些第三通孔開口235O的側壁可以是漸縮的。在氧化物蝕刻製程之後，可以移除第三罩幕層530。 Referring to FIG. 16, an oxide etching process may be performed using the third mask layer 530 as a pattern guide to remove a portion of the third insulating layer 233 and a portion of the third passivation layer 231, and simultaneously form a plurality of third via openings. 235O. In some embodiments, the sidewalls of the third via openings 235O may be tapered. After the oxide etch process, the third mask layer 530 may be removed.

參照圖17，可以透過與該些第一通孔215類似的步驟形成該些第三通孔235於該些第三通孔開口235O中，在此不再重複其描述。可以進行像是化學機械研磨的平坦化製程以移除多餘的材料並為後續處理步驟提供實質上平坦的表面。第三鈍化層231、第三絕緣層233、和該些第三通孔235一起構成第三層230。 Referring to FIG. 17 , the third through holes 235 can be formed in the third through hole openings 235O through steps similar to those of the first through holes 215 , and the description thereof will not be repeated here. A planarization process such as chemical mechanical polishing may be performed to remove excess material and provide a substantially planar surface for subsequent processing steps. The third passivation layer 231 , the third insulating layer 233 , and the third through holes 235 together constitute the third layer 230 .

應注意的是，第三通孔235看似沿方向Z偏離第二通孔225，以強調透過第二通孔225的較寬寬度獲得之微影製程的較大容差窗口的益處。也就是說，即使微影製程的對準產生偏移，通孔225、235仍然可以正常電性連接。 It should be noted that the third via 235 appears to be offset from the second via 225 in direction Z to emphasize the benefit of a larger tolerance window for the lithography process obtained through the wider width of the second via 225 . That is to say, even if the alignment of the lithography process deviates, the through holes 225 and 235 can still be electrically connected normally.

參照圖18，可以透過與圖8到圖11所示的第一層210類似的步驟形成第四層240和第五層250，在此不再重複其描述。 Referring to FIG. 18 , the fourth layer 240 and the fifth layer 250 may be formed through steps similar to the first layer 210 shown in FIGS. 8 to 11 , and description thereof will not be repeated here.

參照圖19，可以形成頂部鈍化層203於第五層250上。頂部鈍化層203的製作技術可以包括例如旋塗、層壓、沉積、或其類似技術。沉積可以包括化學氣相沉積。頂部鈍化層203的材料如圖1所示，在此不再重複其描述。層210、220、230、240、250和頂部鈍化層203一起構成多堆疊載體結構200。 Referring to FIG. 19 , a top passivation layer 203 may be formed on the fifth layer 250 . Fabrication techniques for the top passivation layer 203 may include, for example, spin-coating, lamination, deposition, or similar techniques. Deposition may include chemical vapor deposition. The material of the top passivation layer 203 is as shown in FIG. 1 , and its description will not be repeated here. Layers 210 , 220 , 230 , 240 , 250 and top passivation layer 203 together constitute multi-stack carrier structure 200 .

在一些實施例中，在基板101的薄化製程之前，多堆疊載體結構200的厚度TL與基板101的厚度T0的厚度比可以介於大約5：7至大約1之間、或介於大約1：1至大約7：5之間。 In some embodiments, before the thinning process of the substrate 101, the thickness ratio of the thickness TL of the multi-stacked carrier structure 200 to the thickness T0 of the substrate 101 may be between about 5:7 and about 1, or between about 1. :1 to approximately 7:5.

參照圖6、圖20、和圖21，在步驟S15，可以薄化基板101並且可以沿著多堆疊載體結構200的頂部鈍化層203形成複數個第一頂部開口203O。 Referring to FIGS. 6 , 20 , and 21 , in step S15 , the substrate 101 may be thinned and a plurality of first top openings 203O may be formed along the top passivation layer 203 of the multi-stack carrier structure 200 .

參照圖20，可以透過使用晶圓研磨(wafer grinding)、 機械磨耗(mechanical abrasion)、研磨(polishing)、或其類似技術、或使用像是濕蝕刻的化學移除的薄化製程來薄化基板101。應注意的是，在薄化製程期間不需要載體。多堆疊載體結構200可以用作暫時載體以輔助基板101的薄化製程。 Referring to Figure 20, through the use of wafer grinding (wafer grinding), The substrate 101 is thinned by mechanical abrasion, polishing, or similar techniques, or a thinning process using chemical removal such as wet etching. It should be noted that no carrier is required during the thinning process. The multi-stacked carrier structure 200 can be used as a temporary carrier to assist the thinning process of the substrate 101 .

參照圖20，在薄化製程之後，多堆疊載體結構200的厚度TL與基板101的厚度T0的厚度比可以介於大約180：1至大約50：1之間。 Referring to FIG. 20 , after the thinning process, the thickness ratio of the thickness TL of the multi-stack carrier structure 200 to the thickness T0 of the substrate 101 may be between about 180:1 and about 50:1.

參照圖21，可以沿著頂部鈍化層203形成該些第一頂部開口203O以分別並對應地暴露出該些第五通孔255。暴露的第五通孔255可以電性耦合至用於電特性測試的探針。也就是說，可以容易地分析基板經薄化後之半導體元件1A的性能。 Referring to FIG. 21 , the first top openings 203O may be formed along the top passivation layer 203 to respectively and correspondingly expose the fifth via holes 255 . The exposed fifth via hole 255 can be electrically coupled to a probe for electrical characteristic testing. That is, the performance of the semiconductor element 1A after the substrate has been thinned can be easily analyzed.

圖22根據本揭露另一實施例顯示半導體元件1B之製備流程的剖面示意圖。 FIG. 22 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device 1B according to another embodiment of the present disclosure.

參照圖22，半導體元件1B的結構可以與圖21所示的結構相似。圖22中與圖21相同或相似的元件，已以類似的參照符號標記並且省略重複的描述。 Referring to FIG. 22 , the structure of the semiconductor element 1B may be similar to that shown in FIG. 21 . Components in FIG. 22 that are the same as or similar to those in FIG. 21 have been marked with similar reference symbols and repeated descriptions are omitted.

在半導體元件1B中，可以分別並對應地形成該些重分佈層205於該些第五通孔255上。在一些實施例中，該些重分佈層205的形成可以包括使用任何合適的方法(例如，旋塗技術、濺射、其類似的技術)形成一個或多個絕緣層(亦即，頂部鈍化層203)以及形成導電部件(亦即，該些重分佈層205)於絕緣層中。導電部件的形成可以包括圖案化絕緣層(例如，使用微影及/或蝕刻製程)以及形成導電部件於圖案化的絕緣層中(例如，透過使用罩幕層來定義導電部件的形狀，並使用無電/電化學電鍍製程來沉積種子層)。例如，該些第一頂部開口203O可以定義 該些重分佈層205的圖案。可以形成該些重分佈層205於該些第一頂部開口203O中。 In the semiconductor device 1B, the redistribution layers 205 can be respectively and correspondingly formed on the fifth through holes 255 . In some embodiments, the formation of the redistribution layers 205 may include forming one or more insulating layers (ie, top passivation layer 203 ) and forming conductive components (ie, the redistribution layers 205 ) in the insulating layer. The formation of the conductive features may include patterning the insulating layer (e.g., using lithography and/or etching processes) and forming the conductive features in the patterned insulating layer (e.g., by using a mask layer to define the shape of the conductive features, and using electroless/electrochemical plating process to deposit the seed layer). For example, the first top openings 203O can define The patterns of the redistribution layers 205 . The redistribution layers 205 can be formed in the first top openings 203O.

圖23根據本揭露另一實施例以流程圖的形式顯示半導體元件1C的製備方法20。圖24到圖32根據本揭露另一實施例顯示半導體元件1C之製備流程的剖面示意圖。 FIG. 23 shows a method 20 of manufacturing a semiconductor device 1C in the form of a flowchart according to another embodiment of the present disclosure. 24 to 32 are cross-sectional schematic diagrams showing a fabrication process of a semiconductor device 1C according to another embodiment of the present disclosure.

參照圖23到圖27，在步驟S21，可以提供一犧牲載體401，並且可以暫時形成一多堆疊載體結構200於犧牲載體401上。 Referring to FIGS. 23 to 27 , in step S21 , a sacrificial carrier 401 may be provided, and a multi-stacked carrier structure 200 may be temporarily formed on the sacrificial carrier 401 .

參照圖24，可以形成一蝕刻停止層207於犧牲載體401上。一般來說，蝕刻停止層207可以在形成導電部件時提供停止蝕刻製程的機制。蝕刻停止層207可以優選地包括蝕刻選擇性與相鄰層的蝕刻選擇性不同的介電材料。例如，蝕刻停止層207可以包括氮化矽、碳氮化矽、碳氧化矽、或其類似材料，且可以透過化學氣相沈積或電漿輔助化學氣相沉積來沈積蝕刻停止層207。 Referring to FIG. 24 , an etch stop layer 207 may be formed on the sacrificial carrier 401 . In general, the etch stop layer 207 can provide a mechanism to stop the etch process when forming conductive features. The etch stop layer 207 may preferably include a dielectric material having an etch selectivity different from that of an adjacent layer. For example, the etch stop layer 207 may include silicon nitride, silicon carbonitride, silicon oxycarbide, or similar materials, and the etch stop layer 207 may be deposited by chemical vapor deposition or plasma assisted chemical vapor deposition.

參照圖24，形成一第一絕緣層213於蝕刻停止層207上的製作技術可以包括例如像是化學氣相沉積或電漿輔助化學氣相沉積的沉積製程。第一絕緣層213的材料如圖1所示，在此不再重複其描述。可以形成第一罩幕層510於第一絕緣層213上。第一罩幕層510可以包括一圖案，其定義了複數個第一通孔215的位置。 Referring to FIG. 24 , fabrication techniques for forming a first insulating layer 213 on the etch stop layer 207 may include, for example, deposition processes such as chemical vapor deposition or plasma-assisted chemical vapor deposition. The material of the first insulating layer 213 is as shown in FIG. 1 , and its description will not be repeated here. A first mask layer 510 can be formed on the first insulating layer 213 . The first mask layer 510 may include a pattern that defines the positions of the plurality of first through holes 215 .

參照圖25，可以使用第一罩幕層510作為圖案引導來進行氧化物蝕刻製程以移除第一絕緣層213的一部分，並同時形成該些第一通孔開口215O。可以透過該些第一通孔開口215O暴露出蝕刻停止層207的一部分。在氧化物蝕刻製程期間，第一絕緣層213與蝕刻停止層207的蝕刻速率比可以介於大約100：1至大約1.05：1之間、介於大約15：1至大約2：1 之間、或介於大約10：1至大約2：1之間。在氧化物蝕刻製程之後，可以移除第一罩幕層510。 Referring to FIG. 25 , an oxide etching process may be performed using the first mask layer 510 as a pattern guide to remove a portion of the first insulating layer 213 and simultaneously form the first via openings 215O. A portion of the etch stop layer 207 may be exposed through the first via openings 215O. During the oxide etch process, the etch rate ratio of the first insulating layer 213 to the etch stop layer 207 may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1. between, or between about 10:1 and about 2:1. After the oxide etch process, the first mask layer 510 may be removed.

參照圖26，可以形成複數個第一通孔215於該些第一通孔開口215O中。可以進行像是化學機械研磨的平坦化製程直到暴露出第一絕緣層213的頂表面以移除多餘的材料並為後續處理步驟提供實質上平坦的表面。該些第一通孔215的材料如圖1所示，在此不再重複其描述。第一絕緣層213和該些第一通孔215一起構成第一層210。 Referring to FIG. 26 , a plurality of first through holes 215 may be formed in the first through hole openings 215O. A planarization process such as chemical mechanical polishing may be performed until the top surface of the first insulating layer 213 is exposed to remove excess material and provide a substantially planar surface for subsequent processing steps. The materials of the first through holes 215 are as shown in FIG. 1 , and the description thereof will not be repeated here. The first insulating layer 213 and the first through holes 215 together constitute the first layer 210 .

參照圖27，可以透過類似於圖12到圖19所示的步驟形成第二層220、第三層230、第四層240、和第五層250，在此不再重複其描述。第一層210、第二層220、第三層230、第四層240、第五層250、和蝕刻停止層207一起構成多堆疊載體結構200。 Referring to FIG. 27 , the second layer 220 , the third layer 230 , the fourth layer 240 , and the fifth layer 250 may be formed through steps similar to those shown in FIGS. 12 to 19 , and description thereof will not be repeated here. The first layer 210 , the second layer 220 , the third layer 230 , the fourth layer 240 , the fifth layer 250 , and the etch stop layer 207 together constitute the multi-stacked carrier structure 200 .

參照圖23、圖28、和圖29，在步驟S23，可以提供一基板101，可以形成一中間介電層103於基板101上，可以形成複數個導電襯墊105於中間介電層103中，以及可以將多堆疊載體結構200接合至中間介電層103上。 23, FIG. 28, and FIG. 29, in step S23, a substrate 101 can be provided, an intermediate dielectric layer 103 can be formed on the substrate 101, and a plurality of conductive pads 105 can be formed in the intermediate dielectric layer 103, And the multi-stack carrier structure 200 may be bonded to the interlayer dielectric layer 103 .

參照圖28，可以透過與圖1和圖7所示類似的步驟形成基板101、中間介電層103、和該些導電襯墊105，在此不再重複其描述。 Referring to FIG. 28 , the substrate 101 , the interlayer dielectric layer 103 , and the conductive pads 105 may be formed through steps similar to those shown in FIGS. 1 and 7 , and the description thereof will not be repeated here.

參照圖29，可以將多堆疊載體結構200翻轉並接合至中間介電層103上。在一些實施例中，可以透過混合接合製程將多堆疊載體結構200接合至中間介電層103上。在一些實施例中，混合接合製程可以包括像是熱壓接合(thermo-compression bonding)、鈍化覆蓋層輔助接合(passivation-capping-layer assisted bonding)、或表面活化接合。在一些實施例中，混合接合製程的製程壓力可以介於大約100MPa至大約 150MPa之間。在一些實施例中，混合接合製程的製程溫度可以介於大約室溫(例如，25℃)至大約400℃之間。在一些實施例中，表面處理(像是濕化學清洗和氣體/氣相熱處理)可用於降低混合接合製程的製程溫度或縮短混合接合製程的時間消耗。在一些實施例中，混合接合製程可以包括例如介電質與介電質(dielectric-to-dielectric)接合、金屬與金屬(metal-to-metal)接合、和金屬與介電質(metal-to-dielectric)接合。在一些實施例中，可以在接合製程之後進行熱退火製程以增強介電質與介電質接合並引起金屬與金屬接合的熱膨脹，從而進一步提高接合品質。 Referring to FIG. 29 , the multi-stacked carrier structure 200 may be flipped over and bonded onto the intermediate dielectric layer 103 . In some embodiments, the multi-stacked carrier structure 200 may be bonded to the interlayer dielectric layer 103 through a hybrid bonding process. In some embodiments, the hybrid bonding process may include, for example, thermo-compression bonding, passivation-capping-layer assisted bonding, or surface-activated bonding. In some embodiments, the process pressure of the hybrid bonding process may range from about 100 MPa to about Between 150MPa. In some embodiments, the process temperature of the hybrid bonding process may be between about room temperature (eg, 25° C.) to about 400° C. In some embodiments, surface treatments such as wet chemical cleaning and gas/vapor phase heat treatment can be used to reduce the process temperature or shorten the time consumption of the hybrid bonding process. In some embodiments, the hybrid bonding process may include, for example, dielectric-to-dielectric bonding, metal-to-metal bonding, and metal-to-dielectric bonding. -dielectric) joint. In some embodiments, a thermal annealing process may be performed after the bonding process to enhance the dielectric-to-dielectric bonding and cause thermal expansion of the metal-to-metal bonding, thereby further improving the bonding quality.

參照圖30，在基板101的薄化製程之前，在一些實施例中，多堆疊載體結構200的厚度TL與基板101的厚度T0的厚度比可以介於大約5：7至大約1：1之間、或介於大約1：1至大約7：5之間。 Referring to FIG. 30 , prior to the thinning process of the substrate 101 , in some embodiments, the thickness ratio of the thickness TL of the multi-stacked carrier structure 200 to the thickness T0 of the substrate 101 may be between about 5:7 and about 1:1. , or between about 1:1 and about 7:5.

參照圖23和圖30到圖32，在步驟S25，可以分離犧牲載體401，可以薄化基板101，並且可以沿著多堆疊載體結構200的蝕刻停止層207形成複數個第二頂部開口207O。 Referring to FIGS. 23 and 30 to 32 , in step S25 , the sacrificial carrier 401 may be separated, the substrate 101 may be thinned, and a plurality of second top openings 207O may be formed along the etch stop layer 207 of the multi-stacked carrier structure 200 .

如圖30所示，可以從蝕刻停止層207分離犧牲載體401。 As shown in FIG. 30 , sacrificial carrier 401 may be separated from etch stop layer 207 .

參照圖31，可以透過使用晶圓研磨、機械磨耗、研磨、或其類似技術、或使用像是濕蝕刻的化學移除的薄化製程來薄化基板101。應注意的是，在薄化過程期間不需要載體。多堆疊載體結構200可以用作暫時載體以輔助基板101的薄化製程。 Referring to FIG. 31 , the substrate 101 may be thinned by a thinning process using wafer grinding, mechanical abrasion, lapping, or similar techniques, or using chemical removal such as wet etching. It should be noted that no carrier is required during the thinning process. The multi-stacked carrier structure 200 can be used as a temporary carrier to assist the thinning process of the substrate 101 .

參照圖31，在基板101的薄化製程之後，多堆疊載體結構200的厚度TL與基板101的厚度T0的厚度比可以介於大約180：1至大約50：1之間。 Referring to FIG. 31 , after the thinning process of the substrate 101 , the thickness ratio of the thickness TL of the multi-stack carrier structure 200 to the thickness T0 of the substrate 101 may be between about 180:1 and about 50:1.

參照圖32，可以沿著蝕刻停止層207形成複數個第二頂部 開口207O以分別並對應地暴露出該些第一通孔215。暴露的第一通孔215可以電性耦合至用於電特性測試的探針。也就是說，可以容易地分析基板經薄化後之半導體元件1C的性能。 Referring to FIG. 32, a plurality of second tops may be formed along the etch stop layer 207. The openings 207O respectively and correspondingly expose the first through holes 215 . The exposed first via hole 215 can be electrically coupled to a probe for electrical characteristic testing. That is, the performance of the semiconductor element 1C after the substrate has been thinned can be easily analyzed.

圖33根據本揭露另一實施例顯示半導體元件1D之製備流程的剖面示意圖。 FIG. 33 is a schematic cross-sectional view showing a fabrication process of a semiconductor device 1D according to another embodiment of the present disclosure.

參照圖33，半導體元件1D的結構可以與圖31所示的結構相似。圖33中與圖31相同或相似的元件，已以類似的參照符號標記並且省略重複的描述。 Referring to FIG. 33 , the structure of the semiconductor element 1D may be similar to that shown in FIG. 31 . Components in FIG. 33 that are the same as or similar to those in FIG. 31 have been marked with similar reference symbols and repeated descriptions are omitted.

在半導體元件1D中，可以完全移除蝕刻停止層207。可以透過類似於圖19所示的步驟形成頂部鈍化層203於第一層210上，在此不再重複其描述。複數個重分佈層205可以沿著頂部鈍化層203形成並分別並對應地形成於該些第一通孔215上。該些重分佈層205可以重新佈線該些第一通孔215以提供更彈性的配置和更多用於電特性測試的接觸面積。該些重分佈層205的材料如圖3所示，在此不再重複其描述。 In the semiconductor element 1D, the etch stop layer 207 may be completely removed. The top passivation layer 203 can be formed on the first layer 210 through steps similar to those shown in FIG. 19 , and the description thereof will not be repeated here. A plurality of redistribution layers 205 may be formed along the top passivation layer 203 and respectively and correspondingly formed on the first through holes 215 . The redistribution layers 205 can rewire the first vias 215 to provide a more flexible configuration and more contact area for electrical characteristic testing. The materials of the redistribution layers 205 are shown in FIG. 3 , and the description thereof will not be repeated here.

本揭露之一方面提供一種半導體元件，包括：一基板；一中間介電層，位於該基板上；一導電襯墊，位於該中間介電層中；以及一多堆疊載體結構。該多堆疊載體結構包括：一第一層，包括位於該中間介電層上的一第一鈍化層、位於該第一鈍化層上的一第一絕緣層、以及一第一通孔，其中該第一通孔沿著該第一鈍化層和該第一絕緣層設置且電性連接至該導電襯墊；一第二層，位於該第一層上且包括位於該第一絕緣層上的一第二鈍化層、位於該第二鈍化層上的一第二絕緣層、以及一第二通孔，其中該第二通孔沿著該第二鈍化層和該第二絕緣層設置且電性連接至該第一通孔；以及一第三層，位於該第二層上且包括位於該第二絕緣層上 的一第三鈍化層、位於該第三鈍化層上的一第三絕緣層、以及一第三通孔，其中該第三通孔沿著該第三鈍化層和該第三絕緣層設置且電性連接至該第二通孔。 An aspect of the present disclosure provides a semiconductor device, including: a substrate; an intermediate dielectric layer on the substrate; a conductive pad in the intermediate dielectric layer; and a multi-stacked carrier structure. The multi-stack carrier structure includes: a first layer including a first passivation layer on the intermediate dielectric layer, a first insulating layer on the first passivation layer, and a first via hole, wherein the A first through hole is arranged along the first passivation layer and the first insulating layer and is electrically connected to the conductive pad; a second layer is located on the first layer and includes a layer located on the first insulating layer A second passivation layer, a second insulating layer on the second passivation layer, and a second through hole, wherein the second through hole is arranged along the second passivation layer and the second insulating layer and is electrically connected to the first via hole; and a third layer on the second layer and including on the second insulating layer a third passivation layer, a third insulating layer on the third passivation layer, and a third via hole, wherein the third via hole is arranged along the third passivation layer and the third insulating layer and electrically connected to the second via.

本揭露之另一方面提供一種多堆疊載體結構，包括：一蝕刻停止層；一第一層，包括位於該蝕刻停止層上的一第一鈍化層、位於該第一鈍化層上的一第一絕緣層、以及一第一通孔，其中該第一通孔沿著該第一鈍化層和該第一絕緣層設置；一第二層，位於該第一層上且包括位於該第一絕緣層上的一第二鈍化層、位於該第二鈍化層上的一第二絕緣層、以及一第二通孔，其中該第二通孔沿著該第二鈍化層和該第二絕緣層設置且電性連接至該第一通孔；以及一第三層，位於該第二層上且包括位於該第二絕緣層上的一第三鈍化層、位於該第三鈍化層上的一第三絕緣層、以及一第三通孔，其中該第三通孔沿著該第三鈍化層和該第三絕緣層設置且電性連接至該第二通孔。 Another aspect of the present disclosure provides a multi-stack carrier structure, including: an etch stop layer; a first layer including a first passivation layer on the etch stop layer, a first passivation layer on the first passivation layer an insulating layer, and a first through hole, wherein the first through hole is arranged along the first passivation layer and the first insulating layer; a second layer, located on the first layer and including the first insulating layer a second passivation layer on the second passivation layer, a second insulating layer on the second passivation layer, and a second via hole, wherein the second via hole is arranged along the second passivation layer and the second insulating layer and electrically connected to the first through hole; and a third layer on the second layer and including a third passivation layer on the second insulating layer, a third insulating layer on the third passivation layer layer, and a third via hole, wherein the third via hole is disposed along the third passivation layer and the third insulating layer and is electrically connected to the second via hole.

本揭露之另一方面提供一種半導體元件的製備方法，包括：提供一基板；形成一中間介電層於該基板上；形成一導電襯墊於該中間介電層中；形成一第一層於該中間介電層上，其中該第一層包括位於該中間介電層上的一第一鈍化層、位於該第一鈍化層上的一第一絕緣層、以及一第一通孔，其中該第一通孔沿著該第一鈍化層和該第一絕緣層設置且電性連接至該導電襯墊；形成一第二層於該第一層上，其中該第二層包括位於該第一絕緣層上的一第二鈍化層、位於該第二鈍化層上的一第二絕緣層、以及一第二通孔，其中該第二通孔沿著該第二鈍化層和該第二絕緣層設置且電性連接至該第一通孔；以及形成一第三層於該第二層上，其中該第三層包括位於該第二絕緣層上的一第三鈍化層、位於該第三鈍化層上的 一第三絕緣層、以及一第三通孔，其中該第三通孔沿著該第三鈍化層和該第三絕緣層設置且電性連接至該第二通孔。該第一層、該第二層、和該第三層一起構成一多堆疊載體結構。 Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, including: providing a substrate; forming an intermediate dielectric layer on the substrate; forming a conductive pad in the intermediate dielectric layer; forming a first layer on the On the intermediate dielectric layer, wherein the first layer includes a first passivation layer on the intermediate dielectric layer, a first insulating layer on the first passivation layer, and a first via hole, wherein the The first via hole is arranged along the first passivation layer and the first insulating layer and is electrically connected to the conductive pad; forming a second layer on the first layer, wherein the second layer includes a layer located on the first layer A second passivation layer on the insulating layer, a second insulating layer on the second passivation layer, and a second through hole, wherein the second through hole is along the second passivation layer and the second insulating layer disposing and electrically connecting to the first through hole; and forming a third layer on the second layer, wherein the third layer includes a third passivation layer on the second insulating layer, a third passivation layer on the third passivation layer on A third insulating layer, and a third through hole, wherein the third through hole is disposed along the third passivation layer and the third insulating layer and is electrically connected to the second through hole. The first layer, the second layer, and the third layer together form a multi-stack carrier structure.

本揭露之另一方面提供一種半導體元件的製備方法，包括：提供一犧牲載體；暫時附接一蝕刻停止層於該犧牲載體上；形成一多堆疊載體結構於該蝕刻停止層上，其中該多堆疊載體結構包括：一第一層，位於該蝕刻停止層上；一第二層，位於該第一層上；以及一第三層，位於該第二層上；提供一基板；形成一中間介電層於該基板上；形成一導電襯墊於該中間介電層中；翻轉該多堆疊載體結構並接合該多堆疊載體結構至該中間介電層上；從該蝕刻停止層分離該犧牲載體；以及薄化該基板。 Another aspect of the present disclosure provides a method for fabricating a semiconductor device, including: providing a sacrificial carrier; temporarily attaching an etch stop layer on the sacrificial carrier; forming a multi-stacked carrier structure on the etch stop layer, wherein the multiple The stacked carrier structure includes: a first layer located on the etch stop layer; a second layer located on the first layer; and a third layer located on the second layer; providing a substrate; forming an interposer an electrical layer on the substrate; forming a conductive pad in the intermediate dielectric layer; flipping the multi-stacked carrier structure and bonding the multi-stacked carrier structure to the intermediate dielectric layer; separating the sacrificial carrier from the etch stop layer ; and thinning the substrate.

由於本揭露之半導體元件的設計，多堆疊載體結構200可以用作暫時載體以輔助基板101的薄化製程。因此，在基板101的薄化製程期間不需要載體。其結果，可以降低半導體元件1A的製造成本。此外，在薄化製程之後，多堆疊載體結構200可以提供連接到半導體元件1A的元件構件的電性路徑。因此，在多堆疊載體結構200存在的情況下，可以容易地分析半導體元件1A的性能。 Due to the design of the semiconductor device of the present disclosure, the multi-stacked carrier structure 200 can be used as a temporary carrier to assist the thinning process of the substrate 101 . Therefore, no carrier is required during the thinning process of the substrate 101 . As a result, the manufacturing cost of the semiconductor element 1A can be reduced. In addition, after the thinning process, the multi-stack carrier structure 200 can provide electrical paths connected to the device components of the semiconductor device 1A. Therefore, the performance of the semiconductor element 1A can be easily analyzed in the presence of the multi-stack carrier structure 200 .

雖然已詳述本揭露及其優點，然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如，可用不同的方法實施上述的許多製程，並且以其他製程或其組合替代上述的許多製程。 Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

再者，本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技 術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此，此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。 Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. skill of the craft Those skilled in the art can understand from the disclosure content of this disclosure that existing or future development processes, machinery, manufacturing, and material compositions that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure , means, method, or steps. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of this application.

1A:半導體元件 1A: Semiconductor components

101:基板 101: Substrate

103:中間介電層 103:Intermediate dielectric layer

105:導電襯墊 105: Conductive gasket

200:多堆疊載體結構 200: Multi-stack carrier structure

203:頂部鈍化層 203: Top passivation layer

203O:第一頂部開口 203O: first top opening

210:第一層 210: first floor

211:第一鈍化層 211: the first passivation layer

213:第一絕緣層 213: The first insulating layer

215:第一通孔 215: the first through hole

215BS:底表面 215BS: bottom surface

215SW:側壁 215SW: side wall

215TS:頂表面 215TS: Top surface

220:第二層 220: second floor

221:第二鈍化層 221: Second passivation layer

223:第二絕緣層 223: Second insulating layer

225:第二通孔 225: Second through hole

225TS:頂表面 225TS: top surface

230:第三層 230: third floor

231:第三鈍化層 231: The third passivation layer

233:第三絕緣層 233: The third insulating layer

235:第三通孔 235: The third through hole

235TS:頂表面 235TS: top surface

240:第四層 240: fourth floor

241:第四鈍化層 241: The fourth passivation layer

243:第四絕緣層 243: The fourth insulating layer

245:第四通孔 245: The fourth through hole

245TS:頂表面 245TS: top surface

250:第五層 250: fifth floor

251:第五鈍化層 251: The fifth passivation layer

253:第五絕緣層 253: fifth insulating layer

255:第五通孔 255: Fifth through hole

255TS:頂表面 255TS: top surface

T0:厚度 T0: Thickness

T1:厚度 T1: Thickness

T2:厚度 T2: Thickness

TL:厚度 TL: Thickness

W0:寬度 W0: width

W1:寬度 W1: width

W2:寬度 W2: width

W3:寬度 W3: width

W4:寬度 W4: width

W5:寬度 W5: width

Z:方向 Z: Direction

Claims (25)

一種半導體元件，包括：一基板；一中間介電層，位於該基板上；一導電襯墊，位於該中間介電層中；以及一多堆疊載體結構，包括：一第一層，包括位於該中間介電層上的一第一鈍化層、位於該第一鈍化層上的一第一絕緣層、以及一第一通孔，其中該第一通孔沿著該第一鈍化層和該第一絕緣層設置且電性連接至該導電襯墊；一第二層，位於該第一層上且包括位於該第一絕緣層上的一第二鈍化層、位於該第二鈍化層上的一第二絕緣層、以及一第二通孔，其中該第二通孔沿著該第二鈍化層和該第二絕緣層設置且電性連接至該第一通孔；以及一第三層，位於該第二層上且包括位於該第二絕緣層上的一第三鈍化層、位於該第三鈍化層上的一第三絕緣層、以及一第三通孔，其中該第三通孔沿著該第三鈍化層和該第三絕緣層設置且電性連接至該第二通孔，該第二通孔具有導電的一填料層，其中該填料層的一頂表面與該第二絕緣層的一頂表面共平面，以及，該第三通孔的一底表面至少部分在該第二通孔的一頂表面之一垂直投影區域之外。 A semiconductor element, comprising: a substrate; an intermediate dielectric layer located on the substrate; a conductive pad located in the intermediate dielectric layer; and a multi-stacked carrier structure comprising: a first layer comprising the A first passivation layer on the intermediate dielectric layer, a first insulating layer on the first passivation layer, and a first through hole, wherein the first through hole is along the first passivation layer and the first The insulating layer is arranged and electrically connected to the conductive pad; a second layer is located on the first layer and includes a second passivation layer located on the first insulating layer, a first passivation layer located on the second passivation layer Two insulating layers, and a second via hole, wherein the second via hole is disposed along the second passivation layer and the second insulating layer and electrically connected to the first via hole; and a third layer, located on the second via hole On the second layer and including a third passivation layer on the second insulating layer, a third insulating layer on the third passivation layer, and a third via hole, wherein the third via hole is along the The third passivation layer and the third insulating layer are disposed and electrically connected to the second through hole, the second through hole has a conductive filler layer, wherein a top surface of the filler layer is connected to a top surface of the second insulating layer The top surfaces are coplanar, and a bottom surface of the third through hole is at least partially outside a vertical projection area of a top surface of the second through hole. 如請求項1所述之半導體元件，其中該多堆疊載體結構的一厚度大於約500微米。 The semiconductor device of claim 1, wherein a thickness of the multi-stacked carrier structure is greater than about 500 microns. 如請求項2所述之半導體元件，其中該第一絕緣層的一厚度小於約200微米。 The semiconductor device of claim 2, wherein a thickness of the first insulating layer is less than about 200 microns. 如請求項2所述之半導體元件，其中該第一鈍化層的一厚度介於大約1微米至大約2微米之間。 The semiconductor device as claimed in claim 2, wherein a thickness of the first passivation layer is between about 1 micron and about 2 microns. 如請求項2所述之半導體元件，其中該第一通孔的一頂表面的一寬度小於該第二通孔的該頂表面的一寬度。 The semiconductor device according to claim 2, wherein a width of a top surface of the first via hole is smaller than a width of the top surface of the second via hole. 如請求項2所述之半導體元件，其中該第二通孔的該頂表面的一寬度小於該第三通孔的一頂表面的一寬度。 The semiconductor device as claimed in claim 2, wherein a width of the top surface of the second via hole is smaller than a width of a top surface of the third via hole. 如請求項2所述之半導體元件，其中該基板的一厚度小於約200微米。 The semiconductor device of claim 2, wherein a thickness of the substrate is less than about 200 microns. 如請求項2所述之半導體元件，其中該基板的一厚度小於約5微米。 The semiconductor device of claim 2, wherein a thickness of the substrate is less than about 5 microns. 如請求項2所述之半導體元件，其中該第一鈍化層包括一氧化物材料。 The semiconductor device as claimed in claim 2, wherein the first passivation layer comprises an oxide material. 如請求項1所述之半導體元件，其中該第一絕緣層包括一氧化物材料，該導電襯墊由至少下列之一的材料組成：鎢、鈷、鋯、鉭、鈦、鋁、釕、銅、金屬碳化物、金屬氮化物、過渡金屬鋁化物、或前述之組合。 The semiconductor device as claimed in claim 1, wherein the first insulating layer comprises an oxide material, and the conductive liner is composed of at least one of the following materials: tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper , metal carbides, metal nitrides, transition metal aluminides, or a combination of the foregoing. 如請求項2所述之半導體元件，更包括一頂部鈍化層，位於該第三層的該第三絕緣層上。 The semiconductor device as claimed in claim 2, further comprising a top passivation layer on the third insulating layer of the third layer. 如請求項11所述之半導體元件，更包括一第一頂部開口，沿著該頂部鈍化層設置以暴露出該第三通孔。 The semiconductor device as claimed in claim 11, further comprising a first top opening disposed along the top passivation layer to expose the third via hole. 如請求項1所述之半導體元件，其中該多堆疊載體結構的一厚度與該基板的一厚度的一厚度比介於大約180：1至大約50：1之間。 The semiconductor device of claim 1, wherein a thickness ratio of a thickness of the multi-stacked carrier structure to a thickness of the substrate is between about 180:1 and about 50:1. 如請求項1所述之半導體元件，其中該第一通孔的一側壁為漸縮的且該第一通孔的一頂表面的一寬度大於該第一通孔的一底表面的一寬度。 The semiconductor device as claimed in claim 1, wherein a sidewall of the first via hole is tapered and a width of a top surface of the first via hole is greater than a width of a bottom surface of the first via hole. 如請求項1所述之半導體元件，其中該第一通孔包括一隔離層，其中該填料層沿著該第一絕緣層和該第一鈍化層設置且位於該導電襯墊上，該隔離層位於該填料層和該第一絕緣層之間且位於該填料層和該第一鈍化層之間。 The semiconductor device as claimed in claim 1, wherein the first via hole includes an isolation layer, wherein the filler layer is disposed along the first insulating layer and the first passivation layer and is located on the conductive pad, the isolation layer Located between the filler layer and the first insulating layer and between the filler layer and the first passivation layer. 如請求項15所述之半導體元件，其中該第一通孔包括一障壁層，位於該填料層和該隔離層之間且位於該填料層和該導電襯墊之間。 The semiconductor device as claimed in claim 15, wherein the first via hole includes a barrier layer between the filler layer and the isolation layer and between the filler layer and the conductive liner. 如請求項16所述之半導體元件，其中該第一通孔包括一黏附層，位於該填料層和該障壁層之間。 The semiconductor device as claimed in claim 16, wherein the first via hole includes an adhesive layer between the filler layer and the barrier layer. 如請求項17所述之半導體元件，其中該第一通孔包括一種子層，位於該填料層和該黏附層之間。 The semiconductor device as claimed in claim 17, wherein the first via hole includes a seed layer located between the filler layer and the adhesion layer. 如請求項1所述之半導體元件，其中該多堆疊載體結構包括一重分佈層，位於該第三通孔上且透過該第三通孔、該第二通孔、和該第一通孔電性耦合至該導電襯墊。 The semiconductor device as claimed in claim 1, wherein the multi-stacked carrier structure includes a redistribution layer located on the third via and electrically conductive through the third via, the second via, and the first via coupled to the conductive pad. 一種多堆疊載體結構，包括：一蝕刻停止層；一第一層，包括位於該蝕刻停止層上的一第一鈍化層、位於該第一鈍化層上的一第一絕緣層、以及一第一通孔，其中該第一通孔沿著該第一鈍化層和該第一絕緣層設置；一第二層，位於該第一層上且包括位於該第一絕緣層上的一第二鈍化層、位於該第二鈍化層上的一第二絕緣層、以及一第二通孔，其中該第二通孔沿著該第二鈍化層和該第二絕緣層設置且電性連接至該第一通孔；以及一第三層，位於該第二層上且包括位於該第二絕緣層上的一第三鈍化層、位於該第三鈍化層上的一第三絕緣層、以及一第三通孔，其中該第三通孔沿著該第三鈍化層和該第三絕緣層設置且電性連接 至該第二通孔，該第二通孔具有導電的一填料層，其中該填料層的一頂表面與該第二絕緣層的一頂表面共平面，以及，該第三通孔的一底表面至少部分在該第二通孔的一頂表面之一垂直投影區域之外。 A multi-stacked carrier structure, comprising: an etch stop layer; a first layer including a first passivation layer on the etch stop layer, a first insulating layer on the first passivation layer, and a first a via hole, wherein the first via hole is disposed along the first passivation layer and the first insulating layer; a second layer is located on the first layer and includes a second passivation layer located on the first insulating layer , a second insulating layer on the second passivation layer, and a second via hole, wherein the second via hole is arranged along the second passivation layer and the second insulating layer and is electrically connected to the first via hole; and a third layer located on the second layer and including a third passivation layer located on the second insulating layer, a third insulating layer located on the third passivation layer, and a third via hole, wherein the third via hole is arranged along the third passivation layer and the third insulating layer and is electrically connected To the second via hole, the second via hole has a conductive filler layer, wherein a top surface of the filler layer is coplanar with a top surface of the second insulating layer, and a bottom of the third via hole The surface is at least partially outside the area of a vertical projection of a top surface of the second through hole. 如請求項20所述之多堆疊載體結構，其中該多堆疊載體結構的一厚度大於約500微米。 The multi-stack carrier structure of claim 20, wherein a thickness of the multi-stack carrier structure is greater than about 500 microns. 如請求項20所述之多堆疊載體結構，其中該第一絕緣層的一厚度小於約200微米。 The multi-stacked carrier structure of claim 20, wherein a thickness of the first insulating layer is less than about 200 microns. 如請求項20所述之多堆疊載體結構，其中該第一鈍化層的一厚度介於大約1微米至大約2微米之間。 The multi-stack carrier structure of claim 20, wherein a thickness of the first passivation layer is between about 1 micron and about 2 microns. 如請求項20所述之多堆疊載體結構，其中該第一通孔的一頂表面的一寬度小於該第二通孔的該頂表面的一寬度。 The multi-stacked carrier structure of claim 20, wherein a width of a top surface of the first via is smaller than a width of the top surface of the second via. 如請求項20所述之多堆疊載體結構，其中該第二通孔的該頂表面的一寬度小於該第三通孔的一頂表面的一寬度。 The multi-stacked carrier structure of claim 20, wherein a width of the top surface of the second via is smaller than a width of a top surface of the third via.
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