TWI802524B - Package structure with FOWBCSP chip type and manufacturing method thereof - Google Patents
Package structure with FOWBCSP chip type and manufacturing method thereof Download PDFInfo
- Publication number
- TWI802524B TWI802524B TW111145037A TW111145037A TWI802524B TW I802524 B TWI802524 B TW I802524B TW 111145037 A TW111145037 A TW 111145037A TW 111145037 A TW111145037 A TW 111145037A TW I802524 B TWI802524 B TW I802524B
- Authority
- TW
- Taiwan
- Prior art keywords
- chip
- substrate
- contacts
- packaging structure
- glass
- Prior art date
Links
Images
Landscapes
- Wire Bonding (AREA)
- Ceramic Capacitors (AREA)
Abstract
一種具有FOWBCSP晶片型態的封裝結構及其製造方法,該封裝結構包含一晶片,其上方包含接點;一第一封裝結構位在該晶片下方與側邊;一基板置於該晶片之上方,其中該基板對應該晶片之接點的位置則形成穿透之板孔,而該基板的上方形成接點;由導線經過基板之板孔連接該基板之接點及該晶片之接點;其中該基板之各該板孔分別形成一第二封裝結構係應用膠材密封該板孔而形成,並且該基板上方的接點具有導接球。 A packaging structure with a FOWBCSP chip type and a manufacturing method thereof, the packaging structure includes a chip, the top of which includes contacts; a first packaging structure is located below and on the side of the chip; a substrate is placed above the chip, Wherein the position of the substrate corresponding to the contact point of the chip forms a penetrating plate hole, and a contact point is formed above the substrate; the lead wire passes through the plate hole of the substrate to connect the contact point of the substrate and the contact point of the chip; wherein the Each of the board holes of the substrate respectively forms a second packaging structure, which is formed by sealing the board holes with adhesive material, and the contacts above the substrate have conductive balls.
Description
本發明係有關於半導體封裝結構,尤其是一種具有FOWBCSP晶片型態的封裝結構及其製造方法。 The present invention relates to a semiconductor package structure, especially a package structure with a FOWBCSP chip type and a manufacturing method thereof.
習知技術的半導體晶片封裝結構中,係將晶片的接點置於上方,基板的接點也置於上方,然後再應用裸露的導線應用晶片的接點連接基板的接點。另外基板上則形成貫穿孔以填注導電材料,使得基板的接點晶由該填注有導電材料的貫穿孔而導引到基板的下方。然後電路板則位在該基板的下方,使得該電路板上的接點與基板的接點相連接,整體上達成電連接的目的。 In the prior art semiconductor chip packaging structure, the contacts of the chip are placed on the top, and the contacts of the substrate are also placed on the top, and then the contacts of the chip are used to connect the contacts of the substrate with exposed wires. In addition, a through hole is formed on the substrate to fill the conductive material, so that the contact crystal of the substrate is guided to the bottom of the substrate through the through hole filled with the conductive material. Then the circuit board is positioned under the substrate, so that the contacts on the circuit board are connected to the contacts on the substrate, and the purpose of electrical connection is achieved as a whole.
封裝時,則必須把晶片及基板完全包覆連接,所以必須封裝一較大之區域以避免導線裸露在外,所以封裝的成本較高且時間也較長。 When packaging, the chip and the substrate must be completely covered and connected, so a larger area must be packaged to avoid the exposed wires, so the cost of packaging is higher and the time is longer.
另外基板上必須形成多個貫穿孔分別灌注導電材料,這些貫穿孔必須分別形成,彼此不可互相連通以避免短路,所以製造上相當耗時、耗工,也增加了整體的製造成本。 In addition, a plurality of through-holes must be formed on the substrate to be poured with conductive materials, and these through-holes must be formed separately and cannot communicate with each other to avoid short circuits. Therefore, the manufacturing is time-consuming and labor-intensive, and increases the overall manufacturing cost.
故本案希望提出一種嶄新的具有FOWBCSP晶片型態的封裝結構及其製造方法,以解決上述先前技術上的缺陷。 Therefore, this case hopes to propose a brand-new packaging structure with FOWBCSP chip type and its manufacturing method to solve the above-mentioned defects in the prior art.
所以本發明的目的係為解決上述習知技術上的間題,本發明中提出一種具有FOWBCSP晶片型態的封裝結構及其製造方法,其優點為在基板上只需要形成少數個板孔,而使得多個導線同時通過一板孔,不若傳統的結構必須形成多個板孔,所以製造期間縮短而且成本也降低。再者本案在封裝時僅需要對有可能裸露導線的少數區域進行封裝,而不必像傳統的結構及封裝的區域片不整個晶片及基板的上方,所以本案的封裝方式可以節省成本及工時。再者因為導線的長度較短而且大部分隱藏在板孔內部,所以不至於造成導線裸露,而導致其他危害的問題。 Therefore, the purpose of the present invention is to solve the problems in the above-mentioned prior art. In the present invention, a packaging structure with a FOWBCSP chip type and its manufacturing method are proposed. The advantage is that only a small number of plate holes need to be formed on the substrate, and Multiple wires pass through one plate hole at the same time, instead of forming multiple plate holes in the traditional structure, so the manufacturing period is shortened and the cost is also reduced. In addition, in this case, only a small number of areas that may be exposed to wires need to be packaged during packaging, instead of the traditional structure and the packaged area is not above the entire chip and substrate, so the packaging method of this case can save costs and man-hours. Furthermore, because the length of the wire is short and most of it is hidden inside the plate hole, it will not cause the wire to be exposed and cause other hazards.
為達到上述目的本發明中提出一種具有FOWBCSP晶片型態的封裝結構,包含:一晶片,該晶片之上方包含接點;一第一封裝結構位在該晶片下方與側邊;一基板置於該晶片之上方,其中該基板對應該晶片之接點的位置則形成穿透之板孔,而該基板的上方形成接點;由導線經過基板之板孔連接該基板之接點及該晶片之接點;以及其中該基板之各該板孔分別形成一第二封裝結構係應用膠材密封該板孔而形成,並且該基板上方的接點具有導接球。 In order to achieve the above object, the present invention proposes a packaging structure with a FOWBCSP chip type, comprising: a chip, the top of the chip includes contacts; a first packaging structure is positioned at the bottom and side of the chip; a substrate is placed on the chip. On the top of the chip, the position of the substrate corresponding to the contact of the chip forms a penetrating plate hole, and the top of the substrate forms a contact; the contact of the substrate and the contact of the chip are connected by a wire passing through the plate hole of the substrate and wherein each of the board holes of the substrate respectively forms a second packaging structure, which is formed by sealing the board holes with adhesive material, and the contacts above the substrate have conductive balls.
本案尚提出一種具有FOWBCSP晶片型態的封裝結構的製造方法,包含下列步驟:步驟A:取一晶片,該晶片之下方含接點;將一非黏性膜置於該晶片的下方,再將載板置於該非黏性膜之下方;並在該晶片的上方與側邊形成第一封裝結構;然後將整體結構運送至預定之位置;步驟B:卸下該載板及該非黏性膜,並將該晶片反轉,以使得該晶片的接點位在該晶片之上方;而該第一封裝結構則反轉至下方;步驟C:將一基板置於該晶片之上方,其中該基板對應該晶片之接點的位置則形成穿透之板孔,而在該基板的上 方形成接點;應用導線經過基板之板孔連接該基板之接點及該晶片之接點;步驟D:應用膠材密封該基板之板孔形成第二封裝結構,並在該基板上方的接點形成導接球,而形成一整合結構。 This case still proposes a kind of manufacturing method that has the package structure of FOWBCSP chip form, comprises the following steps: Step A: Take a chip, the bottom of this chip contains contacts; Place a non-adhesive film on the bottom of this chip, and then The carrier is placed under the non-adhesive film; and a first packaging structure is formed on the top and side of the chip; then the overall structure is transported to a predetermined position; step B: unloading the carrier and the non-adhesive film, and turning the wafer over so that the contacts of the wafer are above the wafer; and the first packaging structure is reversed to the bottom; step C: placing a substrate above the wafer, wherein the substrate is The position of the contact point of the chip should be formed through the plate hole, and on the substrate Form the contacts; use wires to connect the contacts of the substrate and the contacts of the chip through the holes of the substrate; step D: apply glue to seal the holes of the substrate to form a second package structure, and connect the contacts above the substrate The dots form conductive balls to form an integrated structure.
由下文的說明可更進一步瞭解本發明的特徵及其優點,閱讀時並請參考附圖。 The features and advantages of the present invention can be further understood from the following description, please refer to the accompanying drawings when reading.
1:第一封裝結構 1: The first package structure
2:第二封裝結構 2: The second package structure
10:晶片 10: Wafer
11:接點 11: Contact
12:光感測區 12: Light sensing area
20:基板 20: Substrate
21:接點 21: Contact
22:板孔 22: plate hole
23:鏤空區域 23: hollow area
30:導接球 30: Guide and catch the ball
40:電路板 40: circuit board
41:接點 41: contact
42:穿孔 42: perforation
50:內晶片 50: inner chip
51:接點 51: contact
60:導線 60: wire
61:導線 61: wire
70:CMOS晶片 70: CMOS chip
80:隔離膜 80: isolation film
81:擋提 81: Block lift
90:玻璃 90: glass
100:非黏性膜 100: non-adhesive film
110:載板 110: carrier board
200:膠材 200: Glue
231:內接點 231: Inner contact
232:封裝材料 232: Encapsulation material
300:封裝結構 300: package structure
圖1顯示本案之第一實施例之晶片、基板及電路板之分解示意圖。 FIG. 1 shows an exploded view of the chip, substrate and circuit board of the first embodiment of the present invention.
圖2A顯示本案之第一實施例之步驟A之元件配置之截面示意圖。 FIG. 2A shows a schematic cross-sectional view of the device configuration in step A of the first embodiment of the present invention.
圖2B顯示本案之第一實施例之步驟B之元件配置之截面示意圖。 FIG. 2B shows a schematic cross-sectional view of the device configuration in step B of the first embodiment of the present invention.
圖2C顯示本案之第一實施例之步驟B之元件配置之另一截面示意圖。 FIG. 2C shows another schematic cross-sectional view of the device configuration in step B of the first embodiment of the present invention.
圖2D顯示本案之第一實施例之步驟C之元件配置之截面示意圖。 FIG. 2D shows a schematic cross-sectional view of the device configuration in step C of the first embodiment of the present invention.
圖2E顯示本案之第一實施例之步驟D之元件配置之截面示意圖。 FIG. 2E shows a schematic cross-sectional view of the device configuration in step D of the first embodiment of the present invention.
圖2F顯示本案之第一實施例之應用示意圖。 FIG. 2F shows a schematic diagram of the application of the first embodiment of the present invention.
圖3A顯示本案之第一實施例之元件組合之截面示意圖。 FIG. 3A shows a schematic cross-sectional view of the component combination of the first embodiment of the present invention.
圖3B顯示圖3A之元件組合之應用例之截面示意圖。 FIG. 3B shows a schematic cross-sectional view of an application example of the combination of components in FIG. 3A .
圖4A顯示本案之第二實施例之步驟A之元件配置之截面示意圖。 FIG. 4A shows a schematic cross-sectional view of the device configuration in step A of the second embodiment of the present invention.
圖4B顯示本案之第二實施例之步驟B之元件配置之截面示意圖。 FIG. 4B shows a schematic cross-sectional view of the device configuration in step B of the second embodiment of the present invention.
圖4C顯示本案之第二實施例之步驟B之元件配置之另一截面示意圖。 FIG. 4C shows another schematic cross-sectional view of the device configuration in step B of the second embodiment of the present invention.
圖4D顯示本案之第二實施例之步驟C之元件配置之截面示意圖。 FIG. 4D shows a schematic cross-sectional view of the device configuration in step C of the second embodiment of the present invention.
圖4E顯示本案之第二實施例之步驟D之元件配置之截面示意圖。 FIG. 4E shows a schematic cross-sectional view of the device arrangement in step D of the second embodiment of the present invention.
圖5顯示本案之第二實施例之元件組合之截面示意圖。 FIG. 5 shows a schematic cross-sectional view of the component assembly of the second embodiment of the present invention.
圖6顯示本案之第三實施例之多個晶片、基板及電路板之分解示意圖。 FIG. 6 shows an exploded schematic diagram of a plurality of chips, substrates and circuit boards of the third embodiment of the present invention.
圖7A顯示本案之第三實施例之步驟A1之元件配置之截面示意圖。 FIG. 7A shows a schematic cross-sectional view of the device arrangement in step A1 of the third embodiment of the present invention.
圖7B顯示本案之第三實施例之步驟B1之元件配置之截面示意圖。 FIG. 7B shows a schematic cross-sectional view of the device arrangement in step B1 of the third embodiment of the present invention.
圖7C顯示本案之第三實施例之步驟B1之元件配置之另一截面示意圖。 FIG. 7C shows another schematic cross-sectional view of the device arrangement in step B1 of the third embodiment of the present invention.
圖7D顯示本案之第三實施例之步驟C1之元件配置之截面示意圖。 FIG. 7D shows a schematic cross-sectional view of the device arrangement in step C1 of the third embodiment of the present invention.
圖7E顯示本案之第三實施例之步驟D1之元件配置之截面示意圖。 FIG. 7E shows a schematic cross-sectional view of the device arrangement in step D1 of the third embodiment of the present invention.
圖7F顯示本案之第三實施例之應用示意圖。 FIG. 7F shows a schematic diagram of the application of the third embodiment of the present invention.
圖8顯示本案之第四實施例之晶片、基板及電路板之分解示意圖。 FIG. 8 shows an exploded view of the chip, substrate and circuit board of the fourth embodiment of the present case.
圖9A顯示本案之第四實施例之步驟A2之元件配置之截面示意圖。 FIG. 9A shows a schematic cross-sectional view of the device arrangement in step A2 of the fourth embodiment of the present invention.
圖9B顯示本案之第四實施例之步驟B2之元件配置之截面示意圖。 FIG. 9B shows a schematic cross-sectional view of the component arrangement in step B2 of the fourth embodiment of the present invention.
圖9C顯示本案之第四實施例之步驟B2之元件配置之另一截面示意圖。 FIG. 9C shows another schematic cross-sectional view of the device arrangement in step B2 of the fourth embodiment of the present invention.
圖9D顯示本案之第四實施例之步驟C2之元件配置之截面示意圖。 FIG. 9D shows a schematic cross-sectional view of the device arrangement in step C2 of the fourth embodiment of the present invention.
圖9E顯示本案之第四實施例之步驟C2之元件配置之另一截面示意圖。 FIG. 9E shows another schematic cross-sectional view of the device arrangement in step C2 of the fourth embodiment of the present invention.
圖9F顯示本案之第四實施例之步驟D2之元件配置之截面示意圖。 FIG. 9F shows a schematic cross-sectional view of the device arrangement in step D2 of the fourth embodiment of the present invention.
圖9G顯示本案之第四實施例之應用示意圖。 FIG. 9G shows a schematic diagram of the application of the fourth embodiment of the present application.
圖10A顯示本案之第四實施例之元件組合之截面示意圖。 FIG. 10A shows a schematic cross-sectional view of the component combination of the fourth embodiment of the present invention.
圖10B顯示圖10A之元件組合之應用例之截面示意圖。 FIG. 10B shows a schematic cross-sectional view of an application example of the combination of components in FIG. 10A .
圖11顯示本案之第一實施例之製造方法之步驟流程圖。 FIG. 11 shows a flow chart of the steps of the manufacturing method of the first embodiment of the present invention.
圖12顯示本案之第二實施例之製造方法之步驟流程圖。 FIG. 12 shows a flow chart of the steps of the manufacturing method of the second embodiment of the present invention.
圖13顯示本案之第三實施例之製造方法之步驟流程圖。 FIG. 13 shows a flow chart of the steps of the manufacturing method of the third embodiment of the present invention.
圖14顯示本案之第四實施例之製造方法之步驟流程圖。 FIG. 14 shows a flow chart of the steps of the manufacturing method of the fourth embodiment of the present invention.
茲謹就本案的結構組成,及所能產生的功效與優點,配合圖式,舉本 案之一較佳實施例詳細說明如下。 Hereby, I would like to cite the structure of this case, as well as the functions and advantages that can be produced, in conjunction with the diagram. A preferred embodiment of the scheme is described in detail as follows.
請參考圖1至圖2F、及圖11所示,顯示本發明之具有FOWBCSP晶片型態的封裝結構的製造方法之第一實施例,包含下列步驟: Please refer to FIG. 1 to FIG. 2F, and shown in FIG. 11, which shows the first embodiment of the manufacturing method of the packaging structure with the FOWBCSP chip type of the present invention, including the following steps:
步驟A:如圖2A所示,取一晶片10,該晶片10之下方含接點11。將一非黏性膜100置於該晶片10的下方,再將載板110置於該非黏性膜100之下方;並在該晶片10的上方與側邊形成第一封裝結構1。然後將整體結構運送至預定之位置;
Step A: As shown in FIG. 2A , take a
步驟B:如圖2B所示,卸下該載板110及該非黏性膜100,並將該晶片10反轉(如圖2C所示),以使得該晶片10的接點11位在該晶片10之上方;而該第一封裝結構1則反轉至下方。
Step B: As shown in FIG. 2B, remove the
步驟C:如圖2D所示,將一基板20置於該晶片10之上方,其中該基板20對應該晶片10之接點11的位置則形成穿透之板孔22,而在該基板20的上方形成接點21。應用導線60經過基板20之板孔22連接該基板20之接點21及該晶片10之接點11。
Step C: As shown in FIG. 2D, a
步驟D:如圖2E所示,應用膠材200密封該基板20之板孔22形成第二封裝結構2,並在該基板20上方的接點21形成導接球30(該導接球30如錫球或焊球),而形成一整合結構。
Step D: As shown in FIG. 2E , apply
如圖2F所示,應用時可在上述整合結構的該基板20的上方配置一電路板40,其中該電路板40可形成接點41以接引該基板20上方的接點21上的導接球30,以形成電連通。
As shown in FIG. 2F , a
本案應用上述結構形成具有FOWBCSP晶片型態的封裝結構300,如圖3A所示,包含:
In this case, the above-mentioned structure is used to form a
一晶片10,該晶片10之上方包含接點11。
A
一第一封裝結構1位在該晶片10下方與側邊。
A
一基板20置於該晶片10之上方,其中該基板20對應該晶片10之接點11的位置則形成穿透之板孔22,而該基板20的上方形成接點21。由導線60經過基板20之板孔22連接該基板20之接點21及該晶片10之接點11。
A
其中該基板20之各該板孔22分別形成一第二封裝結構2係應用膠材200密封該板孔22而形成,並且該基板20上方的接點21具有導接球30(該導接球30如錫球或焊球)。
Wherein each of the board holes 22 of the
如圖3B所示,應用時該基板20的上方係配置一電路板40,其中該電路板40可形成接點41以接引該基板20上方的接點21上的導接球30,以形成電連通。
As shown in FIG. 3B , a
本案尚包含第二實施例,如圖4A至圖4E、及圖12所示。其中第二實施例的步驟與第一實施例的步驟完全相同,圖3A所示之步驟A及圖3B至圖3C所示之步驟B,其內容與上述第一實施例的步驟A、B完全相同,所以不再此贅述其內容。惟在步驟C中,如圖3D所示,該基板20內部下方形成鏤空區域23,並將鏤空區域23安裝至少一內晶片50(以別於其他不在鏤空區域23之晶片10),該內晶片50以其下方之接點51經由導線61連接鏤空區域23內壁面的該基板20之內接點231(以別於上述基板20上方之接點21),其中該內接點231係貫穿該基板20本身而裸露於該基板20之上方。並應用封裝材料232將該鏤空區域23整體封裝。隨後之步驟D則如圖3E所示,其內容與上述第一實施例的步驟D完全相同,所以不再此贅述。
This case still includes the second embodiment, as shown in FIG. 4A to FIG. 4E and FIG. 12 . Wherein the steps of the second embodiment are exactly the same as the steps of the first embodiment, step A shown in Figure 3A and step B shown in Figure 3B to Figure 3C, its content is completely the same as the steps A and B of the first embodiment above The same, so I won't repeat its content here. However, in step C, as shown in FIG. 3D, a
如圖5所示,所以經由上述的步驟,原圖3中的具有FOWBCSP晶片型態
的封裝結構300更進一步形成如圖5所示的型態。圖5中的結構與圖3相同的元件具有相同的結構及功效,所以不再贅述其細節,惟圖5中之結構尚包含:
As shown in Figure 5, so through the above steps, the original Figure 3 has a FOWBCSP wafer type
The
該基板20內部下方形成鏤空區域23,並且該鏤空區域23安裝至少一內晶片50(以別於其他不在鏤空區域23之晶片10),該內晶片50的下方之接點51經由導線61連接鏤空區域23內壁面的該基板20之內接點231(以別於上述基板20上方之接點21),其中該內接點231係貫穿該基板20本身而裸露於該基板20之上方。並由封裝材料232封裝該鏤空區域23。
A hollowed-
本案尚包含第三實施例,如圖6至圖7E、及圖13所示,其中顯示本案中同時封裝多個晶片10的結構,其處理步驟如下:
This case still includes the third embodiment, as shown in Figure 6 to Figure 7E and Figure 13, which shows the structure of packaging
步驟A1:如圖7A所示,取多個晶片10,各該晶片10之下方含接點11。將一非黏性膜100置於該多個晶片10的下方,再將載板110置於該非黏性膜100之下方;並在該多個晶片10的上方與側邊形成第一封裝結構1。然後將整體結構運送至預定之位置;
Step A1: As shown in FIG. 7A, take a plurality of
步驟B1:如圖7B所示,卸下該載板110及該非黏性膜100,並將該多個晶片10反轉(如圖7C所示),以使得各該晶片10的接點11位在對應之各該晶片10之上方;而該第一封裝結構1則反轉至下方。
Step B1: As shown in FIG. 7B, remove the
步驟C1:如圖7D所示,將一基板20置於該多個晶片10之上方,其中該基板20對應該多個晶片10之接點11的位置則形成穿透之多個板孔22,而在該基板20的上方形成多個接點21。應用多數導線60經過基板20之多個板孔22連接該基板20之多個接點21及該多個晶片10之接點11。
Step C1: As shown in FIG. 7D , place a
步驟D1:如圖7E所示,應用膠材200密封該基板20之多個板孔22形成第二封裝結構2,並在該基板20上方的多個接點21形成多個導接球30(該導接球
30如錫球或焊球)。
Step D1: As shown in FIG. 7E , apply
如圖7F所示,應用時可視需要依據各個晶片10的位置進行切割,而使得各個晶片10及其相關的基板20等形成一整合結構;再將上述整合結構的該基板20的上方配置電路板40,該電路板40可形成接點41以接引該基板20上方的接點21上的導接球30,以形成電連通。
As shown in FIG. 7F , during application, cutting may be performed according to the position of each
本案中上述的晶片10可以是MCU晶片或邏輯晶片等各種不同形式的晶片。
In this case, the
本案尚包含第四實施例,如圖8至圖9G、及圖14所示,其中在上述各實施例中的晶片10也可以是CMOS晶片70,其詳細的操作步驟說明如下:
This case still includes the fourth embodiment, as shown in Fig. 8 to Fig. 9G and Fig. 14, wherein the
步驟A2:如圖9A所示,取一晶片10,該晶片10為CMOS晶片70,該晶片10之下方包含接點11及光感測區12用於接收外部的光線並傳入內部以令CMOS感光。將一非黏性膜100置於該晶片10的下方,再將載板110置於該非黏性膜100之下方;並在該晶片10的上方與側邊形成第一封裝結構1。然後將整體結構運送至預定之位置;
Step A2: As shown in FIG. 9A, take a
步驟B2:如圖9B所示,卸下該載板110及該非黏性膜100,並將該晶片10反轉(如圖9C所示),以使得該晶片10的該接點11及該光感測區12位在該晶片10之上方;而該第一封裝結構1則反轉至下方。
Step B2: As shown in FIG. 9B, remove the
步驟C2:如圖9D所示,將一基板20置於該晶片10之上方,其中該基板20對應該晶片10之接點11及光感測區12之位置則形成穿透之板孔22,而在該基板20的上方形成接點21;
Step C2: As shown in FIG. 9D , place a
然後在該晶片10的該光感測區12的上方形成隔離膜80,在該隔離膜80的兩側分別形成擋堤81,然後將該隔離膜80去除,在該兩擋堤81之間放置
玻璃90(如圖9E所示);以及
Then an
隨後應用導線60經過基板20之板孔22連接該基板20之接點21及該晶片10之接點11。
Then,
步驟D2:如圖9F所示,應用膠材200密封該基板20之板孔22形成第二封裝結構2,而並不覆蓋該玻璃90,以使得該玻璃90外露,而使得外部的光線可以直接經由該玻璃90照射該CMOS晶片70,並在該基板20上方的接點21形成導接球30(該導接球30如錫球或焊球),而形成一整合結構。
Step D2: As shown in FIG. 9F , apply
如圖9G所示,應用時可在上述整合結構的該基板20的上方配置電路板40,其中該電路板40為軟板,且該電路板40上形成一穿透之穿孔42,該穿孔42的位置係對應於該玻璃90,而使得外部的光線可以經由該穿孔42穿透該玻璃90而照射該CMOS晶片70。其中該電路板40可形成接點41以接引該基板20上方的接點21上的導接球30,以形成電連通。
As shown in FIG. 9G , a
本案應用上述結構形成具有FOWBCSP晶片型態的封裝結構300,如圖10A所示,包含:
In this case, the above-mentioned structure is used to form a
一CMOS晶片70,該晶片10之上方包含接點11及光感測區12。
A
一第一封裝結構1位在該CMOS晶片70下方與側邊。
A
一基板20置於該CMOS晶片70之上方,其中該基板20對應該CMOS晶片70之接點11及光感測區12之位置則形成穿透之板孔22;而該基板20的上方形成接點21。由導線60經過基板20之板孔22連接該基板20之接點21及該CMOS晶片70之接點11。
A
兩擋堤81,位於該CMOS晶片70的該光感測區12的上方的兩側。
Two
一玻璃90置於該兩擋堤81之間。
A
其中該基板20之各該板孔22分別形成一第二封裝結構2係應用膠材200密封該板孔22而形成,而並不覆蓋該玻璃90,以使得該玻璃90外露,因此外部的光線可以直接經由該玻璃90照射該CMOS晶片70。
Each of the plate holes 22 of the
該基板20上方的接點21具有導接球30(該導接球30如錫球或焊球)。
The
如圖10B所示,應用時該基板20的上方係配置一電路板40,其中該電路板40可形成接點41以接引該基板20上方的接點21上的導接球30,以形成電連通。
As shown in FIG. 10B , a
同樣的,如同上述第三實施例,本案也可以應用多個CMOS晶片70互相並排以進行上述的封裝程序,因其製程同於第三實施例,所以茲不說明其細節。
Similarly, like the above-mentioned third embodiment,
本案的優點為在基板上只需要形成少數個板孔,而使得多個導線同時通過一板孔,不若傳統的結構必須形成多個板孔,所以製造期間縮短而且成本也降低。再者本案在封裝時僅需要對有可能裸露導線的少數區域進行封裝,而不必像傳統的結構及封裝的區域片不整個晶片及基板的上方,所以本案的封裝方式可以節省成本及工時。再者因為導線的長度較短而且大部分隱藏在板孔內部,所以不至於造成導線裸露,而導致其他危害的問題。 The advantage of this case is that only a few plate holes need to be formed on the substrate, so that multiple wires pass through one plate hole at the same time, unlike the traditional structure that must form multiple plate holes, so the manufacturing period is shortened and the cost is also reduced. In addition, in this case, only a small number of areas that may be exposed to wires need to be packaged during packaging, instead of the traditional structure and the packaged area is not above the entire chip and substrate, so the packaging method of this case can save costs and man-hours. Furthermore, because the length of the wire is short and most of it is hidden inside the plate hole, it will not cause the wire to be exposed and cause other hazards.
綜上所述,本案人性化之體貼設計,相當符合實際需求。其具體改進現有缺失,相較於習知技術明顯具有突破性之進步優點,確實具有功效之增進,且非易於達成。本案未曾公開或揭露於國內與國外之文獻與市場上,已符合專利法規定。 To sum up, the humanized and thoughtful design of this case is quite in line with actual needs. Its specific improvement has existing deficiencies, and compared with the prior art, it has the advantage of breakthrough progress, and indeed has the enhancement of efficacy, and it is not easy to achieve. This case has not been published or disclosed in domestic and foreign literature and market, which is in compliance with the provisions of the patent law.
上列詳細說明係針對本發明之一可行實施例之具體說明,惟該實施例並非用以限制本發明之專利範圍,凡未脫離本發明技藝精神所為之等效實 施或變更,均應包含於本案之專利範圍中。 The above detailed description is a specific description of a feasible embodiment of the present invention, but this embodiment is not used to limit the patent scope of the present invention, any equivalent practice that does not depart from the technical spirit of the present invention Any implementation or modification shall be included in the patent scope of this case.
1:第一封裝結構 1: The first package structure
2:第二封裝結構 2: The second package structure
10:晶片 10: Wafer
11:接點 11: Contact
20:基板 20: Substrate
21:接點 21: Contact
22:板孔 22: plate hole
30:導接球 30: Guide and catch the ball
40:電路板 40: circuit board
41:接點 41: contact
60:導線 60: wire
200:膠材 200: Glue
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW111145037A TWI802524B (en) | 2018-03-16 | 2018-03-16 | Package structure with FOWBCSP chip type and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW111145037A TWI802524B (en) | 2018-03-16 | 2018-03-16 | Package structure with FOWBCSP chip type and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
TW202315017A TW202315017A (en) | 2023-04-01 |
TWI802524B true TWI802524B (en) | 2023-05-11 |
Family
ID=86943022
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW111145037A TWI802524B (en) | 2018-03-16 | 2018-03-16 | Package structure with FOWBCSP chip type and manufacturing method thereof |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI802524B (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030092217A1 (en) * | 2001-02-02 | 2003-05-15 | Coyle Anthony L. | Flip chip semiconductor device in a molded chip scale package (CSP) and method of assembly |
TWM538241U (en) * | 2016-02-23 | 2017-03-11 | 冠亞智財股份有限公司 | Multi-chips in system level and wafer level package structure |
TWM538264U (en) * | 2016-09-08 | 2017-03-11 | 正崴精密工業股份有限公司 | Audio jack connector |
-
2018
- 2018-03-16 TW TW111145037A patent/TWI802524B/en active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030092217A1 (en) * | 2001-02-02 | 2003-05-15 | Coyle Anthony L. | Flip chip semiconductor device in a molded chip scale package (CSP) and method of assembly |
TWM538241U (en) * | 2016-02-23 | 2017-03-11 | 冠亞智財股份有限公司 | Multi-chips in system level and wafer level package structure |
TWM538264U (en) * | 2016-09-08 | 2017-03-11 | 正崴精密工業股份有限公司 | Audio jack connector |
Also Published As
Publication number | Publication date |
---|---|
TW202315017A (en) | 2023-04-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11961867B2 (en) | Electronic device package and fabricating method thereof | |
TW526598B (en) | Manufacturing method of semiconductor device and semiconductor device | |
US6864434B2 (en) | Warpage-preventive circuit board and method for fabricating the same | |
US7719104B2 (en) | Circuit board structure with embedded semiconductor chip and method for fabricating the same | |
US20050248011A1 (en) | Flip chip semiconductor package for testing bump and method of fabricating the same | |
KR20190088235A (en) | Semiconductor package including multi-dies stack and method of fabricating the same | |
TWI556379B (en) | Semiconductor package and manufacturing method thereof | |
TW201813025A (en) | Packing structure and packing method | |
US9613894B2 (en) | Electronic package | |
JP2010141295A (en) | Shrink package on board | |
US10755994B2 (en) | Semiconductor package structure and semiconductor substrate | |
US10396040B2 (en) | Method for fabricating electronic package having a protruding barrier frame | |
KR100959604B1 (en) | Wafer level semiconductor package and method of manufacturing the same | |
TW201611202A (en) | Semiconductor package and method for fabricating the same | |
TW201032307A (en) | Window type semiconductor package | |
US20090134504A1 (en) | Semiconductor package and packaging method for balancing top and bottom mold flows from window | |
TWI802524B (en) | Package structure with FOWBCSP chip type and manufacturing method thereof | |
TWI801369B (en) | Package structure with FOWBCSP chip type and manufacturing method thereof | |
TWM565400U (en) | Packaging structure for FOWBCSP chip form | |
TWI576979B (en) | Package substrate and method for manufacturing the same | |
TWI590349B (en) | Chip package and chip packaging process | |
TW202127641A (en) | Package structure with FOWBCSP CMOS chip module where most of wires are hidden in the plate aperture and capable of shortening manufacturing time with reduced cost | |
KR20070120376A (en) | Method of fabricating chip scale package | |
TWI528512B (en) | Chip package structure and process | |
KR100764164B1 (en) | Printed circuit board, package using the printed circuit board and making method of the same |