TWI802478B - Active component substrate - Google Patents

Active component substrate Download PDF

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TWI802478B
TWI802478B TW111128219A TW111128219A TWI802478B TW I802478 B TWI802478 B TW I802478B TW 111128219 A TW111128219 A TW 111128219A TW 111128219 A TW111128219 A TW 111128219A TW I802478 B TWI802478 B TW I802478B
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gate
semiconductor structure
dielectric layer
layer
source
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TW111128219A
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TW202406157A (en
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黃震鑠
范揚順
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友達光電股份有限公司
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Priority to CN202211602600.6A priority patent/CN116072683A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1233—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different thicknesses of the active layer in different devices

Abstract

An active component substrate includes a substrate, a first active component and a second active component electrically connected to the first active component. The first active component includes a first bottom gate, a first semiconductor structure, a first top gate, a first source and a first drain. The first source is electrically connected to the first bottom gate. The second active component includes a second bottom gate, a second semiconductor structure, a second top gate, a second source and a second drain. The thickness of the second semiconductor structure is smaller than the thickness of the first semiconductor structure. The second bottom gate is electrically connected to the second top gate.

Description

主動元件基板Active component substrate

本發明是有關於一種主動元件基板。The invention relates to an active component substrate.

薄膜電晶體是場效電晶體的一種，可以透過在玻璃基板上沈積多層的金屬層、半導體層以及介電層來形成。目前，許多電子裝置中會包括不同用途的薄膜電晶體。舉例來說，許多顯示裝置中包括薄膜電晶體陣列基板，薄膜電晶體陣列中包括開關元件以及驅動元件，其中開關元件用於控制驅動元件的閘極。藉由開關元件與驅動元件互相配合，可以控制通過驅動元件之電流的大小。Thin film transistors are a type of field effect transistors, which can be formed by depositing multiple layers of metal layers, semiconductor layers, and dielectric layers on a glass substrate. Currently, many electronic devices include thin film transistors for different purposes. For example, many display devices include a thin film transistor array substrate, and the thin film transistor array includes switching elements and driving elements, wherein the switching elements are used to control the gates of the driving elements. By cooperating with the switching element and the driving element, the magnitude of the current passing through the driving element can be controlled.

本發明提供一種主動元件基板，可以提升第一主動元件的長時間開啟的可靠度，同時增加第二主動元件的開啟電流（turn on current）。The present invention provides an active element substrate, which can improve the long-time turn-on reliability of the first active element and increase the turn-on current (turn on current) of the second active element.

本發明的至少一實施例提供一種主動元件基板。主動元件基板包括基板、第一主動元件以及電性連接至第一主動元件的第二主動元件。第一主動元件以及第二主動元件位於基板之上。第一主動元件包括第一底閘極、第一半導體結構、第一頂閘極、第一源極以及第一汲極。第一半導體結構位於第一底閘極與第一頂閘極之間。第一源極以及第一汲極電性連接至第一半導體結構。第一源極電性連接至第一底閘極。第二主動元件包括第二底閘極、第二半導體結構、第二頂閘極、第二源極以及第二汲極。第二半導體結構位於第二底閘極與第二頂閘極之間。第二半導體結構的厚度小於第一半導體結構的厚度。第二底閘極電性連接第二頂閘極。第二源極以及第二汲極電性連接至第二半導體結構。At least one embodiment of the present invention provides an active device substrate. The active device substrate includes a substrate, a first active device and a second active device electrically connected to the first active device. The first active element and the second active element are located on the substrate. The first active device includes a first bottom gate, a first semiconductor structure, a first top gate, a first source and a first drain. The first semiconductor structure is located between the first bottom gate and the first top gate. The first source and the first drain are electrically connected to the first semiconductor structure. The first source is electrically connected to the first bottom gate. The second active device includes a second bottom gate, a second semiconductor structure, a second top gate, a second source and a second drain. The second semiconductor structure is located between the second bottom gate and the second top gate. The thickness of the second semiconductor structure is smaller than the thickness of the first semiconductor structure. The second bottom gate is electrically connected to the second top gate. The second source and the second drain are electrically connected to the second semiconductor structure.

圖1A是依照本發明的一實施例的一種主動元件基板的上視示意圖。圖1B是圖1A的線a-a’、線b-b’以及線c-c’的剖面示意圖。為了方便說明，圖1A顯示了主動元件基板10的第一底閘極BG1、第一頂閘極TG1、第一源極S1、第一汲極D1、第二底閘極BG2、第二頂閘極TG2、第二源極S2以及第二汲極D2，並省略繪示其他構件。FIG. 1A is a schematic top view of an active device substrate according to an embodiment of the present invention. Fig. 1B is a schematic cross-sectional view of line a-a', line b-b' and line c-c' in Fig. 1A. For the convenience of illustration, FIG. 1A shows the first bottom gate BG1, the first top gate TG1, the first source S1, the first drain D1, the second bottom gate BG2, and the second top gate of the active element substrate 10. TG2, the second source S2 and the second drain D2, and other components are omitted.

請參考圖1A至圖1B，主動元件基板10包括基板SB、第一主動元件TFT1以及第二主動元件TFT2。在一些實施例中，第二主動元件TFT2電性連接至第一主動元件TFT1，但本發明不以此為限。Please refer to FIG. 1A to FIG. 1B , the active device substrate 10 includes a substrate SB, a first active device TFT1 and a second active device TFT2 . In some embodiments, the second active device TFT2 is electrically connected to the first active device TFT1 , but the invention is not limited thereto.

基板SB之材質可為玻璃、石英、有機聚合物或是不透光/反射材料（例如：導電材料、金屬、晶圓、陶瓷或其他可適用的材料）或是其他可適用的材料。若使用導電材料或金屬時，則在基板SB上覆蓋一層絕緣層（未繪示），以避免短路問題。在一些實施例中，基板SB為軟性基板，且基板SB的材料例如為聚乙烯對苯二甲酸酯（polyethylene terephthalate, PET）、聚二甲酸乙二醇酯（polyethylene naphthalate, PEN）、聚酯（polyester, PES）、聚甲基丙烯酸甲酯（polymethylmethacrylate, PMMA）、聚碳酸酯（polycarbonate, PC）、聚醯亞胺(polyimide, PI）或金屬軟板（Metal Foil）或其他可撓性材質。The material of the substrate SB can be glass, quartz, organic polymer or opaque/reflective material (for example: conductive material, metal, wafer, ceramic or other applicable materials) or other applicable materials. If conductive materials or metals are used, an insulating layer (not shown) is covered on the substrate SB to avoid short circuit problems. In some embodiments, the substrate SB is a flexible substrate, and the material of the substrate SB is, for example, polyethylene terephthalate (polyethylene terephthalate, PET), polyethylene glycol ester (polyethylene naphthalate, PEN), polyester (polyester, PES), polymethylmethacrylate (polymethylmethacrylate, PMMA), polycarbonate (polycarbonate, PC), polyimide (polyimide, PI) or metal soft board (Metal Foil) or other flexible materials .

緩衝層BL位於基板SB上，緩衝層BL為單層或多層結構，且緩衝層BL的材料可以包括氧化矽、氮氧化矽或其他合適的材料或上述材料的堆疊層。The buffer layer BL is located on the substrate SB. The buffer layer BL has a single-layer or multi-layer structure, and the material of the buffer layer BL may include silicon oxide, silicon oxynitride or other suitable materials or stacked layers of the above materials.

第一主動元件TFT1以及第二主動元件TFT2位於基板SB之上。在本實施例中，第一主動元件TFT1以及第二主動元件TFT2位於緩衝層BL之上。The first active device TFT1 and the second active device TFT2 are located on the substrate SB. In this embodiment, the first active device TFT1 and the second active device TFT2 are located on the buffer layer BL.

第一主動元件TFT1包括第一底閘極BG1、第一半導體結構SM1、第一頂閘極TG1、第一源極S1以及第一汲極D1。第二主動元件TFT2包括第二底閘極BG2、第二半導體結構SM2、第二頂閘極TG2、第二源極S2以及第二汲極D2。The first active element TFT1 includes a first bottom gate BG1 , a first semiconductor structure SM1 , a first top gate TG1 , a first source S1 and a first drain D1 . The second active element TFT2 includes a second bottom gate BG2 , a second semiconductor structure SM2 , a second top gate TG2 , a second source S2 and a second drain D2 .

第一底閘極BG1以及第二底閘極BG2位於緩衝層BL上。在一些實施例中，第一底閘極BG1以及第二底閘極BG2包括相同或不同的材料。在一些實施例中，第一底閘極BG1以及第二底閘極BG2的材料可包括金屬，例如鉻（Cr）、金（Au）、銀（Ag）、銅（Cu）、錫（Sn）、鉛（Pb）、鉿（Hf）、鎢（W）、鉬（Mo）、釹（Nd）、鈦（Ti）、鉭（Ta）、鋁（Al）、鋅（Zn）或上述金屬的任意組合之合金或上述金屬及/或合金之疊層，但本發明不以此為限。第一底閘極BG1以及第二底閘極BG2也可以使用其他導電材料，例如：金屬的氮化物、金屬的氧化物、金屬的氮氧化物、金屬與其它導電材料的堆疊層或是其他具有導電性質之材料。The first bottom gate BG1 and the second bottom gate BG2 are located on the buffer layer BL. In some embodiments, the first bottom gate BG1 and the second bottom gate BG2 include the same or different materials. In some embodiments, the material of the first bottom gate BG1 and the second bottom gate BG2 may include metals, such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn) , lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn) or any of the above metals Combination alloys or stacks of the above metals and/or alloys, but the present invention is not limited thereto. The first bottom gate BG1 and the second bottom gate BG2 can also use other conductive materials, such as: metal nitride, metal oxide, metal oxynitride, stacked layers of metal and other conductive materials, or other conductive materials. Conductive materials.

第一閘介電層GI1位於第一底閘極BG1以及第二底閘極BG2上。在本實施例中，第一閘介電層GI1接觸第一底閘極BG1以及第二底閘極BG2的上表面。在一些實施例中，第一閘介電層GI1的材料包括氧化矽、氮氧化矽、氧化鋁、氧化鉿或其他合適的材料。The first gate dielectric layer GI1 is located on the first bottom gate BG1 and the second bottom gate BG2 . In this embodiment, the first gate dielectric layer GI1 contacts the upper surfaces of the first bottom gate BG1 and the second bottom gate BG2 . In some embodiments, the material of the first gate dielectric layer GI1 includes silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide or other suitable materials.

第一半導體結構SM1與第二半導體結構SM2位於第一閘介電層GI1上。第一閘介電層GI1位於第一底閘極BG1與第一半導體結構SM1之間以及第二底閘極BG2與第二半導體結構SM2之間。在一些實施例中，第一半導體結構SM1包括第一源極區sr1、第一汲極區dr1以及位於第一源極區sr1與第一汲極區dr1之間的第一通道區ch1。類似地，第二半導體結構SM2包括第二源極區sr2、第二汲極區dr2以及位於第二源極區sr2與第二汲極區dr2之間的第二通道區ch2。第一源極區sr1、第一汲極區dr1、第二源極區sr2以及第二汲極區dr2經摻雜（例如氫摻雜）而具有低於第一通道區ch1以及第二通道區ch2的電阻率。The first semiconductor structure SM1 and the second semiconductor structure SM2 are located on the first gate dielectric layer GI1 . The first gate dielectric layer GI1 is located between the first bottom gate BG1 and the first semiconductor structure SM1 and between the second bottom gate BG2 and the second semiconductor structure SM2. In some embodiments, the first semiconductor structure SM1 includes a first source region sr1 , a first drain region dr1 , and a first channel region ch1 between the first source region sr1 and the first drain region dr1 . Similarly, the second semiconductor structure SM2 includes a second source region sr2 , a second drain region dr2 , and a second channel region ch2 located between the second source region sr2 and the second drain region dr2 . The first source region sr1, the first drain region dr1, the second source region sr2, and the second drain region dr2 are doped (for example, hydrogen doped) to have a lower density than the first channel region ch1 and the second channel region. The resistivity of ch2.

在本實施例中，第二半導體結構SM2的厚度t2小於第一半導體結構SM1的厚度t1。在一些實施例中，藉由增加第一半導體結構SM1的厚度t1，可以降低第一通道區ch1的電阻率，藉此降低第一主動元件TFT1的閾值電壓（Vth），並提升第一主動元件TFT1的開啟電流。In this embodiment, the thickness t2 of the second semiconductor structure SM2 is smaller than the thickness t1 of the first semiconductor structure SM1 . In some embodiments, by increasing the thickness t1 of the first semiconductor structure SM1, the resistivity of the first channel region ch1 can be reduced, thereby reducing the threshold voltage (Vth) of the first active device TFT1 and improving the first active device. Turn-on current of TFT1.

第一半導體結構SM1可以為單層結構或多層結構。在本實施例中，第一半導體結構SM1為多層結構，且包括第一半導體層OS1以及第二半導體層OS2。第二半導體層OS2重疊於第一半導體層OS1，且第一半導體層OS1相較於第二半導體層OS2更靠近基板SB。在一些實施例中，第二半導體結構SM2為單層結構，且第二半導體層OS2與第二半導體結構SM2屬於相同圖案化層。The first semiconductor structure SM1 may be a single-layer structure or a multi-layer structure. In this embodiment, the first semiconductor structure SM1 is a multi-layer structure, and includes a first semiconductor layer OS1 and a second semiconductor layer OS2. The second semiconductor layer OS2 overlaps the first semiconductor layer OS1 , and the first semiconductor layer OS1 is closer to the substrate SB than the second semiconductor layer OS2 . In some embodiments, the second semiconductor structure SM2 is a single-layer structure, and the second semiconductor layer OS2 and the second semiconductor structure SM2 belong to the same patterned layer.

在一些實施例中，第一半導體層OS1、第二半導體層OS2與第二半導體結構SM2的材料包括銦鎵錫鋅氧化物（IGTZO）或氧化銦鎵鋅（IGZO）、氧化銦錫鋅（ITZO）、氧化鋁鋅錫（AZTO）、氧化銦鎢鋅（IWZO）等四元金屬化合物或包含鎵（Ga）、鋅（Zn）、銦（In）、錫（Sn）、鋁（Al）、鎢（W）中之任三者的三元金屬構成的氧化物或鑭系稀土摻雜金屬氧化物（例如Ln-IZO）。在一些實施例中，第一半導體層OS1與第二半導體層OS2可包括相同或不同的材料。In some embodiments, the materials of the first semiconductor layer OS1, the second semiconductor layer OS2 and the second semiconductor structure SM2 include indium gallium tin zinc oxide (IGTZO) or indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO ), aluminum zinc tin oxide (AZTO), indium tungsten zinc oxide (IWZO) and other quaternary metal compounds or containing gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), tungsten (W) An oxide composed of any three ternary metals or a lanthanide rare earth-doped metal oxide (such as Ln-IZO). In some embodiments, the first semiconductor layer OS1 and the second semiconductor layer OS2 may include the same or different materials.

第二閘介電層GI2位於第一閘介電層GI1、第一半導體結構SM1與第二半導體結構SM2上。第一半導體結構SM1與第二半導體結構SM2夾在第一閘介電層GI1與第二閘介電層GI2之間。在一些實施例中，第二閘介電層GI2的材料包括氧化矽、氮氧化矽、氧化鋁、氧化鉿或其他合適的材料。The second gate dielectric layer GI2 is located on the first gate dielectric layer GI1 , the first semiconductor structure SM1 and the second semiconductor structure SM2 . The first semiconductor structure SM1 and the second semiconductor structure SM2 are sandwiched between the first gate dielectric layer GI1 and the second gate dielectric layer GI2 . In some embodiments, the material of the second gate dielectric layer GI2 includes silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide or other suitable materials.

第一頂閘極TG1與第二頂閘極TG2位於第二閘介電層GI2上。第二閘介電層GI2位於第一頂閘極TG1與第一半導體結構SM1之間以及第二頂閘極TG2與第二半導體結構SM2之間。第一半導體結構SM1位於第一底閘極BG1與第一頂閘極TG1之間。第二半導體結構SM2位於第二底閘極BG2與第二頂閘極TG2之間。在一些實施例中，第一頂閘極TG1與第二頂閘極TG2包括相同或不同的材料。在一些實施例中，第一頂閘極TG1與第二頂閘極TG2的材料可包括金屬，例如鉻（Cr）、金（Au）、銀（Ag）、銅（Cu）、錫（Sn）、鉛（Pb）、鉿（Hf）、鎢（W）、鉬（Mo）、釹（Nd）、鈦（Ti）、鉭（Ta）、鋁（Al）、鋅（Zn）或上述金屬的任意組合之合金或上述金屬及/或合金之疊層，但本發明不以此為限。第一頂閘極TG1與第二頂閘極TG2也可以使用其他導電材料，例如：金屬的氮化物、金屬的氧化物、金屬的氮氧化物、金屬與其它導電材料的堆疊層或是其他具有導電性質之材料。The first top gate TG1 and the second top gate TG2 are located on the second gate dielectric layer GI2 . The second gate dielectric layer GI2 is located between the first top gate TG1 and the first semiconductor structure SM1 and between the second top gate TG2 and the second semiconductor structure SM2. The first semiconductor structure SM1 is located between the first bottom gate BG1 and the first top gate TG1 . The second semiconductor structure SM2 is located between the second bottom gate BG2 and the second top gate TG2 . In some embodiments, the first top gate TG1 and the second top gate TG2 include the same or different materials. In some embodiments, the materials of the first top gate TG1 and the second top gate TG2 may include metals, such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn) , lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn) or any of the above metals Combination alloys or stacks of the above metals and/or alloys, but the present invention is not limited thereto. The first top gate TG1 and the second top gate TG2 can also use other conductive materials, such as: metal nitride, metal oxide, metal oxynitride, stacked layers of metal and other conductive materials, or other materials with Conductive materials.

在本實施例中，第二主動元件TFT2為第二底閘極BG2電性連接第二頂閘極TG2的雙閘極型薄膜電晶體（本文將其稱為TG-sync薄膜電晶體）。舉例來說，第二頂閘極TG2透過接觸孔V1而連接至第二底閘極BG2，其中接觸孔V1穿過第一閘介電層GI1與第二閘介電層GI2。In this embodiment, the second active element TFT2 is a double-gate TFT (herein referred to as a TG-sync TFT) in which the second bottom gate BG2 is electrically connected to the second top gate TG2 . For example, the second top gate TG2 is connected to the second bottom gate BG2 through the contact hole V1 , wherein the contact hole V1 passes through the first gate dielectric layer GI1 and the second gate dielectric layer GI2 .

第一層間介電層ILD1位於第一頂閘極TG1與第二頂閘極TG2上。第二層間介電層ILD2位於第一層間介電層ILD1上。在一些實施例中，第一層間介電層ILD1與第二層間介電層ILD2的材料包括氧化矽、氮氧化矽、氧化鋁、氧化鉿、有機絕緣材料或其他合適的材料。The first interlayer dielectric layer ILD1 is located on the first top gate TG1 and the second top gate TG2 . The second interlayer dielectric layer ILD2 is on the first interlayer dielectric layer ILD1. In some embodiments, the materials of the first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2 include silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, organic insulating materials, or other suitable materials.

第一源極S1、第一汲極D1、第二源極S2以及第二汲極D2位於第二層間介電層ILD2上。第一源極S1以及第一汲極D1分別透過接觸孔H1、H2而電性連接至第一半導體結構SM1的第一源極區sr1以及第一汲極區dr1，第二源極S2以及第二汲極D2分別透過接觸孔H3、H4而電性連接至第二半導體結構SM2的第二源極區sr2以及第二汲極區dr2，其中接觸孔H1~H4穿過第二閘介電層GI2、第一層間介電層ILD1與第二層間介電層ILD2。在一些實施例中，第一源極S1、第一汲極D1、第二源極S2以及第二汲極D2的材料可包括金屬，例如鉻（Cr）、金（Au）、銀（Ag）、銅（Cu）、錫（Sn）、鉛（Pb）、鉿（Hf）、鎢（W）、鉬（Mo）、釹（Nd）、鈦（Ti）、鉭（Ta）、鋁（Al）、鋅（Zn）或上述金屬的任意組合之合金或上述金屬及/或合金之疊層，但本發明不以此為限。第一源極S1、第一汲極D1、第二源極S2以及第二汲極D2也可以使用其他導電材料，例如：金屬的氮化物、金屬的氧化物、金屬的氮氧化物、金屬與其它導電材料的堆疊層或是其他具有導電性質之材料。保護層PL覆蓋第一源極S1、第一汲極D1、第二源極S2以及第二汲極D2。The first source S1 , the first drain D1 , the second source S2 and the second drain D2 are located on the second interlayer dielectric layer ILD2 . The first source S1 and the first drain D1 are respectively electrically connected to the first source region sr1 and the first drain region dr1 of the first semiconductor structure SM1 through the contact holes H1 and H2, the second source S2 and the second drain region of the first semiconductor structure SM1. The two drains D2 are electrically connected to the second source region sr2 and the second drain region dr2 of the second semiconductor structure SM2 respectively through the contact holes H3 and H4, wherein the contact holes H1-H4 pass through the second gate dielectric layer GI2 , the first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2 . In some embodiments, the materials of the first source S1, the first drain D1, the second source S2, and the second drain D2 may include metals, such as chromium (Cr), gold (Au), silver (Ag) , copper (Cu), tin (Sn), lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al) , zinc (Zn) or an alloy of any combination of the above metals or a laminate of the above metals and/or alloys, but the present invention is not limited thereto. The first source S1, the first drain D1, the second source S2 and the second drain D2 can also use other conductive materials, such as: metal nitride, metal oxide, metal oxynitride, metal and Stacked layers of other conductive materials or other materials with conductive properties. The protection layer PL covers the first source S1 , the first drain D1 , the second source S2 and the second drain D2 .

在本實施例中，第一主動元件TFT1為第一源極S1電性連接至第一底閘極BG1的雙閘極型薄膜電晶體（本文將其稱為source-sync薄膜電晶體）。舉例來說，第一源極S1透過接觸孔V2而連接至第一底閘極BG1，其中接觸孔V2穿過第一閘介電層GI1、第二閘介電層GI2、第一層間介電層ILD1與第二層間介電層ILD2。在其他實施例中，第一源極S1未直接接觸第一底閘極BG1，且第一源極S1透過其他轉接電極而電性連接第一底閘極BG1。In this embodiment, the first active element TFT1 is a double-gate thin film transistor (referred to as a source-sync thin film transistor herein) in which the first source S1 is electrically connected to the first bottom gate BG1 . For example, the first source S1 is connected to the first bottom gate BG1 through the contact hole V2, wherein the contact hole V2 passes through the first gate dielectric layer GI1, the second gate dielectric layer GI2, the first interlayer dielectric The electrical layer ILD1 and the second interlayer dielectric layer ILD2. In other embodiments, the first source S1 does not directly contact the first bottom gate BG1 , and the first source S1 is electrically connected to the first bottom gate BG1 through other transfer electrodes.

表1為TG-sync薄膜電晶體與source-sync薄膜電晶體在半導體結構相同的情況下，各種特性的比較。在表1中，◎代表優秀，○代表尚可，▽代表差。 表1   TG-sync source-sync 開啟電流（ Ion ） ◎ ▽ 閾 值電壓（ Vth ） ○ ◎ 閾 值電壓均勻性（ Vth U% ） ◎ ○ 汲 極端引入的勢壘降低（ DIBL ） ◎ ◎ 飽和開啟電流（ Saturation Ion ） ◎ ◎ 正偏壓 - 溫度應力（ PBTS ） ▽ ◎ 負偏壓 - 溫度應力（ NBTS ） ◎ ◎ 負偏壓 - 照光應力（ NBIS ） ◎ ◎ Table 1 is a comparison of various characteristics of TG-sync thin film transistors and source-sync thin film transistors under the same semiconductor structure. In Table 1, ◎ represents excellent, ○ represents acceptable, and ▽ represents poor. Table 1 TG-sync source-sync Turn-on current ( Ion ) ◎ ▽ Threshold Voltage ( Vth ) ○ ◎ Threshold Voltage Uniformity ( Vth U% ) ◎ ○ Drain -introduced barrier lowering ( DIBL ) ◎ ◎ Saturation turn-on current ( Saturation Ion ) ◎ ◎ Positive Bias - Temperature Stress ( PBTS ) ▽ ◎ Negative Bias - Temperature Stress ( NBTS ) ◎ ◎ Negative Bias - Illumination Stress ( NBIS ) ◎ ◎

由表1可以得知，TG-Sync薄膜電晶體適合用作開關薄膜電晶體（Switching TFT）。頂閘極電性連接至底閘極的設置可以增加開啟電流。雖然TG-Sync薄膜電晶體會有PBTS（Positive gate bias temperature stress）的問題。然而，由於開關薄膜電晶體需要開啟的時間相對短暫，將TG-Sync薄膜電晶體使用於開關薄膜電晶體不容易出現可靠度的問題。It can be seen from Table 1 that the TG-Sync thin film transistor is suitable for use as a switching thin film transistor (Switching TFT). The setting that the top gate is electrically connected to the bottom gate can increase the turn-on current. Although TG-Sync thin film transistors have PBTS (Positive gate bias temperature stress) problems. However, since the switch thin film transistor needs to be turned on for a relatively short time, the use of the TG-Sync thin film transistor for the switch thin film transistor is not prone to reliability problems.

此外，Source-Sync薄膜電晶體適合用作驅動薄膜電晶體（Driving TFT）。底閘極電性連接至源極的設置可以增加長期開啟的可靠性。然而，由於底閘極電性連接至低電位（例如接地電位），會導致Source-Sync薄膜電晶體的開啟電流變小。In addition, Source-Sync thin film transistors are suitable for driving TFTs. The setting that the bottom gate is electrically connected to the source can increase the reliability of long-term turn-on. However, since the bottom gate is electrically connected to a low potential (such as ground potential), the turn-on current of the Source-Sync thin film transistor will be reduced.

在圖1A至圖1B的實施例中，藉由增加第一半導體結構SM1的厚度t1，可以改善第一主動元件TFT1（Source-Sync薄膜電晶體）的開啟電流小的問題。此外，由於第二半導體結構SM2的厚度t2較小，可以改善第二主動元件TFT2（TG-Sync薄膜電晶體）的漏電問題。In the embodiment of FIG. 1A to FIG. 1B , by increasing the thickness t1 of the first semiconductor structure SM1 , the problem of small turn-on current of the first active element TFT1 (Source-Sync thin film transistor) can be improved. In addition, since the thickness t2 of the second semiconductor structure SM2 is small, the leakage problem of the second active element TFT2 (TG-Sync thin film transistor) can be improved.

圖2A是依照本發明的一些實施例的第一主動元件（Source-Sync薄膜電晶體）的第一半導體結構的厚度與閾值電壓的實驗數據圖。圖2A顯示了在第一狀況下之第一半導體結構的厚度與閾值電壓的關係以及在第二狀況下之第一半導體結構的厚度與閾值電壓的關係，其中第一狀況與第二狀況的差異在於：在第一狀況中，在沉積第一閘介電層GI1（請參考圖1B）時，二氧化氮對上矽甲烷的比例較高，且第一閘介電層GI1的厚度為1800埃；在第二狀況中，在沉積第一閘介電層GI1（請參考圖1B）時，二氧化氮對上矽甲烷的比例較低，且第一閘介電層GI1的厚度為2150埃。2A is an experimental data diagram of the thickness and threshold voltage of the first semiconductor structure of the first active device (Source-Sync TFT) according to some embodiments of the present invention. 2A shows the relationship between the thickness of the first semiconductor structure and the threshold voltage under the first condition and the relationship between the thickness of the first semiconductor structure and the threshold voltage under the second condition, wherein the difference between the first condition and the second condition In the first case, when depositing the first gate dielectric layer GI1 (please refer to FIG. 1B ), the ratio of nitrogen dioxide to upper silane is high, and the thickness of the first gate dielectric layer GI1 is 1800 angstroms ; In the second case, when depositing the first gate dielectric layer GI1 (please refer to FIG. 1B ), the ratio of nitrogen dioxide to upper silane is low, and the thickness of the first gate dielectric layer GI1 is 2150 angstroms.

圖2B是依照本發明的一些實施例的第一主動元件（Source-Sync薄膜電晶體）的第一半導體結構的厚度與開啟電流的實驗數據圖。2B is an experimental data diagram of the thickness and turn-on current of the first semiconductor structure of the first active device (Source-Sync TFT) according to some embodiments of the present invention.

由圖2A與圖2B可以得知，隨著第一半導體結構SM1（請參考圖1B）的厚度t1增加，第一主動元件TFT1的閾值電壓減少，且開啟電流提升。It can be seen from FIG. 2A and FIG. 2B that as the thickness t1 of the first semiconductor structure SM1 (please refer to FIG. 1B ) increases, the threshold voltage of the first active element TFT1 decreases and the turn-on current increases.

圖3是依照本發明的一些實施例的第一主動元件（Source-Sync薄膜電晶體）在長時間操作後的開啟電流的衰退（Ion drop）與閾值電壓的變化（Vth shift）。在圖3中，第一主動元件在90˚C下操作1小時，其中第一汲極與第一源極之間的電壓差Vds為20V，且操作電流為100uA。此外，在圖3的第一主動元件中，第一通道區的寬為50微米，且長為6微米。FIG. 3 shows the decay of the turn-on current (Ion drop) and the change of the threshold voltage (Vth shift) of the first active device (Source-Sync thin film transistor) after long-time operation according to some embodiments of the present invention. In Fig. 3, the first active device was operated at 90°C for 1 hour, the voltage difference Vds between the first drain and the first source was 20V, and the operating current was 100uA. In addition, in the first active device shown in FIG. 3 , the first channel region has a width of 50 microns and a length of 6 microns.

由圖3可以得知，隨著第一半導體結構的厚度提升，第一主動元件在長前間操作後的電流衰退較小，且閾值電壓的衰退也較小。It can be seen from FIG. 3 that as the thickness of the first semiconductor structure increases, the current degradation of the first active device after long-term operation is smaller, and the threshold voltage degradation is also smaller.

圖4A至圖4E是圖1的主動元件基板10的製造方法的剖面示意圖。4A to 4E are schematic cross-sectional views of the manufacturing method of the active device substrate 10 of FIG. 1 .

請參考圖4A，形成第一底閘極BG1與第二底閘極BG2於緩衝層BL上。在一些實施例中，形成第一底閘極BG1與第二底閘極BG2的方法包括：形成導電材料層（未繪出）於緩衝層BL上；形成圖案化光阻層（未繪出）於導電材料層上；以圖案化光阻層為遮罩蝕刻導電材料層，以形成第一底閘極BG1與第二底閘極BG2；最後，移除圖案化光阻層。換句話說，第一底閘極BG1與第二底閘極BG2屬於同一圖案化層。Referring to FIG. 4A , a first bottom gate BG1 and a second bottom gate BG2 are formed on the buffer layer BL. In some embodiments, the method for forming the first bottom gate BG1 and the second bottom gate BG2 includes: forming a conductive material layer (not shown) on the buffer layer BL; forming a patterned photoresist layer (not shown) On the conductive material layer; use the patterned photoresist layer as a mask to etch the conductive material layer to form the first bottom gate BG1 and the second bottom gate BG2; finally, remove the patterned photoresist layer. In other words, the first bottom gate BG1 and the second bottom gate BG2 belong to the same patterned layer.

接著，形成第一閘介電層GI1於第一底閘極BG1與第二底閘極BG2上。之後，形成第一半導體層OS1’於第一閘介電層GI1上。第一半導體層OS1’重疊於第一底閘極BG1。Next, a first gate dielectric layer GI1 is formed on the first bottom gate BG1 and the second bottom gate BG2 . After that, a first semiconductor layer OS1' is formed on the first gate dielectric layer GI1. The first semiconductor layer OS1' overlaps the first bottom gate BG1.

請參考圖4B，形成第二半導體層OS2’於第一半導體層OS1’上，同時形成第二半導體結構SM2’於第一閘介電層GI1上。第二半導體結構SM2’重疊於第二底閘極BG2。在一些實施例中，形成第二半導體層OS2’與第二半導體結構SM2’的方法包括：形成半導體材料層（未繪出）於第一閘介電層GI1以及第一半導體層OS1’上；形成圖案化光阻層（未繪出）於半導體材料層上；以圖案化光阻層為遮罩蝕刻半導體材料層，以形成第二半導體層OS2’與第二半導體結構SM2’；最後，移除圖案化光阻層。換句話說，第二半導體層OS2’與第二半導體結構SM2’屬於同一圖案化層。Referring to FIG. 4B, a second semiconductor layer OS2' is formed on the first semiconductor layer OS1', and a second semiconductor structure SM2' is formed on the first gate dielectric layer GI1. The second semiconductor structure SM2' overlaps the second bottom gate BG2. In some embodiments, the method for forming the second semiconductor layer OS2' and the second semiconductor structure SM2' includes: forming a semiconductor material layer (not shown) on the first gate dielectric layer GI1 and the first semiconductor layer OS1'; forming a patterned photoresist layer (not shown) on the semiconductor material layer; using the patterned photoresist layer as a mask to etch the semiconductor material layer to form a second semiconductor layer OS2' and a second semiconductor structure SM2'; finally, moving Remove the patterned photoresist layer. In other words, the second semiconductor layer OS2' and the second semiconductor structure SM2' belong to the same patterned layer.

在本實施例中，第一半導體結構SM1’包括第一半導體層OS1’與第二半導體層OS2’的堆疊，因此，第一半導體結構SM1’的厚度大於第二半導體結構SM2’的厚度。In this embodiment, the first semiconductor structure SM1' includes a stack of the first semiconductor layer OS1' and the second semiconductor layer OS2', therefore, the thickness of the first semiconductor structure SM1' is greater than the thickness of the second semiconductor structure SM2'.

請參考圖4C，形成第二閘介電層GI2於第一半導體結構SM1’與第二半導體結構SM2’上。Referring to FIG. 4C , a second gate dielectric layer GI2 is formed on the first semiconductor structure SM1' and the second semiconductor structure SM2'.

接著，形成第一頂閘極TG1與第二頂閘極TG2於第二閘介電層GI2上。在一些實施例中，形成第一頂閘極TG1與第二頂閘極TG2的方法包括：形成導電材料層（未繪出）於第二閘介電層GI2上；形成圖案化光阻層（未繪出）於導電材料層上；以圖案化光阻層為遮罩蝕刻導電材料層，以形成第一頂閘極TG1與第二頂閘極TG2；最後，移除圖案化光阻層。換句話說，第一頂閘極TG1與第二頂閘極TG2屬於同一圖案化層。Next, a first top gate TG1 and a second top gate TG2 are formed on the second gate dielectric layer GI2 . In some embodiments, the method for forming the first top gate TG1 and the second top gate TG2 includes: forming a conductive material layer (not shown) on the second gate dielectric layer GI2; forming a patterned photoresist layer ( not shown) on the conductive material layer; using the patterned photoresist layer as a mask to etch the conductive material layer to form the first top gate TG1 and the second top gate TG2; finally, remove the patterned photoresist layer. In other words, the first top gate TG1 and the second top gate TG2 belong to the same patterned layer.

以第一頂閘極TG1與第二頂閘極TG2為罩幕，執行摻雜製程P，以形成包括第一源極區sr1、第一汲極區dr1以及第一通道區ch1的第一半導體結構SM1以及包括第二源極區sr2、第二汲極區dr2以及第二通道區ch2的第二半導體結構SM2。在一些實施例中，摻雜製程P例如為氫電漿摻雜或其他合適的製程。Using the first top gate TG1 and the second top gate TG2 as a mask, perform a doping process P to form a first semiconductor including a first source region sr1, a first drain region dr1, and a first channel region ch1 The structure SM1 and the second semiconductor structure SM2 including the second source region sr2 , the second drain region dr2 and the second channel region ch2 . In some embodiments, the doping process P is, for example, hydrogen plasma doping or other suitable processes.

在一些實施例中，在形成第一頂閘極TG1與第二頂閘極TG2之前，對第一閘介電層GI1以及第二閘介電層GI2執行蝕刻製程，以形成暴露出第二底閘極BG2的接觸孔V1。接著，形成第二頂閘極TG2於接觸孔V1中，以電性連接第二底閘極BG2。In some embodiments, before forming the first top gate TG1 and the second top gate TG2, an etching process is performed on the first gate dielectric layer GI1 and the second gate dielectric layer GI2 to form the exposed second bottom gate. The contact hole V1 of the gate BG2. Next, a second top gate TG2 is formed in the contact hole V1 to be electrically connected to the second bottom gate BG2.

請參考圖4D，形成第一層間介電層ILD1於第一頂閘極TG1與第二頂閘極TG2上。形成第二層間介電層ILD2於第一層間介電層ILD1上。接著，執行一次或多次蝕刻製程，以形成暴露出第一源極區sr1、第一汲極區dr1、第二源極區sr2以及第二汲極區dr2的接觸孔H1~H4。在一些實施例中，在形成接觸孔H1~H4的同時，形成暴露出第一底閘極BG1的接觸孔V2。Referring to FIG. 4D , a first interlayer dielectric layer ILD1 is formed on the first top gate TG1 and the second top gate TG2 . A second interlayer dielectric layer ILD2 is formed on the first interlayer dielectric layer ILD1. Next, one or more etching processes are performed to form contact holes H1 - H4 exposing the first source region sr1 , the first drain region dr1 , the second source region sr2 and the second drain region dr2 . In some embodiments, while forming the contact holes H1 ˜ H4 , the contact hole V2 exposing the first bottom gate BG1 is formed.

最後，請回到圖1A至圖1B，形成第一源極S1、第一汲極D1、第二源極S2以及第二汲極D2於第二層間介電層ILD2上，第一源極S1、第一汲極D1、第二源極S2以及第二汲極D2分別填入接觸孔H1~H4中。在一些實施例中，第一源極S1還填入接觸孔V2中。Finally, please return to FIG. 1A to FIG. 1B to form the first source S1, the first drain D1, the second source S2 and the second drain D2 on the second interlayer dielectric layer ILD2, the first source S1 , the first drain D1 , the second source S2 and the second drain D2 are respectively filled in the contact holes H1 - H4 . In some embodiments, the first source S1 is also filled into the contact hole V2.

最後，選擇性地形成保護層PL於第一源極S1、第一汲極D1、第二源極S2以及第二汲極D2上。至此，主動元件基板10大致完成。Finally, a protection layer PL is selectively formed on the first source S1 , the first drain D1 , the second source S2 and the second drain D2 . So far, the active device substrate 10 is roughly completed.

圖5是依照本發明的一實施例的一種主動元件基板的剖面示意圖。在此必須說明的是，圖5的實施例沿用圖1A至圖1B的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。FIG. 5 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention. It must be noted here that the embodiment in FIG. 5 follows the component numbers and partial contents of the embodiment in FIGS. 1A to 1B , wherein the same or similar symbols are used to indicate the same or similar components, and the same technical content illustrate. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

圖5的主動元件基板20與圖1A至圖1B的主動元件基板10的主要差異在於：在主動元件基板20中，第一主動元件TFT1選擇性地包括轉接電極TE。The main difference between the active device substrate 20 in FIG. 5 and the active device substrate 10 in FIGS. 1A to 1B is that in the active device substrate 20 , the first active device TFT1 optionally includes a transfer electrode TE.

請參考圖5，轉接電極TE電性連接第一底閘極BG1與第一源極S1。轉接電極TE分離於第一頂閘極TG1與第二頂閘極TG2。舉例來說，轉接電極TE透過接觸孔V2而連接至第一底閘極BG1，其中接觸孔V2穿過第一閘介電層GI1與第二閘介電層GI2。在一些實施例中，轉接電極TE、第一頂閘極TG1與第二頂閘極TG2屬於相同圖案化層，換句話說，轉接電極TE、第一頂閘極TG1與第二頂閘極TG2可以藉由同一次的圖案化製程所形成。另外，在本實施例中，在形成第一源極S1之前，在形成接觸孔H1~H4的同時，形成暴露出轉接電極TE的接觸孔V2’。接著，形成第一源極S1於接觸孔V2’中以連接轉接電極TE。Please refer to FIG. 5 , the transfer electrode TE is electrically connected to the first bottom gate BG1 and the first source S1 . The transfer electrode TE is separated from the first top gate TG1 and the second top gate TG2 . For example, the transfer electrode TE is connected to the first bottom gate BG1 through the contact hole V2, wherein the contact hole V2 passes through the first gate dielectric layer GI1 and the second gate dielectric layer GI2. In some embodiments, the transfer electrode TE, the first top gate TG1 and the second top gate TG2 belong to the same patterned layer, in other words, the transfer electrode TE, the first top gate TG1 and the second top gate The pole TG2 can be formed by the same patterning process. In addition, in this embodiment, before forming the first source electrode S1, while forming the contact holes H1-H4, the contact hole V2' exposing the via electrode TE is formed. Next, a first source S1 is formed in the contact hole V2' to connect with the transfer electrode TE.

圖6是依照本發明的一實施例的一種主動元件基板的剖面示意圖。在此必須說明的是，圖6的實施例沿用圖1A至圖1B的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。FIG. 6 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention. It must be noted here that the embodiment in FIG. 6 follows the component numbers and part of the content of the embodiment in FIG. 1A to FIG. illustrate. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

圖6的主動元件基板30與圖1A至圖1B的主動元件基板10的主要差異在於：在主動元件基板30中，第一半導體結構SM1與第二半導體結構SM2屬於不同圖案化層。The main difference between the active device substrate 30 in FIG. 6 and the active device substrate 10 in FIGS. 1A to 1B is that in the active device substrate 30 , the first semiconductor structure SM1 and the second semiconductor structure SM2 belong to different patterned layers.

請參考圖6，第一閘介電層GI1位於第一底閘極BG1、第二底閘極BG2與緩衝層BL上。第一半導體結構SM1位於第一閘介電層GI1上。第一閘介電層GI1位於第一底閘極BG1與第一半導體結構SM1之間。Please refer to FIG. 6 , the first gate dielectric layer GI1 is located on the first bottom gate BG1 , the second bottom gate BG2 and the buffer layer BL. The first semiconductor structure SM1 is located on the first gate dielectric layer GI1 . The first gate dielectric layer GI1 is located between the first bottom gate BG1 and the first semiconductor structure SM1.

第二閘介電層GI2位於第一半導體結構SM1與第一閘介電層GI1上。第二半導體結構SM2位於第二閘介電層GI2上。第二閘介電層GI2以及第一閘介電層GI1位於第二底閘極BG2與第二半導體結構SM2之間。The second gate dielectric layer GI2 is located on the first semiconductor structure SM1 and the first gate dielectric layer GI1 . The second semiconductor structure SM2 is located on the second gate dielectric layer GI2. The second gate dielectric layer GI2 and the first gate dielectric layer GI1 are located between the second bottom gate BG2 and the second semiconductor structure SM2.

第三閘介電層GI3位於第二閘介電層GI2與第二半導體結構SM2上。The third gate dielectric layer GI3 is located on the second gate dielectric layer GI2 and the second semiconductor structure SM2.

第一頂閘極TG1以及第二頂閘極TG2位於第三閘介電層GI3上。第二閘介電層GI2位於第一頂閘極TG1與第一半導體結構SM1之間。第三閘介電層GI3位於第一頂閘極TG1與第一半導體結構SM1之間以及第二頂閘極TG2與第二半導體結構SM2之間。The first top gate TG1 and the second top gate TG2 are located on the third gate dielectric layer GI3 . The second gate dielectric layer GI2 is located between the first top gate TG1 and the first semiconductor structure SM1. The third gate dielectric layer GI3 is located between the first top gate TG1 and the first semiconductor structure SM1 and between the second top gate TG2 and the second semiconductor structure SM2.

在本實施例中，第一半導體結構SM1與第二半導體結構SM2皆為單層結構，但本發明不以此為限。在其他實施例中，第一半導體結構SM1為多層結構，而第二半導體結構SM2為單層結構。In this embodiment, both the first semiconductor structure SM1 and the second semiconductor structure SM2 are single-layer structures, but the present invention is not limited thereto. In other embodiments, the first semiconductor structure SM1 is a multi-layer structure, and the second semiconductor structure SM2 is a single-layer structure.

在圖6的實施例中，藉由增加第一半導體結構SM1的厚度t1，可以改善第一主動元件TFT1（Source-Sync薄膜電晶體）的開啟電流小的問題。此外，由於第二半導體結構SM2的厚度t2較小，可以改善第二主動元件TFT2（TG-Sync薄膜電晶體）的漏電問題。In the embodiment of FIG. 6 , by increasing the thickness t1 of the first semiconductor structure SM1 , the problem of small turn-on current of the first active element TFT1 (Source-Sync thin film transistor) can be improved. In addition, since the thickness t2 of the second semiconductor structure SM2 is small, the leakage problem of the second active element TFT2 (TG-Sync thin film transistor) can be improved.

圖7A至圖7D是圖6的主動元件基板30的製造方法的剖面示意圖。7A to 7D are schematic cross-sectional views of the manufacturing method of the active device substrate 30 of FIG. 6 .

請參考圖7A，形成第一底閘極BG1與第二底閘極BG2於緩衝層BL上。在一些實施例中，第一底閘極BG1與第二底閘極BG2屬於同一圖案化層。Referring to FIG. 7A , a first bottom gate BG1 and a second bottom gate BG2 are formed on the buffer layer BL. In some embodiments, the first bottom gate BG1 and the second bottom gate BG2 belong to the same patterned layer.

接著，形成第一閘介電層GI1於第一底閘極BG1與第二底閘極BG2上。之後，形成第一半導體結構SM1’於第一閘介電層GI1上。第一半導體結構SM1’重疊於第一底閘極BG1。Next, a first gate dielectric layer GI1 is formed on the first bottom gate BG1 and the second bottom gate BG2 . After that, a first semiconductor structure SM1' is formed on the first gate dielectric layer GI1. The first semiconductor structure SM1' overlaps the first bottom gate BG1.

請參考圖7B，形成第二閘介電層GI2於第一半導體結構SM1’以及第一閘介電層GI1上。接著，形成第二半導體結構SM2’於第二閘介電層GI2上。第二半導體結構SM2’重疊於第二底閘極BG2。Referring to FIG. 7B, a second gate dielectric layer GI2 is formed on the first semiconductor structure SM1' and the first gate dielectric layer GI1. Next, a second semiconductor structure SM2' is formed on the second gate dielectric layer GI2. The second semiconductor structure SM2' overlaps the second bottom gate BG2.

在本實施例中，第一半導體結構SM1’的厚度大於第二半導體結構SM2’的厚度。In this embodiment, the thickness of the first semiconductor structure SM1' is greater than the thickness of the second semiconductor structure SM2'.

在本實施例中，第一半導體結構SM1’、第二閘介電層GI2以及第二半導體結構SM2’依序形成，但本發明不以此為限。在其他實施例中，先形成第二半導體結構SM2’，接著形成第二閘介電層GI2，最後才形成第一半導體結構SM1’。換句話說，在其他實施例中，第二閘介電層GI2形成於第二半導體結構SM2’上，且第一半導體結構SM1’形成於第二閘介電層GI2上。In this embodiment, the first semiconductor structure SM1', the second gate dielectric layer GI2 and the second semiconductor structure SM2' are formed sequentially, but the invention is not limited thereto. In other embodiments, the second semiconductor structure SM2' is formed first, followed by the second gate dielectric layer GI2, and finally the first semiconductor structure SM1' is formed. In other words, in other embodiments, the second gate dielectric layer GI2 is formed on the second semiconductor structure SM2', and the first semiconductor structure SM1' is formed on the second gate dielectric layer GI2.

請參考圖7C，形成第三閘介電層GI3於第二閘介電層GI2與第二半導體結構SM2’上。Referring to FIG. 7C , a third gate dielectric layer GI3 is formed on the second gate dielectric layer GI2 and the second semiconductor structure SM2'.

接著，形成第一頂閘極TG1與第二頂閘極TG2於第二閘介電層GI2上。在一些實施例中，第一頂閘極TG1與第二頂閘極TG2屬於同一圖案化層。Next, a first top gate TG1 and a second top gate TG2 are formed on the second gate dielectric layer GI2 . In some embodiments, the first top gate TG1 and the second top gate TG2 belong to the same patterned layer.

以第一頂閘極TG1與第二頂閘極TG2為罩幕，執行摻雜製程P，以形成包括第一源極區sr1、第一汲極區dr1以及第一通道區ch1的第一半導體結構SM1以及包括第二源極區sr2、第二汲極區dr2以及第二通道區ch2的第二半導體結構SM2。Using the first top gate TG1 and the second top gate TG2 as a mask, perform a doping process P to form a first semiconductor including a first source region sr1, a first drain region dr1, and a first channel region ch1 The structure SM1 and the second semiconductor structure SM2 including the second source region sr2 , the second drain region dr2 and the second channel region ch2 .

在一些實施例中，在形成第一頂閘極TG1與第二頂閘極TG2之前，對第一閘介電層GI1以及第二閘介電層GI2執行蝕刻製程，以形成暴露出第二底閘極BG2的接觸孔V1。接著，形成第二頂閘極TG2於接觸孔V1中，以電性連接第二底閘極BG2。In some embodiments, before forming the first top gate TG1 and the second top gate TG2, an etching process is performed on the first gate dielectric layer GI1 and the second gate dielectric layer GI2 to form the exposed second bottom gate. The contact hole V1 of the gate BG2. Next, a second top gate TG2 is formed in the contact hole V1 to be electrically connected to the second bottom gate BG2.

請參考圖7D，形成第一層間介電層ILD1於第一頂閘極TG1與第二頂閘極TG2上。形成第二層間介電層ILD2於第一層間介電層ILD1上。接著，執行一次或多次蝕刻製程，以形成暴露出第一源極區sr1、第一汲極區dr1、第二源極區sr2以及第二汲極區dr2的接觸孔H1~H4。在一些實施例中，在形成接觸孔H1~H4的同時，形成暴露出第一底閘極BG1的接觸孔V2。Referring to FIG. 7D , a first interlayer dielectric layer ILD1 is formed on the first top gate TG1 and the second top gate TG2 . A second interlayer dielectric layer ILD2 is formed on the first interlayer dielectric layer ILD1. Next, one or more etching processes are performed to form contact holes H1 - H4 exposing the first source region sr1 , the first drain region dr1 , the second source region sr2 and the second drain region dr2 . In some embodiments, while forming the contact holes H1 ˜ H4 , the contact hole V2 exposing the first bottom gate BG1 is formed.

最後，請回到圖6，形成第一源極S1、第一汲極D1、第二源極S2以及第二汲極D2於第二層間介電層ILD2上，第一源極S1、第一汲極D1、第二源極S2以及第二汲極D2分別填入接觸孔H1~H4中。在一些實施例中，第一源極S1還填入接觸孔V2中以電性連接第一底閘極BG1。Finally, please return to FIG. 6, form the first source S1, the first drain D1, the second source S2 and the second drain D2 on the second interlayer dielectric layer ILD2, the first source S1, the first The drain D1 , the second source S2 and the second drain D2 are respectively filled in the contact holes H1 - H4 . In some embodiments, the first source S1 is further filled into the contact hole V2 to be electrically connected to the first bottom gate BG1 .

最後，選擇性地形成保護層PL於第一源極S1、第一汲極D1、第二源極S2以及第二汲極D2上。至此，主動元件基板30大致完成。Finally, a protection layer PL is selectively formed on the first source S1 , the first drain D1 , the second source S2 and the second drain D2 . So far, the active device substrate 30 is roughly completed.

圖8是依照本發明的一實施例的一種主動元件基板的剖面示意圖。在此必須說明的是，圖8的實施例沿用圖6的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。FIG. 8 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 8 follows the component numbers and part of the content of the embodiment of FIG. 6 , wherein the same or similar numbers are used to denote the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

圖8的主動元件基板40與圖6的主動元件基板30的主要差異在於：在主動元件基板40中，第一半導體結構SM1位於第二閘介電層GI2與第三閘介電層GI3之間，且第二半導體結構SM2位於第一閘介電層GI1與第二閘介電層GI2之間。The main difference between the active device substrate 40 in FIG. 8 and the active device substrate 30 in FIG. 6 is that in the active device substrate 40, the first semiconductor structure SM1 is located between the second gate dielectric layer GI2 and the third gate dielectric layer GI3 , and the second semiconductor structure SM2 is located between the first gate dielectric layer GI1 and the second gate dielectric layer GI2 .

請參考圖8，第一閘介電層GI1位於第一底閘極BG1與第一半導體結構SM1之間以及第二底閘極BG2與第二半導體結構SM2之間。Please refer to FIG. 8 , the first gate dielectric layer GI1 is located between the first bottom gate BG1 and the first semiconductor structure SM1 and between the second bottom gate BG2 and the second semiconductor structure SM2 .

第二閘介電層GI2位於第一底閘極BG1與第一半導體結構SM1之間以及第二頂閘極TG1與第二半導體結構SM2之間。The second gate dielectric layer GI2 is located between the first bottom gate BG1 and the first semiconductor structure SM1 and between the second top gate TG1 and the second semiconductor structure SM2.

第三閘介電層GI3位於第一頂閘極TG1與第一半導體結構SM1之間以及第二頂閘極TG2與第二半導體結構SM2之間。The third gate dielectric layer GI3 is located between the first top gate TG1 and the first semiconductor structure SM1 and between the second top gate TG2 and the second semiconductor structure SM2.

在本實施例中，第一半導體結構SM1與第二半導體結構SM2皆為單層結構，但本發明不以此為限。在其他實施例中，第一半導體結構SM1為多層結構，而第二半導體結構SM2為單層結構。In this embodiment, both the first semiconductor structure SM1 and the second semiconductor structure SM2 are single-layer structures, but the present invention is not limited thereto. In other embodiments, the first semiconductor structure SM1 is a multi-layer structure, and the second semiconductor structure SM2 is a single-layer structure.

在圖8的實施例中，藉由增加第一半導體結構SM1的厚度t1，可以改善第一主動元件TFT1（Source-Sync薄膜電晶體）的開啟電流小的問題。此外，由於第二半導體結構SM2的厚度t2較小，可以改善第二主動元件TFT2（TG-Sync薄膜電晶體）的漏電問題。In the embodiment of FIG. 8 , by increasing the thickness t1 of the first semiconductor structure SM1 , the problem of small turn-on current of the first active element TFT1 (Source-Sync thin film transistor) can be improved. In addition, since the thickness t2 of the second semiconductor structure SM2 is small, the leakage problem of the second active element TFT2 (TG-Sync thin film transistor) can be improved.

圖9是依照本發明的一實施例的一種主動元件基板的剖面示意圖。圖10是依照本發明的一實施例的一種畫素電路的示意圖。FIG. 9 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention. FIG. 10 is a schematic diagram of a pixel circuit according to an embodiment of the present invention.

在本實施例中，主動元件基板包括畫素電路PX，畫素電路包括第一主動元件TFT1、第二主動元件TFT2、第三主動元件TFT3、發光二極體LED以及電容C。第一主動元件TFT1以及第二主動元件TFT2的結構可以參考圖1A、圖1B以及相關內容，於此不再贅述。In this embodiment, the active device substrate includes a pixel circuit PX, and the pixel circuit includes a first active device TFT1 , a second active device TFT2 , a third active device TFT3 , a light emitting diode LED and a capacitor C. The structures of the first active element TFT1 and the second active element TFT2 can refer to FIG. 1A , FIG. 1B and related contents, and will not be repeated here.

請參考圖1B與圖9，第三主動元件TFT3具有類似於第二主動元件TFT2的結構。第三主動元件TFT3位於基板SB之上，且包括第三底閘極BG3、第三半導體結構SM3、第三頂閘極TG3、第三源極S3以及第三汲極D3。Referring to FIG. 1B and FIG. 9 , the third active device TFT3 has a structure similar to that of the second active device TFT2 . The third active element TFT3 is located on the substrate SB and includes a third bottom gate BG3 , a third semiconductor structure SM3 , a third top gate TG3 , a third source S3 and a third drain D3 .

第三底閘極BG3位於緩衝層BL上。在一些實施例中，第一底閘極BG1、第二底閘極BG2以及第三底閘極BG3包括相同或不同的材料。在一些實施例中，第一底閘極BG1、第二底閘極BG2以及第三底閘極BG3屬於相同圖案化層。換句話說，第一底閘極BG1、第二底閘極BG2以及第三底閘極BG3同時形成。The third bottom gate BG3 is located on the buffer layer BL. In some embodiments, the first bottom gate BG1 , the second bottom gate BG2 and the third bottom gate BG3 include the same or different materials. In some embodiments, the first bottom gate BG1 , the second bottom gate BG2 and the third bottom gate BG3 belong to the same patterned layer. In other words, the first bottom gate BG1 , the second bottom gate BG2 and the third bottom gate BG3 are formed simultaneously.

第一閘介電層GI1位於第三底閘極BG3上。在本實施例中，第一閘介電層GI1接觸第三底閘極BG3的上表面。The first gate dielectric layer GI1 is located on the third bottom gate BG3. In this embodiment, the first gate dielectric layer GI1 contacts the upper surface of the third bottom gate BG3.

第三半導體結構SM3位於第一閘介電層GI1上。第一閘介電層GI1位於第三底閘極BG3與第三半導體結構SM3之間。在一些實施例中，第三半導體結構SM3包括第三源極區sr3、第三汲極區dr3以及位於第三源極區sr3與第三汲極區dr3之間的第三通道區ch3。第三源極區sr3以及第三汲極區dr3經摻雜（例如氫摻雜）而具有低於第三通道區ch3的電阻率。The third semiconductor structure SM3 is located on the first gate dielectric layer GI1. The first gate dielectric layer GI1 is located between the third bottom gate BG3 and the third semiconductor structure SM3. In some embodiments, the third semiconductor structure SM3 includes a third source region sr3 , a third drain region dr3 , and a third channel region ch3 between the third source region sr3 and the third drain region dr3 . The third source region sr3 and the third drain region dr3 are doped (for example hydrogen doped) to have a lower resistivity than the third channel region ch3 .

在一些實施例中，第三半導體結構SM3與第二半導體結構SM2屬於相同圖案化層。換句話說，第三半導體結構SM3與第二半導體結構SM2同時形成。在一些實施例中，第三半導體結構SM3的厚度t3與第二半導體結構SM2的厚度t2相同，且第三半導體結構SM3與第二半導體結構SM2包括相同的材料。In some embodiments, the third semiconductor structure SM3 and the second semiconductor structure SM2 belong to the same patterned layer. In other words, the third semiconductor structure SM3 is formed simultaneously with the second semiconductor structure SM2. In some embodiments, the thickness t3 of the third semiconductor structure SM3 is the same as the thickness t2 of the second semiconductor structure SM2, and the third semiconductor structure SM3 and the second semiconductor structure SM2 include the same material.

第二閘介電層GI2位於第三半導體結構SM3上。第三半導體結構SM3夾在第一閘介電層GI1與第二閘介電層GI2之間。The second gate dielectric layer GI2 is located on the third semiconductor structure SM3. The third semiconductor structure SM3 is sandwiched between the first gate dielectric layer GI1 and the second gate dielectric layer GI2 .

第三頂閘極TG3位於第二閘介電層GI2上。第二閘介電層GI2位於第三頂閘極TG3與第三半導體結構SM3之間。第三半導體結構SM3位於第三底閘極BG3與第三頂閘極TG3之間。在一些實施例中，第一頂閘極TG1、第二頂閘極TG2以及第三頂閘極TG3包括相同或不同的材料。在一些實施例中，第一頂閘極TG1、第二頂閘極TG2以及第三頂閘極TG3屬於相同圖案化層。換句話說，第一頂閘極TG1、第二頂閘極TG2以及第三頂閘極TG3同時形成。The third top gate TG3 is located on the second gate dielectric layer GI2. The second gate dielectric layer GI2 is located between the third top gate TG3 and the third semiconductor structure SM3. The third semiconductor structure SM3 is located between the third bottom gate BG3 and the third top gate TG3. In some embodiments, the first top gate TG1 , the second top gate TG2 and the third top gate TG3 include the same or different materials. In some embodiments, the first top gate TG1 , the second top gate TG2 and the third top gate TG3 belong to the same patterned layer. In other words, the first top gate TG1 , the second top gate TG2 and the third top gate TG3 are formed simultaneously.

在本實施例中，第三主動元件TFT3為第三底閘極BG3電性連接第三頂閘極TG3的雙閘極型薄膜電晶體（TG-sync薄膜電晶體）。舉例來說，第三頂閘極TG3透過接觸孔V3而連接至第三底閘極BG3，其中接觸孔V3穿過第一閘介電層GI1與第二閘介電層GI2。In this embodiment, the third active element TFT3 is a double-gate thin film transistor (TG-sync thin film transistor) in which the third bottom gate BG3 is electrically connected to the third top gate TG3 . For example, the third top gate TG3 is connected to the third bottom gate BG3 through the contact hole V3, wherein the contact hole V3 passes through the first gate dielectric layer GI1 and the second gate dielectric layer GI2.

第一層間介電層ILD1位於第三頂閘極TG3上。第二層間介電層ILD2位於第一層間介電層ILD1上。The first interlayer dielectric layer ILD1 is located on the third top gate TG3. The second interlayer dielectric layer ILD2 is on the first interlayer dielectric layer ILD1.

第三源極S3以及第三汲極D3位於第二層間介電層ILD2上。第三源極S3以及第三汲極D3分別透過接觸孔H5、H6而電性連接至第三半導體結構SM3的第三源極區sr3以及第三汲極區dr3，其中接觸孔H5、H6穿過第二閘介電層GI2、第一層間介電層ILD1與第二層間介電層ILD2。在一些實施例中，第一源極S1、第一汲極D1、第二源極S2、第二汲極D2、第三源極S3以及第三汲極D3包括相同或不同的材料。在一些實施例中，第一源極S1、第一汲極D1、第二源極S2、第二汲極D2、第三源極S3以及第三汲極D3屬於相同圖案化層。換句話說，第一源極S1、第一汲極D1、第二源極S2、第二汲極D2、第三源極S3以及第三汲極D3同時形成。The third source S3 and the third drain D3 are located on the second interlayer dielectric layer ILD2. The third source S3 and the third drain D3 are respectively electrically connected to the third source region sr3 and the third drain region dr3 of the third semiconductor structure SM3 through the contact holes H5 and H6, wherein the contact holes H5 and H6 pass through through the second gate dielectric layer GI2 , the first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2 . In some embodiments, the first source S1 , the first drain D1 , the second source S2 , the second drain D2 , the third source S3 and the third drain D3 include the same or different materials. In some embodiments, the first source S1 , the first drain D1 , the second source S2 , the second drain D2 , the third source S3 and the third drain D3 belong to the same patterned layer. In other words, the first source S1 , the first drain D1 , the second source S2 , the second drain D2 , the third source S3 and the third drain D3 are formed simultaneously.

請同時參考圖1B、圖9以及圖10，在畫素電路PX中，第一主動元件TFT1的第一汲極D1電性連接至電壓V DD，第一源極S1電性連接至發光二極體LED（例如為有機發光二極體或無機發光二極體）的其中一端、電容C的其中一端以及第三主動元件TFT3的第三汲極D3；第一頂閘極TG1電性連接至電容C的其中另一端以及第二主動元件TFT2的第二源極S2。發光二極體LED的其中另一端電性連接至電壓V SS，電壓V DD高於V SS。 Please refer to FIG. 1B, FIG. 9 and FIG. 10 at the same time. In the pixel circuit PX, the first drain D1 of the first active element TFT1 is electrically connected to the voltage V DD , and the first source S1 is electrically connected to the light-emitting diode. One end of the body LED (such as an organic light emitting diode or an inorganic light emitting diode), one end of the capacitor C, and the third drain D3 of the third active element TFT3; the first top gate TG1 is electrically connected to the capacitor The other end of C and the second source S2 of the second active element TFT2. The other end of the light-emitting diode LED is electrically connected to the voltage V SS , and the voltage V DD is higher than V SS .

第二主動元件TFT2的第二汲極D2電性連接至資料線電壓V DL，第二頂閘極TG2電性連接至第一掃描線電壓V SCAN1。 The second drain D2 of the second active element TFT2 is electrically connected to the data line voltage V DL , and the second top gate TG2 is electrically connected to the first scan line voltage V SCAN1 .

第三主動元件TFT3的第三源極S3電性連接至共用線電壓V COM，第三頂閘極TG3電性連接至第二掃描線電壓V SCAN2。 The third source S3 of the third active element TFT3 is electrically connected to the common line voltage V COM , and the third top gate TG3 is electrically connected to the second scan line voltage V SCAN2 .

在本實施例中，第二主動元件TFT2作為開關薄膜電晶體，第一主動元件TFT1作為驅動薄膜電晶體，且第二主動元件TFT2用於控制第一主動元件TFT1之第一頂閘極TG1的開關。第三主動元件TFT3作為感測薄膜電晶體，用於將通過第一主動元件TFT1之驅動電流的資訊傳送給外部晶片。In this embodiment, the second active element TFT2 is used as a switching thin film transistor, the first active element TFT1 is used as a driving thin film transistor, and the second active element TFT2 is used to control the first top gate TG1 of the first active element TFT1. switch. The third active element TFT3 is used as a sensing thin film transistor for transmitting the information of the driving current passing through the first active element TFT1 to an external chip.

綜上所述，本發明可以提升第一主動元件的長時間開啟的可靠度，同時增加第二主動元件與第三主動元件的開啟電流。To sum up, the present invention can improve the long-time turn-on reliability of the first active element, and increase the turn-on current of the second active element and the third active element at the same time.

10,20,30,40:主動元件基板 a-a’,b-b’,c-c’:線 BG1:第一底閘極 BG2:第二底閘極 BG3:第三底閘極 BL:緩衝層 C:電容 ch1:第一通道區 ch2:第二通道區 ch3:第三通道區 D1:第一汲極 D2:第二汲極 D3:第三汲極 dr1:第一汲極區 dr2:第二汲極區 dr3:第三汲極區 GI1:第一閘介電層 GI2:第二閘介電層 GI3:第三閘介電層 H1~H6,V1~V3,V2’:接觸孔 ILD1:第一層間介電層 ILD2:第二層間介電層 OS1,OS1’:第一半導體層 OS2,OS2’:第二半導體層 P:摻雜製程 PL:保護層 PX:畫素電路 S1:第一源極 S2:第二源極 S3:第三源極 SB:基板 SM1,SM1’:第一半導體結構 SM2,SM2’:第二半導體結構 SM3:第三半導體結構 sr1:第一源極區 sr2:第二源極區 sr3:第三源極區 TFT1:第一主動元件 TFT2:第二主動元件 TFT3:第三主動元件 TG1:第一頂閘極 TG2:第二頂閘極 TG3:第三頂閘極 t1~t3:厚度 V COM:共用線電壓 V DD,V SS:電壓 V DL:資料線電壓 V SCAN1:第一掃描線電壓 V SCAN2:第二掃描線電壓10,20,30,40: active component substrate a-a', b-b', c-c': line BG1: first bottom gate BG2: second bottom gate BG3: third bottom gate BL: Buffer layer C: capacitor ch1: first channel area ch2: second channel area ch3: third channel area D1: first drain D2: second drain D3: third drain dr1: first drain area dr2: The second drain region dr3: the third drain region GI1: the first gate dielectric layer GI2: the second gate dielectric layer GI3: the third gate dielectric layer H1~H6, V1~V3, V2': contact hole ILD1 : first interlayer dielectric layer ILD2: second interlayer dielectric layer OS1, OS1': first semiconductor layer OS2, OS2': second semiconductor layer P: doping process PL: protective layer PX: pixel circuit S1: First source S2: second source S3: third source SB: substrate SM1, SM1': first semiconductor structure SM2, SM2': second semiconductor structure SM3: third semiconductor structure sr1: first source region sr2: second source region sr3: third source region TFT1: first active element TFT2: second active element TFT3: third active element TG1: first top gate TG2: second top gate TG3: third Top gate t1~t3: thickness V COM : common line voltage V DD , V SS : voltage V DL : data line voltage V SCAN1 : first scan line voltage V SCAN2 : second scan line voltage

圖1A是依照本發明的一實施例的一種主動元件基板的上視示意圖。 圖1B是圖1A的線a-a’、線b-b’以及線c-c’的剖面示意圖。 圖2A是依照本發明的一些實施例的第一主動元件的第一半導體結構的厚度與閾值電壓的實驗數據圖。 圖2B是依照本發明的一些實施例的第一主動元件的第一半導體結構的厚度與開啟電流的實驗數據圖。 圖3是依照本發明的一些實施例的第一主動元件在長時間操作後的開啟電流的衰退與閾值電壓的變化。 圖4A至圖4D是圖1的主動元件基板的製造方法的剖面示意圖。 圖5是依照本發明的一實施例的一種主動元件基板的剖面示意圖。 圖6是依照本發明的一實施例的一種主動元件基板的剖面示意圖。 圖7A至圖7D是圖6的主動元件基板的製造方法的剖面示意圖。 圖8是依照本發明的一實施例的一種主動元件基板的剖面示意圖 圖9是依照本發明的一實施例的一種主動元件基板的剖面示意圖。 圖10是依照本發明的一實施例的一種畫素電路的示意圖。 FIG. 1A is a schematic top view of an active device substrate according to an embodiment of the present invention. Fig. 1B is a schematic cross-sectional view of line a-a', line b-b' and line c-c' in Fig. 1A. FIG. 2A is an experimental data diagram of the thickness and the threshold voltage of the first semiconductor structure of the first active device according to some embodiments of the present invention. 2B is an experimental data diagram of the thickness and turn-on current of the first semiconductor structure of the first active device according to some embodiments of the present invention. FIG. 3 shows the decay of the turn-on current and the variation of the threshold voltage of the first active device after a long time of operation according to some embodiments of the present invention. 4A to 4D are schematic cross-sectional views of the manufacturing method of the active device substrate shown in FIG. 1 . FIG. 5 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention. 7A to 7D are schematic cross-sectional views of the manufacturing method of the active device substrate shown in FIG. 6 . 8 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention FIG. 9 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention. FIG. 10 is a schematic diagram of a pixel circuit according to an embodiment of the present invention.

10:主動元件基板 10: Active component substrate

a-a’,b-b’,c-c’:線 a-a',b-b',c-c': line

BG1:第一底閘極 BG1: the first bottom gate

BG2:第二底閘極 BG2: The second bottom gate

BL:緩衝層 BL: buffer layer

ch1:第一通道區 ch1: the first channel area

ch2:第二通道區 ch2: the second channel area

D1:第一汲極 D1: the first drain

D2:第二汲極 D2: the second drain

dr1:第一汲極區 dr1: the first drain region

dr2:第二汲極區 dr2: the second drain region

GI1:第一閘介電層 GI1: first gate dielectric layer

GI2:第二閘介電層 GI2: second gate dielectric layer

H1~H4,V1,V2:接觸孔 H1~H4, V1, V2: contact holes

ILD1:第一層間介電層 ILD1: The first interlayer dielectric layer

ILD2:第二層間介電層 ILD2: The second interlayer dielectric layer

OS1:第一半導體層 OS1: first semiconductor layer

OS2:第二半導體層 OS2: Second semiconductor layer

PL:保護層 PL: protective layer

S1:第一源極 S1: first source

S2:第二源極 S2: second source

SB:基板 SB: Substrate

SM1:第一半導體結構 SM1: First Semiconductor Structure

SM2:第二半導體結構 SM2: Second semiconductor structure

sr1:第一源極區 sr1: the first source region

sr2:第二源極區 sr2: second source region

TFT1:第一主動元件 TFT1: the first active element

TFT2:第二主動元件 TFT2: the second active element

TG1:第一頂閘極 TG1: first top gate

TG2:第二頂閘極 TG2: second top gate

t1,t2:厚度 t1, t2: thickness

Claims (10)

一種主動元件基板，包括： 一基板； 一第一主動元件，位於該基板之上，且包括： 一第一底閘極、一第一半導體結構以及一第一頂閘極，其中該第一半導體結構位於該第一底閘極與該第一頂閘極之間；以及 一第一源極以及一第一汲極，電性連接至該第一半導體結構，且該第一源極電性連接至該第一底閘極；以及 一第二主動元件，位於該基板之上，且電性連接至該第一主動元件，其中該第二主動元件包括： 一第二底閘極、一第二半導體結構以及一第二頂閘極，其中該第二半導體結構位於該第二底閘極與該第二頂閘極之間，且該第二半導體結構的厚度小於該第一半導體結構的厚度，且該第二底閘極電性連接該第二頂閘極；以及 一第二源極以及一第二汲極，電性連接至該第二半導體結構。 An active component substrate, comprising: a substrate; A first active element is located on the substrate and includes: a first bottom gate, a first semiconductor structure, and a first top gate, wherein the first semiconductor structure is located between the first bottom gate and the first top gate; and a first source and a first drain electrically connected to the first semiconductor structure, and the first source electrically connected to the first bottom gate; and A second active element is located on the substrate and electrically connected to the first active element, wherein the second active element includes: A second bottom gate, a second semiconductor structure, and a second top gate, wherein the second semiconductor structure is located between the second bottom gate and the second top gate, and the second semiconductor structure a thickness smaller than that of the first semiconductor structure, and the second bottom gate is electrically connected to the second top gate; and A second source and a second drain are electrically connected to the second semiconductor structure. 如請求項1所述的主動元件基板，更包括： 一第一閘介電層，位於該第一底閘極與該第一半導體結構之間以及該第二底閘極與該第二半導體結構之間；以及 一第二閘介電層，位於該第一頂閘極與該第一半導體結構之間以及該第二頂閘極與該第二半導體結構之間。 The active component substrate as described in claim 1, further comprising: a first gate dielectric layer between the first bottom gate and the first semiconductor structure and between the second bottom gate and the second semiconductor structure; and A second gate dielectric layer is located between the first top gate and the first semiconductor structure and between the second top gate and the second semiconductor structure. 如請求項1所述的主動元件基板，更包括： 一第一閘介電層，位於該第一底閘極與該第一半導體結構之間以及該第二底閘極與該第二半導體結構之間； 一第二閘介電層，位於該第一頂閘極與該第一半導體結構之間以及該第二底閘極與該第二半導體結構之間；以及 一第三閘介電層，位於該第一頂閘極與該第一半導體結構之間以及該第二頂閘極與該第二半導體結構之間。 The active component substrate as described in claim 1, further comprising: a first gate dielectric layer located between the first bottom gate and the first semiconductor structure and between the second bottom gate and the second semiconductor structure; a second gate dielectric layer between the first top gate and the first semiconductor structure and between the second bottom gate and the second semiconductor structure; and A third gate dielectric layer is located between the first top gate and the first semiconductor structure and between the second top gate and the second semiconductor structure. 如請求項1所述的主動元件基板，更包括： 一第一閘介電層，位於該第一底閘極與該第一半導體結構之間以及該第二底閘極與該第二半導體結構之間； 一第二閘介電層，位於該第一底閘極與該第一半導體結構之間以及該第二頂閘極與該第二半導體結構之間；以及 一第三閘介電層，位於該第一頂閘極與該第一半導體結構之間以及該第二頂閘極與該第二半導體結構之間。 The active component substrate as described in claim 1, further comprising: a first gate dielectric layer located between the first bottom gate and the first semiconductor structure and between the second bottom gate and the second semiconductor structure; a second gate dielectric layer between the first bottom gate and the first semiconductor structure and between the second top gate and the second semiconductor structure; and A third gate dielectric layer is located between the first top gate and the first semiconductor structure and between the second top gate and the second semiconductor structure. 如請求項1所述的主動元件基板，更包括： 一第三主動元件，位於該基板之上，且包括： 一第三底閘極、一第三半導體結構以及一第三頂閘極，其中該第三半導體結構位於該第三底閘極與該第三頂閘極之間，且該第三底閘極電性連接該第三頂閘極；以及 一第三源極以及一第三汲極，電性連接至該第三半導體結構，其中該第二源極電性連接至該第一頂閘極，且該第一源極電性連接至該第三汲極。 The active component substrate as described in claim 1 further includes: A third active element is located on the substrate and includes: a third bottom gate, a third semiconductor structure and a third top gate, wherein the third semiconductor structure is located between the third bottom gate and the third top gate, and the third bottom gate electrically connected to the third top gate; and A third source and a third drain are electrically connected to the third semiconductor structure, wherein the second source is electrically connected to the first top gate, and the first source is electrically connected to the The third drain. 如請求項5所述的主動元件基板，其中該第三半導體結構與該第二半導體結構包括相同的厚度。The active device substrate as claimed in claim 5, wherein the third semiconductor structure and the second semiconductor structure have the same thickness. 如請求項1所述的主動元件基板，其中該第一半導體結構為單層結構或多層結構。The active device substrate as claimed in claim 1, wherein the first semiconductor structure is a single-layer structure or a multi-layer structure. 如請求項7所述的主動元件基板，其中該第一半導體結構為多層結構，且包括： 一第一半導體層；以及 一第二半導體層，重疊於該第一半導體層，且該第二半導體層與該第二半導體結構屬於同一圖案化層。 The active element substrate as claimed in item 7, wherein the first semiconductor structure is a multilayer structure, and includes: a first semiconductor layer; and A second semiconductor layer overlaps the first semiconductor layer, and the second semiconductor layer and the second semiconductor structure belong to the same patterned layer. 如請求項8所述的主動元件基板，其中該第一半導體層與該第二半導體層包括不同的材料。The active device substrate as claimed in claim 8, wherein the first semiconductor layer and the second semiconductor layer comprise different materials. 如請求項1所述的主動元件基板，其中該第一底閘極與該第二底閘極屬於同一圖案化層，且該第一頂閘極與該第二頂閘極屬於另外同一圖案化層。The active device substrate as claimed in item 1, wherein the first bottom gate and the second bottom gate belong to the same patterned layer, and the first top gate and the second top gate belong to another same patterned layer layer.
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