TWI802474B

TWI802474B - Ic die forming method and ic die structure

Info

Publication number: TWI802474B
Application number: TW111127723A
Authority: TW
Inventors: 張智勝; 陳曜洲
Original assignee: 晶豪科技股份有限公司
Priority date: 2022-07-25
Filing date: 2022-07-25
Publication date: 2023-05-11
Also published as: TW202406019A

Abstract

An integrated circuit die forming method, for forming a plurality of integrated circuit dies on a semiconductor wafer, comprising: forming a first device, a second device in a first die in a first area; forming a metal layer connected to the first device and the second device; forming a third device, a fourth device in a second die in a second area; forming the metal layer connected to the third device and the fourth device, wherein a scribe area exists between the first area and the second area; wherein the first device and the third device are used for synchronization and are components of a class D amplifier; wherein the second device is used for preventing leakage currents of the first die and the fourth device is used for preventing leakage currents of the second die.

Description

IC　晶粒形成方法以及IC　晶粒結構IC Grain Formation Method and IC Grain Structure

本發明係有關於IC （Integrated Circuit，積體電路）晶粒形成方法以及IC 晶粒結構，特別有關於可防止漏電流的IC 晶粒形成方法以及IC 晶粒結構。The present invention relates to an IC (Integrated Circuit) grain forming method and an IC grain structure, and particularly relates to an IC grain forming method and an IC grain structure capable of preventing leakage current.

通常，一個IC封裝 (package) 可以包含多個IC晶粒 (die)。然而，在某些使用場合，IC晶粒需要被分離成多個單一晶粒。在這種情況下，單一晶粒因為其一些物理結構被損壞，可能會產生漏電流。因此，需要一些機制來防止這類漏電流。Generally, an IC package (package) can contain multiple IC dies (die). However, in some applications, the IC die needs to be separated into multiple single dies. In this case, a single die may generate leakage current because some of its physical structure is damaged. Therefore, some mechanism is needed to prevent this type of leakage current.

本發明一目的為提供一種IC 晶粒形成方法，其可產生可防止漏電流的IC 晶粒結構。An object of the present invention is to provide an IC grain formation method, which can produce an IC grain structure that can prevent leakage current.

本發明另一目的為提供一種可防止漏電流的IC 晶粒結構。Another object of the present invention is to provide an IC grain structure that can prevent leakage current.

本發明一實施例揭露了一種IC晶粒形成方法，用以在一半導體晶圓上形成複數個IC晶粒，包含：在一第一區形成一第一晶粒，包含：在該第一區形成一第一裝置；在該第一區形成一第二裝置；形成連接該第一裝置以及該第二裝置的一金屬層；在一第二區形成一第二晶粒，包含：在該第二區形成一第三裝置；在該第二區形成一第四裝置；形成連接該第三裝置以及該第四裝置的該金屬層，其中該第一區以及該第二區間具有一切割區；使該金屬層具有一區段，該區段連接位於該第一區中該金屬層的一部份以及位於該第二區中該金屬層的一部份，以在該切割區延伸；其中該第一裝置以及該第三裝置用以同步且為一D類型放大器的元件；其中該第二裝置用以防止該第一晶粒的漏電流，而該第四裝置用以防止該第二晶粒的漏電流。An embodiment of the present invention discloses a method for forming IC crystal grains, which is used to form a plurality of IC crystal grains on a semiconductor wafer, including: forming a first crystal grain in a first region, including: forming a first crystal grain in the first region forming a first device; forming a second device in the first region; forming a metal layer connecting the first device and the second device; forming a second crystal grain in a second region, including: forming a third device in the second region; forming a fourth device in the second region; forming the metal layer connecting the third device and the fourth device, wherein the first region and the second region have a cutting region; causing the metal layer to have a section connecting a portion of the metal layer in the first region and a portion of the metal layer in the second region to extend in the cutting region; wherein the The first device and the third device are used for synchronization and are components of a D-type amplifier; wherein the second device is used to prevent the leakage current of the first die, and the fourth device is used to prevent the second die from leakage current.

本發明另一實施例揭露了一種IC 晶粒結構，包含一第一晶粒以及一第二晶粒。第一晶粒位於一第一區，包含：位於該第一區中的一第一裝置；位於該第一區中的一第二裝置；一金屬層，耦接該第一裝置以及該第二裝置。第二晶粒位於一第二區，包含：位於該第三區中的一第三裝置；位於該第四區中的一第四裝置；其中該金屬層更連接該第三裝置以及該第四裝置；其中該第一區以及該第二區間具有一切割區；其中該金屬層具有一區段，該區段連接位於該第一區中該金屬層的一部份以及位於該第二區中該金屬層的一部份；其中該第一裝置以及該第三裝置用以同步且為一D類型放大器的元件；其中該第二裝置用以防止該第一晶粒的漏電流，而該第四裝置用以防止該第二晶粒的漏電流。Another embodiment of the present invention discloses an IC grain structure, which includes a first grain and a second grain. The first die is located in a first area, including: a first device located in the first area; a second device located in the first area; a metal layer coupling the first device and the second device device. The second die is located in a second area, including: a third device located in the third area; a fourth device located in the fourth area; wherein the metal layer is further connected to the third device and the fourth device device; wherein the first region and the second region have a cutting region; wherein the metal layer has a section connecting a portion of the metal layer in the first region and in the second region A part of the metal layer; wherein the first device and the third device are used for synchronization and are elements of a D-type amplifier; wherein the second device is used to prevent the leakage current of the first die, and the first device Four means are used to prevent the leakage current of the second die.

根據前述實施例，即使晶粒分離也可以防止晶粒的漏電流。According to the aforementioned embodiments, the leakage current of the die can be prevented even if the die is separated.

以下將以多個實施例來描述本發明的內容，還請留意，各實施例中的元件可透過硬體 (例如裝置或電路)或是韌體 (例如微處理器中寫入至少一程式)來實施。此外，以下描述中的”第一”、”第二”以及類似描述僅用來定義不同的元件、參數、資料、訊號或步驟。並非用以限定其次序。舉例來說，第一裝置和第二裝置可為具有相同結構但為不同的裝置。The content of the present invention will be described below with multiple embodiments. Please also note that the components in each embodiment can be implemented through hardware (such as a device or circuit) or firmware (such as writing at least one program in a microprocessor) to implement. In addition, "first", "second" and similar descriptions in the following descriptions are only used to define different elements, parameters, data, signals or steps. It is not intended to limit the order. For example, the first device and the second device may be different devices having the same structure.

第1圖繪示了根據本發明一實施例的IC晶粒結構的方塊圖。如第1圖所示，IC晶粒結構100包含第一晶粒DI1和第二晶粒DI2。此外，第一晶粒DI1包含第一裝置DV1和第二裝置DV2，第二晶粒DI2包含第三裝置DV3和第四裝置DV4。金屬線ML位於第一晶粒DI1和第二晶粒DI2之間，用以連接第一裝置DV1和第三裝置DV3。第一裝置DV1和第三裝置DV3用以同步且是D類放大器的元件。此外，第二裝置DV2用以防止第一晶粒DI1的漏電流，第四裝置DV4用以防止第二晶粒DI2的漏電流。FIG. 1 illustrates a block diagram of an IC die structure according to an embodiment of the present invention. As shown in FIG. 1 , the IC die structure 100 includes a first die DI1 and a second die DI2 . In addition, the first die DI1 includes a first device DV1 and a second device DV2, and the second die DI2 includes a third device DV3 and a fourth device DV4. The metal line ML is located between the first die DI1 and the second die DI2 for connecting the first device DV1 and the third device DV3 . The first device DV1 and the third device DV3 are used for synchronization and are components of a class D amplifier. In addition, the second device DV2 is used to prevent the leakage current of the first die DI1 , and the fourth device DV4 is used to prevent the leakage current of the second die DI2 .

在一實施例中，第一晶粒DI1是發射端 (transmitter)，第二晶粒DI2是接收端 (receiver)。此外，在一實施例中，第一裝置DV1是時脈產生器，第三裝置DV3是三角波產生器。在此情況下，第三裝置DV3接收第一裝置DV1產生的時脈信號，並根據此時脈信號產生D類放大器所使用的三角波。在一實施例中，包含第三裝置DV3的D類放大器產生PWM(脈衝寬度調變，Pulse Width Modulation)信號，此PWM信號對應於第三裝置DV3產生的三角波。通過這種方式，可以使包含第一裝置DV1的D類放大器和包含第三裝置DV3的D類放大器同步。以下將描述第二裝置DV2和第四裝置DV4的詳細結構的例子。In one embodiment, the first die DI1 is a transmitter, and the second die DI2 is a receiver. Furthermore, in one embodiment, the first device DV1 is a clock generator, and the third device DV3 is a triangle wave generator. In this case, the third device DV3 receives the clock signal generated by the first device DV1, and generates a triangular wave used by the class D amplifier according to the clock signal. In one embodiment, the class D amplifier including the third device DV3 generates a PWM (Pulse Width Modulation, Pulse Width Modulation) signal, and the PWM signal corresponds to the triangular wave generated by the third device DV3. In this way, the class D amplifier comprising the first means DV1 and the class D amplifier comprising the third means DV3 can be synchronized. Examples of detailed structures of the second device DV2 and the fourth device DV4 will be described below.

在一實施例中，IC晶粒結構100還包含切割區Sb。對於某些應用，第一晶粒DI1和第二晶粒DI2可以相互連接並一起動作。然而，對於某些應用，第一裝置DI1和第二裝置DI2需要被分離。例如，第一裝置DI1和第二裝置DI2使用於兩個彼此無關的獨立電路。在這種情況下，切割區Sb會被切割使得金屬線ML也被切割，使第一晶粒DI1和第二晶粒DI2分離。In one embodiment, the IC die structure 100 further includes a cutting region Sb. For some applications, the first die DI1 and the second die DI2 may be connected to each other and act together. However, for some applications, the first device DI1 and the second device DI2 need to be separated. For example, the first device DI1 and the second device DI2 are used in two independent circuits that have nothing to do with each other. In this case, the cutting region Sb is cut so that the metal line ML is also cut to separate the first die DI1 from the second die DI2 .

在一實施例中，如果D類放大器應用於雙聲道喇叭，則第一晶粒DI1和第二晶粒DI2不分離。此外，如果D類放大器應用於單聲道喇叭，則第一晶粒DI1和第二晶粒DI2不分離。In an embodiment, if the class D amplifier is applied to a two-channel speaker, the first die DI1 and the second die DI2 are not separated. In addition, if the class D amplifier is applied to a mono speaker, the first die DI1 and the second die DI2 are not separated.

第2圖、第3圖以及第4圖繪示了根據本發明不同實施例的，具防漏電流機制的IC晶粒結構的電路圖。在以下實施例中，是應用第二裝置DV2和第四裝置DV4來防止在第一晶粒DI1和第二晶粒DI2分離之後發生漏電流。這裡所說的“分離”是指第一裝置DI1和第二裝置DI2被切斷且彼此不連接。然而，第二裝置DV2和第四裝置DV4可用於防止在任何情況下發生的漏電流，而不限於兩個晶粒的分離。例如，當第一晶粒DI1和第二晶粒DI2連接並在單一IC中的睡眠模式下動作時，可能會發生漏電流。還請了解，在以下部份實施例中，僅以第二裝置DV2為例進行說明。第四裝置DV4可以包含相同的結構，但為了簡潔省略其說明。FIG. 2 , FIG. 3 and FIG. 4 illustrate circuit diagrams of IC grain structures with anti-leakage current mechanism according to different embodiments of the present invention. In the following embodiments, the second device DV2 and the fourth device DV4 are applied to prevent leakage current from occurring after the first die DI1 and the second die DI2 are separated. The "separation" mentioned here means that the first device DI1 and the second device DI2 are cut off and not connected to each other. However, the second device DV2 and the fourth device DV4 may be used to prevent leakage current occurring in any case, not limited to separation of two dies. For example, when the first die DI1 and the second die DI2 are connected and operate in a sleep mode in a single IC, leakage current may occur. Please also understand that in some of the following embodiments, only the second device DV2 is used as an example for illustration. The fourth device DV4 may include the same structure, but its description is omitted for brevity.

在第2圖的實施例中，第二裝置DV2包含連接到金屬線ML的開關電路SW1，其可以控制第一晶粒DI1和第二晶粒DI2之間導通或不導通。開關電路SW1由分離信號SS控制，可在接收到表示第一晶粒DI1和第二晶粒DI2分離的分離信號SS時關閉(不導通)，且在接收到表示第一裝置DI1和第二裝置DI2沒有分離的分離信號 SS時開啟(導通)。在一實施例中，開關電路SW1為一NMOSFET，其閘極接收分離訊號SS，但不以此為限。In the embodiment of FIG. 2 , the second device DV2 includes a switch circuit SW1 connected to the metal line ML, which can control conduction or non-conduction between the first die DI1 and the second die DI2 . The switch circuit SW1 is controlled by the separation signal SS, and can be closed (non-conductive) when receiving the separation signal SS indicating that the first die DI1 and the second die DI2 are separated, and can be turned off (non-conductive) when receiving the separation signal SS indicating that the first device DI1 and the second device are separated. DI2 turns ON (conduction) when there is no separation signal SS of separation. In one embodiment, the switch circuit SW1 is an NMOSFET whose gate receives the separation signal SS, but not limited thereto.

在第3圖的實施例中，第二裝置DV2包含邏輯電路，其可以輸出對應於控制信號(例如，分離信號SS)的邏輯值。如第3圖所示，邏輯電路包含及閘301，其若接收代表第一晶粒DI1和第二晶粒DI2分離的分離信號SS時，則輸出預定邏輯值0。在第3圖的實施例中，第一晶粒DI1還包含反及閘303，其接收觸發信號Tr1和Tr2以產生分離信號SS。在一實施例中，邏輯電路還包含緩衝閘305、307，但不限於此。觸發信號Tr1和Tr2可以通過各種機制產生，稍後將詳細描述其例子。In the embodiment of FIG. 3, the second device DV2 comprises a logic circuit, which can output a logic value corresponding to the control signal (eg, the separation signal SS). As shown in FIG. 3 , the logic circuit includes an AND gate 301 , which outputs a predetermined logic value 0 when receiving a separation signal SS representing the separation of the first die DI1 and the second die DI2 . In the embodiment of FIG. 3 , the first die DI1 further includes an NAND gate 303 , which receives the trigger signals Tr1 and Tr2 to generate the separation signal SS. In one embodiment, the logic circuit further includes buffer gates 305 and 307 , but is not limited thereto. The trigger signals Tr1 and Tr2 can be generated by various mechanisms, examples of which will be described in detail later.

在第4圖的實施例中，第二裝置DV2包含反相器IVl，其可以選擇性的輸出第一電流和小於第一電流的第二電流。在一實施例中，反相器IV1的輸出電流由其上拉電流IP1控制。具體來說，反相器IV1在第一晶粒DI1和第二晶粒DI2未分離時輸出第一電流，在第一晶粒DI1和第二晶粒DI2分離時輸出第二電流。如此一來，當第一晶粒DI1與第二晶粒DI2分離時，第一晶粒DI1輸出的電流較小，可減少漏電流。In the embodiment shown in FIG. 4, the second device DV2 includes an inverter IV1, which can selectively output a first current and a second current smaller than the first current. In one embodiment, the output current of the inverter IV1 is controlled by its pull-up current IP1. Specifically, the inverter IV1 outputs a first current when the first die DI1 and the second die DI2 are not separated, and outputs a second current when the first die DI1 and the second die DI2 are separated. In this way, when the first die DI1 is separated from the second die DI2 , the output current of the first die DI1 is smaller, which can reduce the leakage current.

請注意，在第4圖的實施例中，反相器IV1連接到反相器IV2，其具有耦接到小下拉電流ID1的輸入端。然而，反相器IV1的配置不限於此例。Note that in the embodiment of FIG. 4, inverter IV1 is connected to inverter IV2, which has an input coupled to a small pull-down current ID1. However, the configuration of the inverter IV1 is not limited to this example.

反相器IVl可用以防止第一晶粒DIl的漏電流。在一實施例中，第二裝置DV2還包含用以防止第二晶粒DI2的漏電流的反相器IV3，並且還包含連接到反相器IV3的反相器IV4。反相器IV1和IV2通過金屬線ML1連接，反相器IV3和IV4通過金屬線ML2連接。反相器IV3接收上拉電流IP2，而反相器IV4的輸入端耦接下拉電流ID2。反相器IV3、IV4的動作與反相器IV1、IV2中的動作相同。The inverter IV1 can be used to prevent the leakage current of the first die DI1. In one embodiment, the second device DV2 further includes an inverter IV3 for preventing leakage current of the second die DI2, and further includes an inverter IV4 connected to the inverter IV3. Inverters IV1 and IV2 are connected by a metal line ML1, and inverters IV3 and IV4 are connected by a metal line ML2. The inverter IV3 receives the pull-up current IP2, and the input terminal of the inverter IV4 is coupled to the pull-down current ID2. The operations of inverters IV3, IV4 are the same as those of inverters IV1, IV2.

此外，在本例中，第3圖中的觸發信號Trl、Tr2分別由反相器IV2和IV4產生。在這種情況下，觸發信號Tr1、Tr2的邏輯值在第一晶粒DI1和第二晶粒DI2分離時會產生變化，因此第3圖中的分離信號SS的邏輯值也會相應變化。此外，在這種情況下，在第一晶粒DI1和第二晶粒DI2分離之後，反相器IV1、IV3的輸出電流變為較小的電流。輸出電流的變化可以由任何機制觸發。例如，輸出電流的變化可以由對應第一晶粒DI1和第二晶粒DI2的分離的控制信號觸發。又例如，可在第一晶粒DI1與第二晶粒DI2分離後，手動觸發輸出電流的變化。In addition, in this example, the trigger signals Tr1 and Tr2 in Fig. 3 are generated by inverters IV2 and IV4 respectively. In this case, the logic values of the trigger signals Tr1 and Tr2 will change when the first die DI1 and the second die DI2 are separated, so the logic value of the separation signal SS in FIG. 3 will also change accordingly. Also, in this case, after the separation of the first die DI1 and the second die DI2 , the output currents of the inverters IV1 , IV3 become smaller currents. Changes in output current can be triggered by any mechanism. For example, the change of the output current may be triggered by separate control signals corresponding to the first die DI1 and the second die DI2 . For another example, after the first die DI1 is separated from the second die DI2 , the change of the output current can be manually triggered.

如上所述，當第一晶粒DI1和第二晶粒DI2不分離時，第一裝置DV1和第三裝置DV3可以同步。這種機制也可以通過第4圖所示的實施例來實現。As described above, when the first die DI1 and the second die DI2 are not separated, the first device DV1 and the third device DV3 may be synchronized. This mechanism can also be implemented by the embodiment shown in FIG. 4 .

更詳細來說，如果第一晶粒DI1和第二晶粒DI2分離，則觸發信號Trl的邏輯值通過反相器IV2的輸入端的小下拉電流IDl固定為1。如此一來，第二晶粒DI2中的第三裝置DV3會依據另一來源的時脈信號產生三角波，而非依據第一晶粒DI1中的第一裝置DV1的時脈信號。同樣的，若第一晶粒DI1與第二晶粒DI2分離，則觸發信號Tr2的邏輯值通過反相器IV4輸入端的小下拉電流ID2固定為1。如此一來，第一晶粒DI1中的第一裝置DV1不會產生時脈信號至第二晶粒DI2。反之，如果第一晶粒DI1和第二晶粒DI2不分離，反相器IV3的輸入為0，則反相器IV3的輸出為1且傳輸到反相器IV4，並覆蓋了小拉降低電流 ID2。如此，反相器IV4輸出的觸發信號Tr2為0，從而第一裝置DV1產生時脈信號給第二裝置DI2進行同步。In more detail, if the first die DI1 and the second die DI2 are separated, the logic value of the trigger signal Tr1 is fixed to 1 by the small pull-down current ID1 at the input terminal of the inverter IV2. In this way, the third device DV3 in the second die DI2 generates a triangular wave according to a clock signal from another source instead of the clock signal of the first device DV1 in the first die DI1 . Similarly, if the first die DI1 is separated from the second die DI2 , the logic value of the trigger signal Tr2 is fixed at 1 by the small pull-down current ID2 at the input terminal of the inverter IV4 . In this way, the first device DV1 in the first die DI1 will not generate a clock signal to the second die DI2 . Conversely, if the first die DI1 and the second die DI2 are not separated, the input of the inverter IV3 is 0, the output of the inverter IV3 is 1 and transmitted to the inverter IV4, and covers the small pull-down current ID2. In this way, the trigger signal Tr2 output by the inverter IV4 is 0, so that the first device DV1 generates a clock signal to the second device DI2 for synchronization.

第5圖繪示了根據本發明一實施例的IC晶粒結構的剖面圖。還請留意，本發明提供的IC晶粒結構不限於包含這樣的剖面圖。如第5圖所示，IC晶粒結構500包含元件CDV1、CDV2、金屬層MR(上述實施例中的金屬線ML、ML1、ML2)、接觸窗(Contact) Cn1、Cn2和隔離層IL1、IL2、IL3 、IL4、IL5 和 IL6。在一實施例中，元件CDV1、CDV2分別代表第一裝置DV1和第三裝置DV3中的元件，例如電晶體。然而，元件CDV1、CDV2可以分別表示整個第一裝置DV1和整個第二裝置DV2。元件CDV1位於第一區Ar1中，部件CDV2位於第二區Ar2中。第二裝置DV2的元件也可位於第一區Ar1中，第四裝置DV4的元件也可位於第二區Ar2中。此外，隔離層IL1、IL2、IL3、IL4、IL5和IL6是絕緣材料。如第5圖所示，接觸窗Cn1、Cn2和隔離層IL3設置在金屬層MR之上。在這種情況下，上述實施例中的金屬線ML、ML1、ML2是由其他材料覆蓋的金屬線，而不是第一晶粒DI1和第二晶粒DI2之間的金屬線。FIG. 5 illustrates a cross-sectional view of an IC die structure according to an embodiment of the present invention. Please also note that the IC die structures provided by the present invention are not limited to include such cross-sectional views. As shown in FIG. 5, IC grain structure 500 includes elements CDV1, CDV2, metal layer MR (metal lines ML, ML1, ML2 in the above-mentioned embodiment), contact windows (Contact) Cn1, Cn2 and isolation layers IL1, IL2 , IL3, IL4, IL5 and IL6. In one embodiment, the components CDV1 and CDV2 respectively represent components in the first device DV1 and the third device DV3 , such as transistors. However, the elements CDV1, CDV2 may represent the entirety of the first device DV1 and the entirety of the second device DV2, respectively. The component CDV1 is located in the first area Ar1, and the component CDV2 is located in the second area Ar2. Components of the second device DV2 may also be located in the first region Ar1 and components of the fourth device DV4 may also be located in the second region Ar2. In addition, the isolation layers IL1, IL2, IL3, IL4, IL5, and IL6 are insulating materials. As shown in FIG. 5, the contact windows Cn1, Cn2 and the isolation layer IL3 are disposed on the metal layer MR. In this case, the metal lines ML, ML1, ML2 in the above embodiments are metal lines covered by other materials, not the metal lines between the first die DI1 and the second die DI2.

根據前述實施例，可以獲得一種IC晶粒形成方法，其用在半導體晶片上形成複數個IC晶粒。第6圖繪示了根據本發明一實施例的IC 晶粒形成方法的流程圖，其包含以下步驟。請參閱第1圖、第5圖和第6圖以更清楚地理解本發明的概念。According to the foregoing embodiments, an IC die forming method for forming a plurality of IC dies on a semiconductor wafer can be obtained. FIG. 6 shows a flowchart of a method for forming IC dies according to an embodiment of the present invention, which includes the following steps. Please refer to Fig. 1, Fig. 5 and Fig. 6 to understand the concept of the present invention more clearly.

步驟601Step 601

在第一區Arl中形成第一晶粒DIl。First crystal grains DI1 are formed in the first region Ar1.

更詳細來說，步驟601包含：在第一區Arl中形成第一裝置DVl；在第一區Ar1中形成第二裝置DV2；以及形成連接到第一裝置DV1和第二裝置DV2的金屬層MR。In more detail, step 601 includes: forming a first device DV1 in the first region Ar1; forming a second device DV2 in the first region Ar1; and forming a metal layer MR connected to the first device DV1 and the second device DV2 .

步驟603Step 603

在第二區Ar2中形成第二晶粒DI2。Second crystal grains DI2 are formed in the second region Ar2.

更詳細而言，步驟603包含：在第二區Ar2中形成第三裝置DV3；在第二區Ar2中形成第四裝置DV4；以及形成連接第三裝置和第四裝置的金屬層MR，其中第一區Ar1和第二區Ar2被切割區Sb隔開。In more detail, step 603 includes: forming a third device DV3 in the second region Ar2; forming a fourth device DV4 in the second region Ar2; and forming a metal layer MR connecting the third device and the fourth device, wherein the first The first area Ar1 and the second area Ar2 are separated by the cutting area Sb.

步驟605Step 605

使金屬層MR具有一區段，此區段連接位於第一區Ar1中金屬層MR的一部份以及位於第二區Ar2中金屬層MR的一部份，以在切割區Sb延伸。The metal layer MR has a section connecting a part of the metal layer MR in the first region Ar1 and a part of the metal layer MR in the second region Ar2 to extend in the cutting region Sb.

第一裝置DVl和第三裝置DV3可用以同步且是D類放大器的元件。如第1圖所示，在一實施例中，第一裝置DV1是時脈產生器，第三裝置DV3是三角波產生器。在此情況下，第三裝置DV3接收第一裝置DV1產生的時脈信號，並根據時脈信號為產生D類放大器使用的三角波。在一實施例中，包含第三裝置DV3的D類放大器會產生對應於第三裝置DV3產生的三角波的PWM信號。The first device DV1 and the third device DV3 can be used for synchronization and are components of a class D amplifier. As shown in FIG. 1 , in one embodiment, the first device DV1 is a clock generator, and the third device DV3 is a triangle wave generator. In this case, the third device DV3 receives the clock signal generated by the first device DV1, and generates a triangular wave used by the class D amplifier according to the clock signal. In one embodiment, the class D amplifier including the third device DV3 generates a PWM signal corresponding to the triangular wave generated by the third device DV3.

此外，第二裝置DV2可用以防止第一晶粒DI1的漏電流，第四裝置DV4可用以防止第二晶粒DI2的漏電流。In addition, the second device DV2 can be used to prevent the leakage current of the first die DI1, and the fourth device DV4 can be used to prevent the leakage current of the second die DI2.

其他詳細步驟已詳細說明於前述實施例，故在此不再贅述。Other detailed steps have been described in the foregoing embodiments in detail, so they will not be repeated here.

根據前述實施例，即使晶粒分離也可以防止晶粒的漏電流。以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 According to the aforementioned embodiments, the leakage current of the die can be prevented even if the die is separated. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100、500:IC晶粒結構 301:及閘 303:反及閘 305、307:緩衝閘 500:IC晶粒結構 CDV1、CDV2:元件 Cn1、Cn2:接觸窗 DI1:第一晶粒 DI2:第二晶粒 DV1:第一裝置 DV2:第二裝置 DV3:第三裝置 DV4:第四裝置 ID1:小下拉電流 ID2:下拉電流 IL1、IL2、IL3、IL4、IL5、IL6、IL7:隔離層 IP1、IP2:上拉電流 IV1、IV2、IV3、IV4:反相器 ML、ML1、ML2:金屬線 MR:金屬層 Sb:切割區 SS:分離信號 SW1,SW2:開關電路 Tr1、Tr2:觸發信號100, 500: IC grain structure 301: and gate 303: Reverse and gate 305, 307: buffer gate 500: IC Grain Structure CDV1, CDV2: components Cn1, Cn2: contact window DI1: First Die DI2: Second Die DV1: first device DV2: second device DV3: third device DV4: The fourth device ID1: small pull-down current ID2: pull-down current IL1, IL2, IL3, IL4, IL5, IL6, IL7: isolation layer IP1, IP2: pull-up current IV1, IV2, IV3, IV4: Inverters ML, ML1, ML2: metal wire MR: metal layer Sb: cutting area SS: separate signal SW1, SW2: switch circuit Tr1, Tr2: trigger signal

第1圖繪示了根據本發明一實施例的IC晶粒結構的方塊圖。第2圖、第3圖以及第4圖繪示了根據本發明不同實施例的，具防漏電流機制的IC晶粒結構的電路圖。第5圖繪示了根據本發明一實施例的IC晶粒結構的剖面圖。第6圖繪示了根據本發明一實施例的IC 晶粒形成方法的流程圖。 FIG. 1 illustrates a block diagram of an IC die structure according to an embodiment of the present invention. FIG. 2 , FIG. 3 and FIG. 4 illustrate circuit diagrams of IC grain structures with anti-leakage current mechanism according to different embodiments of the present invention. FIG. 5 illustrates a cross-sectional view of an IC die structure according to an embodiment of the present invention. FIG. 6 shows a flow chart of an IC die forming method according to an embodiment of the present invention.

100:IC晶粒結構 100: IC grain structure

DI1:第一晶粒 DI1: First Die

DI2:第二晶粒 DI2: Second Die

DV1:第一裝置 DV1: first device

DV2:第二裝置 DV2: second device

DV3:第三裝置 DV3: third device

DV4:第四裝置 DV4: The fourth device

ML:金屬線 ML: metal wire

Sb:切割區 Sb: cutting area

Claims

一種IC晶粒形成方法，用以在一半導體晶圓上形成複數個IC晶粒，包含：在一第一區形成一第一晶粒，包含：在該第一區形成一第一裝置；在該第一區形成一第二裝置；形成連接該第一裝置以及該第二裝置的一金屬層；在一第二區形成一第二晶粒，包含：在該第二區形成一第三裝置；在該第二區形成一第四裝置；形成連接該第三裝置以及該第四裝置的該金屬層，其中該第一區以及該第二區間具有一切割區；使該金屬層具有一區段，該區段連接位於該第一區中該金屬層的一部份以及位於該第二區中該金屬層的一部份，以在該切割區延伸；其中該第一裝置以及該第三裝置用以同步且為一D類型放大器的元件；其中該第二裝置用以防止該第一晶粒的漏電流，而該第四裝置用以防止該第二晶粒的漏電流。 A method for forming IC crystal grains, used to form a plurality of IC crystal grains on a semiconductor wafer, comprising: forming a first grain in a first region, comprising: forming a first device in the first region; forming a second device in the first region; forming a metal layer connecting the first device and the second device; forming a second grain in a second region, comprising: forming a third device in the second region; forming a fourth device in the second region; forming the metal layer connecting the third device and the fourth device, wherein the first region and the second region have a cutting region; causing the metal layer to have a section connecting a portion of the metal layer in the first region and a portion of the metal layer in the second region to extend in the cutting region; Wherein the first device and the third device are used for synchronization and are elements of a D-type amplifier; Wherein the second device is used to prevent the leakage current of the first die, and the fourth device is used to prevent the leakage current of the second die.

如請求項1所述的IC晶粒形成方法，其中該第一裝置為一時脈產生器且該第三裝置為一三角波產生器。The IC die forming method as claimed in claim 1, wherein the first device is a clock generator and the third device is a triangular wave generator.

如請求項1所述的IC晶粒形成方法，更包含：在該第二裝置中形成一開關電路，其中該開關電路可控制該第一晶粒和該第二晶粒導通或不導通。 The method for forming IC grains as described in claim item 1 further includes: A switch circuit is formed in the second device, wherein the switch circuit can control the conduction or non-conduction of the first crystal grain and the second crystal grain.

如請求項3所述的IC晶粒形成方法，其中該開關電路若接收到代表該第一晶粒和該第二晶粒被分離的一分離信號時，則該開關電路關閉。The IC die forming method as claimed in claim 3, wherein if the switch circuit receives a separation signal representing that the first die and the second die are separated, the switch circuit is turned off.

如請求項1所述的IC晶粒形成方法，更包含：在該第二裝置內形成一邏輯電路，其中該邏輯電路可對應一控制信號來輸出一邏輯值。 The method for forming IC grains as described in claim item 1 further includes: A logic circuit is formed in the second device, wherein the logic circuit can output a logic value corresponding to a control signal.

如請求項5所述的IC晶粒形成方法，其中該控制訊號為一分離信號，該邏輯電路在該分離信號代表該第一晶粒和該第二晶粒被分離時輸出一預定邏輯值。The IC die forming method as claimed in claim 5, wherein the control signal is a separation signal, and the logic circuit outputs a predetermined logic value when the separation signal indicates that the first die and the second die are separated.

如請求項1所述的IC晶粒形成方法，更包含：在該第二裝置內形成一反相器，該反相器可選擇性的輸出一第一電流以及小於該第一電流的一第二電流。 The method for forming IC grains as described in claim item 1 further includes: An inverter is formed in the second device, and the inverter can selectively output a first current and a second current smaller than the first current.

如請求項7所述的IC晶粒形成方法，其中當第一晶粒和該第二晶粒未被分離時該反相器輸出該第一電流，且當第一晶粒和該第二晶粒被分離時該反相器輸出該第二電流。The IC grain forming method as claimed in item 7, wherein the inverter outputs the first current when the first grain and the second grain are not separated, and when the first grain and the second grain The inverter outputs the second current when the particles are separated.

如請求項1所述的IC晶粒形成方法，其中形成一第一金屬層的該步驟更包含：在該金屬層上形成複數隔絕層以及接觸窗。 The method for forming IC grains as claimed in item 1, wherein the step of forming a first metal layer further comprises: Multiple isolation layers and contact windows are formed on the metal layer.

如請求項1所述的IC晶粒形成方法，更包含：若該D類放大器被使用在單聲道喇叭，則不分離該第一晶粒和該第二晶粒；若該D類放大器被使用在雙聲道喇叭，則分離該第一晶粒和該第二晶粒。 The method for forming IC grains as described in claim item 1 further includes: If the class D amplifier is used in a mono speaker, the first die and the second die are not separated; If the class D amplifier is used in a two-channel speaker, the first die and the second die are separated.

一種IC 晶粒結構，包含：一第一晶粒，位於一第一區，包含：位於該第一區中的一第一裝置；位於該第一區中的一第二裝置；一金屬層，耦接該第一裝置以及該第二裝置；以及一第二晶粒，位於一第二區，包含：位於該第三區中的一第三裝置；位於該第四區中的一第四裝置；其中該金屬層更連接該第三裝置以及該第四裝置；其中該第一區以及該第二區間具有一切割區；其中該金屬層具有一區段，該區段連接位於該第一區中該金屬層的一部份以及位於該第二區中該金屬層的一部份；其中該第一裝置以及該第三裝置用以同步且為一D類型放大器的元件；其中該第二裝置用以防止該第一晶粒的漏電流，而該第四裝置用以防止該第二晶粒的漏電流。 An IC die structure comprising: A first die, located in a first region, comprising: a first device located in the first zone; a second device located in the first zone; a metal layer coupling the first device and the second device; and A second die, located in a second region, comprising: a third device located in the third zone; a fourth device located in the fourth zone; wherein the metal layer is further connected to the third device and the fourth device; Wherein the first zone and the second zone have a cutting zone; wherein the metal layer has a section connecting a portion of the metal layer in the first region and a portion of the metal layer in the second region; Wherein the first device and the third device are used for synchronization and are components of a D-type amplifier; Wherein the second device is used to prevent the leakage current of the first die, and the fourth device is used to prevent the leakage current of the second die.

如請求項11所述的IC晶粒結構，其中該第一裝置為一時脈產生器且該第三裝置為一三角波產生器。The IC die structure as claimed in claim 11, wherein the first device is a clock generator and the third device is a triangular wave generator.

如請求項11所述的IC晶粒結構，更包含：一開關電路，其中該開關電路可控制該第一晶粒和該第二晶粒導通或不導通。 The IC grain structure as described in claim item 11 further includes: A switch circuit, wherein the switch circuit can control the conduction or non-conduction of the first crystal grain and the second crystal grain.

如請求項13所述的IC晶粒結構，其中該開關電路若接收到代表該第一晶粒和該第二晶粒被分離的一分離信號時，則該開關電路關閉。The IC die structure as claimed in claim 13, wherein if the switch circuit receives a separation signal representing that the first die and the second die are separated, the switch circuit is turned off.

如請求項11所述的IC晶粒結構，更包含：一邏輯電路，位於該第二裝置內，其中該邏輯電路可對應一控制信號來輸出一邏輯值。 The IC grain structure as described in claim item 11 further includes: A logic circuit is located in the second device, wherein the logic circuit can output a logic value corresponding to a control signal.

如請求項15所述的IC晶粒結構，其中該控制訊號為一分離信號，該邏輯電路在該分離信號代表該第一晶粒和該第二晶粒被分離時輸出一預定邏輯值。The IC die structure as claimed in claim 15, wherein the control signal is a separation signal, and the logic circuit outputs a predetermined logic value when the separation signal indicates that the first die and the second die are separated.

如請求項11所述的IC晶粒結構，更包含：一反相器，位於該第二裝置內，該反相器可選擇性的輸出一第一電流以及小於該第一電流的一第二電流。 The IC grain structure as described in claim item 11 further includes: An inverter is located in the second device, and the inverter can selectively output a first current and a second current smaller than the first current.

如請求項17所述的IC晶粒結構，其中當第一晶粒和該第二晶粒未被分離時該反相器輸出該第一電流，且當第一晶粒和該第二晶粒被分離時該反相器輸出該第二電流。The IC grain structure as claimed in claim 17, wherein the inverter outputs the first current when the first grain and the second grain are not separated, and when the first grain and the second grain When separated, the inverter outputs the second current.

如請求項11所述的IC晶粒結構，更包含：複數隔絕層以及接觸窗。 The IC grain structure as described in claim item 11 further includes: Multiple insulating layers and contact windows.

如請求項11所述的IC晶粒結構，其中若該D類放大器被使用在單聲道喇叭，則該第一晶粒和該第二晶粒不分離；其中若該D類放大器被使用在雙聲道喇叭，則該第一晶粒和該第二晶粒分離。 IC grain structure as claimed in claim 11, Wherein if the class D amplifier is used in a monophonic speaker, the first crystal grain and the second crystal grain are not separated; Wherein if the class-D amplifier is used in a two-channel speaker, the first die and the second die are separated.