TWI802321B - Laterally double diffused metal oxide semiconductor device - Google Patents

Laterally double diffused metal oxide semiconductor device Download PDF

Info

Publication number
TWI802321B
TWI802321B TW111109829A TW111109829A TWI802321B TW I802321 B TWI802321 B TW I802321B TW 111109829 A TW111109829 A TW 111109829A TW 111109829 A TW111109829 A TW 111109829A TW I802321 B TWI802321 B TW I802321B
Authority
TW
Taiwan
Prior art keywords
region
semiconductor device
metal oxide
oxide semiconductor
diffused metal
Prior art date
Application number
TW111109829A
Other languages
Chinese (zh)
Other versions
TW202339256A (en
Inventor
陳柏安
Original Assignee
新唐科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 新唐科技股份有限公司 filed Critical 新唐科技股份有限公司
Priority to TW111109829A priority Critical patent/TWI802321B/en
Priority to CN202210490696.5A priority patent/CN116799059A/en
Application granted granted Critical
Publication of TWI802321B publication Critical patent/TWI802321B/en
Publication of TW202339256A publication Critical patent/TW202339256A/en

Links

Images

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Bipolar Transistors (AREA)

Abstract

A laterally double diffused metal oxide semiconductor device includes a substrate with a well region, a body doped region in the well region, a body pick-up region in the body doped region, source regions at two sides of the body pickup region in the body doped region, drain regions, a thick oxide layer between the drain region and the body doped region, finger gates, conductive structures, and a gate insulating layer. The thick oxide layer defines the active region. The finger gates are respectively disposed outside the source regions on the active region, wherein each of the finger gates includes branch parts, and the branch parts are arranged parallel to each other and extend above the thick oxide layer. The conductive structures are between the branches and across the active region and the thick oxide layer, wherein the conductor structures are electrically insulated from the finger gates. The gate insulating layer is disposed between the finger gate and the active region and between the conductor structure and the active region.

Description

橫向雙擴散金氧半導體裝置Lateral double diffused metal oxide semiconductor device

本發明是有關於一種半導體裝置,且特別是有關於一種橫向雙擴散金氧半導體(LDMOS)裝置。The present invention relates to a semiconductor device, and more particularly to a lateral double diffused metal oxide semiconductor (LDMOS) device.

橫向雙擴散金氧半導體裝置是一種廣泛用於開關穩壓器的裝置,因為其具有在特定導通電阻(Ron_sp)和汲極至源極的崩潰電壓(BVdss)之間取得平衡的性能。一般應用於高壓的橫向雙擴散金氧半導體元件在設計上,需要具備相當高的崩潰電壓,同時在操作時又要具有低導通電阻。Lateral double-diffused MOS devices are widely used in switching regulators because of their performance in a balance between specific on-resistance (Ron_sp) and drain-to-source breakdown voltage (BVdss). Generally, the design of the lateral double-diffused metal oxide semiconductor device used in high voltage needs to have a relatively high breakdown voltage, and at the same time, it must have a low on-resistance during operation.

此外,除了直流(DC)特性,橫向雙擴散金氧半導體元件的交流(AC)特性在高頻操作方面也很重要,即其閘汲極電荷(Qgd)。在設計元件時,通常以特定導通電阻(Ron_sp)× 閘汲極電荷(Qgd)的大小為評量指標(Figure of Merit,FOM),此值代表的是元件功率消耗多寡。In addition, besides the direct current (DC) characteristic, the alternating current (AC) characteristic of the lateral double diffused metal oxide semiconductor device is also important in high frequency operation, namely its gate drain charge (Qgd). When designing components, the specific on-resistance (Ron_sp) × gate drain charge (Qgd) is usually used as the evaluation index (Figure of Merit, FOM), and this value represents the power consumption of the component.

因此,目前各界都著眼於如何設計出具有良好AC特性與DC特性的橫向雙擴散金氧半導體元件。Therefore, all circles are currently focusing on how to design a lateral double-diffused metal oxide semiconductor device with good AC characteristics and DC characteristics.

本發明提供一種橫向雙擴散金氧半導體裝置,能根據功率需求達到良好的AC特性與DC特性,亦即本發明可根據功率需求調整FOM且無須調整製程條件。The present invention provides a lateral double-diffused metal oxide semiconductor device, which can achieve good AC characteristics and DC characteristics according to power requirements, that is, the present invention can adjust FOM according to power requirements without adjusting process conditions.

本發明的橫向雙擴散金氧半導體裝置,包括基底、體摻雜區、體拾取區、數個源極區、數個汲極區、厚氧化層、數個指狀閘極、數個導體結構以及閘絕緣層。基底具有井區,體摻雜區設置在所述井區內,且體拾取區設置在所述體摻雜區內。源極區分別設置在體拾取區兩側的體摻雜區內。汲極區分別設置在與體摻雜區相隔一第一距離的井區內。厚氧化層則設置在汲極區與體摻雜區之間,以定義出主動區,且厚氧化層與體摻雜區相隔一第二距離。指狀閘極分別設置在數個源極區的外側的主動區上,其中每個指狀閘極包括數個分支部,分支部平行排列並延伸至厚氧化層上。導體結構則設置在分支部之間並橫跨主動區與厚氧化層,其中所述導體結構與所述指狀閘極電性絕緣。閘絕緣層則位於指狀閘極與主動區之間以及位於導體結構與主動區之間。The lateral double-diffused metal oxide semiconductor device of the present invention includes a substrate, a body doped region, a body pick-up region, several source regions, several drain regions, a thick oxide layer, several finger gates, and several conductor structures and gate insulation. The substrate has a well region, a body-doped region is disposed in the well region, and a body pickup region is disposed in the body-doped region. The source regions are respectively arranged in the body doping regions on both sides of the body pickup region. The drain regions are respectively arranged in the well regions separated from the body doped regions by a first distance. The thick oxide layer is disposed between the drain region and the body-doped region to define the active region, and the thick oxide layer is separated from the body-doped region by a second distance. Finger-shaped gates are respectively arranged on the outer active regions of several source regions, wherein each finger-shaped gate includes several branch parts, and the branch parts are arranged in parallel and extend to the thick oxide layer. The conductor structure is disposed between the branches and straddles the active region and the thick oxide layer, wherein the conductor structure is electrically insulated from the finger gate. The gate insulating layer is located between the gate fingers and the active area and between the conductor structure and the active area.

在本發明的一實施例中,設置在兩個分支部之間的上述導體結構的數目為一個或數個。In an embodiment of the present invention, the number of the above-mentioned conductor structures disposed between the two branch portions is one or several.

在本發明的一實施例中,上述導體結構連接至源極電極。In an embodiment of the present invention, the above conductor structure is connected to the source electrode.

在本發明的一實施例中,上述導體結構是電性浮動的(floating)。In an embodiment of the present invention, the above conductor structure is electrically floating.

在本發明的一實施例中,上述厚氧化層可由分離的數個區塊構成,且區塊之間的井區被定義為降低表面電場(Reduced Surface Field,RESURF)區,所述降低表面電場區平行排列在分支部與導體結構之間,並延伸至汲極區。In an embodiment of the present invention, the above-mentioned thick oxide layer may be composed of several separated blocks, and the well area between the blocks is defined as a Reduced Surface Field (RESURF) region, and the reduced surface electric field The regions are arranged in parallel between the branch portion and the conductor structure and extend to the drain region.

在本發明的一實施例中,上述導體結構與上述指狀閘極是相同材料。In an embodiment of the present invention, the conductor structure and the gate finger are made of the same material.

在本發明的一實施例中,上述導體結構可以是n型多晶矽、p型多晶矽或未摻雜的多晶矽。In an embodiment of the present invention, the above-mentioned conductor structure may be n-type polysilicon, p-type polysilicon or undoped polysilicon.

在本發明的一實施例中,上述源極區與上述汲極區為第一導電型之摻雜區,上述體摻雜區與上述體拾取區為第二導電型之摻雜區。In an embodiment of the present invention, the source region and the drain region are doped regions of the first conductivity type, and the body doped region and the body pickup region are doped regions of the second conductivity type.

在本發明的一實施例中,上述基底為第二導電型之基底,且上述井區為第一導電型之井區。In an embodiment of the present invention, the substrate is a substrate of the second conductivity type, and the well region is a well region of the first conductivity type.

在本發明的一實施例中,上述第一導電型是n型,上述第二導電型是p型。In an embodiment of the present invention, the first conductivity type is n-type, and the second conductivity type is p-type.

基於上述,本發明的橫向雙擴散金氧半導體裝置包括指狀閘極與設置在指狀閘極的分支部之間的導體結構,由於導體結構與指狀閘極電性絕緣,所以指狀閘極能維持裝置的低特定導通電阻(Ron_sp),而導體結構能加速充電時間(charging time),因此可以根據操作電壓的範圍,改變導體結構的數目來得到適宜的FOM值。由於導體結構與指狀閘極可以利用相同的製程形成,所以只需改變佈局設計,無須調整製程條件或增加步驟,即可完成本發明的橫向雙擴散金氧半導體裝置的製作。Based on the above, the lateral double-diffused metal oxide semiconductor device of the present invention includes a finger gate and a conductor structure disposed between the branch portions of the finger gate. Since the conductor structure is electrically insulated from the finger gate, the finger gate It can maintain the low specific on-resistance (Ron_sp) of the device, and the conductor structure can accelerate the charging time (charging time). Therefore, according to the operating voltage range, the number of conductor structures can be changed to obtain a suitable FOM value. Since the conductor structure and finger gates can be formed by the same process, the lateral double-diffused metal oxide semiconductor device of the present invention can be fabricated only by changing the layout design without adjusting process conditions or adding steps.

為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

以下實施例中所附的圖式是為了能更完整地描述本發明的實施例,然而本發明仍可使用許多不同的形式來實施,不限於所記載的實施例。此外,為了清楚起見,各個區域或膜層的相對厚度、距離及位置可能縮小或放大。另外,在圖式中使用相似或相同的元件符號表示相似或相同的部位或特徵的存在。The attached drawings in the following embodiments are for more complete description of the embodiments of the present invention, however, the present invention can still be implemented in many different forms, not limited to the described embodiments. In addition, the relative thicknesses, distances and positions of various regions or layers may be reduced or exaggerated for clarity. In addition, the use of similar or identical reference numerals in the drawings indicates the existence of similar or identical parts or features.

圖1是依照本發明的第一實施例的一種橫向雙擴散金氧半導體裝置的俯視示意圖。圖2是沿圖1的II-II’線段的橫向雙擴散金氧半導體裝置的剖面示意圖。圖3是沿圖1的III-III’線段的橫向雙擴散金氧半導體裝置的剖面示意圖。FIG. 1 is a schematic top view of a lateral double-diffused metal oxide semiconductor device according to a first embodiment of the present invention. Fig. 2 is a schematic cross-sectional view of a lateral double-diffused metal oxide semiconductor device along line II-II' in Fig. 1 . Fig. 3 is a schematic cross-sectional view of the lateral double-diffused metal oxide semiconductor device along line III-III' in Fig. 1 .

請同時參照圖1至圖3,第一實施例的橫向雙擴散金氧半導體裝置包括基底100、體摻雜區102、體拾取(pick-up)區104、數個源極區106、數個汲極區108、厚氧化層110、數個指狀閘極112、數個導體結構114以及閘絕緣層116。基底100具有井區101,井區101如為第一導電型之井區,基底100則是第二導電型之基底。體摻雜區102設置在井區101內,且體拾取區104設置在體摻雜區102內,其中體摻雜區102與體拾取區104為第二導電型之摻雜區,且體拾取區104的摻雜濃度大於體摻雜區102的摻雜濃度。源極區106分別設置在體拾取區104兩側的體摻雜區102內,且源極區106與汲極區108為第一導電型之摻雜區,源極區106會連接至源極電極(未示出)。在一實施例中,上述第一導電型是n型,上述第二導電型是p型;在另一實施例中,上述第一導電型是p型,上述第二導電型是n型。Please refer to FIG. 1 to FIG. 3 at the same time. The lateral double-diffused metal oxide semiconductor device of the first embodiment includes a substrate 100, a body doped region 102, a body pick-up (pick-up) region 104, several source regions 106, several Drain region 108 , thick oxide layer 110 , gate fingers 112 , conductor structures 114 and gate insulating layer 116 . The substrate 100 has a well region 101. If the well region 101 is a well region of the first conductivity type, the substrate 100 is a substrate of the second conductivity type. The body doped region 102 is disposed in the well region 101, and the body pickup region 104 is disposed in the body doped region 102, wherein the body doped region 102 and the body pickup region 104 are doped regions of the second conductivity type, and the body pickup region 104 is disposed in the body doped region 102. The doping concentration of region 104 is greater than the doping concentration of bulk doped region 102 . The source region 106 is respectively disposed in the body doped region 102 on both sides of the body pickup region 104, and the source region 106 and the drain region 108 are doped regions of the first conductivity type, and the source region 106 is connected to the source electrodes (not shown). In one embodiment, the first conductivity type is n-type, and the second conductivity type is p-type; in another embodiment, the first conductivity type is p-type, and the second conductivity type is n-type.

請參照圖1,汲極區108分別設置在與體摻雜區102相隔一第一距離d1的井區101內,汲極區108會連接至汲極電極(未示出)。厚氧化層110則設置在汲極區108與體摻雜區102之間,以定義出主動區AA;也就是說,主動區AA包括體摻雜區102、體拾取區104、源極區106、汲極區108以及部分井區101所在的區域。所述厚氧化層110又稱為飄移氧化層(DOX),代表從汲極區108到閘極112之間的氧化層,其中厚氧化層110例如區域氧化(local oxidation of silicon,LOCOS)結構,亦可為淺溝槽絕緣(shallow trench isolation,STI)結構。在第一實施例中,厚氧化層110與體摻雜區102相隔一第二距離d2,亦即第二距離d2小於第一距離d1,且第一距離d1約等於第二距離d2加上厚氧化層110的寬度的總和,其中厚氧化層110的寬度是指厚氧化層110在橫向方向(例如與體拾取區104的延伸方向垂直的方向)上的大小。指狀閘極112則分別設置在源極區106的外側的主動區AA上,其中每個指狀閘極112包括數個分支部112a,這些分支部112a平行排列並延伸至厚氧化層110上。Referring to FIG. 1 , the drain regions 108 are respectively disposed in the well regions 101 separated by a first distance d1 from the body doped regions 102 , and the drain regions 108 are connected to a drain electrode (not shown). The thick oxide layer 110 is disposed between the drain region 108 and the body-doped region 102 to define the active region AA; that is, the active region AA includes the body-doped region 102, the body pickup region 104, and the source region 106. , the region where the drain region 108 and part of the well region 101 are located. The thick oxide layer 110 is also called a drift oxide layer (DOX), representing the oxide layer between the drain region 108 and the gate electrode 112, wherein the thick oxide layer 110 is, for example, a local oxidation of silicon (LOCOS) structure, It may also be a shallow trench isolation (STI) structure. In the first embodiment, the thick oxide layer 110 is separated from the body doped region 102 by a second distance d2, that is, the second distance d2 is smaller than the first distance d1, and the first distance d1 is approximately equal to the second distance d2 plus the thickness The sum of the widths of the oxide layer 110 , wherein the width of the thick oxide layer 110 refers to the size of the thick oxide layer 110 in a lateral direction (eg, a direction perpendicular to the extending direction of the body pickup region 104 ). The gate fingers 112 are respectively disposed on the active region AA outside the source region 106 , wherein each gate finger 112 includes a plurality of branch portions 112a, and these branch portions 112a are arranged in parallel and extend to the thick oxide layer 110 .

請參照圖3,由於指狀閘極112(的分支部112a)從源極區106的外側延伸至厚氧化層110上,所以指狀閘極112的存在能使整體裝置具有低特定導通電阻(Ron_sp),且分支部112a覆蓋厚氧化層110的範圍可根據需求增加或減少,並不侷限在本實施例的圖式中。Referring to FIG. 3, since the finger gate 112 (the branch portion 112a) extends from the outside of the source region 106 to the thick oxide layer 110, the existence of the finger gate 112 can make the overall device have a low specific on-resistance ( Ron_sp), and the range of the branch portion 112a covering the thick oxide layer 110 can be increased or decreased according to requirements, and is not limited to the drawing of this embodiment.

請繼續參照圖1,導體結構114是設置在兩條分支部112a之間並橫跨主動區AA與厚氧化層110,且導體結構114與指狀閘極112電性絕緣。因此,由圖2的剖面圖來觀察導體結構114,可得到一個類似場板的結構,且在本實施例中,導體結構114連接至源極電極(未示出),但本發明並不限於此;在另一實施例中,導體結構114可為電性浮動的(floating)。若是以縮短充電時間的觀點來看,導體結構114較佳是連接至源極電極,亦即與源極區106等電位。下表1顯示本發明的橫向雙擴散金氧半導體裝置的各種性能的表現。Please continue to refer to FIG. 1 , the conductive structure 114 is disposed between the two branch portions 112 a and straddles the active area AA and the thick oxide layer 110 , and the conductive structure 114 is electrically insulated from the finger gate 112 . Therefore, observing the conductor structure 114 from the cross-sectional view of FIG. 2, a structure similar to a field plate can be obtained, and in this embodiment, the conductor structure 114 is connected to the source electrode (not shown), but the present invention is not limited to Here; in another embodiment, the conductor structure 114 can be electrically floating (floating). From the viewpoint of shortening the charging time, the conductive structure 114 is preferably connected to the source electrode, that is, is at the same potential as the source region 106 . Table 1 below shows various performances of the lateral double-diffused metal oxide semiconductor device of the present invention.

表1    指狀閘極的性能 導體結構的性能 本發明 汲極電流(Ids) 1 ↓↓ 充電時間 1 ↓↓↓ ↓↓ Ron_sp 1 ↑↑ FOM 1 ↓↓ 可調整 表中的「1」代表與一整塊連續閘極的性能一樣;「↑」代表增加,越多箭號則增加程度越大;「↓」代表降低,越多箭號則降低程度越大。 Table 1 Finger gate performance Conductor Structure Properties this invention Drain Current (Ids) 1 ↓↓ charging time 1 ↓↓↓ ↓↓ Ron_sp 1 ↑↑ FOM 1 ↓↓ adjustable "1" in the table means the same performance as a whole continuous gate; "↑" means increase, the more arrows there are, the greater the increase; "↓" means decrease, the more arrows, the greater the decrease.

從表1可得到,導體結構114能大幅降低充電時間,並且可通過改變指狀閘極112(的分支部112a)與導體結構114的數目比例,來調整充電時間與Ron_sp。因此,本發明的橫向雙擴散金氧半導體裝置具有可調整的FOM,詳細將於第二實施例說明。It can be seen from Table 1 that the conductor structure 114 can greatly reduce the charging time, and the charging time and Ron_sp can be adjusted by changing the number ratio of the finger gate 112 (the branch portion 112 a ) to the conductor structure 114 . Therefore, the lateral double-diffused MOS device of the present invention has an adjustable FOM, which will be described in detail in the second embodiment.

另外,圖1顯示導體結構114與分支部112a的同一側邊是對齊的,但本發明並不限於此;在另一實施例中,導體結構114的長度可能更長或更短,例如導體結構114比分支部112a更接近汲極區108;或者,分支部112a比導體結構114更接近汲極區108。In addition, FIG. 1 shows that the conductor structure 114 is aligned with the same side of the branch portion 112a, but the present invention is not limited thereto; in another embodiment, the length of the conductor structure 114 may be longer or shorter, such as the conductor structure 114 is closer to the drain region 108 than the branch portion 112 a ; or, the branch portion 112 a is closer to the drain region 108 than the conductor structure 114 .

若是以簡化製程的觀點來看,導體結構114與指狀閘極112可以是相同材料,採用相同的光罩與蝕刻製程。舉例來說,導體結構114可以是n型多晶矽、p型多晶矽或未摻雜的多晶矽,其中若指狀閘極112是n型多晶矽,則導體結構114也選用n型多晶矽的話,即可與指狀閘極112一起製作。相反地,導體結構114如為p型多晶矽或未摻雜的多晶矽,可能需要另行製作。From the point of view of simplifying the process, the conductor structure 114 and the finger gate 112 can be made of the same material, and the same photomask and etching process can be used. For example, the conductor structure 114 can be n-type polysilicon, p-type polysilicon or undoped polysilicon, wherein if the gate finger 112 is n-type polysilicon, then the conductor structure 114 can also be n-type polysilicon, which can be compatible with the fingers Formed gate 112 together. On the contrary, if the conductor structure 114 is p-type polysilicon or undoped polysilicon, it may need to be fabricated separately.

請同時參照圖1和圖2,閘絕緣層116是位於指狀閘極112與主動區AA之間以及位於導體結構114與主動區AA之間;亦即,閘絕緣層116是位於指狀閘極112與井區101之間,且閘絕緣層116是位於導體結構114與井區101之間。閘絕緣層116例如氧化矽層。Please refer to FIG. 1 and FIG. 2 at the same time, the gate insulating layer 116 is located between the finger gate 112 and the active area AA and between the conductor structure 114 and the active area AA; that is, the gate insulating layer 116 is located between the finger gate Between the electrode 112 and the well region 101 , and the gate insulating layer 116 is located between the conductor structure 114 and the well region 101 . The gate insulating layer 116 is, for example, a silicon oxide layer.

圖4是依照本發明的第二實施例的一種橫向雙擴散金氧半導體裝置的俯視示意圖,其中使用與第一實施例相同的元件符號來表示相同的部分與構件,且相同的部分與構件的相關內容也可參照第一實施例的內容,不再贅述。4 is a schematic top view of a lateral double-diffused metal oxide semiconductor device according to a second embodiment of the present invention, in which the same parts and components are represented by the same element symbols as those in the first embodiment, and the same parts and components are For relevant content, reference may also be made to the content of the first embodiment, and details are not repeated here.

請參照圖4,本實施例與第一實施例的差異在於,設置在兩個分支部112a之間的導體結構400、402的數目不只一個。由於FOM的定義是Ron_sp × 閘汲極電荷(Qgd),其中Qgd與閘極與汲極電容(Cgd)相關,Ron_sp 與指狀閘極112的分支部112a數量相關,所以增加導體結構402的數量能改變Cgd,從而改變Qgd,同時指狀閘極112的分支部112a數量減少會提高Ron_sp,進而達到調整FOM的效果。Referring to FIG. 4 , the difference between this embodiment and the first embodiment is that the number of conductor structures 400 , 402 disposed between the two branch portions 112 a is more than one. Since the definition of FOM is Ron_sp × gate-drain charge (Qgd), where Qgd is related to the gate-drain capacitance (Cgd), and Ron_sp is related to the number of branches 112a of the finger gate 112, so the number of conductor structures 402 is increased Cgd can be changed, thereby changing Qgd, and at the same time, reducing the number of branches 112a of the finger gate 112 will increase Ron_sp, thereby achieving the effect of adjusting FOM.

圖5是依照本發明的第三實施例的一種橫向雙擴散金氧半導體裝置的俯視示意圖,其中使用與第一實施例相同的元件符號來表示相同的部分與構件,且相同的部分與構件的相關內容也可參照第一實施例的內容,不再贅述。5 is a schematic top view of a lateral double-diffused metal oxide semiconductor device according to a third embodiment of the present invention, wherein the same parts and components are represented by the same element symbols as in the first embodiment, and the same parts and components are For relevant content, reference may also be made to the content of the first embodiment, and details are not repeated here.

請參照圖5,本實施例與第一實施例的差異在於,厚氧化層可由分離的數個區塊500構成,且區塊500之間的井區101被定義為降低表面電場(Reduced Surface Field,RESURF)區502。RESURF區502能進一步降低第三實施例的橫向雙擴散金氧半導體裝置的Ron_sp。所述RESURF區502平行排列在分支部112a與導體結構114之間,並且RESURF區502還延伸至汲極區108。每個區塊500的長度可略大於導體結構114的長度,其中前述長度是指區塊500與導體結構114在縱向方向上的大小。Please refer to FIG. 5 , the difference between this embodiment and the first embodiment is that the thick oxide layer can be composed of several separated blocks 500, and the well region 101 between the blocks 500 is defined as a Reduced Surface Field (Reduced Surface Field) , RESURF) District 502. The RESURF region 502 can further reduce Ron_sp of the lateral double-diffused MOS device of the third embodiment. The RESURF region 502 is arranged in parallel between the branch portion 112 a and the conductor structure 114 , and the RESURF region 502 also extends to the drain region 108 . The length of each block 500 may be slightly longer than the length of the conductive structure 114 , wherein the aforementioned length refers to the size of the block 500 and the conductive structure 114 in the longitudinal direction.

綜上所述,在本發明的橫向雙擴散金氧半導體裝置中,指狀閘極能維持裝置的低特定導通電阻,設置在指狀閘極的分支部之間的至少一個導體結構能加速充電時間,因此可以根據操作電壓的範圍,通過導體結構的數目多寡或者通過分支部與導體結構的數目比例來調整FOM。另外,若是導體結構與指狀閘極採用相同的製程置作,則無須調整製程條件或增加步驟,具有節省製造成本與時間的優勢。In summary, in the lateral double-diffused metal oxide semiconductor device of the present invention, the gate finger can maintain the low specific on-resistance of the device, and at least one conductor structure arranged between the branches of the gate finger can accelerate charging Therefore, the FOM can be adjusted according to the operating voltage range, by the number of conductor structures or by the ratio of the number of branches to conductor structures. In addition, if the conductor structure and the gate fingers are fabricated by the same process, there is no need to adjust process conditions or add steps, which has the advantage of saving manufacturing cost and time.

雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

100:基底 101:井區 102:體摻雜區 104:體拾取區 106:源極區 108:汲極區 110:厚氧化層 112:指狀閘極 112a:分支部 114、400、402:導體結構 116:閘絕緣層 500:區塊 502:降低表面電場區 AA:主動區 d1:第一距離 d2:第二距離100: base 101: well area 102: Body doped region 104: volume pickup area 106: source region 108: Drain area 110: thick oxide layer 112: finger gate 112a: branch 114, 400, 402: conductor structure 116: gate insulating layer 500: block 502: Reduced surface electric field area AA: active area d1: first distance d2: the second distance

圖1是依照本發明的第一實施例的一種橫向雙擴散金氧半導體裝置的俯視示意圖。 圖2是沿圖1的II-II’線段的橫向雙擴散金氧半導體裝置的剖面示意圖。 圖3是沿圖1的III-III’線段的橫向雙擴散金氧半導體裝置的剖面示意圖。 圖4是依照本發明的第二實施例的一種橫向雙擴散金氧半導體裝置的俯視示意圖。 圖5是依照本發明的第三實施例的一種橫向雙擴散金氧半導體裝置的俯視示意圖。 FIG. 1 is a schematic top view of a lateral double-diffused metal oxide semiconductor device according to a first embodiment of the present invention. Fig. 2 is a schematic cross-sectional view of a lateral double-diffused metal oxide semiconductor device along line II-II' in Fig. 1 . Fig. 3 is a schematic cross-sectional view of the lateral double-diffused metal oxide semiconductor device along line III-III' in Fig. 1 . FIG. 4 is a schematic top view of a lateral double-diffused metal oxide semiconductor device according to a second embodiment of the present invention. FIG. 5 is a schematic top view of a lateral double-diffused metal oxide semiconductor device according to a third embodiment of the present invention.

101:井區 101: well area

102:體摻雜區 102: Body doped region

104:體拾取區 104: volume pickup area

106:源極區 106: source region

108:汲極區 108: Drain area

110:厚氧化層 110: thick oxide layer

112:指狀閘極 112: finger gate

112a:分支部 112a: branch

114:導體結構 114: Conductor structure

AA:主動區 AA: active area

d1:第一距離 d1: first distance

d2:第二距離 d2: the second distance

Claims (10)

一種橫向雙擴散金氧半導體裝置,包括: 基底,具有井區; 體摻雜區,設置在所述井區內; 體拾取區,設置在所述體摻雜區內; 數個源極區,分別設置在所述體拾取區兩側的所述體摻雜區內; 數個汲極區,分別設置在與所述體摻雜區相隔一第一距離的所述井區內; 厚氧化層,設置在所述數個汲極區與所述體摻雜區之間,以定義出主動區,且所述厚氧化層與所述體摻雜區相隔一第二距離; 數個指狀閘極,分別設置在所述數個源極區的外側的所述主動區上,其中每個所述指狀閘極包括數個分支部,所述數個分支部平行排列並延伸至所述厚氧化層上; 數個導體結構,設置在所述數個分支部之間並橫跨所述主動區與所述厚氧化層,其中所述數個導體結構與所述數個指狀閘極電性絕緣;以及 閘絕緣層,位於所述指狀閘極與所述主動區之間以及位於所述導體結構與所述主動區之間。 A lateral double diffused metal oxide semiconductor device, comprising: a substrate having a well region; a body doped region disposed in the well region; a body pickup region disposed within the body doped region; Several source regions are respectively arranged in the body doped region on both sides of the body pickup region; A plurality of drain regions are respectively arranged in the well region separated from the body-doped region by a first distance; a thick oxide layer disposed between the plurality of drain regions and the body-doped region to define an active region, and the thick oxide layer is separated from the body-doped region by a second distance; A plurality of finger-shaped gates are respectively arranged on the active region outside the plurality of source regions, wherein each of the finger-shaped gates includes several branch parts, and the several branch parts are arranged in parallel and extending onto said thick oxide layer; a plurality of conductor structures disposed between the plurality of branches and across the active region and the thick oxide layer, wherein the plurality of conductor structures are electrically insulated from the plurality of finger gates; and The gate insulating layer is located between the gate fingers and the active area and between the conductor structure and the active area. 如請求項1所述的橫向雙擴散金氧半導體裝置,其中設置在兩個所述分支部之間的所述導體結構的數目為一個或數個。The lateral double-diffused metal oxide semiconductor device according to claim 1, wherein the number of the conductor structures disposed between the two branch portions is one or several. 如請求項1所述的橫向雙擴散金氧半導體裝置,其中所述數個導體結構連接至源極電極。The lateral double diffused metal oxide semiconductor device as claimed in claim 1, wherein the plurality of conductor structures are connected to the source electrode. 如請求項1所述的橫向雙擴散金氧半導體裝置,其中所述數個導體結構是電性浮動的。The lateral double diffused metal oxide semiconductor device as claimed in claim 1, wherein the plurality of conductor structures are electrically floating. 如請求項1所述的橫向雙擴散金氧半導體裝置,其中所述厚氧化層由分離的數個區塊構成,且所述數個區塊之間的所述井區被定義為數個降低表面電場(RESURF)區,所述數個降低表面電場區平行排列在所述分支部與所述導體結構之間,並延伸至所述數個汲極區。The lateral double-diffused metal oxide semiconductor device as claimed in claim 1, wherein the thick oxide layer is composed of several separated blocks, and the well region between the several blocks is defined as several lower surface An electric field (RESURF) region, the plurality of RESURF regions are arranged in parallel between the branch portion and the conductor structure, and extend to the plurality of drain regions. 如請求項1所述的橫向雙擴散金氧半導體裝置,其中所述數個導體結構與所述指狀閘極是相同材料。The lateral double-diffused metal oxide semiconductor device as claimed in claim 1, wherein the plurality of conductor structures and the gate fingers are made of the same material. 如請求項1所述的橫向雙擴散金氧半導體裝置,其中所述數個導體結構為n型、p型或未摻雜的多晶矽。The lateral double-diffused metal oxide semiconductor device as claimed in claim 1, wherein the plurality of conductor structures are n-type, p-type or undoped polysilicon. 如請求項1所述的橫向雙擴散金氧半導體裝置,其中所述源極區與所述汲極區為第一導電型之摻雜區,所述體摻雜區與所述體拾取區為第二導電型之摻雜區。The lateral double-diffused metal oxide semiconductor device according to claim 1, wherein the source region and the drain region are doped regions of the first conductivity type, and the body doped region and the body pick-up region are The doped region of the second conductivity type. 如請求項8所述的橫向雙擴散金氧半導體裝置,其中所述基底為所述第二導電型之基底,且所述井區為所述第一導電型之井區。The lateral double-diffused metal oxide semiconductor device according to claim 8, wherein the substrate is a substrate of the second conductivity type, and the well region is a well region of the first conductivity type. 如請求項8所述的橫向雙擴散金氧半導體裝置,其中所述第一導電型為n型,所述第二導電型為p型。The lateral double-diffused metal oxide semiconductor device according to claim 8, wherein the first conductivity type is n-type, and the second conductivity type is p-type.
TW111109829A 2022-03-17 2022-03-17 Laterally double diffused metal oxide semiconductor device TWI802321B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW111109829A TWI802321B (en) 2022-03-17 2022-03-17 Laterally double diffused metal oxide semiconductor device
CN202210490696.5A CN116799059A (en) 2022-03-17 2022-05-07 Lateral double-diffusion metal oxide semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW111109829A TWI802321B (en) 2022-03-17 2022-03-17 Laterally double diffused metal oxide semiconductor device

Publications (2)

Publication Number Publication Date
TWI802321B true TWI802321B (en) 2023-05-11
TW202339256A TW202339256A (en) 2023-10-01

Family

ID=87424463

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111109829A TWI802321B (en) 2022-03-17 2022-03-17 Laterally double diffused metal oxide semiconductor device

Country Status (2)

Country Link
CN (1) CN116799059A (en)
TW (1) TWI802321B (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI512998B (en) * 2009-10-09 2015-12-11 Semiconductor Energy Lab Semiconductor device and method for manufacturing the same
TWI730041B (en) * 2016-02-12 2021-06-11 日商半導體能源研究所股份有限公司 Semiconductor device and method for manufacturing the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI512998B (en) * 2009-10-09 2015-12-11 Semiconductor Energy Lab Semiconductor device and method for manufacturing the same
TWI730041B (en) * 2016-02-12 2021-06-11 日商半導體能源研究所股份有限公司 Semiconductor device and method for manufacturing the same

Also Published As

Publication number Publication date
TW202339256A (en) 2023-10-01
CN116799059A (en) 2023-09-22

Similar Documents

Publication Publication Date Title
US10068965B1 (en) Lateral high-voltage device
TWI455311B (en) Laterally diffused metal-oxide-semiconductor device
US11791386B2 (en) Semiconductor device
US20090101990A1 (en) Simiconductor integrated circuit device and method of manufacturing the same
TW202005092A (en) Laterally diffused metal oxide semiconductor device and method for manufacturing same
TW201719890A (en) High voltage integrated circuits having improved on-resistance value and improved breakdown voltage
CN107546274B (en) LDMOS device with step-shaped groove
US11894458B2 (en) Lateral double-diffused metal oxide semiconductor field effect transistor
TW201810691A (en) Diode, junction field effect transistor, and semiconductor device
CN108511527A (en) Vertical double-diffusion metal-oxide-semiconductor field effect transistor and preparation method thereof with charge compensation block
US20150115362A1 (en) Lateral Diffused Metal Oxide Semiconductor
TWI802321B (en) Laterally double diffused metal oxide semiconductor device
TWI473267B (en) Mosfet device
TWI398951B (en) Vertical type mosfet device structure with split gates and method for manufacturing the same
US20150115361A1 (en) Lateral Diffused Metal Oxide Semiconductor
TW201351641A (en) High voltage metal-oxide-semiconductor transistor device
TWI578534B (en) High voltage metal-oxide-semiconductor transistor device
CN111384176B (en) Semiconductor device with a semiconductor element having a plurality of electrodes
TWI815280B (en) Transistor structure
TWI724834B (en) Semiconductor device having floating conductive layer
TWI762253B (en) Semiconductor device
US10847610B2 (en) Semiconductor device
TWI497691B (en) Ultra high voltage mos tarnsistor device
KR20240077426A (en) Semiconductor device
CN114464682A (en) Transverse double-diffusion semiconductor field effect transistor with stress dielectric layer and manufacturing method thereof