TWI799029B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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本揭露的一些實施方式包含一種半導體裝置與其製造方法。Some embodiments of the present disclosure include a semiconductor device and a manufacturing method thereof.
在一些記憶體中,記憶體可包含電容、通道層、字元線與位元線。在一些實施方式中,記憶體的電容可為金屬絕緣層金屬(Metal-Insulator-Metal,MIM)電容元件,此種電容包含由兩個高導電性的電極層與夾在中間的絕緣層形成。金屬絕緣層金屬電容在每單位面積下有較高的電容的優勢,因此廣泛應用於記憶體當中。In some memories, the memory may include capacitors, channel layers, word lines and bit lines. In some embodiments, the capacitor of the memory may be a Metal-Insulator-Metal (MIM) capacitor element, which is formed by two highly conductive electrode layers and an insulating layer sandwiched between them. MIL capacitors have the advantage of higher capacitance per unit area, so they are widely used in memory.
本揭露的一些實施方式提供一種製造半導體裝置的方法,包含形成第一介電層。蝕刻第一介電層,以形成溝槽於第一介電層中。形成底部電極層於溝槽的側壁的下部與溝槽的底部。沿著溝槽的側壁的上部與底部電極層,形成絕緣層。沿著絕緣層,形成上部電極層於絕緣層上。形成第一觸點層於溝槽中與上部電極層上,其中氧化物層形成在第一觸點層的頂表面上。執行第一蝕刻製程蝕刻第一觸點層的頂表面上的氧化物層、上部電極層、絕緣層與第一介電層,其中第一蝕刻製程對氧化物層、上部電極層、絕緣層與第一介電層具有實質相同的蝕刻選擇性,且第一蝕刻製程移除氧化物層以暴露第一觸點層。執行第二蝕刻製程蝕刻第一觸點層,以形成位於第一觸點層上的凹槽。以及形成第二觸點層於凹槽中。Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device, including forming a first dielectric layer. Etching the first dielectric layer to form trenches in the first dielectric layer. A bottom electrode layer is formed on the lower portion of the sidewall of the trench and the bottom of the trench. An insulating layer is formed along the upper and bottom electrode layers of the sidewalls of the trench. Along the insulating layer, an upper electrode layer is formed on the insulating layer. A first contact layer is formed in the trench and on the upper electrode layer, wherein an oxide layer is formed on a top surface of the first contact layer. performing a first etching process to etch the oxide layer, the upper electrode layer, the insulating layer, and the first dielectric layer on the top surface of the first contact layer, wherein the first etching process is effective for the oxide layer, the upper electrode layer, the insulating layer, and the first dielectric layer. The first dielectric layer has substantially the same etch selectivity, and the first etch process removes the oxide layer to expose the first contact layer. A second etching process is performed to etch the first contact layer to form a groove on the first contact layer. and forming a second contact layer in the groove.
在一些實施方式中,執行第一蝕刻製程的蝕刻劑包含三氯化硼、氯氣或其組合。In some embodiments, the etchant for performing the first etching process includes boron trichloride, chlorine gas or a combination thereof.
在一些實施方式中,執行第一蝕刻製程的蝕刻劑不包含氟。In some embodiments, the etchant used to perform the first etching process does not contain fluorine.
在一些實施方式中,當執行第一蝕刻製程時,上部電極層、絕緣層與第一介電層被移除的厚度與氧化物層的厚度實質相同。In some embodiments, when performing the first etching process, the upper electrode layer, the insulating layer and the first dielectric layer are removed to a thickness substantially the same as that of the oxide layer.
在一些實施方式中,在完成第一蝕刻製程之後,第一觸點層、上部電極層、絕緣層與第一介電層的複數個上表面實質對齊。In some embodiments, after the first etching process is completed, the first contact layer, the upper electrode layer, the insulating layer are substantially aligned with the plurality of upper surfaces of the first dielectric layer.
在一些實施方式中,在完成第一蝕刻製程之後,絕緣層的上表面與第一介電層的上表面之間具有垂直高度,且垂直高度在3奈米之內。In some embodiments, after the first etching process is completed, there is a vertical height between the upper surface of the insulating layer and the upper surface of the first dielectric layer, and the vertical height is within 3 nm.
在一些實施方式中,形成底部電極層於溝槽的側壁的下部包含沿著溝槽的側壁與溝槽的底部,形成電極層,以及移除電極層的上部,以形成沿著溝槽的側壁的下部的底部電極層。In some embodiments, forming the bottom electrode layer on the lower portion of the sidewall of the trench includes forming the electrode layer along the sidewall of the trench and the bottom of the trench, and removing the upper portion of the electrode layer to form the sidewall along the trench. The lower part of the bottom electrode layer.
在一些實施方式中,本揭露的一些實施方式提供一種半導體裝置,包含第一介電層、電容結構與電晶體。電容結構在第一介電層之中,並包含底部電極層、絕緣層、上部電極層、第一觸點層與第二觸點層。底部電極層覆蓋第一介電層的側壁的下部。絕緣層覆蓋第一介電層的側壁的上部與底部電極層。上部電極層覆蓋絕緣層,絕緣層的上表面與第一介電層的上表面之間具有垂直高度,且垂直高度在3奈米之內。第一觸點層覆蓋上部電極層的下部。第二觸點層覆蓋上部電極層的上部且第二觸點層在第一觸點層上。電晶體位於電容結構上且與電容結構電性連接。In some embodiments, some embodiments of the present disclosure provide a semiconductor device including a first dielectric layer, a capacitor structure and a transistor. The capacitor structure is in the first dielectric layer and includes a bottom electrode layer, an insulating layer, an upper electrode layer, a first contact layer and a second contact layer. The bottom electrode layer covers the lower portion of the sidewall of the first dielectric layer. The insulating layer covers the upper portion of the sidewall of the first dielectric layer and the bottom electrode layer. The upper electrode layer covers the insulating layer, and there is a vertical height between the upper surface of the insulating layer and the upper surface of the first dielectric layer, and the vertical height is within 3 nanometers. The first contact layer covers a lower portion of the upper electrode layer. The second contact layer covers the upper portion of the upper electrode layer and the second contact layer is on the first contact layer. The transistor is located on the capacitor structure and is electrically connected with the capacitor structure.
在一些實施方式中,半導體裝置更包含通道層與字元線。通道層在電容結構上並接觸電容結構。字元線環繞通道層。In some embodiments, the semiconductor device further includes a channel layer and a word line. The channel layer is on and contacts the capacitive structure. The word lines wrap around the channel layer.
在一些實施方式中,半導體裝置更包含位元線,在通道層上並連接通道層。In some embodiments, the semiconductor device further includes a bit line on and connected to the channel layer.
綜上所述,本揭露的一些實施方式的製程可實質將電容結構的上表面平坦化,因此電容結構的上表面為實質平坦的。如此一來,可降低所得的記憶體中因上表面不平坦所帶來的缺陷。To sum up, the manufacturing process of some embodiments of the present disclosure can substantially planarize the upper surface of the capacitor structure, so the upper surface of the capacitor structure is substantially flat. In this way, defects caused by uneven top surfaces in the resulting memory can be reduced.
以下將以圖式揭露本揭露之複數個實施方式,為明確說明起見,許多實務上的細節將在以下敘述中一併說明。然而,應瞭解到,這些實務上的細節不應用以限制本揭露。也就是說,在本揭露部分實施方式中,這些實務上的細節是非必要的。此外,為簡化圖式起見,一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。The following will disclose multiple implementations of the present disclosure with diagrams, and for the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. That is to say, in some embodiments of the present disclosure, these practical details are unnecessary. In addition, for the sake of simplifying the drawings, some well-known structures and components will be shown in a simple and schematic manner in the drawings.
本揭露的一些實施方式是關於製造記憶體中的電容結構的製程。使用本揭露的一些實施方式的製程可改善電容結構的上表面平坦度,使得電容結構的上表面為實質平坦的。如此一來,可降低所得的記憶體中因上表面不平坦所帶來的缺陷。Some embodiments of the present disclosure relate to processes for fabricating capacitor structures in memory. Using the process of some embodiments of the present disclosure can improve the flatness of the upper surface of the capacitor structure, so that the upper surface of the capacitor structure is substantially flat. In this way, defects caused by uneven top surfaces in the resulting memory can be reduced.
第1圖繪示本揭露的一些實施方式的半導體裝置100的橫截面視圖。在一些實施方式中,半導體裝置100為記憶體,例如動態隨機存取記憶體(Dynamic Random Access Memory,DRAM)。半導體裝置100可包含第一介電層101、電容結構CA與電晶體TR。電容結構CA位於第一介電層101中。在一些實施方式中,第一介電層101可包含下方的第一介電子層102與在第一介電子層102上的第二介電子層104。第一介電子層102與第二介電子層104可由不同的介電材料製成。FIG. 1 illustrates a cross-sectional view of a
電容結構CA在第一介電層101之中,使得第一介電層101環繞電容結構CA。電容結構CA可包含底部電極層112、絕緣層114、上部電極層116、第一觸點層122與第二觸點層124。底部電極層112覆蓋並接觸第一介電層101的側壁的下部。絕緣層114覆蓋並接觸第一介電層101的側壁的上部與底部電極層112。上部電極層116覆蓋並接觸絕緣層114,絕緣層114的上表面突出於第一介電層101的上表面並與第一介電層101的上表面之間具有垂直高度H,且垂直高度H在3奈米之內。第一觸點層122覆蓋並接觸上部電極層116的下部。第二觸點層124覆蓋並接觸上部電極層116的上部且位於第一觸點層122上。The capacitive structure CA is in the first
在電容結構CA中,底部電極層112、絕緣層114、上部電極層116可共同視為電容,而第一觸點層122與第二觸點層124作為觸點,用以連接電容與上方的電晶體TR。In the capacitor structure CA, the
電晶體TR包含通道層144、字元線134、閘極介電層142與位元線164,且電晶體TR藉由第一觸點層122與第二觸點層124與電容結構CA電性連接,因此第一觸點層122與第二觸點層124可視為電晶體TR的源/汲極之一。通道層144在電容結構CA上並接觸電容結構CA的第二觸點層124。閘極介電層142位於通道層144的側壁。字元線134環繞通道層144與閘極介電層142,並接觸閘極介電層142。此外,字元線134與閘極介電層142可被第二介電層132與第三介電層136環繞,使得字元線134與閘極介電層142嵌入於第二介電層132與第三介電層136中。位元線164在通道層144的上方。在一些實施方式中,位元線164透過透明導電層162連接至通道層144。並且,位元線164可被第四介電層152環繞,使得位元線164嵌入於第四介電層152中。位元線164可更包含用於連接至外部電路的結構,使得半導體裝置100可進一步連接至外界電路。The transistor TR includes a
第2圖至第12圖繪示根據本揭露的一些實施方式的半導體裝置100的製程的中間階段的橫截面視圖。參考第2圖,形成第一介電層101。在一些實施方式中,雖未在第2圖中繪示,第一介電層101可形成在具有金屬線、通孔件的互連結構上。在一些實施方式中,可先形成第一介電子層102,接著在第一介電子層102上形成第二介電子層104。第一介電子層102與第二介電子層104由不同介電材料形成,因此第一介電子層102與第二介電子層104之間具有明顯的界面。舉例而言,第一介電子層102可以由氧化矽形成,而第二介電子層104可由氮化矽形成。2 to 12 illustrate cross-sectional views of intermediate stages of the manufacturing process of the
參考第3圖,蝕刻第一介電層101,以形成溝槽T於第一介電層101中。可藉由任何適合的方式來形成溝槽T。舉例而言,可使用乾式蝕刻、濕式蝕刻或其組合來在形成溝槽T。在完成溝槽T之後,溝槽T可暴露在下方的互連結構的金屬線或通孔件,使得在後續製程中在溝槽T中形成的電容結構CA的底部電極層112(見第1圖)可進一步連接至下方的互連結構10。Referring to FIG. 3 , the
參考第4圖與第5圖,形成底部電極層112於溝槽T的側壁的下部。具體而言,形成底部電極層112包含沿著溝槽T的側壁與底部,形成電極層111,如第4圖所示。電極層111為完整覆蓋溝槽T的側壁與底部的共形層。接著,移除電極層111的上部,以形成沿著溝槽T的側壁的下部與溝槽T的底部的底部電極層112,如第5圖所示。因此,在一些實施方式中,底部電極層112暴露第一介電層101的側壁的上部。在另一些實施方式中,在沿著溝槽T的側壁與底部形成電極層111之後,可不移除電極層111的上部分。亦即,電極層111可直接作為底部電極層使用,且底部電極層不會暴露溝槽T的側壁。在一些實施方式中,電極層111與底部電極層112由導電材料製成,例如氮化鈦(TiN)。可使用任何適合的沉積製程例如化學氣相沉積、物理氣相沉積、原子層沉積或類似者來形成電極層111,並藉由適合的蝕刻製程,例如非等向性蝕刻,來移除電極層111的上部以形成底部電極層112。Referring to FIG. 4 and FIG. 5 , the
參考第6圖,接著,沿著溝槽T的側壁的上部與底部電極層112,形成絕緣層114。絕緣層114共形地沿著溝槽T的側壁的上部與底部電極層112形成,因此絕緣層114同時接觸第一介電層101的側壁上部與底部電極層112。此外,絕緣層114也完全覆蓋底部電極層112的上表面、側壁與底部。在另一些底部電極層為電極層111的實施方式中,絕緣層114可完全覆蓋住電極層111的側壁與底部,使得電極層111的上表面在第一介電層101與絕緣層114之間暴露出。在一些實施方式中,絕緣層114由高介電常數(例如介電常數高於3.9)材料製成,例如氧化鋯(ZrOx)。可使用任何適合的沉積製程例如化學氣相沉積、物理氣相沉積、原子層沉積或類似者來形成絕緣層114。Referring to FIG. 6 , next, an insulating
參考第7圖,沿著絕緣層114,形成上部電極層116於絕緣層114上。在一些實施方式中,上部電極層116由導電材料製成,例如氮化鈦(TiN)。在一些實施方式中,上部電極層116由與電極層111、底部電極層112相同的材料製成。可使用任何適合的沉積製程例如化學氣相沉積、物理氣相沉積、原子層沉積或類似者來形成上部電極層116。Referring to FIG. 7 , along the insulating
參考第8圖,形成第一觸點層122於溝槽T中與上部電極層116上,其中氧化物層123形成在第一觸點層122的頂表面。具體而言,在形成完上部電極層116之後,可填充適當的觸點材料至溝槽T中,使得觸點材料完全覆蓋住上部電極層116的側壁與底部,以形成第一觸點層122。在一些實施方式中,第一觸點層122可由適當的半導體或導體材料形成,例如多晶矽。在一些實施方式中,由於第一觸點層122的頂表面暴露於空氣中,因此第一觸點層122的頂表面可能會被氧化而形成氧化物層123。亦即,第一觸點層122與氧化物層123由不同材料形成,且氧化物層123包含第一觸點層122的材料的氧化物。Referring to FIG. 8 , the
參考第9圖,執行第一蝕刻製程以蝕刻第一觸點層122的頂表面上的氧化物層123、上部電極層116、絕緣層114與第一介電層101。具體而言,在一些實施方式中,一部分的第一觸點層122將會被移除,來形成第二觸點層(見第11圖)。然而,由於第一觸點層122與第一觸點層122上的氧化物層123由不同材料形成,若要移除一部分的第一觸點層122,需先移除氧化物層123。在一些實施方式中,可在第一蝕刻製程中,同時蝕刻氧化物層123、上部電極層116、絕緣層114與第一介電層101。當執行第一蝕刻製程時,氧化物層123可被完全移除,且上部電極層116、絕緣層114與第一介電層101被移除的厚度與氧化物層123的厚度實質相同。亦即,第一蝕刻製程為一平坦化蝕刻製程,且在第一蝕刻製程完成之後,第一蝕刻製程移除氧化物層123以暴露第一觸點層122。Referring to FIG. 9 , a first etching process is performed to etch the
由於氧化物層123、上部電極層116、絕緣層114與第一介電層101由不同材料形成,因此第一蝕刻製程對氧化物層123、上部電極層116、絕緣層114與第一介電層101具有實質相同的蝕刻選擇性,使得第一蝕刻製程完成後,第一觸點層122、上部電極層116、絕緣層114與第一介電層101的上表面實質對齊。可使用任何適合的蝕刻劑來執行第一蝕刻製程。在一些實施方式中,執行第一蝕刻製程的蝕刻劑包含三氯化硼、氯氣或其組合,且執行第一蝕刻製程的蝕刻劑不包含氟。在一些實施方式中,第一蝕刻製程的偏功率在約40瓦至60瓦之間。在一些實施方式中,第一蝕刻製程的溫度在約攝氏40度至攝氏60度之間。使用所揭露的蝕刻氣體與條件可有效以實質相同的速率蝕刻氧化物層123、上部電極層116、絕緣層114與第一介電層101,使得第一觸點層122、上部電極層116、絕緣層114與第一介電層101的上表面實質對齊。因此,不會因為上部電極層116、絕緣層114與第一介電層101的不平整上表面,而造成後續用於形成第二觸點層124的材料堆積在不平整表面,進而造成短路的問題。在一些實施方式中,「實質對齊」表示上部電極層116的上表面、絕緣層114的上表面與第一介電層101的上表面之間的最大垂直距離在3奈米之內。舉例而言,絕緣層114的上表面與第一介電層101的上表面之間具有垂直高度H,且垂直高度H在3奈米之內。Since the
參考第10圖,在執行第一蝕刻製程之後,接著執行第二蝕刻製程蝕刻第一觸點層122,以形成位於第一觸點層122上的凹槽R。具體而言,第二蝕刻製程為具有高蝕刻選擇性的蝕刻製程,因此在第二蝕刻製程中,僅移除部分第一觸點層122,而不移除上部電極層116、絕緣層114與第一介電層101。如此一來,被移除的第一觸點層122形成凹槽R,且凹槽R暴露出上部電極層116的側壁,亦即凹槽R由第一觸點層122與上部電極層116界定。在一些實施方式中,第二蝕刻製程的蝕刻劑包含六氟化硫、氬氣或其組合。由於上部電極層116、絕緣層114與第一介電層101的表面實質對齊,因此第二觸點層124不會堆積在不平整表面,也可以減少短路的發生。Referring to FIG. 10 , after the first etching process is performed, a second etching process is performed to etch the
參考第11圖,形成第二觸點層124於凹槽R中。所得的第二觸點層124在第一觸點層122上並接觸上部電極層116的側壁。在一些實施方式中,第二觸點層124可由適當的半導體或導體材料形成,例如氧化銦錫(ITO)。Referring to FIG. 11 , the
當完成第11圖的製程之後,也完成半導體製程的電容結構CA的形成。在電容結構CA中,底部電極層112、絕緣層114與上部電極層116可共同視為電容,而第一觸點層122與第二觸點層124作為觸點,用以連接電容與電晶體的通道層。After the process of FIG. 11 is completed, the formation of the capacitive structure CA of the semiconductor process is also completed. In the capacitor structure CA, the
參考第12圖,在完成電容結構CA的形成之後,可進一步在電容結構CA上形成其他元件,例如通道層144。舉例而言,可接著在第一介電層101與電容結構CA上依序形成第二介電層132、字元線134與第三介電層136。第二介電層132與第三介電層136可由任何適合的介電材料形成。舉例而言,第二介電層132與第三介電層136可由氧化矽、氮化矽、氮氧化矽、碳氮氧化矽或類似者形成。在一些實施方式中,第二介電層132與第三介電層136可由相同的介電材料形成。字元線134可由任何適合的金屬形成,例如鎢。接著,可執行適當的蝕刻製程蝕刻第二介電層132、字元線134與第三介電層136,並在第二介電層132、字元線134與第三介電層136中形成暴露電容結構CA的第二觸點層124的開口。接著,可沿著開口的側壁形成閘極介電層142。在形成閘極介電層142之後,在開口中填充適合的半導體材料,例如氧化銦鎵鋅(IGZO),以在開口中形成通道層144。當通道層144由氧化銦鎵鋅(IGZO)形成時,通道層144可具有低漏電的優勢。Referring to FIG. 12 , after the formation of the capacitive structure CA is completed, other elements, such as the
回到第1圖。在形成通道層144之後,可接著在通道層144上形成其他元件,例如位元線164。舉例而言,可在第三介電層136、閘極介電層142與通道層144上形成第四介電層152。第四介電層152可由任何適合的介電材料形成。舉例而言,第四介電層152可由氧化矽、氮化矽、氮氧化矽、碳氮氧化矽或類似者形成。在一些實施方式中,第二介電層132第三介電層136與第四介電層152可由相同的介電材料形成。接著,可執行適當的蝕刻製程蝕刻第四介電層152,並在第四介電層152中形成暴露通道層144的開口。接著,可在開口的底面與通道層144上形成透明導電層162,並在開口中與透明導電層162上填充金屬材料以形成位元線164。在一些實施方式中,位元線164由鎢形成。Go back to Figure 1. After the
綜上所述,使用本揭露的一些實施方式的蝕刻製程可改善電容結構的上表面平坦度。具體而言,當使用本揭露的蝕刻製程移除觸點層上的氧化物層時,由於本揭露的蝕刻製程可在同一個製程中,以實質相同的蝕刻速率、蝕刻選擇性移除環繞氧化層的上部電極層、絕緣層與介電層。如此一來,當移除觸點層上的氧化物層時,在下方的觸點層可與上部電極層、絕緣層、介電層的上表面實質對齊。因此,所形成的電容結構具有實質平坦的上表面,可降低所得的半導體裝置中因上表面不平坦所帶來的缺陷,例如觸點材料堆積在不平坦表面而造成的短路問題。In summary, using the etching process according to some embodiments of the present disclosure can improve the flatness of the upper surface of the capacitor structure. Specifically, when using the etching process of the present disclosure to remove the oxide layer on the contact layer, since the etching process of the present disclosure can remove the surrounding oxide with substantially the same etching rate and etch selectivity in the same process. The upper electrode layer, insulating layer and dielectric layer of the layer. In this way, when the oxide layer on the contact layer is removed, the underlying contact layer can be substantially aligned with the upper surfaces of the upper electrode layer, insulating layer, and dielectric layer. Therefore, the formed capacitor structure has a substantially flat top surface, which can reduce defects caused by uneven top surfaces in the resulting semiconductor device, such as short circuit problems caused by contact material accumulated on the uneven surface.
雖然本揭露已以實施方式揭露如上,然其並非用以限定本揭露,任何熟習此技藝者,在不脫離本揭露之精神和範圍內,當可作各種之更動與潤飾,因此本揭露之保護範圍當視後附之申請專利範圍所界定者為準。Although this disclosure has been disclosed as above in the form of implementation, it is not intended to limit this disclosure. Anyone who is familiar with this technology can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, the protection of this disclosure The scope shall be defined by the appended patent application scope.
100:半導體裝置100: Semiconductor device
101:第一介電層101: the first dielectric layer
102:第一介電子層102: The first dielectric layer
104:第二介電子層104: The second dielectric layer
111:電極層111: electrode layer
112:底部電極層112: Bottom electrode layer
114:絕緣層114: insulation layer
116:上部電極層116: Upper electrode layer
122:第一觸點層122: The first contact layer
123:氧化物層123: oxide layer
124:第二觸點層124: Second contact layer
132:第二介電層132: second dielectric layer
134:字元線134: character line
136:第三介電層136: The third dielectric layer
142:閘極介電層142: gate dielectric layer
144:通道層144: Channel layer
152:第四介電層152: The fourth dielectric layer
162:透明導電層162: transparent conductive layer
164:位元線164: bit line
CA:電容結構CA: capacitor structure
H:垂直高度H: vertical height
R:凹槽R: Groove
T:溝槽T: Groove
TR:電晶體TR: Transistor
第1圖繪示本揭露的一些實施方式的半導體裝置的橫截面視圖。 第2圖至第12圖繪示根據本揭露的一些實施方式的半導體裝置的製程的中間階段的橫截面視圖。 FIG. 1 illustrates a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. 2 to 12 illustrate cross-sectional views of intermediate stages in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure.
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無 Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none
100:半導體裝置 100:Semiconductor device
101:第一介電層 101: the first dielectric layer
102:第一介電子層 102: The first dielectric layer
104:第二介電子層 104: The second dielectric layer
112:底部電極層 112: Bottom electrode layer
114:絕緣層 114: insulation layer
116:上部電極層 116: Upper electrode layer
122:第一觸點層 122: The first contact layer
124:第二觸點層 124: Second contact layer
132:第二介電層 132: second dielectric layer
134:字元線 134: character line
136:第三介電層 136: The third dielectric layer
142:閘極介電層 142: gate dielectric layer
144:通道層 144: Channel layer
152:第四介電層 152: The fourth dielectric layer
162:透明導電層 162: transparent conductive layer
164:位元線 164: bit line
CA:電容結構 CA: capacitor structure
H:垂直高度 H: vertical height
TR:電晶體 TR: Transistor
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TW201438176A (en) * | 2013-02-22 | 2014-10-01 | Micron Technology Inc | Semiconductor devices including WSiX and methods of fabrication |
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TW202139408A (en) * | 2020-04-14 | 2021-10-16 | 南亞科技股份有限公司 | Semiconductor device structure with air gap structure and method for forming the same |
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TW201438176A (en) * | 2013-02-22 | 2014-10-01 | Micron Technology Inc | Semiconductor devices including WSiX and methods of fabrication |
US20210167083A1 (en) * | 2019-11-29 | 2021-06-03 | SK Hynix Inc. | Vertical semiconductor device and method for fabricating the same |
TW202139408A (en) * | 2020-04-14 | 2021-10-16 | 南亞科技股份有限公司 | Semiconductor device structure with air gap structure and method for forming the same |
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