TWI798716B - Method for processing a substrate and the transistor structure formed on the substrate - Google Patents

Method for processing a substrate and the transistor structure formed on the substrate Download PDF

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TWI798716B
TWI798716B TW110120928A TW110120928A TWI798716B TW I798716 B TWI798716 B TW I798716B TW 110120928 A TW110120928 A TW 110120928A TW 110120928 A TW110120928 A TW 110120928A TW I798716 B TWI798716 B TW I798716B
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gallium nitride
buffer layer
substrate
aluminum gallium
layer
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TW202248474A (en
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李文中
林逸庠
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合晶科技股份有限公司
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Abstract

The present invention provides a method for processing a substrate, which includes the following steps. First, a substrate is provided. And, the grinding process is performed, which includes using the grinding unit to grind the edge of the substrate. And, the polishing process is performed, which includes adding a polishing liquid between the polishing unit and the substrate, and using the polishing unit to polish the edge of the substrate. Further, the roughness measurement process is performed, which includes measuring the edge roughness of the substrate. Wherein the processed substrate satisfies a target wafer inclined angle and a target edge roughness, and the target wafer inclined angle is between 11 to 22 degrees, and the edge roughness is between 0.01 and 0.05 nm. Grinding and polishing the edge of the substrate with the method for processing substrate provided by the present invention, the edge roughness of the substrate may be reduced, so that the transistor structure formed on the substrate may has better epitaxy quality.

Description

基板加工方法及形成於基板上之電晶體結構 Substrate processing method and transistor structure formed on the substrate

本發明提供一種基板加工方法及形成於基板上之電晶體結構，且特別涉及一種對基板邊緣進行研磨及拋光的基板加工方法，以及形成於經上述基板加工方法處理之基板上的電晶體結構。 The invention provides a substrate processing method and a transistor structure formed on the substrate, and particularly relates to a substrate processing method for grinding and polishing the edge of the substrate, and a transistor structure formed on the substrate processed by the substrate processing method.

由於氮化鎵材料具有良好的材料特性，例如高崩潰電壓、優秀的壓電效應、高電子飽和速度以及高電流密度，使其非常適合應用於高功率的半導體元件。因此，近幾年來氮化鎵材料在業界受到多方面的關注及應用，例如5G通訊、電動車、雷達衛星通訊及無線電傳輸等。 Due to the good material properties of gallium nitride materials, such as high breakdown voltage, excellent piezoelectric effect, high electron saturation velocity and high current density, it is very suitable for high-power semiconductor components. Therefore, in recent years, gallium nitride materials have received a lot of attention and applications in the industry, such as 5G communications, electric vehicles, radar satellite communications, and radio transmission.

然而，在習知的電晶體元件中，氮化鎵與矽基板之間具有晶格常數及熱膨脹係數差異過大的問題，其會造成矽基板與形成於其上的氮化鎵之間產生過大的晶格失配(lattice mismatch~17%)及熱膨脹係數失配(CTE mismatch ~54%)。在此情況下，氮化鎵在成長中會產生很大的拉應力，並形成高密度的螺旋錯位(threading dislocations)，進而使所形成的晶圓形狀彎曲甚至產生裂紋，最終可能導致氮化鎵電晶體的漏電流增加且性能降低。 However, in conventional transistor devices, there is a problem that the difference in lattice constant and thermal expansion coefficient between GaN and the silicon substrate is too large, which will cause too large a gap between the silicon substrate and the GaN formed thereon. Lattice mismatch (lattice mismatch~17%) and thermal expansion coefficient mismatch (CTE mismatch ~54%). In this case, GaN will generate a lot of tensile stress during the growth and form high-density threading dislocations, which will make the shape of the formed wafer bend or even crack, which may eventually lead to GaN Transistor leakage current increases and performance degrades.

為了解決上述問題，目前的主流技術為在矽基板與氮化鎵之間成長氮化鋁成核層。然而，若是矽基板的邊緣粗糙度過高或者損傷層過深，其在形成磊晶的過程中可能導致金屬回熔的現象，並且在形成磊晶的外延過程中可能會產生裂痕，使得成品無法進行後續的利用。 In order to solve the above problems, the current mainstream technology is to grow an aluminum nitride nucleation layer between the silicon substrate and the gallium nitride. However, if the edge roughness of the silicon substrate is too high or the damage layer is too deep, it may lead to metal melting back during the epitaxy formation process, and cracks may occur during the epitaxy epitaxy process, so that the finished product cannot be processed. for subsequent use.

有鑑於此，本發明人乃累積多年相關領域之研究及實務經驗，提供一種基板加工方法及形成於基板上之電晶體結構，以改善先前技術中所面臨的問題。 In view of this, the inventors have accumulated many years of research and practical experience in related fields to provide a substrate processing method and a transistor structure formed on the substrate to improve the problems faced in the prior art.

為了解決上述先前技術的問題，本發明提供一種基板加工方法及形成於基板上之電晶體結構，其透過在形成磊晶之前對基板邊緣進行研磨及拋光，以調整基板的晶圓傾斜角度並且降低基板的邊緣粗糙度，進而提高後續形成之電晶體結構的晶體品質。 In order to solve the problems of the above-mentioned prior art, the present invention provides a substrate processing method and a transistor structure formed on the substrate, which can adjust the wafer tilt angle of the substrate and reduce the The edge roughness of the substrate improves the crystal quality of the subsequent transistor structure.

基於上述目的，本發明提供一種基板加工方法，其包含以下步驟。首先，提供一基板。進行研磨製程，包含使用研磨單元對基板的邊緣進行研磨，且經研磨製程加工的基板具有一晶圓傾斜角度。進行拋光製程，包含將拋光劑加入至拋光單元與基板之間，並且使用拋光單元對基板的邊緣進行拋光。以及，進行粗糙度量測製程，包含量測基板的邊緣粗糙度。其中，完工的基板的晶圓傾斜角度及邊緣粗糙度分別滿足一目標晶圓傾斜角度及一目標邊緣粗糙度，且目標晶圓傾斜角度介於11至22度，並且目標邊緣粗糙度介於0.01至0.05nm。 Based on the above purpose, the present invention provides a substrate processing method, which includes the following steps. First, a substrate is provided. The grinding process includes grinding the edge of the substrate with a grinding unit, and the substrate processed by the grinding process has a wafer tilt angle. A polishing process is performed, including adding a polishing agent between the polishing unit and the substrate, and using the polishing unit to polish the edge of the substrate. And, a roughness measurement process is performed, including measuring the edge roughness of the substrate. Wherein, the wafer tilt angle and edge roughness of the completed substrate meet a target wafer tilt angle and a target edge roughness respectively, and the target wafer tilt angle is between 11 and 22 degrees, and the target edge roughness is between 0.01 to 0.05nm.

較佳地，目標晶圓傾斜角度為19.5度。 Preferably, the tilt angle of the target wafer is 19.5 degrees.

較佳地，拋光製程的製程時間介於60至360秒。 Preferably, the process time of the polishing process ranges from 60 to 360 seconds.

較佳地，拋光單元為圓/平邊拋光單元或者凹口(Notch)拋光單元。 Preferably, the polishing unit is a round/flat edge polishing unit or a notch (Notch) polishing unit.

較佳地，拋光劑為含有二氧化矽懸浮顆粒的氫氧化鉀溶液。 Preferably, the polishing agent is a potassium hydroxide solution containing silicon dioxide suspended particles.

基於上述目的，本發明進一步提供一種電晶體結構，其包含基板、設置在基板上的氮化鋁成核層、設置在氮化鋁成核層上的第一氮化鋁鎵緩衝層、設置在第一氮化鋁鎵緩衝層上的第二氮化鋁鎵緩衝層、設置在第二氮化鋁鎵緩衝層上的第三氮化鋁鎵緩衝層、設置在第三氮化鋁鎵緩衝層上的高阻層、設置在高阻層上的本質氮化鎵層、設置在本質氮化鎵層上的氮化鋁鎵電子提供層以及設置在氮化鋁鎵電子提供層上的覆蓋層。其中，基板經過上述基板加工方法的處理。 Based on the above purpose, the present invention further provides a transistor structure, which includes a substrate, an aluminum nitride nucleation layer disposed on the substrate, a first aluminum gallium nitride buffer layer disposed on the aluminum nitride nucleation layer, and a first aluminum gallium nitride buffer layer disposed on the The second aluminum gallium nitride buffer layer on the first aluminum gallium nitride buffer layer, the third aluminum gallium nitride buffer layer arranged on the second aluminum gallium nitride buffer layer, the third aluminum gallium nitride buffer layer arranged on the third aluminum gallium nitride buffer layer The high resistance layer on the high resistance layer, the intrinsic gallium nitride layer disposed on the high resistance layer, the aluminum gallium nitride electron supply layer disposed on the intrinsic gallium nitride layer, and the covering layer disposed on the aluminum gallium nitride electron supply layer. Wherein, the substrate is processed by the above-mentioned substrate processing method.

較佳地，基板的邊緣經過研磨製程的加工而具有一目標晶圓傾斜角度，且目標晶圓傾斜角度介於11至22度。 Preferably, the edge of the substrate is processed by a grinding process to have a target wafer tilt angle, and the target wafer tilt angle ranges from 11 to 22 degrees.

較佳地，基板的邊緣經過拋光製程的加工而具有目標邊緣粗糙度，且目標邊緣粗糙度介於0.01至0.05nm。 Preferably, the edge of the substrate is processed by a polishing process to have a target edge roughness, and the target edge roughness ranges from 0.01 to 0.05 nm.

較佳地，第一氮化鋁鎵緩衝層的化學組成為AlaGa1-aN，且0.75≦a<1，第二氮化鋁鎵緩衝層的化學組成為AlbGa1-bN，且0.5≦b≦0.75，以及第三氮化鋁鎵緩衝層的化學組成為AlcGa1-cN，且0.3≦c≦0.5，並且第一氮化鋁鎵緩衝層、第二氮化鋁鎵緩衝層及第三氮化鋁鎵緩衝層為碳摻雜、鐵摻雜、鎂摻雜或鋅摻雜，並且第一氮化鋁鎵緩衝層、第二氮化鋁鎵緩衝層及第三氮化鋁鎵緩衝層的摻雜濃度分別為1E17 atoms/cm3、3E17 atoms/cm3以及5E17 atoms/cm3。 Preferably, the chemical composition of the first aluminum gallium nitride buffer layer is Al a Ga 1-a N, and 0.75≦a<1, and the chemical composition of the second aluminum gallium nitride buffer layer is Al b Ga 1-b N , and 0.5≦b≦0.75, and the chemical composition of the third aluminum gallium nitride buffer layer is Al c Ga 1-c N, and 0.3≦c≦0.5, and the first aluminum gallium nitride buffer layer, the second nitride The AlGaN buffer layer and the third AlGaN buffer layer are carbon-doped, iron-doped, magnesium-doped or zinc-doped, and the first AlGaN buffer layer, the second AlGaN buffer layer and the second AlGaN buffer layer are The doping concentrations of the AlGaN buffer layer are 1E17 atoms/cm 3 , 3E17 atoms/cm 3 and 5E17 atoms/cm 3 respectively.

較佳地，高阻層為氮化鎵，且高阻層為碳摻雜、鐵摻雜、鎂摻雜或鋅摻雜，並且高阻層的摻雜濃度為1E19 atoms/cm3，並且覆蓋層為鎂摻雜的P 型氮化鎵或P型氮化鋁鎵，且其摻雜濃度為1E19 atoms/cm3，並且當覆蓋層為P型氮化鋁鎵時，其化學組成為AlyGa1-yN，且0.1≦y≦0.3。 Preferably, the high-resistance layer is gallium nitride, and the high-resistance layer is carbon-doped, iron-doped, magnesium-doped or zinc-doped, and the doping concentration of the high-resistance layer is 1E19 atoms/cm 3 , and covers The layer is magnesium-doped P-type GaN or P-type AlGaN, and its doping concentration is 1E19 atoms/cm 3 , and when the covering layer is P-type AlGaN, its chemical composition is Al y Ga 1-y N, and 0.1≦y≦0.3.

綜上所述，本發明提供一種基板加工方法及形成於基板上之電晶體結構，其透過在基板上形成磊晶之前對基板邊緣進行研磨及拋光，以調整基板的晶圓傾斜角度並降低基板的邊緣粗糙度，並且將先前製程造成的損傷層移除，進而使得後續形成之電晶體結構具有較佳的晶體品質。 In summary, the present invention provides a substrate processing method and a transistor structure formed on the substrate. By grinding and polishing the edge of the substrate before forming epitaxy on the substrate, the wafer tilt angle of the substrate can be adjusted and the substrate can be lowered. The edge roughness is improved, and the damaged layer caused by the previous process is removed, so that the subsequent transistor structure has better crystal quality.

W:基板 W: Substrate

GU:研磨單元 GU: Grinding unit

GU_A:中心部 GU_A: center part

GU_B:研磨部 GU_B: Grinding Department

PU:拋光單元 PU: polishing unit

PL:拋光劑 PL: polish

θ1,θ2:目標晶圓傾斜角度 θ1, θ2: target wafer tilt angle

100:電晶體結構 100: Transistor structure

20:氮化鋁成核層 20: Aluminum nitride nucleation layer

31:第一氮化鋁鎵緩衝層 31: The first aluminum gallium nitride buffer layer

32:第二氮化鋁鎵緩衝層 32: Second AlGaN buffer layer

33:第三氮化鋁鎵緩衝層 33: The third aluminum gallium nitride buffer layer

40:高阻層 40: High resistance layer

50:本質氮化鎵層 50: Intrinsic gallium nitride layer

60:氮化鋁鎵電子提供層 60: Aluminum gallium nitride electron supply layer

70:覆蓋層 70: Overlay

S101,S102,S103,S104:步驟 S101, S102, S103, S104: steps

為了更清楚地說明本發明的技術方案，下面將對實施例中所需要使用的圖式作簡單地介紹；第1圖為根據本發明實施例的基板加工方法的流程圖；第2圖為根據本發明實施例的基板加工方法中的研磨製程的示意圖；第3圖為根據本發明實施例的研磨單元的局部示意圖；第4圖為根據本發明實施例的基板的晶圓傾斜角度的示意圖；第5圖為根據本發明實施例的基板加工方法中的拋光製程的示意圖；以及第6圖為根據本發明實施例的電晶體結構的示意圖。 In order to illustrate the technical solution of the present invention more clearly, the drawings that need to be used in the embodiments will be briefly introduced below; Fig. 1 is a flow chart of a substrate processing method according to an embodiment of the present invention; Fig. 2 is based on A schematic diagram of the grinding process in the substrate processing method of the embodiment of the present invention; FIG. 3 is a partial schematic diagram of the grinding unit according to the embodiment of the present invention; FIG. 4 is a schematic diagram of the wafer tilt angle of the substrate according to the embodiment of the present invention; FIG. 5 is a schematic diagram of a polishing process in a substrate processing method according to an embodiment of the present invention; and FIG. 6 is a schematic diagram of a transistor structure according to an embodiment of the present invention.

本發明之優點、特徵以及達到之技術方法將參照例示性實施例及所附圖式進行更詳細地說明而更容易理解，且本發明可以不同形式來實現，故不應被理解僅限於此處所陳述的實施例，相反地，對所屬技術領域具有通常知 識者而言，所提供的實施例將使本揭露更加透徹與全面且完整地傳達本發明的範疇，且本發明的保護範圍將僅為所附加的申請專利範圍所定義。 The advantages, features and technical methods achieved by the present invention will be described in more detail with reference to exemplary embodiments and accompanying drawings to make it easier to understand, and the present invention can be implemented in different forms, so it should not be understood as being limited to what is presented here The stated embodiments, on the contrary, have common knowledge in the technical field For those who are knowledgeable, the provided embodiments will make this disclosure more thorough, comprehensive and completely convey the scope of the present invention, and the protection scope of the present invention will only be defined by the appended claims.

應當理解的是，儘管術語「第一」、「第二」等在本發明中可用於描述各種元件、部件、區域、層及/或部分，但是這些元件、部件、區域、層及/或部分不應受這些術語的限制。這些術語僅用於將一個元件、部件、區域、層及/或部分與另一個元件、部件、區域、層及/或部分區分開。因此，下文討論的「第一元件」、「第一部件」、「第一區域」、「第一層」及/或「第一部分」可以被稱為「第二元件」、「第二部件」、「第二區域」、「第二層」及/或「第二部分」，而不悖離本發明的精神和教示。 It should be understood that although the terms "first", "second" and the like may be used in the present invention to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections Should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer and/or section from another element, component, region, layer and/or section. Accordingly, "first element", "first component", "first region", "first layer" and/or "first portion" discussed below may be referred to as "second element", "second component" , "second region", "second layer" and/or "second part", without departing from the spirit and teachings of the present invention.

另外，術語「包括」及/或「包含」指所述特徵、區域、整體、步驟、操作、元件及/或部件的存在，但不排除一個或多個其他特徵、區域、整體、步驟、操作、元件、部件及/或其組合的存在或添加。 In addition, the terms "comprising" and/or "comprising" refer to the presence of stated features, regions, integers, steps, operations, elements and/or parts, but do not exclude one or more other features, regions, integers, steps, operations , the presence or addition of elements, parts and/or combinations thereof.

除非另有定義，本發明所使用的所有術語(包括技術和科學術語)具有與本發明所屬技術領域的具有通常知識者通常理解的相同含義。將進一步理解的是，諸如在通常使用的字典中定義的那些術語應當被解釋為具有與它們在相關技術和本發明的上下文中的含義一致的定義，並且將不被解釋為理想化或過度正式的意義，除非本文中明確地這樣定義。 Unless otherwise defined, all terms (including technical and scientific terms) used in this invention have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have definitions consistent with their meanings in the context of the relevant art and the present invention, and will not be interpreted as idealistic or overly formal unless otherwise expressly defined herein.

在下文中將結合附圖對本發明進行進一步的詳細說明。這些附圖均為簡化的示意圖，僅以示意方式說明本發明的基本結構，並且為了清楚起見而誇大了元件的比例及尺寸，因此這些附圖並不作為對本發明的限定。 The present invention will be further described in detail below in conjunction with the accompanying drawings. These drawings are all simplified schematic diagrams, which only schematically illustrate the basic structure of the present invention, and exaggerate the proportion and size of components for the sake of clarity, so these drawings are not intended to limit the present invention.

請一併參閱第1圖至第5圖所示，第1圖為根據本發明實施例的基板加工方法的流程圖；第2圖為根據本發明實施例的基板加工方法中的研磨製程 的示意圖；第3圖為根據本發明實施例的研磨單元的局部示意圖；第4圖為根據本發明實施例的基板的晶圓傾斜角度的示意圖；以及，第5圖為根據本發明實施例的基板加工方法中的拋光製程的示意圖。 Please also refer to Figures 1 to 5. Figure 1 is a flowchart of a substrate processing method according to an embodiment of the present invention; Figure 2 is a polishing process in a substrate processing method according to an embodiment of the present invention. Fig. 3 is a partial schematic diagram of a grinding unit according to an embodiment of the present invention; Fig. 4 is a schematic diagram of a wafer tilt angle of a substrate according to an embodiment of the present invention; and Fig. 5 is a schematic diagram according to an embodiment of the present invention A schematic diagram of a polishing process in a substrate processing method.

如第1圖所繪示，本發明提供一種基板加工方法，其包含以下步驟。首先，步驟S101，提供一基板W。步驟S102，進行研磨製程，包含使用研磨單元GU對基板W的邊緣進行研磨。步驟S103，包含將拋光劑PL加入至拋光單元PU與基板W之間，並且使用拋光單元PU對基板W的邊緣進行拋光。以及，步驟S104，進行粗糙度量測製程，包含量測基板W的邊緣粗糙度。 As shown in FIG. 1 , the present invention provides a substrate processing method, which includes the following steps. First, in step S101 , a substrate W is provided. Step S102 , performing a grinding process, including grinding the edge of the substrate W by using the grinding unit GU. Step S103 includes adding a polishing agent PL between the polishing unit PU and the substrate W, and using the polishing unit PU to polish the edge of the substrate W. And, step S104 , performing a roughness measurement process, including measuring the edge roughness of the substrate W.

具體來說，在步驟S101中，首先提供一矽晶圓作為待處理的基板W，但本發明不限定於此。在其他實施例中，可以使用諸如碳化矽晶圓或藍寶石晶圓的晶圓作為待處理的基板。 Specifically, in step S101 , firstly, a silicon wafer is provided as the substrate W to be processed, but the present invention is not limited thereto. In other embodiments, wafers such as silicon carbide wafers or sapphire wafers may be used as substrates to be processed.

在步驟S102中，使用研磨單元GU對基板W的邊緣進行研磨，以調整基板W的晶圓傾斜角度。具體來說，如第2圖所繪示，在本實施例中使用去角輪作為研磨單元GU，但本發明不限定於此。在其他實施例中，可以使用其他種類的研磨裝置進行研磨製程，以達到相同的調整基板的晶圓傾斜角度之目的。 In step S102 , the edge of the substrate W is ground by using the grinding unit GU to adjust the wafer tilt angle of the substrate W. Specifically, as shown in FIG. 2 , in this embodiment, a chamfering wheel is used as the grinding unit GU, but the present invention is not limited thereto. In other embodiments, other types of grinding devices can be used to perform the grinding process, so as to achieve the same purpose of adjusting the wafer tilt angle of the substrate.

進一步地，如第3圖所繪示，研磨單元GU包含中心部GU_A及研磨部GU_B，中心部GU_A用以連接旋轉軸及旋轉馬達(圖中未繪示出)，以帶動環繞中心部GU_A設置的研磨部GU_B旋轉，進而透過旋轉中的研磨部GU_B接觸基板W的邊緣進行研磨，以在研磨的過程中調整基板W的晶圓傾斜角度。 Further, as shown in FIG. 3, the grinding unit GU includes a central part GU_A and a grinding part GU_B, and the central part GU_A is used to connect a rotating shaft and a rotating motor (not shown in the figure), so as to drive and set around the central part GU_A The grinding unit GU_B rotates, and then grinds the edge of the substrate W through the rotating grinding unit GU_B, so as to adjust the wafer tilt angle of the substrate W during the grinding process.

並且，如第4圖所繪示，經過研磨製程加工的基板W的邊緣滿足一目標晶圓傾斜角度θ1、θ2，此目標晶圓傾斜角度θ1、θ2介於11至22度的範圍內，且較佳為19.5度。 Moreover, as shown in FIG. 4, the edge of the substrate W processed by the grinding process satisfies a target wafer tilt angle θ1, θ2, and the target wafer tilt angle θ1, θ2 is in the range of 11 to 22 degrees, and Preferably it is 19.5 degrees.

此外，基板W的上半部具有上目標晶圓傾斜角度θ1且下半部具有下目標晶圓傾斜角度θ2，且在本實施例中，上目標晶圓傾斜角度θ1及下目標晶圓傾斜角度θ2相同，其兩者皆同樣介於11至22度的範圍內，且較佳為19.5度，但本發明不限定於此。在其他實施例中，上目標晶圓傾斜角度θ1及下目標晶圓傾斜角度θ2可以具有不同的大小。 In addition, the upper half of the substrate W has an upper target wafer tilt angle θ1 and the lower half has a lower target wafer tilt angle θ2, and in this embodiment, the upper target wafer tilt angle θ1 and the lower target wafer tilt angle θ2 is the same, both of which are also in the range of 11 to 22 degrees, and preferably 19.5 degrees, but the present invention is not limited thereto. In other embodiments, the upper target wafer tilt angle θ1 and the lower target wafer tilt angle θ2 may have different sizes.

進一步地，在步驟S103中，如第5圖所繪示，首先將拋光劑PL加入至拋光單元PU與基板W之間，並且一邊使拋光單元PU旋轉，一邊將基板W的邊緣接觸拋光單元PU的圓邊部分以進行拋光，並且拋光製程的時間介於60至360秒的範圍內。此外，在本實施例中，使用圓/平邊拋光單元作為拋光單元PU，並使用其圓邊部分以進行拋光製程，但本發明不限定於此。在其他實施例中，可以使用圓/平邊拋光單元的平邊部分或者凹口(Notch)拋光單元等其他種類的拋光裝置進行拋光製程，以達到相同的降低基板的邊緣粗糙度之目的。 Further, in step S103, as shown in FIG. 5, the polishing agent PL is firstly added between the polishing unit PU and the substrate W, and while the polishing unit PU is rotated, the edge of the substrate W is brought into contact with the polishing unit PU. The rounded edge portion of the ring is polished, and the time of the polishing process is in the range of 60 to 360 seconds. In addition, in this embodiment, a round/flat edge polishing unit is used as the polishing unit PU, and its round edge portion is used to perform the polishing process, but the invention is not limited thereto. In other embodiments, other types of polishing devices such as the flat portion of the round/flat polishing unit or the notch polishing unit can be used to perform the polishing process to achieve the same purpose of reducing the edge roughness of the substrate.

值得一提的是，在本實施例中，研磨製程中所使用的拋光劑PL為含有二氧化矽懸浮顆粒的氫氧化鉀溶液，但本發明不限定於此。在其他實施例中，使用者可以根據需求選擇任意合適種類的拋光劑。藉由上述配置，使得拋光劑PL、拋光單元PU與基板W之間發生機械摩擦作用時，含有二氧化矽懸浮顆粒的氫氧化鉀拋光劑PL可以進一步與基板W發生化學作用，以進一步降低基板W的邊緣粗糙度。 It is worth mentioning that, in this embodiment, the polishing agent PL used in the polishing process is a potassium hydroxide solution containing silicon dioxide suspended particles, but the invention is not limited thereto. In other embodiments, the user can select any suitable type of polishing agent according to needs. With the above configuration, when mechanical friction occurs between the polishing agent PL, the polishing unit PU, and the substrate W, the potassium hydroxide polishing agent PL containing silicon dioxide suspended particles can further chemically interact with the substrate W to further reduce the substrate W. W's edge roughness.

此外，在進行研磨製程前先使用原子力顯微鏡(Atomic Force Microscopic，AFM)以量測的基板W的邊緣粗糙度，其數值介於1.07至1.15nm，在本發明不限定於此。在其他實施例中，可以使用諸如白光干涉儀、X光繞射分析儀及傅立葉轉換紅外線光譜儀(Fourier Transform Infrared Spectroscopy，FTIR) 的裝置以量測基板的邊緣粗糙度。如果在邊緣粗糙度較高的基板上形成磊晶，所形成的磊晶品質可能會較低，並且在磊晶外延的過程中可能會產生裂縫，而導致所形成的成品無法進行後續的利用。 In addition, the edge roughness of the substrate W measured by an Atomic Force Microscopic (AFM) before the polishing process is 1.07 to 1.15 nm, and the present invention is not limited thereto. In other embodiments, such as white light interferometer, X-ray diffraction analyzer and Fourier Transform Infrared Spectroscopy (Fourier Transform Infrared Spectroscopy, FTIR) can be used The device to measure the edge roughness of the substrate. If epitaxy is formed on a substrate with high edge roughness, the quality of the epitaxy formed may be low, and cracks may be generated during the epitaxy epitaxy process, so that the formed finished product cannot be used subsequently.

因此，在執行步驟S102及步驟S103的研磨製程及拋光製程後，接續執行步驟S104的粗糙度量測製程，以確認經處理的基板W的邊緣粗糙度是否合乎標準。在步驟S104中，使用原子力顯微鏡再次量測基板W的邊緣粗糙度，以確認基板W的邊緣粗糙度是否在容許範圍內，其中完工的基板W的邊緣粗糙度的容許範圍介於0.01至0.05nm。由此可知，研磨製程可以有效地降低基板W的邊緣粗糙度，以使後續形成於基板W上的磊晶層具有較佳的晶體品質，並且可以減少磊晶外延時裂縫產生的可能性。此外，在本實施例中使用原子力顯微鏡以量測基板W的邊緣粗糙度，但本發明不限定於此。在其他實施例中，可以使用諸如白光干涉儀、X光繞射分析儀及傅立葉轉換紅外線光譜儀(Fourier Transform Infrared Spectroscopy，FTIR)的裝置以量測基板的邊緣粗糙度。 Therefore, after performing the grinding process and the polishing process in step S102 and step S103 , the roughness measuring process in step S104 is performed continuously to confirm whether the edge roughness of the processed substrate W meets the standard. In step S104, the atomic force microscope is used to measure the edge roughness of the substrate W again to confirm whether the edge roughness of the substrate W is within the allowable range, wherein the allowable range of the edge roughness of the finished substrate W is between 0.01 and 0.05 nm . It can be seen that the grinding process can effectively reduce the edge roughness of the substrate W, so that the epitaxial layer formed on the substrate W subsequently has better crystal quality, and can reduce the possibility of cracks during epitaxy. In addition, in this embodiment, an atomic force microscope is used to measure the edge roughness of the substrate W, but the present invention is not limited thereto. In other embodiments, devices such as white light interferometer, X-ray diffraction analyzer and Fourier Transform Infrared Spectroscopy (FTIR) can be used to measure the edge roughness of the substrate.

請參閱第6圖所示，第6圖為根據本發明實施例的電晶體結構的示意圖。 Please refer to FIG. 6, which is a schematic diagram of a transistor structure according to an embodiment of the present invention.

如第6圖所繪示，本發明進一步提供一種電晶體結構100，其包含基板W、設置在基板W上的氮化鋁成核層20、設置在氮化鋁成核層20上的第一氮化鋁鎵緩衝層31、設置在第一氮化鋁鎵緩衝層31上的第二氮化鋁鎵緩衝層32、設置在第二氮化鋁鎵緩衝層32上的第三氮化鋁鎵緩衝層33、設置在第三氮化鋁鎵緩衝層33上的高阻層40、設置在高阻層40上的本質氮化鎵層50、設置在本質氮化鎵層50上的氮化鋁鎵電子提供層60以及設置在氮化鋁鎵電子提供層60上的覆蓋層70。其中，在本實施例中所述之基板W為經過上述基板加工方法的處理 的矽晶圓，但本發明不限定於此。在其他其實施例中，可以使用諸如碳化矽晶圓或藍寶石晶圓的晶圓作為基板。 As shown in FIG. 6, the present invention further provides a transistor structure 100, which includes a substrate W, an aluminum nitride nucleation layer 20 disposed on the substrate W, and a first aluminum nitride nucleation layer 20 disposed on the aluminum nitride nucleation layer 20. AlGaN buffer layer 31, second AlGaN buffer layer 32 disposed on the first AlGaN buffer layer 31, third AlGaN disposed on the second AlGaN buffer layer 32 The buffer layer 33, the high resistance layer 40 disposed on the third AlGaN buffer layer 33, the intrinsic gallium nitride layer 50 disposed on the high resistance layer 40, the aluminum nitride disposed on the intrinsic gallium nitride layer 50 The gallium electron supply layer 60 and the capping layer 70 disposed on the aluminum gallium nitride electron supply layer 60 . Wherein, the substrate W described in this embodiment is processed by the above-mentioned substrate processing method silicon wafer, but the present invention is not limited thereto. In other embodiments, wafers such as silicon carbide wafers or sapphire wafers may be used as substrates.

值得一提的是，在本實施例中所使用的基板W經過上述基板加工方法的處理而具有一目標晶圓傾斜角度及一目標邊緣粗糙度，且此目標晶圓傾斜角度介於11至22度，並且目標邊緣粗糙度介於0.01至0.05nm。 It is worth mentioning that the substrate W used in this embodiment has a target wafer tilt angle and a target edge roughness after being processed by the above-mentioned substrate processing method, and the target wafer tilt angle is between 11 to 22 degree, and the target edge roughness is between 0.01 and 0.05nm.

在本實施例中，氮化鋁成核層20使用有機金屬化學氣相沉積法(Metal-organic Chemical Vapor Deposition，MOCVD)以形成於基板W上，其成長溫度介於900~1000℃，並且氮化鋁成核層20的厚度介於50至500nm。 In this embodiment, the aluminum nitride nucleation layer 20 is formed on the substrate W by Metal-organic Chemical Vapor Deposition (MOCVD), and its growth temperature is between 900-1000° C. The thickness of the Al2O nucleation layer 20 ranges from 50 to 500 nm.

第一氮化鋁鎵緩衝層31、第二氮化鋁鎵緩衝層32以及第三氮化鋁鎵緩衝層33同樣使用有機金屬化學氣相沉積法以依序形成於氮化鋁成核層20上，其成長溫度介於1000~1200℃。其中，第一氮化鋁鎵緩衝層31的化學組成為AlaGa1-aN，且0.75≦a<1，第二氮化鋁鎵緩衝層32的化學組成為AlbGa1-bN，且0.5≦b≦0.75，以及第三氮化鋁鎵緩衝層33的化學組成為AlcGa1-cN，且0.3≦c≦0.5，並且第一氮化鋁鎵緩衝層31、第二氮化鋁鎵緩衝層32以及第三氮化鋁鎵緩衝層33的厚度皆介於50至1000nm。 The first AlGaN buffer layer 31, the second AlGaN buffer layer 32 and the third AlGaN buffer layer 33 are also sequentially formed on the AlGaN nucleation layer 20 by metalorganic chemical vapor deposition. On the other hand, its growth temperature is between 1000~1200℃. Wherein, the chemical composition of the first aluminum gallium nitride buffer layer 31 is Al a Ga 1-a N, and 0.75≦a<1, and the chemical composition of the second aluminum gallium nitride buffer layer 32 is Al b Ga 1-b N , and 0.5≦b≦0.75, and the chemical composition of the third aluminum gallium nitride buffer layer 33 is Al c Ga 1-c N, and 0.3≦c≦0.5, and the first aluminum gallium nitride buffer layer 31, the second The thicknesses of the AlGaN buffer layer 32 and the third AlGaN buffer layer 33 are both 50-1000 nm.

進一步地，第一氮化鋁鎵緩衝層31、第二氮化鋁鎵緩衝層32及第三氮化鋁鎵緩衝層33可以為碳摻雜、鐵摻雜、鎂摻雜或鋅摻雜，並且第一氮化鋁鎵緩衝層31、第二氮化鋁鎵緩衝層32及第三氮化鋁鎵緩衝層33的摻雜濃度分別為1E17 atoms/cm3、3E17 atoms/cm3以及5E17 atoms/cm3。 Further, the first AlGaN buffer layer 31, the second AlGaN buffer layer 32 and the third AlGaN buffer layer 33 may be carbon-doped, iron-doped, magnesium-doped or zinc-doped, And the doping concentrations of the first AlGaN buffer layer 31, the second AlGaN buffer layer 32 and the third AlGaN buffer layer 33 are 1E17 atoms/cm 3 , 3E17 atoms/cm 3 and 5E17 atoms /cm 3 .

高阻層40同樣使用有機金屬化學氣相沉積法以形成於第三氮化鋁鎵緩衝層33上，其成長溫度介於1000~1200℃。其中，高阻層40為氮化鎵，其 厚度介於0.5~5um，且高阻層40可以為碳摻雜、鐵摻雜、鎂摻雜或鋅摻雜，並且高阻層40的摻雜濃度為1E19 atoms/cm3。 The high resistance layer 40 is also formed on the third AlGaN buffer layer 33 by metalorganic chemical vapor deposition at a growth temperature of 1000-1200°C. Wherein, the high-resistance layer 40 is gallium nitride, and its thickness is between 0.5-5um, and the high-resistance layer 40 can be carbon-doped, iron-doped, magnesium-doped or zinc-doped, and the doping of the high-resistance layer 40 The concentration is 1E19 atoms/cm 3 .

成長本質氮化鎵層50同樣使用有機金屬化學氣相沉積法以形成於高阻層40上，其成長溫度介於1000~1200℃，且本質氮化鎵層50的厚度介於0.2~1um。 The intrinsic GaN layer 50 is also grown on the high resistance layer 40 by metalorganic chemical vapor deposition, the growth temperature is 1000-1200°C, and the thickness of the intrinsic GaN layer 50 is 0.2-1um.

並且，氮化鋁鎵電子提供層60同樣使用有機金屬化學氣相沉積法以形成於本質氮化鎵層50上，其成長溫度介於1000~1200℃。其中，氮化鋁鎵電子提供層60的化學組成為AlxGa1-xN，且0.1<x<0.3，並且其厚度介於10至40nm。 Moreover, the AlGaN electron supply layer 60 is also formed on the intrinsic GaN layer 50 by metalorganic chemical vapor deposition, and its growth temperature is between 1000-1200°C. Wherein, the chemical composition of the AlGaN electron supply layer 60 is AlxGa1 -xN , and 0.1<x<0.3, and its thickness is between 10 to 40 nm.

最後，覆蓋層70同樣使用有機金屬化學氣相沉積法以形成於氮化鋁鎵電子提供層60上，其成長溫度介於1000~1200℃。其中，覆蓋層70可以為鎂摻雜的P型氮化鎵或P型氮化鋁鎵，且其摻雜濃度為1E19 atoms/cm3。並且，當覆蓋層70為P型氮化鋁鎵時，其化學組成為AlyGa1-yN，且0.1≦y≦0.3。此外，當覆蓋層70為P型氮化鎵時，其厚度介於10至20nm，而當覆蓋層為P型氮化鋁鎵時，其厚度則介於10至150nm。 Finally, the capping layer 70 is also formed on the AlGaN electron supply layer 60 by metalorganic chemical vapor deposition, and its growth temperature is between 1000-1200°C. Wherein, the capping layer 70 may be magnesium-doped P-type GaN or P-type AlGaN, and its doping concentration is 1E19 atoms/cm 3 . Moreover, when the capping layer 70 is P-type AlGaN, its chemical composition is AlyGa1 -yN , and 0.1≦y≦0.3. In addition, when the capping layer 70 is P-type GaN, its thickness is between 10-20 nm, and when the capping layer is P-type AlGaN, its thickness is between 10-150 nm.

進一步地，雖然在上述說明中，皆使用有機金屬化學氣相沉積法以成長本發明之電晶體結構的各層，但在其他實施例中，可以使用其他種類的化學氣相沉積製程或者物理氣相沉積製程以達到相同的效果，例如使用電漿增強化學氣相沉積(PECVD，Plasma Enhanced Chemical Vapor Deposition)、混合物理化學氣相沉積(HPCVD，Hybrid Physical Chemical Vapor Deposition)、真空蒸鍍沉積(Vacuum Evaporation Deposition)、及濺鍍沉積(Sputter Deposition)等，本發明不限定於此。 Further, although in the above description, metalorganic chemical vapor deposition is used to grow each layer of the transistor structure of the present invention, but in other embodiments, other types of chemical vapor deposition process or physical vapor deposition can be used. Deposition process to achieve the same effect, such as using plasma enhanced chemical vapor deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition), mixture physical chemical vapor deposition (HPCVD, Hybrid Physical Chemical Vapor Deposition), vacuum evaporation deposition (Vacuum Evaporation Deposition), and sputter deposition (Sputter Deposition), etc., the present invention is not limited thereto.

綜上所述，本發明提供一種基板加工方法及形成於基板上之電晶體結構。本發明之基板加工方法在形成電晶體結構於基板上之前，先透過研磨製程對基板邊緣進行研磨拋光，以降低基板的邊緣粗糙度，並將先前製程造成的損傷層移除。並且，在進行研磨製程之後接續執行粗糙度量測製程，以透過原子力顯微鏡確認基板的邊緣粗糙度是否在預定目標範圍內。藉由本發明提供之基板加工方法，可以確保後續形成於基板上之電晶體結構具有較佳的晶體品質。 To sum up, the present invention provides a substrate processing method and a transistor structure formed on the substrate. In the substrate processing method of the present invention, before forming the transistor structure on the substrate, the edge of the substrate is ground and polished through a grinding process to reduce the edge roughness of the substrate and remove the damaged layer caused by the previous process. Moreover, after the grinding process is performed, the roughness measurement process is continuously performed to confirm whether the edge roughness of the substrate is within a predetermined target range through an atomic force microscope. With the substrate processing method provided by the present invention, it can ensure that the transistor structure subsequently formed on the substrate has better crystal quality.

本發明已參照例示性實施例進行說明，本領域具有通常知識者可以理解的是，在不脫離申請專利範圍所定義之本發明概念與範疇的清況下，可以對其進行形式與細節上之各種變更及等效佈置，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 The present invention has been described with reference to exemplary embodiments, and it will be understood by those skilled in the art that changes in form and details may be made without departing from the concept and scope of the present invention defined by the claims. Various changes and equivalent arrangements, so the scope of protection of the present invention should be defined by the scope of the appended patent application.

S101,S102,S103,S104:步驟 S101, S102, S103, S104: steps

Claims (9)

一種基板加工方法，包含：提供一基板；進行一研磨製程，包含使用一研磨單元對該基板的邊緣進行研磨，且經該研磨製程加工的該基板具有一晶圓傾斜角度；進行一拋光製程，包含將一拋光劑加入至一拋光單元與該基板之間，並且使用該拋光單元對該基板的邊緣進行拋光；進行一粗糙度量測製程，包含量測該基板的一邊緣粗糙度；設置一氮化鋁成核層，設置在該基板上；設置一第一氮化鋁鎵緩衝層，設置在該氮化鋁成核層上；設置一第二氮化鋁鎵緩衝層，設置在該第一氮化鋁鎵緩衝層上；以及設置一第三氮化鋁鎵緩衝層，設置在該第二氮化鋁鎵緩衝層上；其中，完工的該基板的該晶圓傾斜角度及該邊緣粗糙度分別滿足一目標晶圓傾斜角度及一目標邊緣粗糙度，且該目標晶圓傾斜角度介於11至22度，並且該目標邊緣粗糙度介於0.01至0.05nm；其中該第一氮化鋁鎵緩衝層的化學組成為AlaGa1-aN，且0.75≦a<1，該第二氮化鋁鎵緩衝層的化學組成為AlbGa1-bN，且0.5≦b≦0.75，以及該第三氮化鋁鎵緩衝層的化學組成為AlcGa1-cN，且0.3≦c≦0.5，並且該第一氮化鋁鎵緩衝層、該第二氮化鋁鎵緩衝層及該第三氮化鋁鎵緩衝層為碳摻雜、 鐵摻雜、鎂摻雜或鋅摻雜，並且該第一氮化鋁鎵緩衝層、該第二氮化鋁鎵緩衝層及該第三氮化鋁鎵緩衝層的摻雜濃度分別為1E17 atoms/cm3、3E17 atoms/cm3以及5E17 atoms/cm3。 A substrate processing method, comprising: providing a substrate; performing a grinding process, including using a grinding unit to grind the edge of the substrate, and the substrate processed by the grinding process has a wafer tilt angle; performing a polishing process, including adding a polishing agent between a polishing unit and the substrate, and using the polishing unit to polish the edge of the substrate; performing a roughness measurement process, including measuring an edge roughness of the substrate; setting a An aluminum nitride nucleation layer is arranged on the substrate; a first aluminum gallium nitride buffer layer is arranged on the aluminum nitride nucleation layer; a second aluminum gallium nitride buffer layer is arranged on the first aluminum nitride buffer layer On an aluminum gallium nitride buffer layer; and a third aluminum gallium nitride buffer layer is arranged on the second aluminum gallium nitride buffer layer; wherein, the wafer tilt angle and the edge roughness of the completed substrate Degrees meet a target wafer tilt angle and a target edge roughness respectively, and the target wafer tilt angle is between 11 and 22 degrees, and the target edge roughness is between 0.01 and 0.05 nm; wherein the first aluminum nitride The chemical composition of the gallium buffer layer is Al a Ga 1-a N, and 0.75≦a<1, the chemical composition of the second aluminum gallium nitride buffer layer is Al b Ga 1-b N, and 0.5≦b≦0.75, And the chemical composition of the third aluminum gallium nitride buffer layer is Al c Ga 1-c N, and 0.3≦c≦0.5, and the first aluminum gallium nitride buffer layer, the second aluminum gallium nitride buffer layer and The third aluminum gallium nitride buffer layer is carbon-doped, iron-doped, magnesium-doped or zinc-doped, and the first aluminum gallium nitride buffer layer, the second aluminum gallium nitride buffer layer and the third The doping concentrations of the AlGaN buffer layer are 1E17 atoms/cm 3 , 3E17 atoms/cm 3 and 5E17 atoms/cm 3 . 如請求項1所述之基板加工方法，其中該目標晶圓傾斜角度為19.5度。 The substrate processing method according to claim 1, wherein the tilt angle of the target wafer is 19.5 degrees. 如請求項1所述之基板加工方法，其中該拋光製程的製程時間介於60~360秒。 The substrate processing method as described in claim 1, wherein the polishing process has a process time of 60-360 seconds. 如請求項1所述之基板加工方法，其中該拋光單元為圓/平邊拋光單元或者凹口(Notch)拋光單元。 The substrate processing method according to claim 1, wherein the polishing unit is a round/flat edge polishing unit or a notch polishing unit. 如請求項1所述之基板加工方法，其中該拋光劑為含有二氧化矽懸浮顆粒的氫氧化鉀溶液。 The substrate processing method according to claim 1, wherein the polishing agent is a potassium hydroxide solution containing silicon dioxide suspended particles. 一種電晶體結構，包含：一基板；一氮化鋁成核層，設置在該基板上；一第一氮化鋁鎵緩衝層，設置在該氮化鋁成核層上；一第二氮化鋁鎵緩衝層，設置在該第一氮化鋁鎵緩衝層上；一第三氮化鋁鎵緩衝層，設置在該第二氮化鋁鎵緩衝層上；一高阻層，設置在該第三氮化鋁鎵緩衝層上；一本質氮化鎵層，設置在該高阻層上；一氮化鋁鎵電子提供層，設置在該本質氮化鎵層上；以及一覆蓋層，設置在該氮化鋁鎵電子提供層上； 其中該第一氮化鋁鎵緩衝層的化學組成為AlaGa1-aN，且0.75≦a<1，該第二氮化鋁鎵緩衝層的化學組成為AlbGa1-bN，且0.5≦b≦0.75，以及該第三氮化鋁鎵緩衝層的化學組成為AlcGa1-cN，且0.3≦c≦0.5，並且該第一氮化鋁鎵緩衝層、該第二氮化鋁鎵緩衝層及該第三氮化鋁鎵緩衝層為碳摻雜、鐵摻雜、鎂摻雜或鋅摻雜，並且該第一氮化鋁鎵緩衝層、該第二氮化鋁鎵緩衝層及該第三氮化鋁鎵緩衝層的摻雜濃度分別為1E17 atoms/cm3、3E17 atoms/cm3以及5E17 atoms/cm3。 A transistor structure comprising: a substrate; an aluminum nitride nucleation layer disposed on the substrate; a first aluminum gallium nitride buffer layer disposed on the aluminum nitride nucleation layer; a second nitride an aluminum gallium buffer layer arranged on the first aluminum gallium nitride buffer layer; a third aluminum gallium nitride buffer layer arranged on the second aluminum gallium nitride buffer layer; a high resistance layer arranged on the first aluminum gallium nitride buffer layer On the aluminum gallium nitride buffer layer; an intrinsic gallium nitride layer disposed on the high resistance layer; an aluminum gallium nitride electron supply layer disposed on the intrinsic gallium nitride layer; and a cap layer disposed on the intrinsic gallium nitride layer On the aluminum gallium nitride electron supply layer; wherein the chemical composition of the first aluminum gallium nitride buffer layer is Al a Ga 1-a N, and 0.75≦a<1, the chemical composition of the second aluminum gallium nitride buffer layer The composition is Al b Ga 1-b N, and 0.5≦b≦0.75, and the chemical composition of the third aluminum gallium nitride buffer layer is Al c Ga 1-c N, and 0.3≦c≦0.5, and the first The aluminum gallium nitride buffer layer, the second aluminum gallium nitride buffer layer and the third aluminum gallium nitride buffer layer are carbon-doped, iron-doped, magnesium-doped or zinc-doped, and the first aluminum nitride The doping concentrations of the gallium buffer layer, the second AlGaN buffer layer and the third AlGaN buffer layer are 1E17 atoms/cm 3 , 3E17 atoms/cm 3 and 5E17 atoms/cm 3 , respectively. 如請求項6所述之電晶體結構，其中該基板的邊緣經過一研磨製程的加工而具有一目標晶圓傾斜角度，且該目標晶圓傾斜角度介於11至22度。 The transistor structure as claimed in claim 6, wherein the edge of the substrate is processed by a grinding process to have a target wafer tilt angle, and the target wafer tilt angle is between 11 and 22 degrees. 如請求項6所述之電晶體結構，其中該基板的邊緣經過一拋光製程的加工而具有一目標邊緣粗糙度，且該目標邊緣粗糙度介於0.01至0.05nm。 The transistor structure according to claim 6, wherein the edge of the substrate is processed by a polishing process to have a target edge roughness, and the target edge roughness is in the range of 0.01 to 0.05 nm. 如請求項6所述之電晶體結構，其中該高阻層為氮化鎵，且該高阻層為碳摻雜、鐵摻雜、鎂摻雜或鋅摻雜，並且該高阻層的摻雜濃度為1E19 atoms/cm3，並且該覆蓋層為鎂摻雜的P型氮化鎵或P型氮化鋁鎵，且其摻雜濃度為1E19 atoms/cm3，並且當該覆蓋層為P型氮化鋁鎵時，其化學組成為AlyGa1-yN，且0.1≦y≦0.3。 The transistor structure as claimed in item 6, wherein the high resistance layer is gallium nitride, and the high resistance layer is carbon doped, iron doped, magnesium doped or zinc doped, and the high resistance layer is doped The impurity concentration is 1E19 atoms/cm 3 , and the cladding layer is magnesium-doped P-type gallium nitride or P-type aluminum gallium nitride, and its doping concentration is 1E19 atoms/cm 3 , and when the cladding layer is P Type aluminum gallium nitride, its chemical composition is Al y Ga 1-y N, and 0.1≦y≦0.3.
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TWI257142B (en) * 2000-12-14 2006-06-21 Nitronex Corp Gallium nitride materials and methods
CN104513626A (en) * 2014-12-22 2015-04-15 深圳市力合材料有限公司 Silicon chemical-mechanical polishing solution
CN104526493A (en) * 2014-11-18 2015-04-22 天津中环领先材料技术有限公司 Monocrystalline silicon wafer edge polishing technology
TW201816849A (en) * 2016-08-23 2018-05-01 美商克若密斯股份有限公司 Electronic power devices integrated with an engineered substrate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI257142B (en) * 2000-12-14 2006-06-21 Nitronex Corp Gallium nitride materials and methods
CN104526493A (en) * 2014-11-18 2015-04-22 天津中环领先材料技术有限公司 Monocrystalline silicon wafer edge polishing technology
CN104513626A (en) * 2014-12-22 2015-04-15 深圳市力合材料有限公司 Silicon chemical-mechanical polishing solution
TW201816849A (en) * 2016-08-23 2018-05-01 美商克若密斯股份有限公司 Electronic power devices integrated with an engineered substrate

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