TWI794640B

TWI794640B - Micro-electromechanical system device and method of forming the same

Info

Publication number: TWI794640B
Application number: TW109129066A
Authority: TW
Inventors: 夏佳杰; 拉奇許庫瑪
Original assignee: 世界先進積體電路股份有限公司
Priority date: 2020-08-26
Filing date: 2020-08-26
Publication date: 2023-03-01
Also published as: TW202208271A

Abstract

The present disclosure relates to a micro-electromechanical system (MEMS) device and a method of forming the same. The MEMS device includes a substrate, a cavity, an interconnection structure and a proof mass. The substrate includes a first surface and a second surface opposite to the first surface. The cavity is disposed in the substrate, extending between the first surface and the second surface. The interconnection structure is disposed on the first surface of the substrate, over the cavity. The proof mass is disposed in the cavity, connected to the interconnection structure, the proof mass having a thickness which is smaller than a thickness of the substrate.

Description

微機電裝置及其形成方法 Microelectromechanical device and method of forming same

本發明是關於一種微機電裝置及其形成方法，且特別是關於一種應用於聲學領域的微機電裝置及其形成方法。 The present invention relates to a microelectromechanical device and its forming method, and in particular to a microelectromechanical device and its forming method applied in the field of acoustics.

微機電(micro-electromechanical system,MEMS)裝置乃是利用習知半導體製程來製造的微小機械元件，透過半導體技術例如沉積、或選擇性蝕刻材料層等方式完成具有微米尺寸的機械元件。微機電裝置可利用電磁(electromagnetic)、電致伸縮(electrostrictive)、熱電(thermoelectric)、壓電(piezoelectric)或壓阻(piezoresistive)等效應進行操作，而兼具電子及機械的雙重功能，因此，常應用於微電子領域，如加速器(accelerometer)、陀螺儀(gyroscope)、反射鏡(mirror)或聲學感測器(acoustic sensor)等。 A micro-electromechanical system (MEMS) device is a micro-mechanical element manufactured using conventional semiconductor manufacturing processes. A micron-sized mechanical element is completed through semiconductor techniques such as deposition or selective etching of material layers. Micro-electromechanical devices can operate by using effects such as electromagnetic, electrostrictive, thermoelectric, piezoelectric, or piezoresistive, and have both electronic and mechanical functions. Therefore, It is often used in the field of microelectronics, such as accelerators, gyroscopes, mirrors or acoustic sensors.

近年來，由於無線藍芽(true wireless stereo,TWS)耳機的快速發展，可將微機電系統加速器產品用於感測聲音的振動，為聲學換能器帶來新的視野。將微機電系統速器產品設置於該無線藍芽耳機內，可讓該無線藍芽耳機即使處於雜訊高或雜訊較多的周圍環境下依然能有力地擷取聲音。然而，因微機電系統加速器產品目前較普遍應用於手機領域，因此，其結構設計上多偏向厚而大，以致並不能滿足無線藍芽耳機微型化的設計需求。如此，目前仍然需要一種新設計的加速器以應用於聲學領域。 In recent years, due to the rapid development of wireless Bluetooth (true wireless stereo, TWS) earphones, MEMS accelerator products can be used to sense the vibration of sound, bringing new horizons for acoustic transducers. Setting the MEMS accelerator product in the wireless bluetooth earphone can make the wireless bluetooth earphone remain stable even in the surrounding environment with high noise or a lot of noise. However, it can effectively capture the sound. However, since MEMS accelerator products are currently widely used in the field of mobile phones, their structural design tends to be thick and large, so that they cannot meet the miniaturization design requirements of wireless Bluetooth headsets. Thus, there is still a need for a newly designed accelerator for application in the field of acoustics.

本發明提供一種微機電裝置及其形成方法，該微機電裝置具有微型化的檢測質量塊(proof mass)，其厚度相對小於基底的厚度，因此，該微機電裝置可應用於無線藍芽耳機，從而輔助麥克風的語音振動。 The present invention provides a micro-electro-mechanical device and a method for forming the same. The micro-electro-mechanical device has a miniaturized proof mass whose thickness is relatively smaller than that of the substrate. Therefore, the micro-electro-mechanical device can be applied to wireless bluetooth earphones, Thereby assisting the voice vibration of the microphone.

為達上述目的，本發明的一實施例係提供一種微機電裝置，包含基底、溝槽、互連結構以及質量塊。該基底具有一第一表面以及相對於該第一表面的一第二表面。該溝槽設置在該基底內，該溝槽延伸於該第一表面以及該第二表面之間。該互連結構設置在該基底的該第一表面上，並且位在該溝槽的上方。該質量塊設置在該溝槽內並連接該互連結構，該質量塊的厚度小於該基底的厚度。 To achieve the above purpose, an embodiment of the present invention provides a MEMS device, including a substrate, a groove, an interconnection structure, and a proof mass. The base has a first surface and a second surface opposite to the first surface. The groove is disposed in the base, and the groove extends between the first surface and the second surface. The interconnection structure is disposed on the first surface of the substrate and is located above the trench. The quality block is arranged in the groove and connected to the interconnection structure, and the thickness of the mass block is smaller than the thickness of the substrate.

為達上述目的，本發明的另一實施例係提供一種微機電裝置的形成方法，包含以下步驟。首先，提供一基底，該基底具有一第一表面以及相對於該第一表面的一第二表面。接著，於該基底內形成一溝槽，該溝槽延伸於該第一表面以及該第二表面之間。然後，於該基底的該第一表面上形成一互連結構，該互連結構位在該溝槽的上方。最後，於該溝槽內形成一質量塊，該質量塊連接該互連結構，該質量塊的厚度小於該基底的厚度。 To achieve the above purpose, another embodiment of the present invention provides a method for forming a MEMS device, which includes the following steps. Firstly, a base is provided, and the base has a first surface and a second surface opposite to the first surface. Then, a groove is formed in the substrate, and the groove extends between the first surface and the second surface. Then, an interconnection structure is formed on the first surface of the substrate, and the interconnection structure is located above the trench. Finally, a mass is formed in the trench, the mass is connected to the interconnection structure, and the mass The thickness of the block is less than the thickness of the substrate.

100:基底 100: base

101:第一表面 101: First Surface

102:第二表面 102: second surface

103:溝槽 103: Groove

103a:開口 103a: opening

105:質量塊 105: mass block

110:氧化層 110: oxide layer

111:底切部分 111: Undercut part

120:第一遮罩層 120: The first mask layer

120a:開口 120a: opening

130:保護層 130: protective layer

140:第二遮罩層 140: Second mask layer

140a:圖案 140a: pattern

200:互連結構 200: Interconnect structure

210:懸掛區域 210: Hanging area

201:介電層 201: dielectric layer

203:金屬層 203: metal layer

205:連接墊 205: connection pad

207:穿孔 207: perforation

300:矽覆絕緣基底 300: silicon-covered insulating substrate

301:第一表面 301: first surface

302:第二表面 302: second surface

303:溝槽 303: Groove

303a:開口 303a: opening

305:質量塊 305: mass block

311:第一半導體層 311: the first semiconductor layer

313:絕緣層 313: insulating layer

313a:開口 313a: opening

313b:圖案 313b: pattern

313c:底切部分 313c: undercut part

315:第二半導體層 315: the second semiconductor layer

320:氧化層 320: oxide layer

321:底切部分 321: Undercut part

330:保護層 330: protective layer

340:遮罩層 340: mask layer

T1、T2、T3:厚度 T1, T2, T3: Thickness

T2’:厚度 T2': Thickness

第1圖為本發明一微機電裝置(MEMS device)於形成互連結構(interconnection structure)後的剖面示意圖。 FIG. 1 is a schematic cross-sectional view of a MEMS device of the present invention after forming an interconnection structure.

第2圖為本發明一微機電裝置於形成遮罩層後的剖面示意圖。 FIG. 2 is a schematic cross-sectional view of a MEMS device of the present invention after forming a mask layer.

第3圖為本發明一微機電裝置於進行一蝕刻製程後的剖面示意圖。 FIG. 3 is a schematic cross-sectional view of a MEMS device of the present invention after an etching process.

第4圖為本發明一微機電裝置於進行另一蝕刻製程後的剖面示意圖。 FIG. 4 is a schematic cross-sectional view of a MEMS device of the present invention after another etching process.

第5圖為本發明一微機電裝置於裝置釋放後的剖面示意圖。 FIG. 5 is a schematic cross-sectional view of a MEMS device of the present invention after the device is released.

第6圖為本發明一微機電裝置於形成互連結構後的剖面示意圖。 FIG. 6 is a schematic cross-sectional view of a MEMS device of the present invention after forming an interconnection structure.

第7圖為本發明一微機電裝置於進行一蝕刻製程後的剖面示意圖。 FIG. 7 is a schematic cross-sectional view of a MEMS device of the present invention after an etching process.

第8圖為本發明一微機電裝置於裝置釋放後的剖面示意圖。 FIG. 8 is a schematic cross-sectional view of a MEMS device of the present invention after the device is released.

為使熟習本發明所屬技術領域之一般技藝者能更進一步了解本發明，下文特列舉本發明之數個較佳實施例，並配合所附圖式，詳細說明本發明的構成內容及所欲達成之功效。並且，熟習本發明所屬技術領域之一般技藝者亦能在不脫離本發明的精神下，參考以下所舉實施例，而將數個不同實施例中的特徵進行替換、重組、混合以完成其他實施例。 In order to enable those who are familiar with the general skills in the technical field of the present invention to further understand the present invention, several preferred embodiments of the present invention are enumerated below, and in conjunction with the attached drawings, the constitutional content and desired achievement of the present invention are described in detail. The effect. Moreover, those skilled in the technical field of the present invention can also refer to the following embodiments without departing from the spirit of the present invention, and replace, reorganize, and mix the features in several different embodiments to complete other implementations example.

本發明中針對「第一部件形成在第二部件上或上方」的敘述，其可以是指「第一部件與第二部件直接接觸」，也可以是指「第一部件與第二部件之間另存在有其他部件」，致使第一部件與第二部件並不直接接觸。此外，本發明中的各種實施例可能使用重複的元件符號和/或文字註記。使用這些重複的元件符號與文字註記是為了使敘述更簡潔和明確，而非用以指示不同的實施例及/或配置之間的關聯性。另外，針對本發明中所提及的空間相關的敘述詞彙，例如：「在...之下」、「在...之上」、「低」、「高」、「下方」、「上方」、「之下」、「之上」、「底」、「頂」和類似詞彙時，為便於敘述，其用法均在於描述圖式中一個部件或特徵與另一個(或多個)部件或特徵的相對關係。除了圖式中所顯示的擺向外，這些空間相關詞彙也用來描述半導體裝置在製作過程中、使用中以及操作時的可能擺向。舉例而言，當半導體裝置被旋轉180度時，原先設置於其他部件「上方」的某部件便會變成設置於其他部件「下方」。因此，隨著半導體裝置的擺向的改變(旋轉90度或其它角度)，用以描述其擺向的空間相關敘述亦應透過對應的方式予以解釋。 The description of "the first component is formed on or over the second component" in the present invention As mentioned above, it may refer to "the first part is in direct contact with the second part", or it may refer to "there are other parts between the first part and the second part", so that the first part and the second part are not directly connected. touch. In addition, various embodiments of the present invention may use repeated reference numerals and/or text notations. The use of these repeated reference numerals and text notations is used to make the description more concise and clear, rather than to indicate the relationship between different embodiments and/or configurations. In addition, for the space-related descriptive words mentioned in the present invention, for example: "below", "above", "low", "high", "below", "above ”, “below”, “above”, “bottom”, “top” and similar terms, for convenience of description, are used to describe the relationship between one component or feature and another (or more) components or features in the drawings. The relative relationship of features. In addition to the orientations shown in the drawings, these space-related terms are also used to describe possible orientations of semiconductor devices during fabrication, use, and operation. For example, when a semiconductor device is rotated by 180 degrees, a component that was originally positioned "above" other components becomes positioned "below" the other components. Therefore, as the swing direction of the semiconductor device is changed (rotated by 90 degrees or other angles), the space-related description used to describe its swing direction should also be interpreted in a corresponding manner.

雖然本發明使用第一、第二、第三等用詞，以敘述種種元件、部件、區域、層、及/或區塊(section)，但應了解此等元件、部件、區域、層、及/或區塊不應被此等用詞所限制。此等用詞僅是用以區分某一元件、部件、區域、層、及/或區塊與另一個元件、部件、區域、層、及/或區塊，其本身並不意含及代表該元件有任何之前的序數，也不代表某一元件與另一元件的排列順序、或是製造方法上的順序。因此，在不背離本發明之具體實施例之範疇下，下列所討論之第一元件、部件、區域、層、或區塊亦可以第二元件、部件、區域、層、或區塊等詞稱之。 Although the present invention uses terms such as first, second, and third to describe various elements, components, regions, layers, and/or sections, it should be understood that these elements, components, regions, layers, and / or blocks should not be limited by such terms. These terms are only used to distinguish one element, component, region, layer, and/or block from another element, component, region, layer, and/or block, and do not imply or represent the element The presence of any preceding ordinal number does not imply an order of arrangement of one element over another, or an order in method of manufacture. Therefore, without departing from the scope of the specific embodiments of the present invention, a first element, component, region, layer, or block discussed below may also be a second element, component, region, layer, or block and so on.

本發明中所提及的「約」或「實質上」之用語通常表示在一給定值或範圍的20%之內，較佳是10%之內，且更佳是5%之內，或3%之內，或2%之內，或1%之內，或0.5%之內。應注意的是，說明書中所提供的數量為大約的數量，亦即在沒有特定說明「約」或「實質上」的情況下，仍可隱含「約」或「實質上」之含義。 The term "about" or "substantially" mentioned in the present invention usually means within 20%, preferably within 10%, and more preferably within 5%, of a given value or range Within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the description are approximate quantities, that is, the meaning of "about" or "substantial" may still be implied if "about" or "substantial" is not specified.

請參照第1圖至第5圖所示，其繪示本發明第一實施例中微機電裝置的形成方法的示意圖。首先，如第1圖所示，提供一基底100，例如一塊狀矽基底(bulk silicon substrate)，基底100例如包含單晶矽、多晶矽、非晶矽或其他合適的材質。在一實施例中，該基底100的厚度T1可約為400微米(micrometers,μm)至500微米，但並不限於此。基底100具有兩相對表面，如第1圖所示的第一表面101以及第二表面102，基底100的第一表面101上還依序形成有一氧化層110以及一互連結構200。氧化層110例如包含氧化矽(silicon oxide,SiO)或二氧化矽(silicon dioxide,SiO₂)，而互連結構200則可以是利用沉積及/或選擇性蝕刻材料層等習知半導體製程所造出之任何合適的半導體結構。在一實施例中，該互連結構200包含堆疊於第一表面101上的至少一介電層201，埋設在至少一介電層201內的至少一金屬層203，以及電連接至少一金屬層203的至少一連接墊205，如第1圖所示，其中，至少一介電層201例如包含氮化矽(silicon nitride,SiN)、氮化鋁(aluminum nitride,AlN)或氮氧化矽(silicon oxynitride,SiON)等介電材質，至少一金屬層203例如包含銅(copper,Cu)、鉬(molybdenum,Mo)、鎢(tungsten, W)或鋁(aluminum,Al)等金屬材質，但不以此為限。 Please refer to FIG. 1 to FIG. 5 , which are schematic diagrams illustrating the method for forming the MEMS device in the first embodiment of the present invention. First, as shown in FIG. 1 , a substrate 100 is provided, such as a bulk silicon substrate. The substrate 100 includes monocrystalline silicon, polycrystalline silicon, amorphous silicon or other suitable materials. In one embodiment, the thickness T1 of the substrate 100 may be about 400 micrometers (micrometers, μm) to 500 micrometers, but not limited thereto. The substrate 100 has two opposite surfaces, such as the first surface 101 and the second surface 102 shown in FIG. 1 , and an oxide layer 110 and an interconnection structure 200 are sequentially formed on the first surface 101 of the substrate 100 . The oxide layer 110 includes, for example, silicon oxide (SiO) or silicon dioxide (silicon dioxide, SiO ₂ ), and the interconnection structure 200 can be formed by conventional semiconductor manufacturing processes such as deposition and/or selective etching of material layers. any suitable semiconductor structure. In one embodiment, the interconnect structure 200 includes at least one dielectric layer 201 stacked on the first surface 101, at least one metal layer 203 embedded in the at least one dielectric layer 201, and at least one metal layer electrically connected At least one connection pad 205 of 203, as shown in FIG. 1, wherein at least one dielectric layer 201 includes, for example, silicon nitride (silicon nitride, SiN), aluminum nitride (aluminum nitride, AlN) or silicon oxynitride (silicon oxynitride, SiON) and other dielectric materials, at least one metal layer 203 includes copper (copper, Cu), molybdenum (molybdenum, Mo), tungsten (tungsten, W) or aluminum (aluminum, Al) and other metal materials, but not This is the limit.

需注意的是，互連結構200進一步包含設置在一懸掛區域210內的一穿孔207，藉此，設置在懸掛區域210內的一結構則可在後續製程中與基底100部分分離而構成一懸掛結構(suspended structure，未繪示)。舉例來說，懸掛結構可進一步包含由上而下依序堆疊於互連結構200內的一頂電極(top electrode，未繪示)、一壓電層(piezoelectric layer，未繪示)以及一底電極(bottom electrode，未繪示)，進而能夠在後續製程中以特定頻率振動。在本實施例中，該懸掛結構可包含懸臂(cantilever)、隔膜(diaphragm)等類似結構，但並不限於此。 It should be noted that the interconnection structure 200 further includes a through hole 207 disposed in a suspension region 210, whereby a structure disposed in the suspension region 210 can be partially separated from the substrate 100 in a subsequent process to form a suspension. Structure (suspended structure, not shown). For example, the suspension structure may further include a top electrode (top electrode, not shown), a piezoelectric layer (piezoelectric layer, not shown) and a bottom stacked sequentially in the interconnection structure 200 from top to bottom. The electrode (bottom electrode, not shown) can vibrate at a specific frequency in the subsequent process. In this embodiment, the suspension structure may include a cantilever, a diaphragm and similar structures, but is not limited thereto.

接著，在互連結構200的頂表面上形成一保護層130，保護層130例如包含氧化矽或二氧化矽，以用於保護設置在互連結構200內的元件。並且，在基底100的第二表面上依序形成第一遮罩層120以及第二遮罩層140，如第2圖所示，以在後續製程中分別用於定義溝槽(cavity)以及質量塊(proof mass)。具體來說，第一遮罩層120上具有一開口120a，開口120a對應於設置在第一表面101上之互連結構200的懸掛區域210，藉此，第二表面102上對應於懸掛區域210的一部分即可自開口120a暴露出，如第2圖所示。在一實施例中，開口120a的尺寸或直徑例如是約為100微米至150微米，但不以此為限。第二遮罩層140係堆疊在第一遮罩層120上，第二遮罩層140包含設置在開口120a內的一圖案140a。換言之，第二遮罩層140的一部分是直接設置在第一遮罩層120上，並完全重疊於第一遮罩層120的頂表面，而第二遮罩層140的另一部分則設置在第一遮罩層120所暴露出的該部分上，如第2圖所示。在本實施例中，第一遮罩層120較佳係包含與第二遮罩層140的材質具不同蝕刻選擇比的材質，舉例來說，第一遮罩層120可包含氧化矽，而第二遮罩層140則可包含一光阻材質，但不限於此。並且，第一遮罩層120的材質較佳係與氧化層110的材質相同，或者，係與氧化層110的材質具有相同的蝕刻選擇比。 Next, a protection layer 130 is formed on the top surface of the interconnection structure 200 . The protection layer 130 includes, for example, silicon oxide or silicon dioxide for protecting components disposed in the interconnection structure 200 . Moreover, a first mask layer 120 and a second mask layer 140 are sequentially formed on the second surface of the substrate 100, as shown in FIG. block (proof mass). Specifically, the first mask layer 120 has an opening 120a corresponding to the suspension area 210 of the interconnect structure 200 disposed on the first surface 101, whereby the second surface 102 corresponds to the suspension area 210 A part can be exposed from the opening 120a, as shown in FIG. 2 . In one embodiment, the size or diameter of the opening 120 a is, for example, about 100 microns to 150 microns, but not limited thereto. The second mask layer 140 is stacked on the first mask layer 120, and the second mask layer 140 includes a pattern 140a disposed in the opening 120a. In other words, a part of the second mask layer 140 is directly disposed on the first mask layer 120 and completely overlaps the top surface of the first mask layer 120, while another part of the second mask layer 140 is disposed on the second mask layer 120. On the part exposed by a mask layer 120, as shown in Fig. 2 Show. In this embodiment, the first mask layer 120 is preferably made of a material having a different etching selectivity than that of the second mask layer 140. For example, the first mask layer 120 may include silicon oxide, and the second mask layer 140 may include silicon oxide. The second mask layer 140 may include a photoresist material, but is not limited thereto. Moreover, the material of the first mask layer 120 is preferably the same as that of the oxide layer 110 , or has the same etching selectivity as the material of the oxide layer 110 .

如第3圖所示，在基底100的背側即第二表面102所在側進行一蝕刻製程，例如是一非等向性乾蝕刻製程，同時透過第一遮罩層120以及第二遮罩層140移除部分的基底100至達到一定深度。需注意的是，在第二遮罩層140的覆蓋下，被圖案140a蓋在下方的基底100不會在蝕刻的過程被移除，因而可在開口120a的範圍內形成部分突出的一輪廓，如第3圖所示。較佳地，被移除的該部分的深度大體上可等同於後續所形成的質量塊的預定厚度。在一實施例中，被移除的該部分的該深度例如約為50微米至100微米，由此，第3圖所示的突出輪廓即具有約為50微米至100微米的厚度T2，但不以此為限。本領域者應可輕易理解，在前述的蝕刻製程中透過該蝕刻製程而達到的一定深度應可依據後續所形成之質量塊的所需厚度進一步調整，而不以前述數值為限。 As shown in FIG. 3, an etching process, such as an anisotropic dry etching process, is performed on the back side of the substrate 100, that is, the side where the second surface 102 is located, and simultaneously penetrates the first mask layer 120 and the second mask layer. 140 removes a portion of the substrate 100 to a certain depth. It should be noted that under the coverage of the second mask layer 140, the substrate 100 covered by the pattern 140a will not be removed during the etching process, so a partially protruding outline can be formed in the range of the opening 120a, As shown in Figure 3. Preferably, the depth of the removed portion may be substantially equal to the predetermined thickness of the subsequently formed mass. In one embodiment, the depth of the removed portion is, for example, about 50 microns to 100 microns, whereby the protruding profile shown in FIG. 3 has a thickness T2 of about 50 microns to 100 microns, but not This is the limit. Those skilled in the art should easily understand that the certain depth achieved through the etching process in the aforementioned etching process should be further adjusted according to the required thickness of the subsequently formed proof mass, and is not limited to the aforementioned value.

然後，如第4圖所示，移除第二遮罩層140，並且在基底100的該背側(即第二表面102所在側)進行另一蝕刻製程，例如是一非等向性乾蝕刻製程，順著前述的該突出輪廓進一步向下蝕刻，移除基底100直至暴露出下方的氧化層110。由此，即可在基底100內形成一溝槽103，溝槽103係延伸於基底100的兩相對表面(第一表面101以及第二表面102)之間，而具有與基底100的厚度T1相同的一深度，並且，透過前述的該突出輪廓，可在溝槽103內形成一質量塊105。如此，可同時形成溝槽103以及質量塊105，並且使得溝槽103以及質量塊105均可對應於設置在第一表面101上之互連結構200的懸掛區域210，如第4圖所示。其中，質量塊105的厚度T2約為50微米至100微米，而溝槽103在鄰接懸掛區域210的底面處則具有一開口103a。 Then, as shown in FIG. 4, the second mask layer 140 is removed, and another etching process, such as an anisotropic dry etching, is performed on the backside of the substrate 100 (ie, the side where the second surface 102 is located). In the manufacturing process, the substrate 100 is removed until the underlying oxide layer 110 is exposed by further etching downward along the aforementioned protruding contour. Thus, a groove 103 can be formed in the substrate 100, the groove 103 extends between two opposite surfaces (the first surface 101 and the second surface 102) of the substrate 100, and has the same thickness T1 as the substrate 100. a depth, and, through Through the aforementioned protruding contour, a proof mass 105 can be formed in the groove 103 . In this way, the groove 103 and the mass 105 can be formed simultaneously, and both the groove 103 and the proof mass 105 can correspond to the suspension region 210 of the interconnection structure 200 disposed on the first surface 101 , as shown in FIG. 4 . Wherein, the thickness T2 of the proof mass 105 is about 50 μm to 100 μm, and the groove 103 has an opening 103 a at the bottom surface adjacent to the suspension area 210 .

隨後，利用相對於質量塊105以及基底100的蝕刻選擇進行另一蝕刻製程，以同時移除第一遮罩層120以及自基底100、質量塊105所暴露出的氧化層110，使得位於下方的懸掛區域210的該底面可被暴露出來。舉例來說，第一遮罩層120以及氧化層110的材質(例如氧化矽)相對於質量塊105以及基底100的材質(例如矽)的蝕刻選擇比例如是大於10，約為10至20，但不以此為限。由此操作下，懸掛區域210的該底面即可自溝槽103部分暴露出，如第5圖所示，而質量塊105則可因此設置在懸掛區域210的該底面上，使得一部分的氧化層110被夾設於懸掛區域210以及質量塊105之間。需注意的是，在完全移除第一遮罩層120並部分移除氧化層110的過程中，剩餘的氧化層110的側壁還可稍微被一併移除，從而形成如第5圖所示的底切(under cut)部分111。此外，在移除第一遮罩層120以及氧化層110的過程中，質量塊105的頂部也會被稍微移除，因此，在該另一蝕刻製程進行之後，質量塊105可能具有一個較小的厚度T2’。較佳地，厚度T2’相較於原始的厚度T2例如是約減少不超過1至10%的程度，以避免過度影響質量塊105的整體重量。然後，再進一步移除保護層130，以釋放位在互連結構200的懸掛區域210內的該懸掛結構，使得該懸掛結構的一側不與基底100相連而呈現一端懸空的態樣，如第5圖所示。在一實施例中，保護層130 的移除可選擇在移除第一遮罩層120以及氧化層110的製程中一併進行，但不限於此。在另一個實施例中，保護層130的移除也可以選擇在移除第一遮罩層120以及氧化層110之後，再通過另一蝕刻製程額外進行。 Subsequently, another etching process is performed using an etching selection relative to the mass block 105 and the substrate 100, so as to simultaneously remove the first mask layer 120 and the oxide layer 110 exposed from the substrate 100 and the mass block 105, so that the underlying The bottom surface of the hanging area 210 may be exposed. For example, the etching selectivity ratio of the material of the first mask layer 120 and the oxide layer 110 (such as silicon oxide) relative to the material of the proof mass 105 and the substrate 100 (such as silicon) is greater than 10, about 10 to 20, but This is not the limit. Under this operation, the bottom surface of the suspension region 210 can be partially exposed from the trench 103, as shown in FIG. 110 is sandwiched between the suspension area 210 and the proof mass 105 . It should be noted that during the process of completely removing the first mask layer 120 and partially removing the oxide layer 110, the sidewalls of the remaining oxide layer 110 can also be slightly removed together, thereby forming The undercut (under cut) part 111 of. In addition, during the process of removing the first mask layer 120 and the oxide layer 110, the top of the proof mass 105 is also slightly removed, so the proof mass 105 may have a smaller The thickness T2'. Preferably, the thickness T2' is reduced by no more than 1 to 10% compared to the original thickness T2, so as to avoid undue influence on the overall weight of the proof mass 105. Then, the protective layer 130 is further removed to release the suspension structure located in the suspension region 210 of the interconnection structure 200, so that one side of the suspension structure is not connected to the substrate 100, but one end is suspended, as shown in the first 5 as shown in Fig. In one embodiment, the protective layer 130 The removal of the first mask layer 120 and the oxide layer 110 may be selected to be removed together, but not limited thereto. In another embodiment, the removal of the protection layer 130 may be additionally performed through another etching process after removing the first mask layer 120 and the oxide layer 110 .

由此，即可形成本發明第一實施例中的微機電裝置。在本實施例中，該微機電裝置包含設置在互連結構200的懸掛區域210內的懸掛結構、溝槽103以及質量塊105，因而可作為一微機電系統加速器，透過該懸掛結構內設置的壓電層在接收到聲波或電訊號時產生相應的振動，並透過質量塊105調整該懸掛結構，使得該懸掛結構具有能符合所需感測之音頻範圍的共振頻率。值得注意的是，本實施例的質量塊105由一部份的基底100製成，因而具有與基底100相同的材質以及與基底100相比較小的尺寸，使得質量塊105的厚度T2’遠比基底100的厚度T1來得薄，例如是約為基底100的厚度T1的1/4至1/8。如此，本發明中具有微型化質量塊105的微機電裝置能夠應用於無線藍芽耳機，從而輔助麥克風的語音振動。 Thus, the MEMS device in the first embodiment of the present invention can be formed. In this embodiment, the MEMS device includes the suspension structure, the groove 103 and the proof mass 105 arranged in the suspension region 210 of the interconnection structure 200, so it can be used as a MEMS accelerator. The piezoelectric layer generates corresponding vibrations when receiving sound waves or electrical signals, and adjusts the suspension structure through the mass block 105, so that the suspension structure has a resonant frequency that can meet the audio frequency range required for sensing. It is worth noting that the mass block 105 of this embodiment is made of a part of the base 100, so it has the same material as the base 100 and has a smaller size than the base 100, so that the thickness T2' of the mass block 105 is much smaller than that of the base 100. The thickness T1 of the substrate 100 is relatively thin, for example, about 1/4 to 1/8 of the thickness T1 of the substrate 100 . In this way, the MEMS device with the miniaturized mass 105 of the present invention can be applied to wireless bluetooth earphones, thereby assisting the voice vibration of the microphone.

本領域具通常知識者也應了解，本發明的微機電裝置及其形成方法並不限於前述，而可具有其他態樣或變化。下文將針對本發明微機電裝置及其形成方法的其他實施例或變化型進行說明。且為簡化說明，以下說明主要針對各實施例不同之處進行詳述，而不再對相同之處作重覆贅述。此外，本發明之各實施例中相同之元件係以相同之標號進行標示，以利於各實施例間互相對照。 Those skilled in the art should also understand that the MEMS device and its forming method of the present invention are not limited to the foregoing, but may have other forms or changes. Other embodiments or variants of the MEMS device and its forming method of the present invention will be described below. And to simplify the description, the following description mainly focuses on the differences of the various embodiments, and the similarities will not be repeated. In addition, the same elements in the various embodiments of the present invention are marked with the same reference numerals to facilitate mutual comparison between the various embodiments.

本發明的另一實施例中另提供了一種微機電裝置及其形成方法，以進一步改善溝槽尺寸或質量塊尺寸的準確性，並且，還能使得該質量塊在該溝槽內的設置定位可更為精確。由於本發明是透過一次性的蝕刻製程直接自基底100的第二表面102部分移除基底100至一定深度，一次性地形成深度約達300微米至350微米的溝槽，所以在某些情況下，當在形成如第4圖以及第5圖所示的溝槽103以及質量塊105時，溝槽103的尺寸或大小可能會在該蝕刻製程中產生明顯的變異。所形成的溝槽103可能會形成如第4圖以及第5圖所示的傾斜側壁，而該傾斜側壁之傾斜角度的變化則會導致溝槽103之開口103a的尺寸變異。舉例來說，若是溝槽103側壁的傾斜角度相差到1度，則溝槽103之開口103a在基底100的第一表面101處的孔徑則會相差到10微米以上，如此可能會衍生靈敏度不佳或感測準確性較差等問題。另一方面，質量塊105的厚度T2’減少有時亦可能導致感測準確性降低的問題。若是質量塊105損失的厚度過大，或是其損失的厚度無法一致，則依據下方的公式(I)，該微機電裝置的最小感測訊號(a_min)也會因此變化。在此情況下，由前述形成方法所獲得的微機電裝置將面臨溝槽或質量塊尺寸變異而不具一致性的衝擊，無法有效率地進行大規模的量產。公式(I)：

，其中，κ_B為博爾茨曼常數(Boltzmann’s constant)；T為絕對溫度；ω ₀為共振頻率；m_i為感測器的質量；Q為質量係數。 In another embodiment of the present invention, a microelectromechanical device and its forming method are provided to further improve the accuracy of the size of the groove or the size of the mass block, and also enable the setting and positioning of the mass block in the groove Can be more precise. Since the present invention directly removes the substrate 100 to a certain depth from the second surface 102 of the substrate 100 through a one-time etching process, a trench with a depth of about 300 microns to 350 microns is formed at one time, so in some cases , when forming the groove 103 and the proof mass 105 as shown in FIG. 4 and FIG. 5 , the size or size of the groove 103 may vary significantly during the etching process. The formed trench 103 may form inclined sidewalls as shown in FIG. 4 and FIG. 5 , and the variation of the inclination angle of the inclined sidewall will cause the size variation of the opening 103 a of the trench 103 . For example, if the inclination angles of the sidewalls of the trenches 103 differ by 1 degree, the apertures of the openings 103a of the trenches 103 at the first surface 101 of the substrate 100 will differ by more than 10 microns, which may lead to poor sensitivity. Or problems such as poor sensing accuracy. On the other hand, the reduction of the thickness T2 ′ of the proof mass 105 may sometimes lead to the problem of reduced sensing accuracy. If the lost thickness of the mass block 105 is too large, or the lost thickness is inconsistent, according to the following formula (I), the minimum sensing signal (a _min ) of the MEMS device will also change accordingly. In this case, the micro-electro-mechanical device obtained by the above-mentioned forming method will face the impact of variation and inconsistency in the size of the groove or the proof mass, and cannot be mass-produced efficiently. Formula (I):

, where, κ _B is Boltzmann's constant (Boltzmann's constant); T is the absolute temperature; ω ₀ is the resonant frequency; _mi is the quality of the sensor; Q is the quality coefficient.

請參照第6圖至第8圖所示，其繪示本發明第二實施例中微機電裝置的形成方法的示意圖。本實施例的形成方法在步驟上大體上與前述實施例相似，而相似之處容不再贅述。而本實施例與前述實施例之間的主要區別在於，本實施例係提供一矽覆絕緣基底 (silicon-on-insulator substrate,SOIsubstrate)300來形成該微機電裝置。 Please refer to FIG. 6 to FIG. 8 , which are schematic diagrams illustrating the method for forming the MEMS device in the second embodiment of the present invention. The steps of the forming method of this embodiment are generally similar to those of the foregoing embodiments, and the similarities will not be repeated here. The main difference between this embodiment and the preceding embodiments is that this embodiment provides a silicon-covered insulating substrate (silicon-on-insulator substrate, SOI substrate) 300 to form the MEMS device.

如第6圖所示，首先，提供一矽覆絕緣基底300，其進一步包含由下而上依序堆疊的一第一半導體層311、一絕緣層313、以及一第二半導體層315，其中，第一半導體層311以及第二半導體層315例如包含單晶矽、多晶矽、非晶矽或其他合適的材質等，而絕緣層313則例如包含氧化矽或二氧化矽等材質。具體來說，矽覆絕緣基底300的厚度T1同樣可約為400微米至500微米，其中，第一半導體層311的厚度T3例如是約為350微米至400微米，而第二半導體層315的厚度T2則約為50微米至100微米，但不以此為限。在一實施例中，矽覆絕緣基底300可經由以下方式形成。首先，分別氧化兩半導體層(未繪示)的表面、再黏合該兩半導體層的氧化表面、並將該兩半導體層的其中之一薄化至一定厚度，該厚度例如約為50微米至100微米，但不以此為限。較佳地，第二半導體層315的厚度T2可等同於後續所形成之質量塊的預定厚度，如50微米等，但不以此為限。本領域者應可輕易理解前述第二半導體層315的厚度還可進一步依據實際產品所需的感測靈敏度而調整(依據前述的公式(I))，不以前述數值為限。 As shown in FIG. 6, first, a silicon-covered insulating substrate 300 is provided, which further includes a first semiconductor layer 311, an insulating layer 313, and a second semiconductor layer 315 stacked sequentially from bottom to top, wherein, The first semiconductor layer 311 and the second semiconductor layer 315 include, for example, monocrystalline silicon, polycrystalline silicon, amorphous silicon, or other suitable materials, while the insulating layer 313 includes, for example, silicon oxide or silicon dioxide. Specifically, the thickness T1 of the silicon-covered insulating substrate 300 can also be about 400 microns to 500 microns, wherein the thickness T3 of the first semiconductor layer 311 is, for example, about 350 microns to 400 microns, and the thickness of the second semiconductor layer 315 T2 is about 50 microns to 100 microns, but not limited thereto. In one embodiment, the silicon-covered insulating substrate 300 can be formed in the following manner. First, respectively oxidize the surfaces of the two semiconductor layers (not shown), then bond the oxidized surfaces of the two semiconductor layers, and thin one of the two semiconductor layers to a certain thickness, such as about 50 microns to 100 microns. microns, but not limited thereto. Preferably, the thickness T2 of the second semiconductor layer 315 may be equal to the predetermined thickness of the subsequently formed proof mass, such as 50 microns, but not limited thereto. Those skilled in the art should easily understand that the thickness of the aforementioned second semiconductor layer 315 can be further adjusted according to the sensing sensitivity required by the actual product (according to the aforementioned formula (I)), and is not limited to the aforementioned value.

此外，矽覆絕緣基底300具有兩相對表面，例如是如第6圖所示的第一表面301以及第二表面302。第一表面301上還依序形成有一氧化層320以及一互連結構200。氧化層320較佳係包含與絕緣層313具相同的蝕刻選擇比的材質，如氧化矽或二氧化矽等，但不限於此，並且，氧化層320與絕緣層313還可具有相同的厚度。接著，於互連結構200 的頂表面上形成一保護層330，以保護設置在互連結構200內的元件，而保護層330可同樣包含氧化矽或二氧化矽等材質。需注意的是，關於本實施例中互連結構200的細部特徵大體上與前述第一實施例相同，容不再贅述。而另需注意的是，矽覆絕緣基底300的絕緣層313內還設置有一開口313a以及一圖案313b，而開口313a以及圖案313b的設置位置均對應於互連結構200的懸掛區域210，如第6圖所示。其中，開口313a係用於定義後續製程中所欲形成的一溝槽，故開口313a的尺寸較佳為該溝槽的預定尺寸，例如是約為100微米至150微米，但不以此為限。而圖案313b則是設置在開口313a之內，用於定義後續製程中所欲形成的一質量塊的形成位置，故圖案313b的尺寸較佳為該質量塊的預定尺寸。換言之，本實施例係將前述實施例中用來定義溝槽103之第一遮罩層120的開口120a以及用來定義質量塊105之第二遮罩層140的圖案140a整合於一單一膜層中，即整合於矽覆絕緣基底300的絕緣層313內。並且，在本實施例中，用於形成該溝槽以及該質量塊的遮罩層是在其他元件(如互連結構200或氧化層320等)形成之前即預先形成，其形成的時機點甚至早在將兩半導體層(第一半導體層311以及第二半導體層315)相互黏合成矽覆絕緣基底300之前。在一實施例中，矽覆絕緣基底300的絕緣層313可經由以下方式形成，首先，氧化兩半導體層(未繪示)的表面、接著，將該兩半導體層的氧化表面圖案化、最後，黏合該兩半導體層的該氧化表面而形成矽覆絕緣基底300。 In addition, the silicon-covered insulating substrate 300 has two opposite surfaces, such as a first surface 301 and a second surface 302 as shown in FIG. 6 . An oxide layer 320 and an interconnection structure 200 are also sequentially formed on the first surface 301 . The oxide layer 320 is preferably made of a material having the same etching selectivity as the insulating layer 313 , such as silicon oxide or silicon dioxide, but not limited thereto, and the oxide layer 320 and the insulating layer 313 may also have the same thickness. Next, in the interconnection structure 200 A protective layer 330 is formed on the top surface of the interconnection structure 200 to protect the components disposed in the interconnection structure 200, and the protective layer 330 may also include materials such as silicon oxide or silicon dioxide. It should be noted that the detailed features of the interconnection structure 200 in this embodiment are generally the same as those in the first embodiment, and will not be repeated here. It should also be noted that an opening 313a and a pattern 313b are disposed in the insulating layer 313 of the silicon-covered insulating substrate 300, and the positions of the opening 313a and the pattern 313b are corresponding to the suspension region 210 of the interconnection structure 200, as shown in the first 6 as shown in Fig. Wherein, the opening 313a is used to define a groove to be formed in the subsequent manufacturing process, so the size of the opening 313a is preferably the predetermined size of the groove, for example, about 100 microns to 150 microns, but not limited thereto . The pattern 313b is disposed in the opening 313a and is used to define the formation position of a mass to be formed in the subsequent process, so the size of the pattern 313b is preferably the predetermined size of the mass. In other words, this embodiment integrates the opening 120a of the first mask layer 120 used to define the trench 103 and the pattern 140a of the second mask layer 140 used to define the mass 105 in the previous embodiments into a single film layer , that is integrated in the insulating layer 313 of the silicon-covered insulating substrate 300 . Moreover, in this embodiment, the mask layer used to form the trench and the mass is pre-formed before other components (such as the interconnection structure 200 or the oxide layer 320, etc.) are formed, and the timing of its formation is even Before the two semiconductor layers (the first semiconductor layer 311 and the second semiconductor layer 315 ) are bonded together to form the insulating substrate 300 covered with silicon. In one embodiment, the insulating layer 313 of the silicon-covered insulating substrate 300 can be formed in the following manner. First, the surfaces of the two semiconductor layers (not shown) are oxidized, then, the oxidized surfaces of the two semiconductor layers are patterned, and finally, The oxidized surfaces of the two semiconductor layers are bonded to form a silicon-covered insulating substrate 300 .

然後，在矽覆絕緣基底300的第二表面302上形成一遮罩層340，遮罩層340具有可對應於懸掛區域210的一開口(未繪示)，以用於在矽覆絕緣基底300內形成一溝槽。在一實施例中，該開口的尺寸可約為100微米至150微米，但不以此為限。遮罩層340例如包含氧化矽或二氧化矽等材質，但不以此為限，而在另一實施例中，遮罩層340亦可選擇包含其他合適的材質。 Then, a mask layer 340 is formed on the second surface 302 of the silicon-covered insulating substrate 300. The mask layer 340 has an opening (not shown) corresponding to the suspension region 210 for forming the silicon-covered insulating substrate 300. A groove is formed in it. In one embodiment, the size of the opening can be About 100 microns to 150 microns, but not limited thereto. The mask layer 340 includes materials such as silicon oxide or silicon dioxide, but is not limited thereto. In another embodiment, the mask layer 340 may also include other suitable materials.

接著，如第7圖所示，透過遮罩層340進行一蝕刻製程，例如是一非等向性乾蝕刻製程，自矽覆絕緣基底300的背側即第二表面302的所在側部分移除矽覆絕緣基底300至一預定深度，直到暴露氧化層320或是下方絕緣層313的圖案313b。換言之，該蝕刻製程是利用氧化層320以及絕緣層313作為一蝕刻停止層，而在矽覆絕緣基底300內形成溝槽303，使得溝槽303可延伸於矽覆絕緣基底300的兩相對表面(第一表面301以及第二表面302)之間，並對應於設置在第一表面301上之互連結構200的懸掛區域210。由此，溝槽303即可具有與矽覆絕緣基底300的厚度T1相同的一深度，而溝槽303在鄰接懸掛區域210的底面處則具有一開口303a，並且，開口303a的尺寸可準確地控制在100微米至150微米左右。同時，在進行該蝕刻製程時，因一部分的第二半導體層315係被遮擋於絕緣層313的圖案313b之下，該部分即可在溝槽303內形成一質量塊305，如第7圖所示。在此設置下，質量塊305的厚度T2(約為50微米至100微米)則可透過第二半導體層315的厚度T2準確地控制，並且，質量塊305的設置位置亦可透過圖案313b在絕緣層313內的位置而一併準確地控制。 Next, as shown in FIG. 7 , an etching process, such as an anisotropic dry etching process, is performed through the mask layer 340 to partially remove the back side of the silicon-covered insulating substrate 300 , that is, the side where the second surface 302 is located. The silicon-covered insulating substrate 300 reaches a predetermined depth until the oxide layer 320 or the pattern 313b of the underlying insulating layer 313 is exposed. In other words, the etching process uses the oxide layer 320 and the insulating layer 313 as an etching stop layer to form the trench 303 in the silicon-covered insulating substrate 300, so that the trench 303 can extend on two opposite surfaces of the silicon-covered insulating substrate 300 ( Between the first surface 301 and the second surface 302 ), and corresponding to the suspension region 210 of the interconnection structure 200 disposed on the first surface 301 . Thus, the trench 303 can have the same depth as the thickness T1 of the silicon-covered insulating substrate 300, and the trench 303 has an opening 303a at the bottom surface adjacent to the suspension region 210, and the size of the opening 303a can be precisely Control it at about 100 microns to 150 microns. At the same time, when performing the etching process, since a part of the second semiconductor layer 315 is shielded under the pattern 313b of the insulating layer 313, this part can form a mass block 305 in the trench 303, as shown in FIG. 7 Show. Under this setting, the thickness T2 of the proof mass 305 (approximately 50 microns to 100 microns) can be accurately controlled through the thickness T2 of the second semiconductor layer 315, and the position of the proof mass 305 can also be insulated through the pattern 313b. The position within the layer 313 is precisely controlled together.

後續，進行另一蝕刻製程，例如是一等向性濕蝕刻製程，以同時移除遮罩層340、圖案313b以及部分暴露的氧化層320，使得下方互連結構200的懸掛區域210的該底面可進一步被暴露出而與溝槽303 相連接，如第8圖所示。如此，質量塊305即是設置在懸掛區域210的該底面上，使得部分的氧化層320夾設在懸掛區域210以及質量塊305之間。需注意的是，在進行該另一蝕刻製程時，剩餘的氧化層320以及絕緣層313的側壁可一併稍微地被移除，從而形成如第8圖所示的底切部分321、313c。而後，則移除保護層330，以釋放互連結構200的懸掛區域210內的該懸掛結構，使得該懸掛結構的一側可不與矽覆絕緣基底300相連而呈現一端懸空的態樣，如第8圖所示。在一實施例中，保護層330可選擇在進行該等向性濕蝕刻製程時一併被移除，但並不限於此，在另一個實施例中，保護層330亦可以選擇單獨地透過另一蝕刻製程進行移除。 Subsequently, another etching process, such as an isotropic wet etching process, is performed to simultaneously remove the mask layer 340, the pattern 313b and the partially exposed oxide layer 320, so that the bottom surface of the suspension region 210 of the lower interconnection structure 200 is can be further exposed while the trench 303 connected as shown in Figure 8. In this way, the mass block 305 is disposed on the bottom surface of the suspension area 210 , so that part of the oxide layer 320 is sandwiched between the suspension area 210 and the mass block 305 . It should be noted that during the other etching process, the remaining oxide layer 320 and the sidewalls of the insulating layer 313 may be slightly removed together, thereby forming the undercut portions 321 and 313c as shown in FIG. 8 . Then, the protection layer 330 is removed to release the suspension structure in the suspension region 210 of the interconnection structure 200, so that one side of the suspension structure may not be connected to the silicon-covered insulating substrate 300, but one end is suspended, as shown in the first 8 is shown in Fig. In one embodiment, the protection layer 330 can be removed together during the isotropic wet etching process, but it is not limited thereto. In another embodiment, the protection layer 330 can also be selected to pass through another An etching process is used for removal.

由此，即可形成本發明第二實施例中的微機電裝置。在本實施例中，該微機電裝置包含設置在互連結構200的懸掛區域210內的懸掛結構、溝槽303以及質量塊305，同樣可作為一微機電系統加速器，透過該懸掛結構內設置的壓電層而在接收到聲波或電訊號能夠振動，並透過質量塊305調整該懸掛結構，使得該懸掛結構具有能符合所需感測之音頻範圍的共振頻率。值得說明的是，在本實施例中，用於定義溝槽303以及質量塊305的遮罩層等已在製程之初即預先整合於矽覆絕緣基底300的絕緣層313內，因而可更為準確地控制溝槽303以及質量塊305的尺寸，以及質量塊305在溝槽303內的設置位置等，進而改善該微機電裝置靈敏度以及感測準確度。此外本實施例的質量塊305同樣由部份的矽覆絕緣基底300製成，而具有與矽覆絕緣基底300(即矽覆絕緣基底300的第一半導體層311)相同的材質，以及與矽覆絕緣基底300相比較小的尺寸，例如是約為矽覆絕緣基底300的厚度T1的1/4至1/8。因此，本發明中具有微型化質量塊305的微機電裝置能夠應用於無線藍芽耳機，從而輔助麥克風的語音振動。 Thus, the MEMS device in the second embodiment of the present invention can be formed. In this embodiment, the MEMS device includes a suspension structure, a groove 303, and a mass 305 arranged in the suspension region 210 of the interconnection structure 200, which can also be used as a MEMS accelerator. The piezoelectric layer can vibrate upon receiving sound waves or electrical signals, and adjust the suspension structure through the mass block 305 so that the suspension structure has a resonant frequency that can meet the audio frequency range required for sensing. It is worth noting that in this embodiment, the mask layer used to define the trench 303 and the mass 305 has been pre-integrated in the insulating layer 313 of the silicon-covered insulating substrate 300 at the beginning of the manufacturing process, so that it can be more The size of the groove 303 and the mass block 305 , and the position of the mass block 305 in the groove 303 are accurately controlled, thereby improving the sensitivity and sensing accuracy of the MEMS device. In addition, the mass 305 of this embodiment is also made of part of the silicon-covered insulating substrate 300, and has the same material as the silicon-coated insulating substrate 300 (ie, the first semiconductor layer 311 of the silicon-covered insulating substrate 300), and the same material as the silicon-coated insulating substrate 300. The relatively small size of the insulating substrate 300 is, for example, about 1/4 to 1/8 of the thickness T1 of the insulating substrate 300 covered with silicon. Therefore, the MEMS device with the miniaturized mass 305 in the present invention can be applied to wireless bluetooth earphones, thereby assisting the voice vibration of the microphone.

整體來說，本發明提供了一種具有微型化檢測質量塊的微機電裝置，其中，該微機電裝置的質量塊係由一部份的基底所形成，從而可獲得與該基底相同的材料並具有與該基底相比較為微小的尺寸。該質量塊的尺寸約為該基底尺寸的1/4至1/8，因此，本發明中具有微型化檢測質量塊的該微機電裝置可應用於無線藍芽耳機，進而輔助麥克風的語音振動。 Generally speaking, the present invention provides a micro-electromechanical device with a miniaturized proof mass, wherein the mass of the micro-electromechanical device is formed by a part of the substrate, so that the same material as the substrate can be obtained and has Relatively small size compared to the substrate. The size of the proof mass is about 1/4 to 1/8 of the size of the substrate. Therefore, the MEMS device with a miniaturized proof mass in the present invention can be applied to a wireless bluetooth earphone, thereby assisting the voice vibration of the microphone.

以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100:基底 100: base

101:第一表面 101: First Surface

102:第二表面 102: second surface

103:溝槽 103: Groove

103a:開口 103a: opening

105:質量塊 105: mass block

110:氧化層 110: oxide layer

111:底切部分 111: Undercut part

200:互連結構 200: Interconnect structure

201:介電層 201: dielectric layer

203:金屬層 203: metal layer

205:連接墊 205: connection pad

207:穿孔 207: perforation

210:懸掛區域 210: Hanging area

T1:厚度 T1: Thickness

T2’:厚度 T2': Thickness

Claims

一種微機電裝置，包含：一基底，具有一第一表面以及相對於該第一表面的一第二表面；一溝槽，設置在該基底內，該溝槽延伸於該第一表面以及該第二表面之間；一互連結構，設置在該基底的該第一表面上，並且位在該溝槽的上方，該互連結構還包括一懸掛區域、以及設置於該懸掛區域內的一穿孔，該穿孔貫穿該互連結構；以及一質量塊，設置在該溝槽內並連接該互連結構，其中，該質量塊的延伸長度小於該懸掛區域的延伸長度，該質量塊鄰近該穿孔並位在該懸掛區域下方，該質量塊的厚度小於該基底的厚度，其中該質量塊包括鄰近該互連結構的一表面，且該質量塊的該表面切齊該基底的該第一表面。 A microelectromechanical device, comprising: a substrate having a first surface and a second surface opposite to the first surface; a groove disposed in the substrate, the groove extending on the first surface and the second surface Between the two surfaces; an interconnection structure disposed on the first surface of the substrate and above the trench, the interconnection structure also includes a suspension area and a through hole disposed in the suspension area , the through hole runs through the interconnection structure; and a mass is arranged in the groove and connected to the interconnection structure, wherein the extension length of the mass block is less than the extension length of the suspension area, the mass block is adjacent to the through hole and Located below the suspension region, the proof-mass has a thickness smaller than the substrate, wherein the proof-mass includes a surface adjacent to the interconnection structure, and the surface of the proof-mass is flush with the first surface of the substrate.

如申請專利範圍第1項所述的微機電裝置，其中該基底包含一塊狀矽基底，該質量塊的材質與該塊狀矽基底的材質相同。 The MEMS device described in item 1 of the scope of the patent application, wherein the substrate includes a monolithic silicon substrate, and the material of the mass is the same as that of the monolithic silicon substrate.

如申請專利範圍第1項所述的微機電裝置，其中該基底包含一矽覆絕緣基底，該矽覆絕緣基底包含由下而上堆疊的一第一半導體層、一絕緣層以及一第二半導體層，該質量塊的材質與該第二半導體層的材質相同。 The micro-electromechanical device as described in item 1 of the scope of application, wherein the substrate comprises a silicon-coated insulating substrate, and the silicon-coated insulating substrate comprises a first semiconductor layer, an insulating layer and a second semiconductor layer stacked from bottom to top layer, the mass block is made of the same material as the second semiconductor layer.

如申請專利範圍第3項所述的微機電裝置，其中該質量塊的厚度與該第二半導體層的厚度相同。 The micro-electro-mechanical device as described in claim 3, wherein the thickness of the proof mass is the same as the thickness of the second semiconductor layer.

如申請專利範圍第3項所述的微機電裝置，其中該溝槽的深度大於該質量塊的厚度。 The micro-electro-mechanical device described in claim 3 of the patent application, wherein the depth of the groove is greater than the thickness of the proof mass.

如申請專利範圍第1項所述的微機電裝置，其中該懸掛區域的設置位置係對應該溝槽以及該質量塊。 The micro-electro-mechanical device described in item 1 of the scope of the patent application, wherein the suspension area is located corresponding to the groove and the mass block.

一種微機電裝置的形成方法，包含：提供一基底，該基底具有一第一表面以及相對於該第一表面的一第二表面；於該基底內形成一溝槽，該溝槽延伸於該第一表面以及該第二表面之間；於該基底的該第一表面上形成一互連結構，該互連結構位在該溝槽的上方，該互連結構還包括一懸掛區域、以及設置於該懸掛區域內的一穿孔，該穿孔貫穿該互連結構；以及於該溝槽內形成一質量塊，該質量塊連接該互連結構、鄰近該穿孔並位在該懸掛區域下方，其中，該質量塊的延伸長度小於該懸掛區域的延伸長度，該質量塊的厚度小於該基底的厚度，其中該質量塊包括鄰近該互連結構的一表面，且該質量塊的該表面切齊該基底的該第一表面。 A method for forming a microelectromechanical device, comprising: providing a substrate, the substrate having a first surface and a second surface opposite to the first surface; forming a groove in the substrate, the groove extending on the first surface Between a surface and the second surface; an interconnection structure is formed on the first surface of the substrate, the interconnection structure is located above the groove, the interconnection structure also includes a suspension area, and is disposed on a through hole in the suspension region, the through hole passing through the interconnection structure; and forming a mass in the trench, the mass connected to the interconnection structure, adjacent to the through hole and below the suspension region, wherein the The extension length of the mass is less than the extension length of the suspension region, the thickness of the mass is less than the thickness of the substrate, wherein the mass includes a surface adjacent to the interconnect structure, and the surface of the mass is flush with the substrate the first surface.

如申請專利範圍第7項所述的微機電裝置的形成方法，其中還包含：於該互連結構形成之前，於該第一表面上形成一氧化層，該氧化層介於該互連結構以及該基底之間；以及於該溝槽以及該質量塊形成之後，移除該氧化層，以部分暴露該互連結構的一底面。 The method for forming a MEMS device as described in item 7 of the scope of the patent application, further comprising: before forming the interconnection structure, forming an oxide layer on the first surface, the oxide layer between the interconnection structure and the substrate; and after the trench and the mass block are formed, removing the oxide layer to partially expose a bottom surface of the interconnection structure.

如申請專利範圍第8項所述的微機電裝置的形成方法，其中於該溝槽以及該質量塊形成之後，移除一部份位在該互連結構以及該質量塊之間的該氧化層。 The method for forming a MEMS device as described in claim 8, wherein after the formation of the trench and the proof mass, a part of the oxide layer located between the interconnection structure and the proof mass is removed .

如申請專利範圍第7項所述的微機電裝置的形成方法，其中該基底包含一塊狀矽基底，該微機電裝置的形成方法還包含：於該第二表面上形成一第一遮罩層，該第一遮罩層包含一開口，以定義該溝槽；以及於該第二表面上形成一第二遮罩層，該第二遮罩層包含一圖案，以定義該質量塊，該圖案位在該開口內。 The method for forming a microelectromechanical device as described in item 7 of the scope of the patent application, wherein the substrate comprises a monolithic silicon substrate, and the method for forming a microelectromechanical device further includes: forming a first mask layer on the second surface , the first mask layer includes an opening to define the groove; and a second mask layer is formed on the second surface, the second mask layer includes a pattern to define the proof mass, the pattern inside the opening.

如申請專利範圍第10項所述的微機電裝置的形成方法，其中該圖案直接形成在該第二表面上。 The method for forming a MEMS device as described in claim 10, wherein the pattern is directly formed on the second surface.

如申請專利範圍第10項所述的微機電裝置的形成方法，其中還包含：透過該第一遮罩層以及該第二遮罩層，於該第二表面上進行一第一蝕刻製程；於該第一蝕刻製程進行之後，移除該第二遮罩層；以及透過該第一遮罩層，於該第二表面上進行一第二蝕刻製程，形成該溝槽以及該質量塊。 The method for forming a MEMS device as described in item 10 of the patent scope, further comprising: performing a first etching process on the second surface through the first mask layer and the second mask layer; After the first etching process is performed, the second mask layer is removed; and through the first mask layer, a second etching process is performed on the second surface to form the Groove and the quality block.

如申請專利範圍第12項所述的微機電裝置的形成方法，其中該質量塊由該塊狀矽基底的一部份所形成。 The method for forming a MEMS device as described in claim 12, wherein the proof mass is formed by a part of the bulk silicon substrate.

如申請專利範圍第7項所述的微機電裝置的形成方法，其中該基底包含一矽覆絕緣基底，該矽覆絕緣基底包含由下而上堆疊的一第一半導體層、一絕緣層以及一第二半導體層。 The method for forming a micro-electromechanical device as described in item 7 of the scope of the patent application, wherein the substrate includes a silicon-covered insulating substrate, and the silicon-coated insulating substrate includes a first semiconductor layer, an insulating layer, and a stacked from bottom to top second semiconductor layer.

如申請專利範圍第14項所述的微機電裝置的形成方法，其中還包含：於該互連結構形成之前，於該絕緣層內形成一開口以及一圖案。 The method for forming a MEMS device as described in claim 14 of the patent scope further includes: before forming the interconnection structure, forming an opening and a pattern in the insulating layer.

如申請專利範圍第15項所述的微機電裝置的形成方法，其中還包含：利用該絕緣層內的該圖案作為一蝕刻遮罩，形成該質量塊；以及利用該絕緣層內的該開口，形成該溝槽的一部分。 The method for forming a MEMS device as described in claim 15 of the patent application, further comprising: using the pattern in the insulating layer as an etching mask to form the proof mass; and using the opening in the insulating layer, forming part of the trench.

如申請專利範圍第15項所述的微機電裝置的形成方法，其中還包含：於該質量塊形成之後，移除該絕緣層內的該圖案。 The method for forming a micro-electromechanical device as described in claim 15 of the patent claims further includes: after the proof mass is formed, removing the pattern in the insulating layer.

如申請專利範圍第15項所述的微機電裝置的形成方法，其中該質量塊由該第二半導體層的一部分所形成。 The method for forming a MEMS device as described in claim 15, wherein the proof mass is formed by a part of the second semiconductor layer.

如申請專利範圍第14項所述的微機電裝置的形成方法，其中該質量塊的厚度與該第二半導體層的厚度相同。 The method for forming a MEMS device as described in claim 14, wherein the thickness of the proof mass is the same as the thickness of the second semiconductor layer.

如申請專利範圍第7項所述的微機電裝置的形成方法，其中更包含：於該溝槽形成之前，形成一保護層覆蓋該互連結構並填入該穿孔；以及完全移除該保護層，以在該溝槽形成之後釋放該互連結構。 The method for forming a MEMS device as described in claim 7 of the patent application, further comprising: before forming the trench, forming a protective layer covering the interconnection structure and filling the through hole; and completely removing the protective layer , to release the interconnect structure after the trench is formed.