TWI791495B - 化合物半導體基板 - Google Patents

化合物半導體基板 Download PDF

Info

Publication number
TWI791495B
TWI791495B TW107108976A TW107108976A TWI791495B TW I791495 B TWI791495 B TW I791495B TW 107108976 A TW107108976 A TW 107108976A TW 107108976 A TW107108976 A TW 107108976A TW I791495 B TWI791495 B TW I791495B
Authority
TW
Taiwan
Prior art keywords
layer
gan
nitride semiconductor
aln
layers
Prior art date
Application number
TW107108976A
Other languages
English (en)
Other versions
TW201843711A (zh
Inventor
生川満久
大內澄人
鈴木悠宜
川村啓介
Original Assignee
日商愛沃特股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商愛沃特股份有限公司 filed Critical 日商愛沃特股份有限公司
Publication of TW201843711A publication Critical patent/TW201843711A/zh
Application granted granted Critical
Publication of TWI791495B publication Critical patent/TWI791495B/zh

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/02433Crystal orientation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02441Group 14 semiconducting materials
    • H01L21/02447Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02455Group 13/15 materials
    • H01L21/02458Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02505Layer structure consisting of more than two layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02505Layer structure consisting of more than two layers
    • H01L21/02507Alternating layers, e.g. superlattice
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02529Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/207Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049Nitrides composed of metals from groups of the periodic table
    • H01L2924/050313th Group
    • H01L2924/05032AlN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/1033Gallium nitride [GaN]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Recrystallisation Techniques (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

本發明係一種化合物半導體基板,其中,化合物半導體基板係具備:SiC(碳化矽)層,和形成於SiC層上之AlN (氮化鋁)緩衝層,和形成於AlN緩衝層上,含有Al(鋁)之氮化物半導體層,和形成於Al氮化物半導體層上的複合層,和形成於複合層上之作為電子行走層之GaN(氮化鎵)層,和形成於GaN層上之作為障壁層之Al氮化物半導體層。複合層係包含:層積於上下方向之複數的C-GaN層,和形成於複數之C-GaN層之間的AlN層。

Description

化合物半導體基板
本發明係有關化合物半導體基板,對於更特定而言,係有關具備SiC(碳化矽)層之化合物半導體基板。
GaN(氮化鎵)係作為比較於Si(矽)而能隙為大,絕緣破壞電場強度為高之寬能隙半導體材料而被知道。GaN係因與其他的寬能隙半導體材料作比較,因亦具有高耐絕緣破壞性之故,期待有對於新世代之低損失的功率裝置之適用。
對於使用GaN之半導體裝置的開端基板(基底基板),使用Si基板之情況,因GaN與Si之間的晶格常數及熱膨脹係數之大的差引起,而容易引起對於基板產生彎曲,以及對於GaN層內產生斷裂之現象。
作為基板的彎曲或對於GaN層內之斷裂的產生對策,例如,對於下述專利文獻1等,係加以揭示有具備:Si基板,和加以形成於Si基板上之3C-SiC層,和加以交互形成之複數的AlN層(氮化鋁)及GaN層之半導體基板。
具備以往之GaN層的半導體基板係亦加以揭示於下述專利文獻2及3等。對於下述專利文獻2係加以揭示有具備:SiC所成之基板,和形成於基板上之AlN所成之核生成層,和形成於核生成層上之AlGaN(氮化鋁鎵)所成之傾斜層,和形成於傾斜層上之GaN所成之氮化物層的半導體構造。
對於下述專利文獻3係加以揭示有具有:基板,和基板上之緩衝層,和緩衝層上之氮化物系半導體所成,包含過渡金屬及碳的高阻抗層,和高阻抗層上之氮化物系半導體所成之通道層的半導體基板。高阻抗層係具有接觸於通道層之同時,自緩衝層側朝向通道層側,過渡金屬的濃度則減少之減少層。朝向碳濃度的通道層而減少之減少率係較朝向於過渡金屬的濃度之通道層而減少之減少率為大。 [先前技術文獻] [專利文獻]
[專利文獻1] 日本特開2013-179121號公報   [專利文獻2] 日本特表2010-521065號公報   [專利文獻3] 日本特開2015-201574號公報
[發明欲解決之課題]
在專利文獻1等的技術中,可某種程度抑制基板的彎曲或對於GaN層內之斷裂的產生,而加以得到比較良好之結晶品質之GaN層。另一方面,對於專利文獻1等之技術中,對於GaN層的厚膜化有界限,而對於耐電壓,同樣地亦有界限。此係當將GaN層作為厚膜化時,因對於基板產生有彎曲,以及對於GaN層內產生有斷裂之故。當考慮作為GaN之功率裝置之用途時,提升使用GaN之半導體裝置的耐電壓者係為重要。
本發明係為了解決上述課題之構成,其目的為提供:具有所期望的品質之化合物半導體基板者。 為了解決課題之手段
依照本發明之一情勢之化合物半導體基板係具備:SiC層,和形成於SiC層上之AlN所成之緩衝層,和形成於緩衝層上,含有Al之氮化物半導體層,和形成於氮化物半導體層上的複合層,和形成於複合層上之GaN所成之電子行走層,和形成於電子行走層上之障壁層,而複合層係包含:層積於上下方向,含有碳之GaN所成之複數的第1層,和形成於各複數第1層之間的AlN所成之第2層。
在上述化合物半導體基板中,理想為各複數之第1層係具有1×1018 個/cm3 以上1×1021 個/cm3 以下之平均碳原子濃度。
在上述化合物半導體基板中,理想為第2層係具有10nm以上15nm以下之厚度。
在上述化合物半導體基板中,理想為第1層係具有550nm以上2000nm以下之厚度。
在上述化合物半導體基板中,理想係在氮化物半導體層內部之Al的組成比係隨著自下部朝向上部而減少。
在上述化合物半導體基板中,理想為氮化物半導體層係包含:含有Al及Ga之第1氮化物半導體層,和接觸於第1氮化物半導體層而加以形成於第1氮化物半導體層上,含有Al之第2氮化物半導體層,和接觸於第2氮化物半導體層而加以形成於第2氮化物半導體層上,含有Al及Ga之第3氮化物半導體層;在第1及第3氮化物半導體層之中至少任一方的層內部之Al的組成比係隨著自下部朝向上部而減少。
在上述化合物半導體基板中,理想為複數之第1層之中,形成於第2層上之第1層係包含壓縮偏差。
在上述化合物半導體基板中,理想係氮化物半導體層係具有900nm以上2μm以下之厚度。 發明效果
如根據本發明,可提供具有所期望品質之化合物半導體基板。
以下,對於本發明之實施形態,依據圖面而加以說明。
[第1實施形態]
圖1係顯示在本發明之第1實施形態的化合物半導體基板CS1之構成的剖面圖。
參照圖1,在本實施形態之化合物半導體基板CS1係包含HEMT(High Electron Mobility Transistor)。化合物半導體基板CS1係具備:Si基板1,和SiC層2,和AlN緩衝層3(AlN所成之緩衝層的一例),和Al氮化物半導體層4(含有Al之氮化物半導體層之一例),和複合層5,和GaN層7(電子行走層之一例),和Al氮化物半導體層10(障壁層之一例)。
Si基板1係例如由p+ 型之Si所成。對於Si基板1表面係露出有(111)面。然而,Si基板1係具有n型之導電型亦可,而亦可為半絕緣性。對於Si基板1表面係露出有(100)面或(110)面亦可。Si基板1係例如具有6英吋直徑,具有900μm之厚度。
SiC層2係接觸於Si基板1,而加以形成於Si基板1上。SiC層2係例如,由3C-SiC、4H-SiC、或6H-SiC等而成。特別是,SiC層2則為加以磊晶成長於Si基板1之情況,一般而言,SiC層2係由3C-SiC而成。
SiC層2係於由碳化Si基板1之表面者而加以得到之SiC所成之基底層上,使用MBE(Molecular Beam Epitaxy)法、CVD(Chemical Vapor Deposition)法、或LPE (Liquid Phase Epitaxy)法等,經由使SiC加以同質磊晶成長之時而加以形成亦可。SiC層2係僅經由碳化Si基板1的表面而加以形成亦可。更且,SiC層2係於Si基板1表面,經由(或夾持緩衝層)使其異質磊晶成長之時而加以形成亦可。SiC層2係例如,加以摻雜N(氮)等,具有n型之導電型。SiC層2係例如,具有0.1μm以上3.5μm以下之厚度。然而,SiC層2係具有p型之導電型亦可,而亦可為半絕緣性。
AlN緩衝層3係接觸於SiC層2,而加以形成於SiC層2上。AlN緩衝層3係達成作為緩和SiC層2與Al氮化物半導體層4之晶格常數的差之緩衝層的機能。AlN緩衝層3係例如,使用MOCVD(Metal Organic Chemical Vapor Deposition)法而加以形成。AlN緩衝層3之成長溫度係例如,加以作為1000℃以上1300℃以下。此時,作為Al源氣體係例如,加以使用TMA(Tri Methyl Aluminium),或TEA (Tri Ethyl Aluminium)等。作為N源氣體係例如,使用NH3 (氨氣)。AlN緩衝層3係例如,具有100nm以上1000nm以下之厚度。
Al氮化物半導體層4係接觸於AlN緩衝層3,而加以形成於AlN緩衝層3上。Al氮化物半導體層4係由含有Al之氮化物半導體而成,例如由Alx Ga1-x N(0<x≦1)所表示之材料所成。另外,Al氮化物半導體層4係亦可由Alx Iny Ga1-x-y N(0<x≦1、0≦y<1)所表示之材料而成。Al氮化物半導體層4係達成作為緩和AlN緩衝層3與複合層5中之C-GaN層51a之晶格常數的差之緩衝層的機能。Al氮化物半導體層4係例如,具有500nm以上2μm以下、理想係900nm以上2μm以下之厚度。Al氮化物半導體層4係例如,使用MOCVD法而加以形成。
複合層5係接觸於Al氮化物半導體層4,而加以形成於Al氮化物半導體層4上。複合層5係包含:層積於上下方向(與Si基板1、SiC層2、AlN緩衝層、及Al氮化物半導體層4之層積方向相同方向、圖1中縱方向)之複數的C-GaN層,和形成於各複數之C-GaN層之間的AlN層。換言之,複合層5係具有僅1次以上次數加以交互層積C-GaN層與AlN層之構成,而複合層5的最上層及最下層係均為C-GaN層。C-GaN層係指包含C(碳)之GaN層(摻雜C之GaN層)。C係達成提高GaN層之絕緣性的作用。
構成複合層5之C-GaN層的層數係如2以上即可,而構成複合層5之AlN層的層數亦為任意。本實施形態的複合層5係作為C-GaN層,包含2層之C-GaN層51a及51b(複數之第1層的一例),和1層之AlN層52a(第2層之一例)。C-GaN層51a係構成複合層5的層之中,成為最下層,與Al氮化物半導體層4接觸。C-GaN層51b係構成複合層5的層之中,成為最上層,與GaN層7接觸。AlN層52a係加以形成於C-GaN層51a與C-GaN層51b之間。
構成複合層5的各複數之C-GaN層(在本實施形態中,C-GaN層51a及51b)係例如,具有1×1018 個/cm3 以上1×1021 個/cm3 以下之平均碳原子濃度,而理想為具有3×1018 個/cm3 以上2×1019 個/cm3 之平均碳濃度。構成複合層5的各複數之C-GaN層係具有同一之平均碳濃度亦可,而亦可具有相互不同之平均碳原子濃度。
另外,構成複合層5的各複數之C-GaN層係例如,具有550nm以上2000nm以下之厚度,而理想為具有800nm以上1500nm以下之厚度。構成複合層5的各複數之C-GaN層係具有同一厚度亦可,而亦可具有相互不同之厚度。
構成複合層5的AlN層(在本實施形態中,AlN層52a)係例如,具有10nm以上15nm以下之厚度。構成複合層5的AlN層為複數之情況,構成複合層5的各AlN層係具有同一厚度亦可,而亦可具有相互不同之厚度。
構成複合層5的C-GaN層51a及51b係例如,使用MOCVD法而加以形成。此時,作為Ga源氣體係例如,加以使用TMG(Tri Methyl Gallium),或TEG(Tri Ethyl Gallium)等。作為N源氣體係例如,使用NH3 等。構成複合層5的AlN層係以與AlN緩衝層3同樣的方法而加以形成。
對於在形成C-GaN層51a及51b時,由採用含於TMG的C則呈導入至GaN層之GaN的成長條件者,可摻雜C於GaN層中。作為摻雜C於GaN層中之具體的方法,係有降低GaN之成長溫度之方法,降低GaN之成長壓力的方法,或對於NH3 而言提高TMG之莫耳流量比的方法等。
然而,對於Al氮化物半導體層4與複合層5之間,係介入存在於未摻雜之GaN層等之其他的層亦可。
GaN層7係接觸於複合層5,而加以形成於複合層5上。GaN層7係未摻雜,而為半絕緣性。GaN層7係成為HEMT之電子行走層。GaN層7係例如,具有100nm以上1000nm以下之厚度。GaN層7係例如,使用MOCVD法而加以形成。此時,作為Ga源氣體係例如,加以使用TMG或TEG等。作為N源氣體係例如,使用NH3 等。
Al氮化物半導體層10係接觸於GaN層7,而加以形成於GaN層7上。Al氮化物半導體層10係由含有Al之氮化物半導體而成,例如由Alx Ga1-x N(0<x≦1)所表示之材料所成。另外,Al氮化物半導體層10係亦可由Alx Iny Ga1-x-y N (0<x≦1、0≦y<1)所表示之材料而成。Al氮化物半導體層10係成為HEMT之障壁層。Al氮化物半導體層10係例如,具有10nm以上50nm以下之厚度。Al氮化物半導體層10係以與Al氮化物半導體層4同樣的方法加以形成。
圖2係顯示本發明之第1實施形態之Al氮化物半導體層4內部之Al組成比的分布圖。
參照圖2,在Al氮化物半導體層4內部之Al組成比係隨著自下部朝向上部而減少。Al氮化物半導體層4係含有:Al0.75 Ga0.25 N層41(Al之組成比為0.75之AlGaN層),和Al0.5 Ga0.5 N層42(Al之組成比為0.5之AlGaN層),和Al0.25 Ga0.75 N層43(Al之組成比為0.25之AlGaN層)。Al0.75 Ga0.25 N層41係接觸於AlN緩衝層3,而加以形成於AlN緩衝層3上。Al0.5 Ga0.5 N層42係接觸於Al0.75 Ga0.25 N層41,而加以形成於Al0.75 Ga0.25 N層41上。Al0.25 Ga0.75 N層43係接觸於Al0.5 Ga0.5 N層42,而加以形成於Al0.5 Ga0.5 N層42上。然而,上述之Al組成比係為一例,Al組成比則如隨著自下部朝向上部而減少時,亦可作為其他的組成。
如根據本實施形態,在複合層5中,經由形成AlN層52a於C-GaN層51a與C-GaN層51b之間之時,可抑制Si基板1之彎曲的產生,而可抑制對於C-GaN層51b及GaN層7的斷裂之產生者。對與此等,於以下加以說明。
構成AlN層52a之AlN係對於構成C-GaN層51a之GaN的結晶而言,以不整合之狀態(產生滑動之狀態),磊晶成長於C-GaN層51a上。另一方面,構成C-GaN層51b及GaN層7之GaN係受到構成基底之AlN層52a的AlN之結晶的影響。即,構成C-GaN層51b及GaN層7之GaN係呈繼承構成AlN層52a之AlN的結晶構造地,磊晶成長於AlN層52a上。GaN之晶格常數係較AlN之晶格常數為大之故,構成GaN層51b之GaN之圖1中橫方向的晶格常數係成為較一般的(未含有壓縮偏差)GaN之晶格常數為小。換言之,C-GaN層51b及GaN層7係於其內部含有壓縮偏差。
對於C-GaN層51b及GaN層7形成後之降溫時,因GaN與Si之熱膨脹係數的差引起,C-GaN層51b及GaN層7係自AlN層52a受到應力。此應力係成為Si基板1彎曲之產生的原因,而成為對於C-GaN層51b及GaN層7之斷裂的產生原因。但此應力係經由在C-GaN層51b及GaN層7形成時,導入至C-GaN層51b及GaN層7內部之壓縮偏差而加以緩和。其結果,可抑制Si基板1彎曲之產生,而可抑制對於C-GaN層51b及GaN層7之斷裂的產生。
另外,化合物半導體基板CS1係包含:具有較GaN之絕緣破壊電壓為高之絕緣破壞電壓之C-GaN層51a及51b、AlN層52a、以及Al氮化物半導體層4。其結果,可提升化合物半導體基板之縱方向的耐電壓。
另外,如根據本實施形態,化合物半導體基板CS1則因含有Al氮化物半導體層4於AlN緩衝層3與複合層5中之C-GaN層51a之間之故,可緩和Si之晶格常數與GaN之晶格常數的差。Al氮化物半導體層4之晶格常數係因具有Si之晶格常數與GaN之晶格常數之間的值之故。其結果,可提升C-GaN層51a及51b之結晶品質者。其結果,可抑制Si基板1彎曲之產生,而可抑制對於C-GaN層51a及51b之斷裂的產生者。
另外,如根據本實施形態,如上述,因可加以抑制Si基板1彎曲之產生及對於C-GaN層51b及GaN層7之斷裂的產生之故,可將GaN層7作為厚膜化。
更且,化合物半導體基板CS1係作為C-GaN層51a及51b、以及GaN層7之基底層而包含SiC層2。SiC之晶格常數係因與Si之晶格常數比較而接近於與GaN之晶格常數之故,經由加以形成C-GaN層51a及51b,以及GaN層7於SiC層2上之時,可提升C-GaN層51a及51b,以及GaN層7之結晶品質者。
如上述根據本實施形態時,由劃分各Al氮化物半導體層4、複合層5、及SiC層2之機能者,可使各抑制Si基板1之彎曲的產生之效果,抑制對於C-GaN層51b及GaN層7之斷裂的產生之效果,提升化合物半導體基板CS1之耐電壓的效果,以及提升C-GaN層51a及51b、以及GaN層7之結晶品質的效果增大者。特別是在本實施形態中,由將SiC層2作為基底層者,可改善GaN層7之結晶品質的點之貢獻為大。
如根據本實施形態,有著SiC層2,經由、C-GaN層51a及51b、以及GaN層7之結晶品質所提升之時,可薄化複合層5中之AlN層之厚度,而可更有效率地抑制彎曲的產生及斷裂之產生。另外,有著SiC層2,經由C-GaN層51a之結晶品質所提升之時,可加厚、C-GaN層51a及51b、以及GaN層7之故,而可更改善耐電壓者。亦可提升HEMT之性能者。
[第2實施形態]
圖3係顯示在本發明之第2實施形態的化合物半導體基板CS2之構成的剖面圖。
參照圖3,在本實施形態之化合物半導體基板CS2係與在第1實施形態之化合物半導體基板CS1作比較,複合層5之內部的構成則為不同。具體而言,本實施形態的複合層5係作為C-GaN層,包含3層之C-GaN層51a、51b、及51c(複數之第1層的一例),和2層之AlN層52a及52b(第2層之一例)。C-GaN層51a係構成複合層5的層之中,成為最下層,與Al氮化物半導體層4接觸。AlN層52a係與C-GaN層51a接觸而形成於C-GaN層51a上。C-GaN層51b係與AlN層52a接觸而形成於AlN層52a上。AlN層52b係與C-GaN層51b接觸而形成於C-GaN層51b上。C-GaN層51c係與AlN層52b接觸而形成於AlN層52b上。C-GaN層51c係構成複合層5的層之中,成為最上層,與GaN層7接觸。
然而,上述以外之化合物半導體基板CS2的構成係因與第1實施形態的化合物半導體基板CS1之構成同樣之故,對於同一構件係附上同一符號,而未重複其說明。
如根據本實施形態,可得到與第1實施形態同樣的效果。加上,   因於複合層5中存在有2層之AlN層52a及52b之故,對於上層之GaN層51b及51c、以及GaN層7而言賦予壓縮偏差之效果則變大。其結果,可抑制Si基板1彎曲之產生,而可抑制對於C-GaN層51a、51b、及51c、以及GaN層7之斷裂的產生。
另外,因於複合層5中存在有2層之AlN層52a及52b之故,可提升化合物半導體基板之縱方向的耐電壓者。
[變形例]
在本變形例中,對於化合物半導體基板CS1及CS2之各Al氮化物半導體層4的變形例之構成加以說明。
圖4係顯示本發明之第1變形例之Al氮化物半導體層4內部之Al組成比的分布圖。
參照圖4,在本變形例的Al氮化物半導體層4係包含:AlGaN層4a(第1氮化物半導體層之一例),和AlN中間層44(第2氮化物半導體層之一例),和AlGaN層4b(第3氮化物半導體層之一例)。
AlGaN層4a係接觸於AlN緩衝層3,而加以形成於AlN緩衝層3上。AlGaN層4a係由Al0.75 Ga0.25 N層41(Al之組成比為0.75之AlGaN層)而成。在AlGaN層4a內部之Al之組成比係為一定。
AlN中間層44係加以形成於AlGaN層4a上。AlN中間層44之下面係接觸於AlGaN層4a之上面,而AlN中間層44之上面係接觸於AlGaN層4b之下面。
AlGaN層4b係加以形成於AlN中間層44上。在AlGaN層4b內部之Al的組成比係隨著自下部朝向上部之方向而減少。AlGaN層4b係經由Al0.5 Ga0.5 N層42(Al之組成比為0.5之AlGaN層),和接觸於Al0.5 Ga0.5 N層42而加以形成於Al0.5 Ga0.5 N層42上之Al0.25 Ga0.75 N層43(Al之組成比為0.25之AlGaN層)而加以構成。
圖5係顯示本發明之第2變形例之Al氮化物半導體層4內部之Al組成比的分布圖。
參照圖5,在本變形例的Al氮化物半導體層4係包含:AlGaN層4a(第1氮化物半導體層之一例),和AlN中間層44(第2氮化物半導體層之一例),和AlGaN層4b(第3氮化物半導體層之一例)。
AlGaN層4a係接觸於AlN緩衝層3,而加以形成於AlN緩衝層3上。在AlGaN層4a內部之Al的組成比係隨著自下部朝向上部之方向而減少。AlGaN層4a係經由Al0.75 Ga0.25 N層41(Al之組成比為0.75之AlGaN層),和接觸於Al0.75 Ga0.25 N層41而加以形成於Al0.75 Ga0.25 N層41上之Al0.5 Ga0.5 N層42(Al之組成比為0.5之AlGaN層)而加以構成。
AlN中間層44係加以形成於AlGaN層4a上。AlN中間層44之下面係接觸於AlGaN層4a之上面,而AlN中間層44之上面係接觸於AlGaN層4b之下面。
AlGaN層4b係加以形成於AlN中間層44上。AlGaN層4b係由Al0.25 Ga0.75 N層43(Al之組成比為0.25之AlGaN層)而成。在AlGaN層4b內部之Al之組成比係為一定。
然而,在第1及第2變形例之各化合物半導體基板之上述以外的構成係與上述實施形態情況之構成同樣之故,不重覆其說明。
AlN中間層44係達成使壓縮偏差產生於AlGaN層4b之機能。如第1及第2變形例,由設置AlN中間層44者,更可抑制彎曲或斷裂。
[實施例]
本申請發明者係製造作為試料而具有以下說明之構成之各本發明例1及2,以及比較例。
本發明例1:製造圖1所示之化合物半導體基板CS1。將各C-GaN層51a及51b之厚度作為1450nm,而將AlN層52a之厚度作為15nm。將各C-GaN層51a及51b之平均碳濃度作成1×1019 個/cm3 以上2×1019 個/cm3 以下之範圍內的值。
本發明例2:製造圖3所示之化合物半導體基板CS2。將各C-GaN層51a、51b、及51c之厚度作為967nm,而將各AlN層52a及52b之厚度作為15nm。將各C-GaN層51a、51b、及51c之平均碳濃度作成1×1019 個/cm3 以上2×1019 個/cm3 以下之範圍內的值。
比較例:製造圖6所示之化合物半導體基板CS10。化合物半導體基板CS10係在取代複合層5而加以形成C-GaN層105的點中,與化合物半導體基板CS1(本發明例1)不同,除此以外的構成係與化合物半導體基板CS1(本發明例1)相同。將C-GaN層105之平均碳濃度作成1×1019 個/cm3 以上2×1019 個/cm3 以下之範圍內的值。
本申請發明者們係對於所得到之各試料中,進行經由目視之斷裂產生之有無的確認,和彎曲量的測定,和縱耐電壓(化合物半導體基板之厚度方向的耐電壓)之測定。
圖7係顯示本發明之一實施例之各試料的評估結果的表。然而,在圖7中,作為縱耐電壓,顯示將比較例的縱耐電壓作成基準(零)之情況的值。另外,作為彎曲量,將化合物半導體基板之Si基板作為成下側之情況,對於呈成為凸形地產生彎曲的情況係顯示「凸」的文字,而將化合物半導體基板之Si基板作為成下側之情況,對於呈成為凹形地產生彎曲的情況係顯示「凹」的文字。
參照圖7,在比較例中,對於看到斷裂之產生情況而言,在本發明例1及2中,未看到斷裂之產生。另外,在比較例中,對於凹形成為146μm之大彎曲量而言,在本發明例1中,對於凹形成為43μm之小彎曲量。更且,在本發明例2中,對於凸形成為27μm之彎曲量。然而,本發明例2之凸形的彎曲係因化合物半導體基板內之C-GaN層的壓縮偏差大之情況引起者,顯示抑制斷裂之產生的效果大者。從此等之結果,在本發明例1及2中,了解到比較於比較例而加以抑制斷裂之產生,而改善基板之彎曲。
圖8係顯示本發明之一實施例之縱耐電壓之計測方法的剖面圖。
參照圖7及圖8,於貼上於玻璃板21上之銅板22上,固定成為計測對象之試料的化合物半導體基板CS。於所固定之化合物半導體基板CS的Al氮化物半導體層10上,呈接觸於Al氮化物半導體層10地設置Al所成之電極23。將曲線紀錄器24之一方的端子連接於銅板22,而將另一方的端子連接於電極23。使用曲線紀錄器24而加上電壓於銅板22與電極23之間,計測流動在銅板22與電極23之間的電流(在試料流動於縱方向的電流)之密度。所計測的電流之密度則到達為1×10-6 A/mm2 時,看作試料為絕緣破壞者,將此時之銅板22與電極23之間的電壓作為耐電壓而計測。
測定之結果,在本發明例1中,比較於比較例,縱耐電壓則僅變高60V。在本發明例2中,比較於比較例,縱耐電壓則僅變高85V。從此等結果,在本發明例1及2中,了解到比較於比較例,縱耐電壓則提升者。
[其他]
上述之實施形態及變形例係可作適宜組合者。
上述之實施形態,變形例及實施例係應認為例示在所有的點,並非限制性的構成。本發明之範圍係並非上述之說明,而經由申請專利範圍所示,特意包含有與申請專利範圍均等意思及在範圍內之所有的變更者。
1‧‧‧Si(矽)基板2‧‧‧SiC(碳化矽)層3‧‧‧AlN(氮化鋁)緩衝層4、10‧‧‧Al(鋁)氮化物半導體層4a、4b‧‧‧AlGaN(氮化鋁鎵)層5‧‧‧複合層7‧‧‧GaN(氮化鎵)層21‧‧‧玻璃板22‧‧‧銅板23‧‧‧電極24‧‧‧曲線紀錄器41‧‧‧Al0.75Ga0.25N層42‧‧‧Al0.5Ga0.5N層43‧‧‧Al0.25Ga0.75N層44‧‧‧AlN中間層51a、51b、51c、105‧‧‧C(碳)-GaN層52a、52b‧‧‧AlN層CS、CS1、CS2、CS10‧‧‧化合物半導體基板
圖1係顯示在本發明之第1實施形態的化合物半導體基板CS1之構成的剖面圖。   圖2係顯示本發明之第1實施形態之Al氮化物半導體層4內部之Al組成比的分布圖。   圖3係顯示在本發明之第2實施形態的化合物半導體基板CS2之構成的剖面圖。   圖4係顯示本發明之第1變形例之Al氮化物半導體層4內部之Al組成比的分布圖。   圖5係顯示本發明之第2變形例之Al氮化物半導體層4內部之Al組成比的分布圖。   圖6係顯示在本發明之一實施例的比較例(化合物半導體基板CS10)之構成的剖面圖。   圖7係顯示本發明之一實施例之各試料的評估結果的表。   圖8係顯示本發明之一實施例之縱耐電壓之計測方法的剖面圖。
1‧‧‧Si(矽)基板
2‧‧‧SiC(碳化矽)層
3‧‧‧AlN(氮化鋁)緩衝層
4、10‧‧‧Al(鋁)氮化物半導體層
5‧‧‧複合層
7‧‧‧GaN(氮化鎵)層
41‧‧‧Al0.75Ga0.25N層
42‧‧‧Al0.5Ga0.5N層
43‧‧‧Al0.25Ga0.75N層
51a、51b‧‧‧C(碳)-GaN層
52a‧‧‧AlN層
CS1‧‧‧化合物半導體基板

Claims (7)

  1. 一種化合物半導體基板,其特徵為具備:SiC層,和形成於前述SiC層上之由AlN所成之緩衝層,和形成於前述緩衝層上,含有Al之氮化物半導體層,和形成於前述氮化物半導體層上之複合層,和形成於前述複合層上之由GaN所成之電子行走層,和形成於前述電子行走層上之障壁層;前述複合層係包含:層積於上下方向,含有碳之由GaN所成之複數的第1層,和形成於前述複數的第1層之各者之間的由AlN所成之第2層,前述第2層係對於前述複數之第1層中,成為前述第2層之基材的第1層而言,以不整合之狀態加以形成,各別前述複數之第1層係具有550nm以上2000nm以下之厚度。
  2. 如申請專利範圍第1項記載之化合物半導體基板,其中,前述複數的第1層之各者係具有1×1018個/cm3以上1×1021個/cm3以下之平均碳原子濃度。
  3. 如申請專利範圍第1項記載之化合物半導體基板,其中,前述第2層係具有10nm以上15nm以下之厚度。
  4. 如申請專利範圍第1項記載之化合物半導體基板,其 中,前述氮化物半導體層內部之Al的組成比係隨著自下部朝向上部而減少。
  5. 如申請專利範圍第1項記載之化合物半導體基板,其中,前述氮化物半導體層係包含:含有Al及Ga之第1氮化物半導體層,和接觸於前述第1氮化物半導體層而形成於前述第1氮化物半導體層上之含有Al之第2氮化物半導體層,和接觸於前述第2氮化物半導體層而形成於前述第2氮化物半導體層上之含有Al及Ga之第3氮化物半導體層;前述第1及前述第3氮化物半導體層之中至少任一方的層內部之Al的組成比係隨著自下部朝向上部而減少。
  6. 如申請專利範圍第1項記載之化合物半導體基板,其中,前述複數之第1層之中,形成於前述第2層上之第1層係包含壓縮偏差。
  7. 如申請專利範圍第1項記載之化合物半導體基板,其中,前述氮化物半導體層係具有900nm以上2μm以下之厚度。
TW107108976A 2017-03-31 2018-03-16 化合物半導體基板 TWI791495B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017071662A JP6781095B2 (ja) 2017-03-31 2017-03-31 化合物半導体基板
JP2017-071662 2017-03-31

Publications (2)

Publication Number Publication Date
TW201843711A TW201843711A (zh) 2018-12-16
TWI791495B true TWI791495B (zh) 2023-02-11

Family

ID=63675322

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107108976A TWI791495B (zh) 2017-03-31 2018-03-16 化合物半導體基板

Country Status (7)

Country Link
US (1) US11316018B2 (zh)
EP (1) EP3605595A4 (zh)
JP (1) JP6781095B2 (zh)
KR (1) KR102457317B1 (zh)
CN (1) CN110402484B (zh)
TW (1) TWI791495B (zh)
WO (1) WO2018180312A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020113693A (ja) * 2019-01-16 2020-07-27 エア・ウォーター株式会社 化合物半導体基板
CN111477536A (zh) * 2020-03-31 2020-07-31 华为技术有限公司 一种半导体外延结构及半导体器件
JP2022018560A (ja) * 2020-07-15 2022-01-27 エア・ウォーター株式会社 化合物半導体基板および化合物半導体基板の製造方法
TWI767425B (zh) * 2020-11-27 2022-06-11 合晶科技股份有限公司 氮化物磊晶片及其製造方法
WO2024084905A1 (ja) * 2022-10-17 2024-04-25 ローム株式会社 窒化物半導体装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008171843A (ja) * 2007-01-05 2008-07-24 Furukawa Electric Co Ltd:The 半導体電子デバイス
TW201413948A (zh) * 2012-09-28 2014-04-01 Fujitsu Ltd 半導體裝置
TW201707063A (zh) * 2015-03-09 2017-02-16 Air Water Inc 化合物半導體基板

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7825432B2 (en) 2007-03-09 2010-11-02 Cree, Inc. Nitride semiconductor structures with interlayer structures
JP2010171032A (ja) * 2009-01-20 2010-08-05 New Japan Radio Co Ltd 窒化物半導体装置形成用基板及び窒化物半導体装置
JP2010239034A (ja) * 2009-03-31 2010-10-21 Furukawa Electric Co Ltd:The 半導体装置の製造方法および半導体装置
JP2011187654A (ja) * 2010-03-08 2011-09-22 Toyoda Gosei Co Ltd Iii族窒化物半導体からなるhemt、およびその製造方法
JP5546514B2 (ja) * 2011-09-20 2014-07-09 古河電気工業株式会社 窒化物半導体素子及び製造方法
JP2013145782A (ja) * 2012-01-13 2013-07-25 Sharp Corp ヘテロ接合型電界効果トランジスタ用のエピタキシャルウエハ
JP5785103B2 (ja) 2012-01-16 2015-09-24 シャープ株式会社 ヘテロ接合型電界効果トランジスタ用のエピタキシャルウエハ
JP6052570B2 (ja) 2012-02-28 2016-12-27 エア・ウォーター株式会社 半導体基板の製造方法
JP2013229493A (ja) * 2012-04-26 2013-11-07 Sharp Corp Iii族窒化物半導体積層基板およびiii族窒化物半導体電界効果トランジスタ
JP6283250B2 (ja) 2014-04-09 2018-02-21 サンケン電気株式会社 半導体基板及び半導体素子
US10109736B2 (en) * 2015-02-12 2018-10-23 Taiwan Semiconductor Manufacturing Co., Ltd. Superlattice buffer structure for gallium nitride transistors
US9530846B2 (en) 2015-03-31 2016-12-27 Coorstek Kk Nitride semiconductor substrate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008171843A (ja) * 2007-01-05 2008-07-24 Furukawa Electric Co Ltd:The 半導体電子デバイス
TW201413948A (zh) * 2012-09-28 2014-04-01 Fujitsu Ltd 半導體裝置
TW201707063A (zh) * 2015-03-09 2017-02-16 Air Water Inc 化合物半導體基板

Also Published As

Publication number Publication date
US20200020778A1 (en) 2020-01-16
KR20190135039A (ko) 2019-12-05
CN110402484B (zh) 2023-11-03
EP3605595A4 (en) 2020-04-15
JP2018174234A (ja) 2018-11-08
TW201843711A (zh) 2018-12-16
EP3605595A1 (en) 2020-02-05
CN110402484A (zh) 2019-11-01
KR102457317B1 (ko) 2022-10-24
JP6781095B2 (ja) 2020-11-04
US11316018B2 (en) 2022-04-26
WO2018180312A1 (ja) 2018-10-04

Similar Documents

Publication Publication Date Title
TWI791495B (zh) 化合物半導體基板
US10186421B2 (en) Composite semiconductor substrate
US10354864B2 (en) Compound semiconductor substrate with SiC layer
TWI814756B (zh) 化合物半導體基板
US11476115B2 (en) Compound semiconductor substrate comprising a SiC layer
TW202034385A (zh) 化合物半導體基板
CN115803890A (zh) 化合物半导体衬底和化合物半导体衬底的制造方法