TWI790977B

TWI790977B - Integrated circuit product and chip floorplan arrangement thereof

Info

Publication number: TWI790977B
Application number: TW111123117A
Authority: TW
Inventors: 林文熙; 何闓廷
Original assignee: 世芯電子股份有限公司
Priority date: 2021-03-26
Filing date: 2021-08-23
Publication date: 2023-01-21
Also published as: TW202249232A; TWI776648B; TWI780870B; CN115132720A; CN115132719A; TW202238908A; TW202238434A

Abstract

An integrated circuit product includes: a first chip to a twelfth chip. The first to fourth chips are respectively arranged in a first quadrant, a fourth quadrant, a third quadrant, and a second quadrant of the integrated circuit product, and the first chip is adjacent to the second chip and the fourth chip. The fifth to eighth chips are respectively arranged in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and any two of the fifth to eighth chips are not adjacent. The ninth to twelfth chips are respectively arranged in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and any two of the ninth to twelfth chips are not adjacent.

Description

積體電路產品及其晶片排佈 Integrated circuit products and their chip layout

本發明涉及積體電路(integrated circuit,IC)之封裝，尤指積體電路封裝之晶片(chip)和/或小晶片(chiplet)(以下統稱為晶片)排佈(floorplan arrangement)。 The present invention relates to the packaging of integrated circuits (IC), especially to the floorplan arrangement of chips and/or chiplets (hereinafter collectively referred to as chips) of IC packaging.

先進封裝為目前積體電路的趨勢。然而，不佳的晶片排佈可能有以下的缺點：浪費面積(導致成品過大而缺乏競爭力)、晶片散熱不佳(降低晶片效能)、輸出和/或輸入走線困難(增加封裝的難度)和/或晶片的相對位置不理想(造成晶片接腳的浪費)。因此，需要一種晶片排佈來解決上述的問題的至少其中之一。 Advanced packaging is the current trend of integrated circuits. However, poor die layout can have the following disadvantages: wasted area (resulting in an uncompetitive finished product that is too large), poor heat dissipation from the die (reducing die performance), and difficult output and/or input routing (increasing packaging difficulty) And/or the relative position of the chip is not ideal (causing waste of chip pins). Therefore, a wafer arrangement is needed to solve at least one of the above-mentioned problems.

有鑑於此，如何減輕或消除上述相關領域中晶片排佈的缺失，實為有待解決的問題。 In view of this, how to alleviate or eliminate the lack of chip arrangement in the above-mentioned related fields is a problem to be solved.

本說明書提供一種積體電路產品的實施例，其包含：一第一晶片；一第二晶片；一第三晶片；一第四晶片；一第五晶片；一第六晶片；一第七晶片；一第八晶片；一第九晶片；一第十晶片；一第十一晶片；以及一第十二晶片。該第一晶片、該第二晶片、該第三晶片、及該第四晶片分別位於該積體電路產品之一第一象限、一第四象限、一第三象限、及一第二象限，且該第一晶片鄰接該第二晶片及該第四晶片。該第五晶片、該第六晶片、該第七晶片、及該第八晶片分別位於該積體電路產品之該第一象限、該第四象限、該第三象限、及該第二象限，且該第五晶片、該第六晶片、該第七晶片、及該第八晶片之任二者不鄰接。該第九晶片、該第十晶片、該第十一晶片、及該第十二晶片分別位於該積體電路產品之該第一象限、該第四象限、該第三象限、及該第二象限，且該第九晶片、該第十晶片、該第十一晶片、及該第十二晶片之任二者不鄰接。 This specification provides an embodiment of an integrated circuit product, which includes: a first chip; a second chip; a third chip; a fourth chip; a fifth chip; a sixth chip; a seventh chip; an eighth wafer; a ninth wafer; a tenth wafer; an eleventh wafer; and a twelfth wafer. the first chip, the second chip, the third chip, and the fourth chip are respectively located in a first quadrant, a fourth quadrant, a third quadrant, and a second quadrant of the integrated circuit product, and The first wafer is adjacent to the second wafer and the fourth wafer. The fifth chip, the sixth chip, the seventh chip, and the eighth chip are respectively located in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and The fifth chip, the sixth chip, the seventh chip, and the Any two of the eight chips are not contiguous. The ninth chip, the tenth chip, the eleventh chip, and the twelfth chip are respectively located in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product , and any two of the ninth wafer, the tenth wafer, the eleventh wafer, and the twelfth wafer are not adjacent.

本說明書另提供一種積體電路產品的實施例，其包含：一第一晶片；一第二晶片；一第三晶片；一第四晶片；一第五晶片；一第六晶片；一第七晶片；一第八晶片；一第九晶片；一第十晶片；一第十一晶片；以及一第十二晶片。該第一晶片、該第二晶片、該第三晶片、該第四晶片、該第五晶片、該第六晶片、該第七晶片、及該第八晶片、該第九晶片、該第十晶片、該第十一晶片、及該第十二晶片實質上位於一平面。倘若將該第一晶片於該平面上相對於該積體電路產品之一中心旋轉九十度，則該第一晶片與該第二晶片或該第四晶片實質上重疊，且倘若將該第一晶片於該平面上相對於該中心旋轉一百八十度，則該第一晶片與該第三晶片實質上重疊。倘若將該第五晶片於該平面上相對於該中心旋轉九十度，則該第五晶片與該第六晶片或該第八晶片實質上重疊，且倘若將該第五晶片於該平面上相對於該中心旋轉一百八十度，則該第五晶片與該第七晶片實質上重疊。倘若將該第九晶片於該平面上相對於該中心旋轉九十度，則該第九晶片與該第十晶片或該第十二晶片實質上重疊，且倘若將該第九晶片於該平面上相對於該中心旋轉一百八十度，則該第九晶片與該第十一晶片實質上重疊。 This specification also provides an embodiment of an integrated circuit product, which includes: a first chip; a second chip; a third chip; a fourth chip; a fifth chip; a sixth chip; a seventh chip ; an eighth chip; a ninth chip; a tenth chip; an eleventh chip; and a twelfth chip. The first wafer, the second wafer, the third wafer, the fourth wafer, the fifth wafer, the sixth wafer, the seventh wafer, and the eighth wafer, the ninth wafer, the tenth wafer , the eleventh wafer, and the twelfth wafer are substantially located on a plane. If the first wafer is rotated ninety degrees on the plane with respect to a center of the integrated circuit product, the first wafer substantially overlaps with the second wafer or the fourth wafer, and if the first When the wafer rotates 180 degrees relative to the center on the plane, the first wafer and the third wafer substantially overlap each other. If the fifth wafer is rotated ninety degrees relative to the center on the plane, the fifth wafer substantially overlaps with the sixth wafer or the eighth wafer, and if the fifth wafer is opposite to the Rotating 180 degrees about the center, the fifth wafer substantially overlaps the seventh wafer. If the ninth wafer is rotated ninety degrees relative to the center on the plane, the ninth wafer substantially overlaps the tenth wafer or the twelfth wafer, and if the ninth wafer is placed on the plane Rotating 180 degrees relative to the center, the ninth wafer substantially overlaps the eleventh wafer.

上述實施例的優點之一，是可充分利用基板面積、避免晶片接腳浪費及邏輯晶片之間容易溝通。 One of the advantages of the above-mentioned embodiment is that the area of the substrate can be fully utilized, waste of chip pins can be avoided, and communication between logic chips is easy.

上述實施例的另一優點，是可充分利用基板面積、簡化光罩複雜度、及提高積體電路產品競爭力。 Another advantage of the above embodiments is that the area of the substrate can be fully utilized, the complexity of the mask can be simplified, and the competitiveness of integrated circuit products can be improved.

本發明的其他優點將搭配以下的說明和圖式進行更詳細的解說。 Other advantages of the present invention will be explained in more detail with the following description and drawings.

100、200、300、400、500、600、700、800、900、1000、1100、 1200:積體電路產品 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200: Integrated circuit products

112、312、412:第一邏輯晶片 112, 312, 412: the first logic chip

114、314、414:第二邏輯晶片 114, 314, 414: second logic chip

116、316、416:第三邏輯晶片 116, 316, 416: the third logic chip

118、318、418:第四邏輯晶片 118, 318, 418: the fourth logic chip

122、322、422、722、922、1022:第一記憶體晶片 122, 322, 422, 722, 922, 1022: the first memory chip

124、332、432、724、932、1032:第二記憶體晶片 124, 332, 432, 724, 932, 1032: the second memory chip

126、324、424、726、924、1024:第三記憶體晶片 126, 324, 424, 726, 924, 1024: the third memory chip

128、334、434、728、934、1034:第四記憶體晶片 128, 334, 434, 728, 934, 1034: the fourth memory chip

132、442:第一其他晶片 132, 442: the first other chips

134、444:第二其他晶片 134, 444: the second other chip

136、446:第三其他晶片 136, 446: the third other chip

138、448:第四其他晶片 138, 448: the fourth other chip

150:基板 150: Substrate

PL:平面 PL: plane

152:微凸塊 152: micro bump

154:凸塊 154: Bump

140:中介層 140: intermediary layer

102:第一邊 102: First side

104:第二邊 104: second side

106:第三邊 106: third side

108:第四邊 108: Fourth side

101、301、401:中心 101, 301, 401: Center

Q1:第一象限 Q1: The first quadrant

Q4:第四象限 Q4: The fourth quadrant

Q3:第三象限 Q3: The third quadrant

Q2:第二象限 Q2: The second quadrant

326、426、926、1026:第五記憶體晶片 326, 426, 926, 1026: the fifth memory chip

336、436、936、1036:第六記憶體晶片 336, 436, 936, 1036: the sixth memory chip

328、428、928、1028:第七記憶體晶片 328, 428, 928, 1028: the seventh memory chip

338、438、938、1038:第八記憶體晶片 338, 438, 938, 1038: the eighth memory chip

W1、W2、W3、W4:寬度 W1, W2, W3, W4: Width

L1、L2、L3、L4:長度 L1, L2, L3, L4: Length

圖1為本發明一實施例的積體電路產品之簡化後的晶片排佈的示意圖。 FIG. 1 is a schematic diagram of a simplified chip layout of an integrated circuit product according to an embodiment of the present invention.

圖2顯示本發明一實施例的積體電路產品之簡化後的側視圖。 FIG. 2 shows a simplified side view of an integrated circuit product according to an embodiment of the present invention.

圖3顯示本發明另一實施例的積體電路產品之簡化後的側視圖。 FIG. 3 shows a simplified side view of an integrated circuit product according to another embodiment of the present invention.

圖4顯示本發明積體電路產品之中心點與象限的分佈。 FIG. 4 shows the distribution of center points and quadrants of the integrated circuit product of the present invention.

圖5為本發明另一實施例的積體電路產品之簡化後的晶片排佈的示意圖。 FIG. 5 is a schematic diagram of a simplified chip layout of an integrated circuit product according to another embodiment of the present invention.

圖6為本發明另一實施例的積體電路產品之簡化後的晶片排佈的示意圖。 FIG. 6 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention.

圖7為本發明另一實施例的積體電路產品之簡化後的晶片排佈的示意圖。 FIG. 7 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention.

圖8為本發明另一實施例的積體電路產品之簡化後的晶片排佈的示意圖。 FIG. 8 is a schematic diagram of a simplified chip layout of an integrated circuit product according to another embodiment of the present invention.

圖9為本發明另一實施例的積體電路產品之簡化後的晶片排佈的示意圖。 FIG. 9 is a schematic diagram of a simplified chip layout of an integrated circuit product according to another embodiment of the present invention.

圖10為本發明另一實施例的積體電路產品之簡化後的晶片排佈的示意圖。 FIG. 10 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention.

圖11為本發明另一實施例的積體電路產品之簡化後的晶片排佈的示意圖。 FIG. 11 is a schematic diagram of a simplified chip layout of an integrated circuit product according to another embodiment of the present invention.

圖12為本發明另一實施例的積體電路產品之簡化後的晶片排佈的示意圖。 FIG. 12 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention.

圖13為本發明另一實施例的積體電路產品之簡化後的晶片排佈的示意圖。 FIG. 13 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention.

圖14為本發明另一實施例的積體電路產品之簡化後的晶片排佈的示意圖。 FIG. 14 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention.

圖15為本發明另一實施例的積體電路產品之簡化後的晶片排佈的示意圖。 FIG. 15 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention.

以下將配合相關圖式來說明本發明的實施例。在圖式中，相同的標號表示相同或類似的元件或方法流程。 Embodiments of the present invention will be described below in conjunction with related figures. In the drawings, the same reference numerals represent the same or similar elements or method flows.

圖1為本發明一實施例的積體電路產品之簡化後的晶片排佈的示意圖。積體電路產品100包含第一邏輯晶片112、第二邏輯晶片114、第三邏輯晶片116、第四邏輯晶片118、第一記憶體晶片122、第二記憶體晶片124、第三記憶體晶片126、第四記憶體晶片128、第一其他晶片132、第二其他晶片134、第三其他晶片136、第四其他晶片138。圖1顯示積體電路產品100的俯視圖，圖2及圖3各自顯示本發明一實施例的積體電路產品之簡化後的側視圖(沿著圖1之A-A'橫截面)。在圖2的實施例中，積體電路產品100包含基板150，圖1所示的該些邏輯晶片、該些記憶體晶片、及該些其他晶片位於基板150的上方之同一平面PL上。基板150與邏輯晶片、記憶體晶片、及其他晶片之間有複數個微凸塊152，基板150下方有複數個凸塊154。在圖3的實施例中，積體電路產品100包含中介層(interposer)140，圖1所示的該些邏輯晶片、該些記憶體晶片、及該些其他晶片位於中介層140的上方。中介層140與基板150之間有複數個微凸塊152，基板150下方有複數個凸塊154。第一邏輯晶片112、第二邏輯晶片114、第三邏輯晶片116、及第四邏輯晶片118可以是具有計算能力的邏輯電路，例如系統單晶片(System on a chip,SoC)。邏輯晶片可以存取記憶體晶片來實現特定的功能，例如，邏輯晶片藉由讀取並執行儲存於記憶體晶片中的程式碼或程式指令來實現該功能。 FIG. 1 is a schematic diagram of a simplified chip layout of an integrated circuit product according to an embodiment of the present invention. The integrated circuit product 100 includes a first logic chip 112 , a second logic chip 114 , a third logic chip 116 , a fourth logic chip 118 , a first memory chip 122 , a second memory chip 124 , and a third memory chip 126 , the fourth memory chip 128 , the first other chip 132 , the second other chip 134 , the third other chip 136 , and the fourth other chip 138 . FIG. 1 shows a top view of an integrated circuit product 100 , and FIGS. 2 and 3 each show a simplified side view (along AA' cross-section of FIG. 1 ) of an integrated circuit product according to an embodiment of the present invention. In the embodiment of FIG. 2 , the integrated circuit product 100 includes a substrate 150 , and the logic chips, the memory chips, and the other chips shown in FIG. 1 are located on the same plane PL above the substrate 150 . There are a plurality of micro-bumps 152 between the substrate 150 and logic chips, memory chips, and other chips, and a plurality of bumps 154 under the substrate 150 . In the embodiment of FIG. 3 , the integrated circuit product 100 includes an interposer 140 , and the logic chips, the memory chips, and the other chips shown in FIG. 1 are located above the interposer 140 . There are a plurality of micro bumps 152 between the interposer 140 and the substrate 150 , and a plurality of bumps 154 under the substrate 150 . The first logic chip 112 , the second logic chip 114 , the third logic chip 116 , and the fourth logic chip 118 may be logic circuits with computing capabilities, such as System on a chip (SoC). The logic chip can access the memory chip to realize a specific function. For example, the logic chip realizes the function by reading and executing the program code or program instructions stored in the memory chip.

回到圖1。積體電路產品100具有第一邊102、第二邊104、第三邊106、及第四邊108。積體電路產品100的該四個邊可以是基板150的四個邊。積體電路產品100還具有中心101。第一邏輯晶片112的一邊與第二邊104實質上重疊(即，第一邏輯晶片112的一邊與第二邊104實質上對齊)，也就是說，第一邏輯晶片112鄰接(adjacent) 第二邊104。類似地，第二邏輯晶片114的一邊與第三邊106實質上重疊、第三邏輯晶片116的一邊與第四邊108實質上重疊，以及第四邏輯晶片118的一邊與第一邊102實質上重疊。 Back to Figure 1. The integrated circuit product 100 has a first side 102 , a second side 104 , a third side 106 , and a fourth side 108 . The four sides of the integrated circuit product 100 may be the four sides of the substrate 150 . The integrated circuit product 100 also has a center 101 . One side of the first logic die 112 substantially overlaps with the second side 104 (that is, one side of the first logic die 112 is substantially aligned with the second side 104), that is, the first logic die 112 adjoins (adjacent) Second side 104. Similarly, one side of the second logic die 114 substantially overlaps the third side 106, one side of the third logic die 116 substantially overlaps the fourth side 108, and one side of the fourth logic die 118 substantially overlaps the first side 102. overlapping.

類似地，第一其他晶片132、第二其他晶片134、第三其他晶片136、及第四其他晶片138各自的一邊分別與第一邊102、第二邊104、第三邊106、及第四邊108實質上重疊。 Similarly, one side of the first other wafer 132, the second other wafer 134, the third other wafer 136, and the fourth other wafer 138 is respectively connected to the first side 102, the second side 104, the third side 106, and the fourth side. Edges 108 substantially overlap.

類似地，第一記憶體晶片122、第二記憶體晶片124、第三記憶體晶片126、及第四記憶體晶片128各自的一邊分別與第一邊102、第二邊104、第三邊106、及第四邊108實質上重疊。此外，因為第一記憶體晶片122、第二記憶體晶片124、第三記憶體晶片126、及第四記憶體晶片128被安排在積體電路產品100的四個角，所以第一記憶體晶片122、第二記憶體晶片124、第三記憶體晶片126、及第四記憶體晶片128各自的另一邊更分別與第二邊104、第三邊106、第四邊108、及第一邊102實質上重疊。 Similarly, one side of the first memory chip 122, the second memory chip 124, the third memory chip 126, and the fourth memory chip 128 is respectively connected to the first side 102, the second side 104, and the third side 106. , and the fourth side 108 substantially overlap. In addition, since the first memory chip 122, the second memory chip 124, the third memory chip 126, and the fourth memory chip 128 are arranged at the four corners of the integrated circuit product 100, the first memory chip 122, the other side of the second memory chip 124, the third memory chip 126, and the fourth memory chip 128 are further connected to the second side 104, the third side 106, the fourth side 108, and the first side 102 respectively. substantially overlap.

如圖1所示，第一邏輯晶片112與第二邏輯晶片114及第四邏輯晶片118鄰接、第二邏輯晶片114與第一邏輯晶片112及第三邏輯晶片116鄰接、第三邏輯晶片116與第二邏輯晶片114及第四邏輯晶片118鄰接、且第四邏輯晶片118與第一邏輯晶片112及第三邏輯晶片116鄰接。在一些實施例中，第一邏輯晶片112、第二邏輯晶片114、第三邏輯晶片116、及第四邏輯晶片118的頂點在中心101互相接觸。然而，第一記憶體晶片122、第二記憶體晶片124、第三記憶體晶片126、及第四記憶體晶片128不互相鄰接，且第一其他晶片132、第二其他晶片134、第三其他晶片136、及第四其他晶片138不互相鄰接。 As shown in FIG. 1 , the first logic die 112 is adjacent to the second logic die 114 and the fourth logic die 118, the second logic die 114 is adjacent to the first logic die 112 and the third logic die 116, and the third logic die 116 is adjacent to the third logic die 116. The second logic die 114 and the fourth logic die 118 are adjacent, and the fourth logic die 118 is adjacent to the first logic die 112 and the third logic die 116 . In some embodiments, the vertices of the first logic die 112 , the second logic die 114 , the third logic die 116 , and the fourth logic die 118 contact each other at the center 101 . However, the first memory chip 122, the second memory chip 124, the third memory chip 126, and the fourth memory chip 128 are not adjacent to each other, and the first other chip 132, the second other chip 134, the third other chip Die 136, and the fourth other die 138 are not adjacent to each other.

在一些實施例中，第一邏輯晶片112、第二邏輯晶片114、第三邏輯晶片116、及第四邏輯晶片118的面積實質上相同，第一記憶體晶片122、第二記憶體晶片124、第三記憶體晶片126、及第四記憶體晶片128的面積實質上相同，而且第一其他晶片132、第二其他晶片134、第三其他晶片136、及第四其他晶片138的面積實質上相同。 In some embodiments, the areas of the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118 are substantially the same, and the first memory chip 122, the second memory chip 124, The third memory chip 126, and the fourth memory chip The areas of the sheets 128 are substantially the same, and the areas of the first other die 132 , the second other die 134 , the third other die 136 , and the fourth other die 138 are substantially the same.

在一些實施例中，第一邏輯晶片112、第二邏輯晶片114、第三邏輯晶片116、及第四邏輯晶片118的組成元件實質上相同，第一記憶體晶片122、第二記憶體晶片124、第三記憶體晶片126、及第四記憶體晶片128的組成元件實質上相同，而且第一其他晶片132、第二其他晶片134、第三其他晶片136、及第四其他晶片138的組成元件實質上相同。前述的組成元件包含但不限於電晶體、電阻、電容、和/或電感。在另一些實施例中，第一邏輯晶片112、第二邏輯晶片114、第三邏輯晶片116、及第四邏輯晶片118的組成元件在種類及數量上相同，第一記憶體晶片122、第二記憶體晶片124、第三記憶體晶片126、及第四記憶體晶片128的組成元件在種類及數量上相同，而且第一其他晶片132、第二其他晶片134、第三其他晶片136、及第四其他晶片138的組成元件在種類及數量上相同。 In some embodiments, the constituent elements of the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118 are substantially the same, and the first memory chip 122, the second memory chip 124 , the third memory chip 126, and the composition elements of the fourth memory chip 128 are substantially the same, and the composition elements of the first other chip 132, the second other chip 134, the third other chip 136, and the fourth other chip 138 essentially the same. The aforementioned components include but are not limited to transistors, resistors, capacitors, and/or inductors. In other embodiments, the components of the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118 are the same in type and quantity, and the first memory chip 122, the second logic chip The components of the memory chip 124, the third memory chip 126, and the fourth memory chip 128 are identical in type and quantity, and the first other chip 132, the second other chip 134, the third other chip 136, and the first other chip 136 The components of the four other chips 138 are the same in type and quantity.

在一些實施例中，第一其他晶片132、第二其他晶片134、第三其他晶片136、及第四其他晶片138是輸入/輸出晶片，包含輸入/輸出電路，第一邏輯晶片112、第二邏輯晶片114、第三邏輯晶片116、及第四邏輯晶片118利用輸入/輸出電路傳送或接收信號。在其他的實施例中，第一其他晶片132、第二其他晶片134、第三其他晶片136、及第四其他晶片138是不包含任何電路的矽晶片。 In some embodiments, the first other die 132, the second other die 134, the third other die 136, and the fourth other die 138 are input/output dies containing input/output circuits, the first logic die 112, the second The logic chip 114 , the third logic chip 116 , and the fourth logic chip 118 use input/output circuits to transmit or receive signals. In other embodiments, the first other die 132 , the second other die 134 , the third other die 136 , and the fourth other die 138 are silicon dies that do not contain any circuitry.

請參閱圖1及圖4。積體電路產品100被互相垂直的X軸及Y軸畫分為四個象限，X軸及Y軸於中心101處相交。第一晶片群組(包含第一邏輯晶片112、第一記憶體晶片122、及第一其他晶片132)位於第一象限Q1；第二晶片群組(包含第二邏輯晶片114、第二記憶體晶片124、及第二其他晶片134)位於第四象限Q4；第三晶片群組(包含第三邏輯晶片116、第三記憶體晶片126、及第三其他晶片136)位於第三象限Q3；第四晶片群組(包含第四邏輯晶片118、第四記憶體晶片128、及第四其他晶片138)位於第二象限Q2。第一邏輯晶片112與第一記憶體晶片122的相對位置等於第二邏輯晶片114(第三邏輯晶片116、或第四邏輯晶片118)與第二記憶體晶片124(第三記憶體晶片126、或第四記憶體晶片128)的相對位置；第一邏輯晶片112與第一其他晶片132的相對位置等於第二邏輯晶片114(第三邏輯晶片116、或第四邏輯晶片118)與第二其他晶片134(第三其他晶片136、或第四其他晶片138)的相對位置；第一記憶體晶片122與第一其他晶片132的相對位置等於第二記憶體晶片124(第三記憶體晶片126、或第四記憶體晶片128)與第二其他晶片134(第三其他晶片136、或第四其他晶片138)的相對位置。 Please refer to Figure 1 and Figure 4. The integrated circuit product 100 is divided into four quadrants by mutually perpendicular X-axis and Y-axis, and the X-axis and Y-axis intersect at a center 101 . The first chip group (including the first logic chip 112, the first memory chip 122, and the first other chip 132) is located in the first quadrant Q1; the second chip group (including the second logic chip 114, the second memory chip Chip 124, and the second other chip 134) are located in the fourth quadrant Q4; the third chip group (comprising the third logic chip 116, the third memory chip 126, and the third other chip 136) is located in the third quadrant Q3; Group of four chips (including the fourth logic chip 118, the fourth chip Memory chip 128, and a fourth other chip 138) are located in the second quadrant Q2. The relative position of the first logic chip 112 and the first memory chip 122 is equal to the second logic chip 114 (the third logic chip 116, or the fourth logic chip 118) and the second memory chip 124 (the third memory chip 126, Or the relative position of the fourth memory chip 128); the relative position of the first logic chip 112 and the first other chip 132 is equal to the second logic chip 114 (the third logic chip 116, or the fourth logic chip 118) and the second other The relative position of the chip 134 (the third other chip 136 or the fourth other chip 138); the relative position of the first memory chip 122 and the first other chip 132 is equal to the second memory chip 124 (the third memory chip 126, or the fourth memory chip 128) relative to the second other chip 134 (the third other chip 136, or the fourth other chip 138).

倘若第一晶片群組在平面PL上相對於中心101順時針旋轉90度，則第一晶片群組與第二晶片群組實質上重疊(即，第一邏輯晶片112與第二邏輯晶片114呈現旋轉對稱、第一記憶體晶片122與第二記憶體晶片124呈現旋轉對稱、以及第一其他晶片132與第二其他晶片134呈現旋轉對稱，其中，旋轉對稱中心為中心101，而旋轉角為90度)。類似地，倘若第一晶片群組在平面PL上相對於中心101逆時針旋轉90度或順時針旋轉270度，則第一晶片群組與第四晶片群組實質上重疊。 If the first die group is rotated clockwise by 90 degrees in the plane PL relative to the center 101, the first die group and the second die group substantially overlap (i.e., the first logic die 112 and the second logic die 114 appear Rotational symmetry, the first memory chip 122 and the second memory chip 124 exhibit rotational symmetry, and the first other chip 132 and the second other chip 134 present rotational symmetry, wherein the center of rotational symmetry is the center 101, and the rotation angle is 90° Spend). Similarly, if the first wafer group is rotated 90 degrees counterclockwise or 270 degrees clockwise relative to the center 101 on the plane PL, the first wafer group substantially overlaps the fourth wafer group.

倘若第一晶片群組在平面PL上相對於中心101旋轉180度，則第一晶片群組與第三晶片群組實質上重疊。換言之，第一晶片群組與第三晶片群組相對於中心101呈現點對稱(point symmetry)(即，第一邏輯晶片112與第三邏輯晶片116點對稱、第一記憶體晶片122與第三記憶體晶片126點對稱、且第一其他晶片132與第三其他晶片136點對稱，對稱中心為中心101)。同理，第二晶片群組與第四晶片群組相對於中心101呈現點對稱。 If the first wafer group is rotated by 180 degrees relative to the center 101 on the plane PL, the first wafer group and the third wafer group substantially overlap. In other words, the first chip group and the third chip group exhibit point symmetry (point symmetry) with respect to the center 101 (that is, the first logic chip 112 and the third logic chip 116 are point symmetric, the first memory chip 122 and the third The memory chip 126 is point-symmetric, and the first other chip 132 is point-symmetric to the third other chip 136, and the center of symmetry is the center 101). Similarly, the second chip group and the fourth chip group are point-symmetrical with respect to the center 101 .

換句話說，在一些實施例中，第一晶片群組、第二晶片群組、第三晶片群組、及第四晶片群組各為積體電路產品100的一個組成單位，也就是說，第一邏輯晶片112、第二邏輯晶片114、第三邏輯晶片116、及第四邏輯晶片118可以分別存取或耦接於第一記憶體晶片122、第二記憶體晶片124、第三記憶體晶片126、及第四記憶體晶片128，且第一邏輯晶片112、第二邏輯晶片114、第三邏輯晶片116、及第四邏輯晶片118可以分別耦接於第一其他晶片132、第二其他晶片134、第三其他晶片136、及第四其他晶片138。這樣的安排的優點之一在於，第一邏輯晶片112(第二邏輯晶片114、第三邏輯晶片116、或第四邏輯晶片118)的對外(即積體電路產品100的外部)接腳可以安排在第二邊104(第三邊106、第四邊108、或第一邊102)，而對內的接腳(例如與第一記憶體晶片122、第二記憶體晶片124、第三記憶體晶片126、第四記憶體晶片128、第一其他晶片132、第二其他晶片134、第三其他晶片136、或第四其他晶片138溝通的接腳)可以安排在與記憶體晶片或其他晶片相鄰的邊上。如此一來，因為積體電路產品100的晶片排佈簡單(只需將第一晶片群組旋轉90度、180度、及270度)，所以積體電路產品100的不同區域可以使用相同的光罩來製造，因而可大幅簡化製程而且不會浪費接腳。 In other words, in some embodiments, each of the first chip group, the second chip group, the third chip group, and the fourth chip group is a constituent unit of the integrated circuit product 100, That is to say, the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118 can respectively access or be coupled to the first memory chip 122, the second memory chip 124, The third memory chip 126, and the fourth memory chip 128, and the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118 can be respectively coupled to the first other chip 132 , a second other wafer 134 , a third other wafer 136 , and a fourth other wafer 138 . One of the advantages of such an arrangement is that the external (i.e. outside of the integrated circuit product 100) pins of the first logic chip 112 (the second logic chip 114, the third logic chip 116, or the fourth logic chip 118) can be arranged On the second side 104 (the third side 106, the fourth side 108, or the first side 102), and the inner pins (such as with the first memory chip 122, the second memory chip 124, the third memory chip chip 126, the fourth memory chip 128, the first other chip 132, the second other chip 134, the third other chip 136, or the pins of the fourth other chip 138) can be arranged in relation to the memory chip or other chips next door. In this way, because the chip arrangement of the integrated circuit product 100 is simple (only need to rotate the first chip group by 90 degrees, 180 degrees, and 270 degrees), different regions of the integrated circuit product 100 can use the same light. Cover to manufacture, thus greatly simplifying the manufacturing process without wasting pins.

在一些實施例中，可以藉由將第一邏輯晶片112、第二邏輯晶片114、第三邏輯晶片116、及第四邏輯晶片118的易發熱部分安排在靠近積體電路產品100的邊，來提升積體電路產品100的散熱效能。此外，因為第一邏輯晶片112、第二邏輯晶片114、第三邏輯晶片116、及第四邏輯晶片118互相鄰接，所以更容易實作第一邏輯晶片112、第二邏輯晶片114、第三邏輯晶片116、及第四邏輯晶片118之間的連線(例如透過中介層140和/或基板150)，換言之，第一邏輯晶片112、第二邏輯晶片114、第三邏輯晶片116、及第四邏輯晶片118之間的溝通(例如交換資料)及協作處理變得更加容易實現。 In some embodiments, by arranging the heat-prone parts of the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118 near the side of the integrated circuit product 100, The heat dissipation performance of the integrated circuit product 100 is improved. In addition, since the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118 are adjacent to each other, it is easier to implement the first logic chip 112, the second logic chip 114, and the third logic chip 112. Chip 116, and the connection (for example through interposer 140 and/or substrate 150) between the 4th logic chip 118, in other words, the 1st logic chip 112, the 2nd logic chip 114, the 3rd logic chip 116, and the 4th logic chip Communication (such as exchanging data) and cooperative processing between logic chips 118 become easier to implement.

在另一些實施例中，第一晶片群組、第二晶片群組、第三晶片群組、及第四晶片群組各為一個正方形；更明確地說，以圖1之第一晶片群組為例，W1+W2=L1+L2，其中，W1是第一記憶體晶片122及第一其他晶片132的寬度，W2是第一邏輯晶片112的寬度，L1是第一記憶體晶片122的長度，L2是第一其他晶片132的長度，而第一邏輯晶片112的長度是L1+L2。再者，因為第一晶片群組、第二晶片群組、第三晶片群組、及第四晶片群組皆為正方形，所以積體電路產品100也是一個正方形。 In other embodiments, the first group of chips, the second group of chips, the third group of chips, and the fourth chip group are each a square; more specifically, taking the first chip group in Figure 1 as an example, W1+W2=L1+L2, wherein W1 is the first memory chip 122 and the first other The width of the chip 132, W2 is the width of the first logic chip 112, L1 is the length of the first memory chip 122, L2 is the length of the first other chip 132, and the length of the first logic chip 112 is L1+L2. Moreover, since the first chip group, the second chip group, the third chip group, and the fourth chip group are all square, the integrated circuit product 100 is also a square.

圖5為本發明另一實施例的積體電路產品之簡化後的晶片排佈的示意圖。圖5顯示積體電路產品200的俯視圖。積體電路產品200與積體電路產品100相似，差別在於第一記憶體晶片122與第一其他晶片132交換位置、第二記憶體晶片124與第二其他晶片134交換位置、第三記憶體晶片126與第三其他晶片136交換位置、以及第四記憶體晶片128與第四其他晶片138交換位置。如此一來，在圖2的實施例中，第一其他晶片132、第二其他晶片134、第三其他晶片136、及第四其他晶片138被安排在積體電路產品200的四個角；因此，第一其他晶片132、第二其他晶片134、第三其他晶片136、及第四其他晶片138各自的一邊分別與第一邊102、第二邊104、第三邊106、及第四邊108實質上重疊，且各自的另一邊更分別與第二邊104、第三邊106、第四邊108、及第一邊102實質上重疊。 FIG. 5 is a schematic diagram of a simplified chip layout of an integrated circuit product according to another embodiment of the present invention. FIG. 5 shows a top view of the integrated circuit product 200 . The integrated circuit product 200 is similar to the integrated circuit product 100, the difference is that the first memory chip 122 exchanges positions with the first other chip 132, the second memory chip 124 exchanges positions with the second other chip 134, and the third memory chip 126 swaps places with a third other die 136 , and fourth memory die 128 swaps places with a fourth other die 138 . In this way, in the embodiment of FIG. 2, the first other chip 132, the second other chip 134, the third other chip 136, and the fourth other chip 138 are arranged at the four corners of the integrated circuit product 200; therefore , one side of the first other wafer 132, the second other wafer 134, the third other wafer 136, and the fourth other wafer 138 is respectively connected to the first side 102, the second side 104, the third side 106, and the fourth side 108 substantially overlap, and each other side substantially overlaps with the second side 104 , the third side 106 , the fourth side 108 , and the first side 102 respectively.

圖6為本發明另一實施例的積體電路產品之簡化後的晶片排佈的示意圖。圖6顯示積體電路產品300的俯視圖。積體電路產品300包含第一邏輯晶片312、第二邏輯晶片314、第三邏輯晶片316、第四邏輯晶片318、第一記憶體晶片322、第二記憶體晶片332、第三記憶體晶片324、第四記憶體晶片334、第五記憶體晶片326、第六記憶體晶片336、第七記憶體晶片328、及第八記憶體晶片338。積體電路產品300的晶片排佈方式及特點與積體電路產品100及積體電路產品200相似，差別在於積體電路產品300的一個晶片群組包含1個邏輯晶片及2個記憶體晶片，但不包含其他晶片。 FIG. 6 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention. FIG. 6 shows a top view of the integrated circuit product 300 . The integrated circuit product 300 includes a first logic chip 312 , a second logic chip 314 , a third logic chip 316 , a fourth logic chip 318 , a first memory chip 322 , a second memory chip 332 , and a third memory chip 324 , the fourth memory chip 334 , the fifth memory chip 326 , the sixth memory chip 336 , the seventh memory chip 328 , and the eighth memory chip 338 . The IC product 300 is similar to the IC product 100 and the IC product 200 in its arrangement and features of chips, the difference being that one chip group of the IC product 300 includes one logic logic chips and 2 memory chips, but not other chips.

在一些實施例中，第一晶片群組(包含第一邏輯晶片312、第一記憶體晶片322、及第二記憶體晶片332)、第二晶片群組(包含第二邏輯晶片314、第三記憶體晶片324、及第四記憶體晶片334)、第三晶片群組(包含第三邏輯晶片316、第五記憶體晶片326、及第六記憶體晶片336)、及第四晶片群組(包含第四邏輯晶片318、第七記憶體晶片328、及第八記憶體晶片338)各為一個正方形。以第一晶片群組為例，W1+W3=L1+L3，其中，W1是第一記憶體晶片322及第二記憶體晶片332的寬度，W3是第一邏輯晶片312的寬度，L1是第一記憶體晶片322的長度，L3是第二記憶體晶片332的長度，而第一邏輯晶片312的長度是L1+L3。倘若將第一晶片群組相對於中心301順時針旋轉90度、180度、及270度，則旋轉後的第一晶片群組的各晶片將分別與第二晶片群組、第三晶片群組、及第四晶片群組中相對應的晶片實質上重疊(第一邏輯晶片312、第二邏輯晶片314、第三邏輯晶片316、及第四邏輯晶片318互相對應，第一記憶體晶片322、第三記憶體晶片324、第五記憶體晶片326、及第七記憶體晶片328互相對應，且第二記憶體晶片332、第四記憶體晶片334、第六記憶體晶片336、及第八記憶體晶片338互相對應)。再者，因為第一晶片群組、第二晶片群組、第三晶片群組、及第四晶片群組皆為正方形，所以積體電路產品300也是一個正方形。 In some embodiments, the first chip group (including the first logic chip 312, the first memory chip 322, and the second memory chip 332), the second chip group (including the second logic chip 314, the third memory chip 324, and the fourth memory chip 334), the third chip group (including the third logic chip 316, the fifth memory chip 326, and the sixth memory chip 336), and the fourth chip group ( Including the fourth logic chip 318 , the seventh memory chip 328 , and the eighth memory chip 338 ) are each a square. Taking the first chip group as an example, W1+W3=L1+L3, wherein, W1 is the width of the first memory chip 322 and the second memory chip 332, W3 is the width of the first logic chip 312, and L1 is the width of the first memory chip 312. The length of a memory chip 322, L3 is the length of the second memory chip 332, and the length of the first logic chip 312 is L1+L3. If the first wafer group is rotated clockwise by 90 degrees, 180 degrees, and 270 degrees relative to the center 301, each wafer of the rotated first wafer group will be aligned with the second wafer group and the third wafer group respectively. , and corresponding chips in the fourth chip group substantially overlap (the first logic chip 312, the second logic chip 314, the third logic chip 316, and the fourth logic chip 318 correspond to each other, the first memory chip 322, The third memory chip 324, the fifth memory chip 326, and the seventh memory chip 328 correspond to each other, and the second memory chip 332, the fourth memory chip 334, the sixth memory chip 336, and the eighth memory chip bulk wafers 338 correspond to each other). Moreover, since the first chip group, the second chip group, the third chip group, and the fourth chip group are all square, the integrated circuit product 300 is also a square.

對第一晶片群組而言，第一邏輯晶片312可以存取第一記憶體晶片322及第二記憶體晶片332。其他晶片群組同理，故不再贅述。 For the first chip group, the first logic chip 312 can access the first memory chip 322 and the second memory chip 332 . The same is true for other chip groups, so no more details are given here.

在一些實施例中，第一邏輯晶片312、第二邏輯晶片314、第三邏輯晶片316、及第四邏輯晶片318的組成元件實質上相同，第一記憶體晶片322、第三記憶體晶片324、第五記憶體晶片326、及第七記憶體晶片328的組成元件實質上相同，而且第二記憶體晶片332、第四記憶體晶片334、第六記憶體晶片336、及第八記憶體晶片338的組成元件實質上相同。前述的組成元件包含但不限於電晶體、電阻、電容、和/或電感。在另一些實施例中，第一邏輯晶片312、第二邏輯晶片314、第三邏輯晶片316、及第四邏輯晶片318的組成元件在種類及數量上相同，第一記憶體晶片322、第三記憶體晶片324、第五記憶體晶片326、及第七記憶體晶片328的組成元件在種類及數量上相同，而且第二記憶體晶片332、第四記憶體晶片334、第六記憶體晶片336、及第八記憶體晶片338的組成元件在種類及數量上相同。 In some embodiments, the components of the first logic chip 312, the second logic chip 314, the third logic chip 316, and the fourth logic chip 318 are substantially the same, and the first memory chip 322 and the third memory chip 324 , the fifth memory chip 326, and the seventh memory chip 328 have substantially the same components, and the second memory chip 332, the fourth memory chip 334, the sixth memory chip 336, and the eighth memory chip Group of 338 components are substantially the same. The aforementioned components include but are not limited to transistors, resistors, capacitors, and/or inductors. In other embodiments, the components of the first logic chip 312, the second logic chip 314, the third logic chip 316, and the fourth logic chip 318 are the same in type and quantity, and the first memory chip 322, the third logic chip The constituent elements of the memory chip 324, the fifth memory chip 326, and the seventh memory chip 328 are identical in type and quantity, and the second memory chip 332, the fourth memory chip 334, and the sixth memory chip 336 , and the eighth memory chip 338 are the same in type and quantity.

在一些實施例中，圖6中的8個記憶體晶片完全相同；換言之，L1=L3。 In some embodiments, the eight memory chips in FIG. 6 are identical; in other words, L1=L3.

在另一些實施例中，圖6中的8個記憶體晶片是第三代高頻寬記憶體(high bandwidth memory generation 3,HBM3)，且W1=L1=L3。 In some other embodiments, the 8 memory chips in FIG. 6 are the third generation high bandwidth memory (high bandwidth memory generation 3, HBM3), and W1=L1=L3.

圖7為本發明另一實施例的積體電路產品之簡化後的晶片排佈的示意圖。圖7顯示積體電路產品400的俯視圖。積體電路產品400包含第一邏輯晶片412、第二邏輯晶片414、第三邏輯晶片416、第四邏輯晶片418、第一記憶體晶片422、第二記憶體晶片432、第三記憶體晶片424、第四記憶體晶片434、第五記憶體晶片426、第六記憶體晶片436、第七記憶體晶片428、第八記憶體晶片438、第一其他晶片442、第二其他晶片444、第三其他晶片446、及第四其他晶片448。積體電路產品400的晶片排佈方式及特點與積體電路產品100及積體電路產品200相似，差別在於積體電路產品400的一個晶片群組包含1個邏輯晶片、2個記憶體晶片、及1個其他晶片。 FIG. 7 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention. FIG. 7 shows a top view of an integrated circuit product 400 . The integrated circuit product 400 includes a first logic chip 412 , a second logic chip 414 , a third logic chip 416 , a fourth logic chip 418 , a first memory chip 422 , a second memory chip 432 , and a third memory chip 424 , the fourth memory chip 434, the fifth memory chip 426, the sixth memory chip 436, the seventh memory chip 428, the eighth memory chip 438, the first other chip 442, the second other chip 444, the third other wafer 446 , and a fourth other wafer 448 . The IC product 400 has similar chip arrangement and features to the IC product 100 and the IC product 200, the difference being that a chip group of the IC product 400 includes 1 logic chip, 2 memory chips, and 1 other chip.

在一些實施例中，第一晶片群組(包含第一邏輯晶片412、第一記憶體晶片422、第二記憶體晶片432、及第一其他晶片442)、第二晶片群組(包含第二邏輯晶片414、第三記憶體晶片424、第四記憶體晶片434、及第二其他晶片444)、第三晶片群組(包含第三邏輯晶片316、第五記憶體晶片326、第六記憶體晶片336、及第三其他晶片446)、及第四晶片群組(包含第四邏輯晶片318、第七記憶體晶片328、第八記憶體晶片338、及第四其他晶片448)各為一個正方形。以第一晶片群組為例，W1+W4=L1+L3+L4，其中，W1是第一記憶體晶片422、第二記憶體晶片432、及第一其他晶片442的寬度，W4是第一邏輯晶片412的寬度，L1是第一記憶體晶片422的長度，L3是第二記憶體晶片432的長度，L4是第一其他晶片442的長度，而第一邏輯晶片412的長度是L1+L3+L4。倘若將第一晶片群組相對於中心401順時針旋轉90度、180度、及270度，則旋轉後的第一晶片群組的各晶片將分別與第二晶片群組、第三晶片群組、及第四晶片群組中相對應的晶片實質上重疊(第一邏輯晶片412、第二邏輯晶片414、第三邏輯晶片416、及第四邏輯晶片418互相對應，第一記憶體晶片422、第三記憶體晶片424、第五記憶體晶片426、及第七記憶體晶片428互相對應，第二記憶體晶片432、第四記憶體晶片434、第六記憶體晶片436、及第八記憶體晶片438互相對應，且第一其他晶片442、第二其他晶片444、第三其他晶片446、及第四其他晶片448互相對應)。再者，因為第一晶片群組、第二晶片群組、第三晶片群組、及第四晶片群組皆為正方形，所以積體電路產品400也是一個正方形。 In some embodiments, the first die group (including the first logic die 412, the first memory die 422, the second memory die 432, and the first other die 442), the second die group (including the second logic chip 414, the third memory chip 424, the fourth memory chip 434, and the second other chip 444), the third chip group (including the third logic chip 316, the fifth memory chip 326, the sixth memory chip chip 336, and the third other chip 446), and the fourth chip group (including the fourth logic chip 318, the seventh memory Die 328, eighth memory die 338, and fourth other die 448) are each a square. Take the first chip group as an example, W1+W4=L1+L3+L4, wherein, W1 is the width of the first memory chip 422, the second memory chip 432, and the first other chip 442, W4 is the first The width of the logic chip 412, L1 is the length of the first memory chip 422, L3 is the length of the second memory chip 432, L4 is the length of the first other chip 442, and the length of the first logic chip 412 is L1+L3 +L4. If the first wafer group is rotated 90 degrees, 180 degrees, and 270 degrees clockwise relative to the center 401, each wafer of the rotated first wafer group will be aligned with the second wafer group and the third wafer group respectively. , and corresponding chips in the fourth chip group substantially overlap (the first logic chip 412, the second logic chip 414, the third logic chip 416, and the fourth logic chip 418 correspond to each other, the first memory chip 422, The third memory chip 424, the fifth memory chip 426, and the seventh memory chip 428 correspond to each other, the second memory chip 432, the fourth memory chip 434, the sixth memory chip 436, and the eighth memory chip Die 438 correspond to each other, and first further die 442, second further die 444, third further die 446, and fourth further die 448 correspond to each other). Moreover, since the first chip group, the second chip group, the third chip group, and the fourth chip group are all square, the integrated circuit product 400 is also a square.

對第一晶片群組而言，第一邏輯晶片412可以存取第一記憶體晶片422及第二記憶體晶片432。其他晶片群組同理，故不再贅述。 For the first chip group, the first logic chip 412 can access the first memory chip 422 and the second memory chip 432 . The same is true for other chip groups, so no more details are given here.

在一些實施例中，第一邏輯晶片412、第二邏輯晶片414、第三邏輯晶片416、及第四邏輯晶片418的組成元件實質上相同，第一記憶體晶片422、第三記憶體晶片424、第五記憶體晶片426、及第七記憶體晶片428的組成元件實質上相同，第二記憶體晶片432、第四記憶體晶片434、第六記憶體晶片436、及第八記憶體晶片438的組成元件實質上相同，而且第一其他晶片442、第二其他晶片444、第三其他晶片446、及第四其他晶片448的組成元件實質上相同。前述的組成元件包含但不限於電晶體、電阻、電容、和/或電感。在另一些實施例中，第一邏輯晶片412、第二邏輯晶片414、第三邏輯晶片416、及第四邏輯晶片418的組成元件在種類及數量上相同，第一記憶體晶片422、第三記憶體晶片424、第五記憶體晶片426、及第七記憶體晶片428的組成元件在種類及數量上相同，第二記憶體晶片432、第四記憶體晶片434、第六記憶體晶片436、及第八記憶體晶片438的組成元件在種類及數量上相同，而且第一其他晶片442、第二其他晶片444、第三其他晶片446、及第四其他晶片448的組成元件在種類及數量上相同。 In some embodiments, the components of the first logic chip 412, the second logic chip 414, the third logic chip 416, and the fourth logic chip 418 are substantially the same, the first memory chip 422, the third memory chip 424 , the fifth memory chip 426, and the seventh memory chip 428 have substantially the same components, the second memory chip 432, the fourth memory chip 434, the sixth memory chip 436, and the eighth memory chip 438 The components are substantially the same, and the components of the first other chip 442, the second other chip 444, the third other chip 446, and the fourth other chip 448 are substantially the same. The aforementioned components include but are not limited to transistors, resistors, capacitors, and/or inductors. in others In the embodiment, the constituent elements of the first logic chip 412, the second logic chip 414, the third logic chip 416, and the fourth logic chip 418 are the same in type and quantity, and the first memory chip 422, the third memory chip 424, the fifth memory chip 426, and the seventh memory chip 428 have the same components in type and quantity, the second memory chip 432, the fourth memory chip 434, the sixth memory chip 436, and the eighth memory chip The components of the memory chip 438 are the same in type and quantity, and the components of the first other chip 442 , the second other chip 444 , the third other chip 446 , and the fourth other chip 448 are the same in type and quantity.

在一些實施例中，圖7中的8個記憶體晶片完全相同；換言之，L1=L3。 In some embodiments, the eight memory chips in FIG. 7 are identical; in other words, L1=L3.

在圖7的實施例中，第二記憶體晶片432、第四記憶體晶片434、第六記憶體晶片436、及第八記憶體晶片438被安排在積體電路產品400的四個角，第一記憶體晶片422(第三記憶體晶片424、第五記憶體晶片426、或第七記憶體晶片428)被安排在第二記憶體晶片432(第四記憶體晶片434、第六記憶體晶片436、或第八記憶體晶片438)與第一其他晶片442(第二其他晶片444、第三其他晶片446、或第四其他晶片448)之間。 In the embodiment of FIG. 7, the second memory chip 432, the fourth memory chip 434, the sixth memory chip 436, and the eighth memory chip 438 are arranged at the four corners of the integrated circuit product 400. A memory chip 422 (the third memory chip 424, the fifth memory chip 426, or the seventh memory chip 428) is arranged on the second memory chip 432 (the fourth memory chip 434, the sixth memory chip 436, or the eighth memory chip 438) and the first other chip 442 (the second other chip 444, the third other chip 446, or the fourth other chip 448).

圖8為本發明另一實施例的積體電路產品之簡化後的晶片排佈的示意圖。圖8顯示積體電路產品500的俯視圖。積體電路產品500與積體電路產品400相似，差別在於第一其他晶片442、第二其他晶片444、第三其他晶片446、及第四其他晶片448被安排在積體電路產品500的四個角，第二記憶體晶片432(第四記憶體晶片434、第六記憶體晶片436、或第八記憶體晶片438)被安排在第一記憶體晶片422(第三記憶體晶片424、第五記憶體晶片426、或第七記憶體晶片428)與第一其他晶片442(第二其他晶片444、第三其他晶片446、或第四其他晶片448)之間。 FIG. 8 is a schematic diagram of a simplified chip layout of an integrated circuit product according to another embodiment of the present invention. FIG. 8 shows a top view of an integrated circuit product 500 . The integrated circuit product 500 is similar to the integrated circuit product 400 except that the first other chip 442, the second other chip 444, the third other chip 446, and the fourth other chip 448 are arranged on the four sides of the integrated circuit product 500. Corner, the second memory chip 432 (the fourth memory chip 434, the sixth memory chip 436, or the eighth memory chip 438) is arranged on the first memory chip 422 (the third memory chip 424, the fifth memory chip 438) between the memory chip 426, or the seventh memory chip 428) and the first other chip 442 (the second other chip 444, the third other chip 446, or the fourth other chip 448).

圖9為本發明另一實施例的積體電路產品之簡化後的晶片排佈的示意圖。圖9顯示積體電路產品600的俯視圖。積體電路產品600與積體電路產品400相似，差別在於第一其他晶片442(第二其他晶片444、第三其他晶片446、或第四其他晶片448)被安排在第一記憶體晶片422(第三記憶體晶片424、第五記憶體晶片426、或第七記憶體晶片428)與第二記憶體晶片432(第四記憶體晶片434、第六記憶體晶片436、或第八記憶體晶片438)之間。 Fig. 9 is the illustration of the simplified chip arrangement of the integrated circuit product of another embodiment of the present invention intention. FIG. 9 shows a top view of an integrated circuit product 600 . The integrated circuit product 600 is similar to the integrated circuit product 400 except that the first other chip 442 (the second other chip 444, the third other chip 446, or the fourth other chip 448) is arranged on the first memory chip 422 ( The third memory chip 424, the fifth memory chip 426, or the seventh memory chip 428) and the second memory chip 432 (the fourth memory chip 434, the sixth memory chip 436, or the eighth memory chip 438).

圖1及圖5~9中的記憶體晶片是第三代高頻寬記憶體(high bandwidth memory generation 3,HBM3)，其形狀為正方形。然而，上述之記憶體晶片也可以是第二代高頻寬記憶體(high bandwidth memory generation 2,HBM2)，如圖10~15(分別對應於圖1及圖5~9)所示。積體電路產品700及積體電路產品800之第一記憶體晶片722、第二記憶體晶片724、第三記憶體晶片726、第四記憶體晶片728、積體電路產品900之第一記憶體晶片922、第二記憶體晶片932、第三記憶體晶片924、第四記憶體晶片934、第五記憶體晶片926、第六記憶體晶片936、第七記憶體晶片928、第八記憶體晶片938、積體電路產品1000、積體電路產品1100、及積體電路產品1200之第一記憶體晶片1022、第二記憶體晶片1032、第三記憶體晶片1024、第四記憶體晶片1034、第五記憶體晶片1026、第六記憶體晶片1036、第七記憶體晶片1028、及第八記憶體晶片1038是第二代高頻寬記憶體。圖10~15的說明可以分別對應於圖1及圖5~9的說明，故不再贅述。 The memory chip in Fig. 1 and Fig. 5-9 is the third generation high bandwidth memory (high bandwidth memory generation 3, HBM3), and its shape is square. However, the memory chips mentioned above can also be high bandwidth memory generation 2 (HBM2), as shown in FIGS. 10-15 (corresponding to FIGS. 1 and 5-9 respectively). The first memory chip 722 , the second memory chip 724 , the third memory chip 726 , the fourth memory chip 728 of the integrated circuit product 700 and the integrated circuit product 800 , the first memory of the integrated circuit product 900 Chip 922, second memory chip 932, third memory chip 924, fourth memory chip 934, fifth memory chip 926, sixth memory chip 936, seventh memory chip 928, eighth memory chip 938, the first memory chip 1022, the second memory chip 1032, the third memory chip 1024, the fourth memory chip 1034, the The fifth memory chip 1026 , the sixth memory chip 1036 , the seventh memory chip 1028 , and the eighth memory chip 1038 are second-generation high-bandwidth memories. The descriptions in FIGS. 10-15 may correspond to the descriptions in FIG. 1 and FIGS. 5-9 respectively, so details are not repeated here.

此外，在其他的實施例中，圖10~15中的記憶體晶片可以是增強型第二代高頻寬記憶體(Enhanced high bandwidth memory generation 2)。 In addition, in other embodiments, the memory chips shown in FIGS. 10-15 may be enhanced high bandwidth memory generation 2 (Enhanced high bandwidth memory generation 2).

綜上所述，本案所提出的晶片排佈可以使晶片在積體電路產品中緊密排列，因此得以充分利用基板面積以提高積體電路產品競爭力。再者，將積體電路產品上的晶片以旋轉對稱和/或點對稱的方式排佈，除了可以避免接腳浪費，還有利於使用相同的光罩來製造積體電路產品的不同部位，因而可簡化光罩複雜度。 To sum up, the arrangement of the chips proposed in this case can make the chips closely arranged in the integrated circuit products, so the substrate area can be fully utilized to improve the competitiveness of the integrated circuit products. Furthermore, arranging the chips on the integrated circuit product in a rotationally symmetrical and/or point-symmetrical manner In addition to avoiding the waste of pins, it is also beneficial to use the same mask to manufacture different parts of the integrated circuit product, thus simplifying the complexity of the mask.

從另一角度而言，將積體電路產品上的晶片以前述的旋轉對稱和/或點對稱方式進行排佈，半導體製造商便可利用同一套光罩製造出面積接近4倍大小的積體電路產品，故可大幅降低積體電路產品的製造成本。 From another point of view, by arranging the chips on the integrated circuit products in the aforementioned rotationally symmetrical and/or point-symmetrical manner, semiconductor manufacturers can use the same set of photomasks to manufacture integrated circuits with an area nearly four times the size. Circuit products, so the manufacturing cost of integrated circuit products can be greatly reduced.

請注意，前述積體電路產品上的晶片排佈方式只是示範性的實施例，並非侷限本發明的實際實施方式。例如，在某些實施例中，可將前述的邏輯晶片、記憶體晶片、和/或其他晶片改以相對於積體電路產品的中心軸(通過中心且與任一邊垂直)呈現線對稱的方式排佈在積體電路產品的四個象限。 Please note that the arrangement of chips on the aforementioned integrated circuit product is only an exemplary embodiment, and does not limit the actual implementation of the present invention. For example, in some embodiments, the aforementioned logic chips, memory chips, and/or other chips can be changed to present a line-symmetrical manner with respect to the central axis (through the center and perpendicular to any side) of the integrated circuit product. Arranged in four quadrants of integrated circuit products.

在說明書及申請專利範圍中使用了某些詞彙來指稱特定的元件，而本領域內的技術人員可能會用不同的名詞來稱呼同樣的元件。本說明書及申請專利範圍並不以名稱的差異來做為區分元件的方式，而是以元件在功能上的差異來做為區分的基準。在說明書及申請專利範圍中所提及的「包含」為開放式的用語，應解釋成「包含但不限定於」。另外，「耦接」一詞在此包含任何直接及間接的連接手段。因此，若文中描述第一元件耦接於第二元件，則代表第一元件可通過電性連接或無線傳輸、光學傳輸等信號連接方式而直接地連接於第二元件，或通過其它元件或連接手段間接地電性或信號連接至第二元件。 Certain words are used to refer to specific elements in the specification and scope of claims, but those skilled in the art may use different terms to refer to the same element. This specification and the scope of the patent application do not use the difference in name as a way to distinguish components, but use the difference in function of components as a basis for differentiation. The "comprising" mentioned in the specification and scope of patent application is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" herein includes any direct and indirect means of connection. Therefore, if it is described that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection means such as wireless transmission or optical transmission, or through other elements or connections. The means is indirectly electrically or signally connected to the second element.

在說明書中所使用的「和/或」的描述方式，包含所列舉的其中一個項目或多個項目的任意組合。另外，除非說明書中特別指明，否則任何單數格的用語都同時包含複數格的含義。 The description of "and/or" used in the specification includes any combination of one or more of the listed items. In addition, unless otherwise specified in the specification, any singular term also includes a plural meaning.

圖式的某些元件的尺寸及相對大小會被加以放大，或者某些元件的形狀會被簡化，以便能更清楚地表達實施例的內容。因此，除非申請人有特別指明，圖式中各元件的形狀、尺寸、相對大小及相對位置等僅是便於說明，而不應被用來限縮本發明的專利範圍。此外，本發明可用許多不同的形式來體現，在解釋本發明時，不應僅侷限於本說明書所提出的實施例態樣。 The dimensions and relative sizes of some elements in the drawings will be exaggerated, or the shapes of some elements will be simplified in order to express the contents of the embodiments more clearly. Therefore, unless otherwise specified by the applicant, the shape, size, relative size and relative position of each element in the drawings Arrangements and the like are for convenience of description only, and should not be used to limit the patent scope of the present invention. In addition, the present invention can be embodied in many different forms, and when explaining the present invention, it should not be limited only to the embodiments presented in this specification.

為了說明上的方便，說明書中可能會使用一些與空間中的相對位置有關的敘述，對圖式中某元件的功能或是該元件與其他元件間的相對空間關係進行描述。例如，「於...上」、「在...上方」、「於...下」、「在...下方」、「高於...」、「低於...」、「向上」、「向下」等等。所屬技術領域中具有通常知識者應可理解，這些與空間中的相對位置有關的敘述，不僅包含所描述的元件在圖式中的指向關係(orientation)，也包含所描述的元件在使用、運作、或組裝時的各種不同指向關係。例如，若將圖式上下顛倒過來，則原先用「於...上」來描述的元件，就會變成「於...下」。因此，在說明書中所使用的「於...上」的描述方式，解釋上包含了「於...下」以及「於...上」兩種不同的指向關係。同理，在此所使用的「向上」一詞，解釋上包含了「向上」以及「向下」兩種不同的指向關係。 For the convenience of description, some descriptions related to relative positions in space may be used in the description to describe the function of a certain component in the drawings or the relative spatial relationship between the component and other components. For example, "on", "above", "below", "below", "above", "below", "Up", "Down", etc. Those with ordinary knowledge in the technical field should understand that these descriptions related to relative positions in space not only include the orientation of the described components in the drawings, but also include the use and operation of the described components. , or various different pointing relationships during assembly. For example, if the drawing is turned upside down, the element originally described as "on" will become "below". Therefore, the description of "on" used in the specification includes two different pointing relationships of "below" and "on". In the same way, the term "upward" used here includes two different pointing relationships of "upward" and "downward".

在說明書及申請專利範圍中，若描述第一元件位於第二元件上、在第二元件上方、連接、接合、耦接於第二元件或與第二元件相接，則表示第一元件可直接位在第二元件上、直接連接、直接接合、直接耦接於第二元件，亦可表示第一元件與第二元件間存在其他元件。相對之下，若描述第一元件直接位在第二元件上、直接連接、直接接合、直接耦接、或直接相接於第二元件，則代表第一元件與第二元件間不存在其他元件。 In the description and scope of the patent application, if it is described that the first element is located on the second element, above the second element, connected, bonded, coupled to the second element, or in contact with the second element, it means that the first element can directly Located on the second element, directly connected, directly bonded, or directly coupled to the second element may also mean that there are other elements between the first element and the second element. In contrast, if it is described that the first element is directly on the second element, directly connected, directly bonded, directly coupled, or directly connected to the second element, it means that there are no other elements between the first element and the second element .

以上僅為本發明的較佳實施例，凡依本發明請求項所做的等效變化與修改，皆應屬本發明的涵蓋範圍。 The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

100:積體電路產品 100:Integrated circuit products

112:第一邏輯晶片 112: The first logic chip

114:第二邏輯晶片 114: second logic chip

116:第三邏輯晶片 116: The third logic chip

118:第四邏輯晶片 118: The fourth logic chip

122:第一記憶體晶片 122: The first memory chip

124:第二記憶體晶片 124: Second memory chip

126:第三記憶體晶片 126: The third memory chip

128:第四記憶體晶片 128: The fourth memory chip

132:第一其他晶片 132: The first other chip

134:第二其他晶片 134: The second other chip

136:第三其他晶片 136: The third other chip

138:第四其他晶片 138: The fourth other chip

102:第一邊 102: First side

104:第二邊 104: second side

106:第三邊 106: third side

108:第四邊 108: Fourth side

101:中心 101: center

W1、W2:寬度 W1, W2: Width

L1、L2:長度 L1, L2: Length

Claims

一種積體電路產品(100；200；300；400；500；600)，包含有：一第一晶片(112；312；412)；一第二晶片(114；314；414)；一第三晶片(116；316；416)；一第四晶片(118；318；418)；一第五晶片(122；322；422)；一第六晶片(124；324；424)；一第七晶片(126；326；426)；一第八晶片(128；328；428)；一第九晶片(132；332；432)；一第十晶片(134；334；434)；一第十一晶片(136；336；436)；以及一第十二晶片(138；338；438)；其中，該第一晶片(112；312；412)、該第二晶片(114；314；414)、該第三晶片(116；316；416)、及該第四晶片(118；318；418)分別位於該積體電路產品之一第一象限、一第四象限、一第三象限、及一第二象限，且該第一晶片(112；312；412)鄰接該第二晶片(114；314；414)及該第四晶片(118；318；418)；該第五晶片(122；322；422)、該第六晶片(124；324；424)、該第七晶片(126；326；426)、及該第八晶片(128；328；428)分別位於該積體電路產品之該第一象限、該第四象限、該第三象限、及該第二象限，且該第五晶片(122；322；422)、該第六晶片(124；324；424)、該第七晶片(126；326；426)、及該第八晶片(128；328；428)之任二者不鄰接；該第九晶片(132；332；432)、該第十晶片(134；334；434)、該第十一晶片(136；336；436)、及該第十二晶片(138；338；438)分別位於該積體電路產品之該第一象限、該第四象限、該第三象限、及該第二象限，且該第九晶片(132；332；432)、該第十晶片(134；334；434)、該第十一晶片(136；336；436)、及該第十二晶片(138；338；438)之任二者不鄰接；且其中，該第一晶片(112；312；412)、該第二晶片(114；314；414)、該第三晶片(116；316；416)、及該第四晶片(118；318；418)分別與該積體電路產品(100；200；300；400；500；600)之一第二邊(104)、一第三邊(106)、一第四邊(108)、及一第一邊(102)鄰接；其中，該第一晶片(112；312；412)、該第二晶片(114；314；414)、該第三晶片(116；316；416)、及該第四晶片(118；318；418)係邏輯晶片；以及該第五晶片(122；322；422)、該第六晶片(124；324；424)、該第七晶片(126；326；426)、及該第八晶片(128；328；428)係記憶體晶片。 An integrated circuit product (100; 200; 300; 400; 500; 600), comprising: a first chip (112; 312; 412); a second chip (114; 314; 414); a third chip (116; 316; 416); a fourth chip (118; 318; 418); a fifth chip (122; 322; 422); a sixth chip (124; 324; 424); a seventh chip (126 ; 326; 426); one eighth chip (128; 328; 428); one ninth chip (132; 332; 432); one tenth chip (134; 334; 434); one eleventh chip (136; 336; 436); and a twelfth wafer (138; 338; 438); wherein, the first wafer (112; 312; 412), the second wafer (114; 314; 414), the third wafer ( 116; 316; 416), and the fourth chip (118; 318; 418) are respectively located in a first quadrant, a fourth quadrant, a third quadrant, and a second quadrant of the integrated circuit product, and the The first wafer (112; 312; 412) adjoins the second wafer (114; 314; 414) and the fourth wafer (118; 318; 418); the fifth wafer (122; 322; 422), the sixth Chip (124; 324; 424), the seventh chip (126; 326; 426), and the eighth chip (128; 328; 428) are respectively located in the first quadrant and the fourth quadrant of the integrated circuit product , the third quadrant, and the second quadrant, and the fifth wafer (122; 322; 422), the sixth wafer (124; 324; 424), the seventh wafer (126; 326; 426), and No two of the eighth chips (128; 328; 428) are adjacent connected; the ninth chip (132; 332; 432), the tenth chip (134; 334; 434), the eleventh chip (136; 336; 436), and the twelfth chip (138; 338; 438) respectively located in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and the ninth chip (132; 332; 432), the tenth chip (134 ; 334; 434), the eleventh wafer (136; 336; 436), and any two of the twelfth wafer (138; 338; 438) are not adjacent; and wherein the first wafer (112; 312 ; 412), the second chip (114; 314; 414), the third chip (116; 316; 416), and the fourth chip (118; 318; 418) and the integrated circuit product (100; 200; 300; 400; 500; 600) a second side (104), a third side (106), a fourth side (108), and a first side (102) adjacent; wherein, the first the die (112; 312; 412), the second die (114; 314; 414), the third die (116; 316; 416), and the fourth die (118; 318; 418) are logic dies; and The fifth chip (122; 322; 422), the sixth chip (124; 324; 424), the seventh chip (126; 326; 426), and the eighth chip (128; 328; 428) are memory body chip.

如請求項1所述的積體電路產品(100；200；300；400；500；600)，其中，該第一晶片(112；312；412)、該第二晶片(114；314；414)、該第三晶片(116；316；416)、該第四晶片(118；318；418)、該第五晶片(122；322；422)、該第六晶片(124；324；424)、該第七晶片(126；326；426)、該第八晶片(128；328；428)、該第九晶片(132；332；432)、該第十晶片(134；334；434)、該第十一晶片(136；336；436)、及該第十二晶片(138；338；438)實質上位於同一平面，該第一晶片(112；312；412)與該第三晶片(116；316；416)相對於該積體電路產品 (100；200；300；400；500；600)之一中心(101；301；401)呈現點對稱，該第二晶片(114；314；414)與該第四晶片(118；318；418)相對於該中心(101；301；401)呈現點對稱，該第五晶片(122；322；422)與該第七晶片(126；326；426)相對於該中心(101；301；401)呈現點對稱，該第六晶片(124；324；424)與該第八晶片(128；328；428)相對於該中心(101；301；401)呈現點對稱，該第九晶片(132；332；432)與該第十一晶片(136；336；436)相對於該中心(101；301；401)呈現點對稱，且該第十晶片(134；334；434)與該第十二晶片(138；338；438)相對於該中心(101；301；401)呈現點對稱。 The integrated circuit product (100; 200; 300; 400; 500; 600) as claimed in claim 1, wherein the first chip (112; 312; 412), the second chip (114; 314; 414) , the third wafer (116; 316; 416), the fourth wafer (118; 318; 418), the fifth wafer (122; 322; 422), the sixth wafer (124; 324; 424), the The seventh chip (126; 326; 426), the eighth chip (128; 328; 428), the ninth chip (132; 332; 432), the tenth chip (134; 334; 434), the tenth chip A chip (136; 336; 436) and the twelfth chip (138; 338; 438) are substantially on the same plane, the first chip (112; 312; 412) and the third chip (116; 316; 416) With respect to the integrated circuit product One center (101; 301; 401) of (100; 200; 300; 400; 500; 600) presents point symmetry, the second chip (114; 314; 414) and the fourth chip (118; 318; 418) Relative to the center (101; 301; 401), presenting point symmetry, the fifth wafer (122; 322; 422) and the seventh wafer (126; 326; 426) present relative to the center (101; 301; 401) Point symmetry, the sixth wafer (124; 324; 424) and the eighth wafer (128; 328; 428) present point symmetry with respect to the center (101; 301; 401), the ninth wafer (132; 332; 432) and the eleventh wafer (136; 336; 436) present point symmetry with respect to the center (101; 301; 401), and the tenth wafer (134; 334; 434) and the twelfth wafer (138 ; 338; 438) exhibit point symmetry with respect to the center (101; 301; 401).

如請求項1所述的積體電路產品(100；200；300；400；500；600)，其中，該第五晶片(122；322；422)、該第六晶片(124；324；424)、該第七晶片(126；326；426)、及該第八晶片(128；328；428)分別與該積體電路產品(100；200；300；400；500；600)之該第一邊(102)、該第二邊(104)、該第三邊(106)、及該第四邊(108)鄰接。 The integrated circuit product (100; 200; 300; 400; 500; 600) as claimed in claim 1, wherein the fifth chip (122; 322; 422), the sixth chip (124; 324; 424) , the seventh chip (126; 326; 426), and the eighth chip (128; 328; 428) and the first side of the integrated circuit product (100; 200; 300; 400; 500; 600) (102), the second side (104), the third side (106), and the fourth side (108) are contiguous.

如請求項3所述的積體電路產品(100)，其中，該第五晶片(122)、該第六晶片(124)、該第七晶片(126)、及該第八晶片(128)更分別與該積體電路產品(100)之該第二邊(104)、該第三邊(106)、該第四邊(108)、及該第一邊(102)鄰接。 The integrated circuit product (100) as described in claim 3, wherein the fifth chip (122), the sixth chip (124), the seventh chip (126), and the eighth chip (128) are further respectively adjacent to the second side (104), the third side (106), the fourth side (108), and the first side (102) of the integrated circuit product (100).

如請求項1所述的積體電路產品(100；200；300；400；500；600)，其中，該第九晶片(132；332；432)、該第十晶片(134；334；434)、該第十一晶片(136；336；436)、及該第十二晶片(138；338；438)分別與該積體電路產品(100；200；300；400；500；600)之該第一邊(102)、該第二邊(104)、該第三邊(106)、及該第四邊(108)鄰接。 The integrated circuit product (100; 200; 300; 400; 500; 600) as claimed in claim 1, wherein the ninth chip (132; 332; 432), the tenth chip (134; 334; 434) , the eleventh chip (136; 336; 436), and the twelfth chip (138; 338; 438) and the integrated circuit product (100; 200; 300; 400; 500; 600) respectively One side (102), the second side (104), the third side (106), and the fourth side (108) are contiguous.

如請求項5所述的積體電路產品(200；300；400；600)，其中，該第九晶片(132；332；432)、該第十晶片(134；334；434)、該第十一晶片(136；336；436)、及該第十二晶片(138；338；438)更分別與該積體電路產品(200；300；400；600)之該第二邊(104)、該第三邊(106)、該第四邊(108)、及該第一邊(102)鄰接。 The integrated circuit product (200; 300; 400; 600) as claimed in claim 5, wherein, The ninth wafer (132; 332; 432), the tenth wafer (134; 334; 434), the eleventh wafer (136; 336; 436), and the twelfth wafer (138; 338; 438) and the second side (104), the third side (106), the fourth side (108), and the first side (102) of the integrated circuit product (200; 300; 400; 600) respectively adjacent.

如請求項1所述的積體電路產品(300；400；500；600)，其中，該第九晶片(332；432)、該第十晶片(334；434)、該第十一晶片(336；436)、及該第十二晶片(338；438)係記憶體晶片。 The integrated circuit product (300; 400; 500; 600) as claimed in claim 1, wherein the ninth chip (332; 432), the tenth chip (334; 434), the eleventh chip (336 ; 436), and the twelfth chip (338; 438) is a memory chip.

如請求項7所述的積體電路產品(400；500；600)，更包含：一第十三晶片(442)；一第十四晶片(444)；一第十五晶片(446)；以及一第十六晶片(448)；其中，該第十三晶片(442)、該第十四晶片(444)、該第十五晶片(446)、及該第十六晶片(448)分別位於該第一象限、該第四象限、該第三象限、及該第二象限；且該第五晶片(422)、該第六晶片(424)、該第七晶片(426)、及該第八晶片(428)、該第九晶片(432)、該第十晶片(434)、該第十一晶片(436)、該第十二晶片(438)、該第十三晶片(442)、該第十四晶片(444)、該第十五晶片(446)、及該第十六晶片(448)具有相同的寬度(W1)。 The integrated circuit product (400; 500; 600) as described in Claim 7, further comprising: a thirteenth chip (442); a fourteenth chip (444); a fifteenth chip (446); and A sixteenth wafer (448); wherein, the thirteenth wafer (442), the fourteenth wafer (444), the fifteenth wafer (446), and the sixteenth wafer (448) are located at the the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant; and the fifth wafer (422), the sixth wafer (424), the seventh wafer (426), and the eighth wafer (428), the ninth wafer (432), the tenth wafer (434), the eleventh wafer (436), the twelfth wafer (438), the thirteenth wafer (442), the tenth wafer The fourth wafer (444), the fifteenth wafer (446), and the sixteenth wafer (448) have the same width (W1).

如請求項8所述的積體電路產品(400；500)，其中，該第五晶片(422)位於該第九晶片(432)與該第十三晶片(442)之間，該第六晶片(424)位於該第十晶片(434)與該第十四晶片(444)之間，該第七晶片(426)位於該第十一晶片(436)與該第十五晶片(446)之間，以及該第八晶片(428)位於該第十二晶片(438)與該第十六晶片(448)之間。 The integrated circuit product (400; 500) according to claim 8, wherein the fifth chip (422) is located between the ninth chip (432) and the thirteenth chip (442), and the sixth chip (424) between the tenth wafer (434) and the fourteenth wafer (444), the seventh wafer (426) between the eleventh wafer (436) and the fifteenth wafer (446) , and the eighth wafer (428) is located between the twelfth wafer (438) and the sixteenth wafer (448).

如請求項9所述的積體電路產品(400)，其中，該第九晶片(432)、該第十晶片(434)、該第十一晶片(436)、及該第十二晶片(438)分別位於該積體電路產品(400)的四個角。 The integrated circuit product (400) as claimed in claim 9, wherein the ninth chip (432), the tenth chip (434), the eleventh chip (436), and the twelfth chip (438 ) are respectively located at the four corners of the integrated circuit product (400).

如請求項9所述的積體電路產品(500)，其中，該第十三晶片(442)、該第十四晶片(444)、該第十五晶片(446)、及該第十六晶片(448)分別位於該積體電路產品(500)的四個角。 The integrated circuit product (500) as claimed in item 9, wherein, the thirteenth chip (442), the fourteenth chip (444), the fifteenth chip (446), and the sixteenth chip (448) are respectively located at four corners of the integrated circuit product (500).

如請求項8所述的積體電路產品(600)，其中，該第十三晶片(442)位於該第五晶片(422)與該第九晶片(432)之間，該第十四晶片(444)位於該第六晶片(424)與該第十晶片(434)之間，該第十五晶片(446)位於該第七晶片(426)與該第十一晶片(436)之間，以及該第十六晶片(448)位於該第八晶片(428)與該第十二晶片(438)之間。 The integrated circuit product (600) as claimed in claim 8, wherein the thirteenth chip (442) is located between the fifth chip (422) and the ninth chip (432), and the fourteenth chip ( 444) between the sixth wafer (424) and the tenth wafer (434), the fifteenth wafer (446) between the seventh wafer (426) and the eleventh wafer (436), and The sixteenth wafer (448) is located between the eighth wafer (428) and the twelfth wafer (438).

一種積體電路產品(100；200；300；400；500；600)，包含有：一第一晶片(112；312；412)；一第二晶片(114；314；414)；一第三晶片(116；316；416)；一第四晶片(118；318；418)；一第五晶片(122；322；422)；一第六晶片(124；324；424)；一第七晶片(126；326；426)；一第八晶片(128；328；428)；一第九晶片(132；332；432)；一第十晶片(134；334；434)；一第十一晶片(136；336；436)；以及一第十二晶片(138；338；438)；其中，該第一晶片(112；312；412)、該第二晶片(114；314；414)、該第三晶片(116；316；416)、該第四晶片(118； 318；418)、該第五晶片(122；322；422)、該第六晶片(124；324；424)、該第七晶片(126；326；426)、及該第八晶片(128；328；428)、該第九晶片(132；332；432)、該第十晶片(134；334；434)、該第十一晶片(136；336；436)、及該第十二晶片(138；338；438)實質上位於一平面(PL)；倘若將該第一晶片(112；312；412)於該平面上相對於該積體電路產品(100；200；300；400；500；600)之一中心(101；301；401)旋轉九十度，則該第一晶片(112；312；412)與該第二晶片(114；314；414)或該第四晶片(118；318；418)實質上重疊，且倘若將該第一晶片(112；312；412)於該平面上相對於該中心(101；301；401)旋轉一百八十度，則該第一晶片(112；312；412)與該第三晶片(116；316；416)實質上重疊；倘若將該第五晶片(122；322；422)於該平面上相對於該中心(101；301；401)旋轉九十度，則該第五晶片(122；322；422)與該第六晶片(124；324；424)或該第八晶片(128；328；428)實質上重疊，且倘若將該第五晶片(122；322；422)於該平面上相對於該中心(101；301；401)旋轉一百八十度，則該第五晶片(122；322；422)與該第七晶片(126；326；426)實質上重疊；倘若將該第九晶片(132；332；432)於該平面上相對於該中心(101；301；401)旋轉九十度，則該第九晶片(132；332；432)與該第十晶片(134；334；434)或該第十二晶片(138；338；438)實質上重疊，且倘若將該第九晶片(132；332；432)於該平面上相對於該中心(101；301；401)旋轉一百八十度，則該第九晶片(132；332；432)與該第十一晶片(136； 336；436)實質上重疊；以及該第一晶片(112；312；412)、該第二晶片(114；314；414)、該第三晶片(116；316；416)、及該第四晶片(118；318；418)分別與該積體電路產品(100；200；300；400；500；600)之一第二邊(104)、一第三邊(106)、一第四邊(108)、及一第一邊(102)鄰接；其中，該第一晶片(112；312；412)、該第二晶片(114；314；414)、該第三晶片(116；316；416)、及該第四晶片(118；318；418)係邏輯晶片；以及該第五晶片(122；322；422)、該第六晶片(124；324；424)、該第七晶片(126；326；426)、及該第八晶片(128；328；428)係記憶體晶片。 An integrated circuit product (100; 200; 300; 400; 500; 600), comprising: a first chip (112; 312; 412); a second chip (114; 314; 414); a third chip (116; 316; 416); a fourth chip (118; 318; 418); a fifth chip (122; 322; 422); a sixth chip (124; 324; 424); a seventh chip (126 ; 326; 426); one eighth chip (128; 328; 428); one ninth chip (132; 332; 432); one tenth chip (134; 334; 434); one eleventh chip (136; 336; 436); and a twelfth wafer (138; 338; 438); wherein, the first wafer (112; 312; 412), the second wafer (114; 314; 414), the third wafer ( 116; 316; 416), the fourth chip (118; 318; 418), the fifth wafer (122; 322; 422), the sixth wafer (124; 324; 424), the seventh wafer (126; 326; 426), and the eighth wafer (128; 328 428), the ninth wafer (132; 332; 432), the tenth wafer (134; 334; 434), the eleventh wafer (136; 336; 436), and the twelfth wafer (138; 338; 438) lies substantially on a plane (PL); if the first chip (112; 312; 412) is on the plane relative to the integrated circuit product (100; 200; 300; 400; 500; 600) One of the centers (101; 301; 401) rotates ninety degrees, then the first wafer (112; 312; 412) and the second wafer (114; 314; 414) or the fourth wafer (118; 318; 418 ) substantially overlap, and if the first wafer (112; 312; 412) is rotated one hundred and eighty degrees in the plane relative to the center (101; 301; 401), the first wafer (112; 312 ; 412) substantially overlaps with the third wafer (116; 316; 416); if the fifth wafer (122; 322; 422) is rotated ninety degrees on the plane relative to the center (101; 301; 401) degree, the fifth wafer (122; 322; 422) substantially overlaps the sixth wafer (124; 324; 424) or the eighth wafer (128; 328; 428), and if the fifth wafer ( 122; 322; 422) is rotated one hundred and eighty degrees relative to the center (101; 301; 401) on the plane, then the fifth wafer (122; 322; 422) and the seventh wafer (126; 326; 426) substantially overlapping; if the ninth wafer (132; 332; 432) is rotated ninety degrees on the plane relative to the center (101; 301; 401), the ninth wafer (132; 332; 432 ) substantially overlaps the tenth wafer (134; 334; 434) or the twelfth wafer (138; 338; 438), and if the ninth wafer (132; 332; 432) is on the plane relative to The center (101; 301; 401) rotates one hundred and eighty degrees, then the ninth wafer (132; 332; 432) and the eleventh wafer (136; 336; 436) substantially overlap; and the first wafer (112; 312; 412), the second wafer (114; 314; 414), the third wafer (116; 316; 416), and the fourth wafer (118; 318; 418) and one second side (104), one third side (106), one fourth side (108) of the integrated circuit product (100; 200; 300; 400; 500; 600) respectively ), and a first side (102); wherein, the first wafer (112; 312; 412), the second wafer (114; 314; 414), the third wafer (116; 316; 416), and the fourth chip (118; 318; 418) is a logic chip; and the fifth chip (122; 322; 422), the sixth chip (124; 324; 424), the seventh chip (126; 326; 426), and the eighth chip (128; 328; 428) is a memory chip.

如請求項13所述的積體電路產品(100；200；300；400；500；600)，其中，該第一晶片(112；312；412)與該第二晶片及該第四晶片(118；318；418)鄰接，且該第二晶片(114；314；414)與該第一晶片及該第三晶片(116；316；416)鄰接。 The integrated circuit product (100; 200; 300; 400; 500; 600) according to claim 13, wherein the first chip (112; 312; 412) and the second chip and the fourth chip (118 ; 318; 418), and the second wafer (114; 314; 414) is adjacent to the first wafer and the third wafer (116; 316; 416).

如請求項13所述的積體電路產品(100；200；300；400；500；600)，其中，該第五晶片(122；322；422)、該第六晶片(124；324；424)、該第七晶片(126；326；426)、及該第八晶片(128；328；428)之任二者不鄰接，且該第九晶片(132；332；432)、該第十晶片(134；334；434)、該第十一晶片(136；336；436)、及該第十二晶片(138；338；438)之任二者不鄰接。 The integrated circuit product (100; 200; 300; 400; 500; 600) as claimed in claim 13, wherein the fifth chip (122; 322; 422), the sixth chip (124; 324; 424) , the seventh wafer (126; 326; 426), and the eighth wafer (128; 328; 428) are not adjacent, and the ninth wafer (132; 332; 432), the tenth wafer ( 134; 334; 434), the eleventh wafer (136; 336; 436), and the twelfth wafer (138; 338; 438) are not contiguous.

如請求項13所述的積體電路產品(100；200；300；400；500；600)，其中，該第五晶片(122；322；422)、該第六晶片(124；324；424)、該第七晶片(126；326；426)、及該第八晶片(128；328；428)分別與該積體電路產品(100；200；300；400；500；600)之該第一邊(102)、該第二邊(104)、該第三邊(106)、及該第四邊(108)鄰接。 The integrated circuit product (100; 200; 300; 400; 500; 600) as claimed in claim 13, wherein the fifth chip (122; 322; 422), the sixth chip (124; 324; 424) , the seventh chip (126; 326; 426), and the eighth chip (128; 328; 428) and the first side of the integrated circuit product (100; 200; 300; 400; 500; 600) (102), the second side (104), the third side (106), and the fourth side (108) are contiguous.

如請求項16所述的積體電路產品(100)，其中，該第五晶片(122)、該第六晶片(124)、該第七晶片(126)、及該第八晶片(128)更分別與該積體電路產品(100)之該第二邊(104)、該第三邊(106)、該第四邊(108)、及該第一邊(102)鄰接。 The integrated circuit product (100) as claimed in claim 16, wherein the fifth chip (122), the sixth chip (124), the seventh chip (126), and the eighth chip (128) are further respectively adjacent to the second side (104), the third side (106), the fourth side (108), and the first side (102) of the integrated circuit product (100).

如請求項13所述的積體電路產品(100；200；300；400；500；600)，其中，該第九晶片(132；332；432)、該第十晶片(134；334；434)、該第十一晶片(136；336；436)、及該第十二晶片(138；338；438)分別與該積體電路產品(100；200；300；400；500；600)之該第一邊(102)、該第二邊(104)、該第三邊(106)、及該第四邊(108)鄰接。 The integrated circuit product (100; 200; 300; 400; 500; 600) as claimed in claim 13, wherein the ninth chip (132; 332; 432), the tenth chip (134; 334; 434) , the eleventh chip (136; 336; 436), and the twelfth chip (138; 338; 438) and the integrated circuit product (100; 200; 300; 400; 500; 600) respectively One side (102), the second side (104), the third side (106), and the fourth side (108) are contiguous.

如請求項18所述的積體電路產品(200；300；400；600)，其中，該第九晶片(132；332；432)、該第十晶片(134；334；434)、該第十一晶片(136；336；436)、及該第十二晶片(138；338；438)更分別與該積體電路產品(200；300；400；600)之該第二邊(104)、該第三邊(106)、該第四邊(108)、及該第一邊(102)鄰接。 The integrated circuit product (200; 300; 400; 600) according to claim 18, wherein the ninth chip (132; 332; 432), the tenth chip (134; 334; 434), the tenth A chip (136; 336; 436), and the twelfth chip (138; 338; 438) are further connected to the second side (104), the The third side (106), the fourth side (108), and the first side (102) are contiguous.

如請求項13所述的積體電路產品(300；400；500；600)，其中，該第九晶片(332；432)、該第十晶片(334；434)、該第十一晶片(336；436)、及該第十二晶片(338；438)係記憶體晶片。 The integrated circuit product (300; 400; 500; 600) according to claim 13, wherein the ninth chip (332; 432), the tenth chip (334; 434), the eleventh chip (336 ; 436), and the twelfth chip (338; 438) is a memory chip.

如請求項20所述的積體電路產品(400；500；600)，更包含：一第十三晶片(442)；一第十四晶片(444)；一第十五晶片(446)；以及一第十六晶片(448)；其中，該第十三晶片(442)、該第十四晶片(444)、該第十五晶片(446)、及該第十六晶片(448)實質上位於該平面(PL)；且該第五晶片(422)、該第六晶片(424)、該第七晶片(426)、及該第八晶片(428)、該第九晶片(432)、該第十晶片(434)、該第十一晶片(436)、該第十二晶片(438)、該第十三晶片(442)、該第十四晶片(444)、該第十五晶片(446)、及該第十六晶片(448)具有相同的寬度(W1)。 The integrated circuit product (400; 500; 600) as described in claim 20, further comprising: a thirteenth chip (442); a fourteenth chip (444); a fifteenth chip (446); and A sixteenth wafer (448); wherein, the thirteenth wafer (442), the fourteenth wafer (444), the fifteenth wafer (446), and the sixteenth wafer (448) are substantially located at the plane (PL); and The fifth wafer (422), the sixth wafer (424), the seventh wafer (426), the eighth wafer (428), the ninth wafer (432), the tenth wafer (434), the The eleventh wafer (436), the twelfth wafer (438), the thirteenth wafer (442), the fourteenth wafer (444), the fifteenth wafer (446), and the sixteenth wafer (448) have the same width (W1).

如請求項21所述的積體電路產品(400；500)，其中，該第五晶片(422)位於該第九晶片(432)與該第十三晶片(442)之間，該第六晶片(424)位於該第十晶片(434)與該第十四晶片(444)之間，該第七晶片(426)位於該第十一晶片(436)與該第十五晶片(446)之間，以及該第八晶片(428)位於該第十二晶片(438)與該第十六晶片(448)之間。 The integrated circuit product (400; 500) according to claim 21, wherein the fifth chip (422) is located between the ninth chip (432) and the thirteenth chip (442), and the sixth chip (424) between the tenth wafer (434) and the fourteenth wafer (444), the seventh wafer (426) between the eleventh wafer (436) and the fifteenth wafer (446) , and the eighth wafer (428) is located between the twelfth wafer (438) and the sixteenth wafer (448).

如請求項22所述的積體電路產品(400)，其中，該第九晶片(432)、該第十晶片(434)、該第十一晶片(436)、及該第十二晶片(438)分別位於該積體電路產品(400)的四個角。 The integrated circuit product (400) as claimed in claim 22, wherein the ninth chip (432), the tenth chip (434), the eleventh chip (436), and the twelfth chip (438 ) are respectively located at the four corners of the integrated circuit product (400).

如請求項22所述的積體電路產品(500)，其中，該第十三晶片(442)、該第十四晶片(444)、該第十五晶片(446)、及該第十六晶片(448)分別位於該積體電路產品(500)的四個角。 The integrated circuit product (500) as claimed in claim 22, wherein the thirteenth chip (442), the fourteenth chip (444), the fifteenth chip (446), and the sixteenth chip (448) are respectively located at four corners of the integrated circuit product (500).

如請求項21所述的積體電路產品(600)，其中，該第十三晶片(442)位於該第五晶片(422)與該第九晶片(432)之間，該第十四晶片(444)位於該第六晶片(424)與該第十晶片(434)之間，該第十五晶片(446)位於該第七晶片(426)與該第十一晶片(436)之間，以及該第十六晶片(448)位於該第八晶片(428)與該第十二晶片(438)之間。 The integrated circuit product (600) as claimed in claim 21, wherein the thirteenth chip (442) is located between the fifth chip (422) and the ninth chip (432), and the fourteenth chip ( 444) between the sixth wafer (424) and the tenth wafer (434), the fifteenth wafer (446) between the seventh wafer (426) and the eleventh wafer (436), and The sixteenth wafer (448) is located between the eighth wafer (428) and the twelfth wafer (438).