TWI788903B - Package structure and manufacturing method thereof - Google Patents

Abstract

A package structure including a first chip, a second chip, an encapsulant, a dam structure, a light-transmitting sheet, a conductive connector, a circuit layer and a conductive terminal is provided. The first chip includes a first active surface. The first active surface has a sensing area. The second chip is arranged such that its second back surface faces the first chip. The encapsulant covers the second chip. The encapsulant has a first encapsulating surface and a second encapsulating surface. The dam structure is disposed on the first encapsulating surface and exposes the sensing area. The light-transmitting sheet is disposed on the dam structure. The conductive connector penetrates the encapsulant. The circuit layer is disposed on the second encapsulating surface. The first chip is electrically connected to the second chip through the conductive connector and the circuit layer. The conductive terminal is disposed on the circuit layer.

Description

封裝結構及其製造方法Package structure and manufacturing method thereof

本發明是有關於一種封裝結構及其製造方法，且特別是有關於一種整合多個晶片的封裝結構及其製造方法。 The present invention relates to a packaging structure and its manufacturing method, and in particular to a packaging structure integrating multiple chips and its manufacturing method.

為了使得電子產品能達到輕薄短小的設計，半導體封裝技術亦跟著日益進展，以發展出符合小體積、重量輕、高密度以及在市場上具有高競爭力等要求的產品。因此，如何整合多個晶片，以提升封裝結構的效能，實已成重要的課題之一。 In order to enable electronic products to achieve light, thin, and small designs, semiconductor packaging technology is also advancing day by day to develop products that meet the requirements of small size, light weight, high density, and high competitiveness in the market. Therefore, how to integrate multiple chips to improve the performance of the packaging structure has become one of the important issues.

本發明提供一種封裝結構及其製造方法，其可以具有較佳的效能。 The invention provides a packaging structure and a manufacturing method thereof, which can have better performance.

本發明的封裝結構包括第一晶片、第二晶片、模封體、阻擋結構、透光片、導電連接件、第一線路層以及導電端子。第一晶片包括第一主動面以及相對於第一主動面的第一背面。第一主動面具有感測區。第二晶片包括第二主動面以及相對於第二主 動面的第二背面。第二晶片以其第二背面面向第一晶片的第一背面的方式配置。模封體覆蓋第二晶片。模封體具有第一模封面及相對於第一模封面的第二模封面。阻擋結構位於第一模封面上且暴露出第一晶片的感測區。透光片位於阻擋結構上。導電連接件貫穿模封體。第一線路層位於第二模封面上。第一晶片藉由導電連接件及第一線路層電性連接第二晶片。導電端子配置於第一線路層上。 The packaging structure of the present invention includes a first chip, a second chip, a molding body, a blocking structure, a light-transmitting sheet, a conductive connector, a first circuit layer and a conductive terminal. The first wafer includes a first active surface and a first back surface opposite to the first active surface. The first active surface has a sensing area. The second wafer includes a second active surface and relative to the second main The second back of the moving surface. The second wafer is arranged such that its second back face faces the first back face of the first wafer. The molding body covers the second chip. The molding body has a first mold surface and a second mold surface opposite to the first mold surface. The blocking structure is located on the first mold surface and exposes the sensing area of the first chip. The light-transmitting sheet is located on the blocking structure. The conductive connector runs through the molded body. The first circuit layer is located on the second mold cover. The first chip is electrically connected to the second chip through the conductive connector and the first circuit layer. The conductive terminal is configured on the first circuit layer.

本發明的封裝結構的製造方法包括以下步驟：提供晶圓，其包括主動面，其中主動面具有感測區；形成阻擋結構於晶圓的主動面上；配置透光片於阻擋結構上；對晶圓形成穿矽導通孔，且於晶圓相對於主動面的背面上形成電性連接穿矽導通孔的線路層；形成覆蓋穿矽導通孔的介電層；於介電層上形成導電連接件；於介電層上配置第二晶片；於介電層上形成覆蓋第二晶片的模封體；於模封體上形成第一線路層，且晶圓藉由導電連接件及第一線路層電性連接第二晶片；以及形成導電端子於第一線路層上。 The manufacturing method of the packaging structure of the present invention includes the following steps: providing a wafer, which includes an active surface, wherein the active surface has a sensing area; forming a blocking structure on the active surface of the wafer; disposing a light-transmitting sheet on the blocking structure; Through-silicon vias are formed on the wafer, and a circuit layer electrically connected to the through-silicon vias is formed on the backside of the wafer opposite to the active surface; a dielectric layer covering the through-silicon vias is formed; a conductive connection is formed on the dielectric layer A second chip is arranged on the dielectric layer; a molding body covering the second chip is formed on the dielectric layer; a first circuit layer is formed on the molding body, and the wafer is connected by a conductive connector and the first circuit The layer is electrically connected to the second chip; and the conductive terminal is formed on the first circuit layer.

本發明的封裝結構的製造方法包括以下步驟：於載板上形成導電連接件；於載板上配置第一晶片，其包括第一主動面以及相對於第一主動面的第一背面，其中第一主動面具有感測區，且第一晶片以其第一主動面面向載板的方式配置；於第一晶片上配置第二晶片，其包括第二主動面以及相對於第二主動面的第二背面，且第二晶片以其第二背面面向第一晶片的第一背面的方式 配置；於載板上形成模封體，其覆蓋第一晶片及第二晶片；於模封體上形成第二線路層；於形成模封體之後，使載板與第一晶片分離，以暴露出第一主動面；於模封體上形成阻擋結構，且阻擋結構暴露出感測區；以及配置透光片於阻擋結構上。 The manufacturing method of the packaging structure of the present invention includes the following steps: forming a conductive connection on the carrier; disposing a first chip on the carrier, which includes a first active surface and a first back surface opposite to the first active surface, wherein the second An active surface has a sensing area, and the first chip is configured in such a way that its first active surface faces the carrier; a second chip is arranged on the first chip, which includes a second active surface and a first active surface relative to the second active surface. Two back faces, and the second wafer faces the first back face of the first wafer with its second back face Configuration; forming a molding body on the carrier board, which covers the first chip and the second chip; forming a second circuit layer on the molding body; after forming the molding body, separating the carrier board from the first chip to expose Exposing the first active surface; forming a blocking structure on the molding body, and the blocking structure exposes the sensing area; and disposing a light-transmitting sheet on the blocking structure.

基於上述，本發明的製造方法及對應的結構可以將適於感測的第一晶片及適於數據處理的第二晶片整合於一封裝結構中。如此一來，可以提升封裝結構的感測處理效能。 Based on the above, the manufacturing method and corresponding structure of the present invention can integrate the first chip suitable for sensing and the second chip suitable for data processing into a package structure. In this way, the sensing processing performance of the package structure can be improved.

100、200:封裝結構 100, 200: package structure

119、119’:晶圓 119, 119': Wafer

110、120、210:晶片 110, 120, 210: chip

110a、110b、110c、120a、120b、120c、210a、210b:面 110a, 110b, 110c, 120a, 120b, 120c, 210a, 210b: surface

110d、210d:感測區 110d, 210d: sensing area

111、111’、121:基材 111, 111', 121: base material

112、122、212:晶片連接墊 112, 122, 212: chip connection pads

123:晶片絕緣層 123: Wafer insulating layer

124:晶片連接件 124: chip connector

124a:表面 124a: surface

115:穿矽導通孔 115:Through silicon via

115e:絕緣層 115e: insulating layer

115f、162f:導電層 115f, 162f: conductive layer

116:氣隙 116: air gap

130:模封體 130: mold sealing body

130a、130b:模封面 130a, 130b: mold cover

136:導電連接件 136: Conductive connector

145:阻擋結構 145: Blocking structure

146:透光片 146: Translucent film

150:介電層 150: dielectric layer

170:重佈線路結構 170:Redistribute the circuit structure

171:線路層或導電層 171: circuit layer or conductive layer

175:絕緣層 175: insulation layer

162、262:線路層 162, 262: line layer

181、281:黏著材 181, 281: Adhesive materials

186:導電端子 186: Conductive terminal

R1、R2:封閉空間 R1, R2: closed space

91、93:載板 91, 93: carrier board

92、94:離型層 92, 94: release layer

圖1A至圖1H是依照本發明的第一實施例的一種封裝結構的製造方法的部分剖視示意圖。 1A to 1H are partial cross-sectional schematic views of a manufacturing method of a packaging structure according to a first embodiment of the present invention.

圖2A至圖2H是依照本發明的第二實施例的一種封裝結構的製造方法的部分剖視示意圖。 2A to 2H are partial cross-sectional schematic views of a manufacturing method of a packaging structure according to a second embodiment of the present invention.

除非另有明確說明，本文所使用之方向用語(例如，上、下、右、左、前、後、頂部、底部)僅作為參看所繪圖式使用且不意欲暗示絕對定向。另外，為求清楚表示，於圖式中可能省略繪示了部分的膜層或構件。 Unless expressly stated otherwise, directional terms (eg, up, down, right, left, front, back, top, bottom) used herein are used by way of reference only and are not intended to imply absolute orientation. In addition, for the sake of clarity, some film layers or components may be omitted in the drawings.

除非另有明確說明，否則本文所述任何方法絕不意欲被解釋為要求按特定順序執行其步驟。 Any method described herein is in no way intended to be construed as requiring performance of its steps in a particular order, unless expressly stated otherwise.

參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。圖式中的層或區域的厚度、尺寸或大小會為了清楚起見而放大。相同或相似之參考號碼表示相同或相似之元件，以下段落將不再一一贅述。 The present invention will be described more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various forms and should not be limited to the embodiments described herein. The thickness, size or magnitude of layers or regions in the drawings may be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

圖1A至圖1H是依照本發明的第一實施例的一種封裝結構的製造方法的部分剖視示意圖。 1A to 1H are partial cross-sectional schematic views of a manufacturing method of a packaging structure according to a first embodiment of the present invention.

請參照圖1A，提供晶圓119’。晶圓119’可以被置於載板(未繪示)上，但本發明不限於此。 Referring to FIG. 1A, a wafer 119' is provided. The wafer 119' can be placed on a carrier (not shown), but the invention is not limited thereto.

晶圓119’可以包括矽基材111’以及多個晶片連接墊(die pad)112。晶片連接墊112例如是鋁墊、銅墊或其他適宜的金屬墊，但本發明不限於此。 The wafer 119' may include a silicon substrate 111' and a plurality of die pads 112. The die connection pads 112 are, for example, aluminum pads, copper pads or other suitable metal pads, but the invention is not limited thereto.

基材111’的一側具有元件區(未繪示)，而元件區所位於的表面可以被稱為主動面110a。晶片連接墊112可以位於主動面110a上。在一般晶片設計中，元件區內的元件(如：晶圓119’中元件區內的元件)可以藉由對應的後段金屬內連線(Back End of Line Interconnect；BEOL Interconnect)電性連接於對應的晶片連接墊(如：晶圓119’中的部分晶片連接墊112)。主動面110a具有感測區110d。感測區110d中可以具有對應的感測元件。感測元件例如是互補式金屬氧化物半導體影像感測器(CMOS Image Sensor；CIS)，但本發明不限於此。 One side of the substrate 111' has a device area (not shown), and the surface on which the device area is located can be called the active surface 110a. Die attach pads 112 may be located on the active surface 110a. In general chip design, the components in the device area (such as: the components in the device area of the wafer 119') can be electrically connected to the corresponding back-end metal interconnects (Back End of Line Interconnect; BEOL Interconnect). die connection pads (for example: part of the die connection pads 112 in the wafer 119'). The active surface 110a has a sensing area 110d. There may be corresponding sensing elements in the sensing region 110d. The sensing element is, for example, a complementary metal oxide semiconductor image sensor (CMOS Image Sensor; CIS), but the invention is not limited thereto.

請繼續參照圖1A，形成絕緣的阻擋結構145於晶圓119’ 的主動面110a上。阻擋結構145可以藉由塗佈、印刷、曝光顯影或其他適宜的方式形成，於本發明並不加以限制。 Please continue to refer to FIG. 1A, an insulating barrier structure 145 is formed on the wafer 119' on the active surface 110a of the The barrier structure 145 can be formed by coating, printing, exposure and development or other suitable methods, which are not limited in the present invention.

請參照圖1A至圖1B，配置透光片146於阻擋結構145上。 Referring to FIG. 1A to FIG. 1B , the transparent sheet 146 is disposed on the blocking structure 145 .

在本實施例中，配置透光片146於阻擋結構145上的步驟可以於第一環境氣壓下進行。舉例而言，配置透光片146於阻擋結構145上的步驟可以於腔體(未繪示)內進行，而腔體內具有對應的第一環境氣壓。 In this embodiment, the step of arranging the transparent sheet 146 on the blocking structure 145 can be performed under the first ambient pressure. For example, the step of arranging the transparent sheet 146 on the blocking structure 145 can be performed in a cavity (not shown), and the cavity has a corresponding first ambient air pressure.

在一實施例中，第一環境氣壓小於一大氣壓。如此一來，在後續的步驟或結構中，可以藉由氣壓差而使透光片146與阻擋結構145之間的接觸更為緊密。 In one embodiment, the first ambient pressure is less than atmospheric pressure. In this way, in subsequent steps or structures, the contact between the transparent sheet 146 and the blocking structure 145 can be made closer by the air pressure difference.

請參照圖1B至圖1C，對晶圓119(標示於圖1C)形成穿矽導通孔(through silicon via；TSV)115，且於晶圓119相對於主動面110a的背面110b上形成電性連接穿矽導通孔115的線路層162。 Referring to FIG. 1B to FIG. 1C , a through silicon via (through silicon via; TSV) 115 is formed on the wafer 119 (marked in FIG. 1C ), and an electrical connection is formed on the back surface 110 b of the wafer 119 opposite to the active surface 110 a. The wiring layer 162 of the TSV 115 .

在本實施例中，可以對晶圓119’的矽基材111’(標示於圖1B)進行薄化製程，然後，從薄化後的矽基材111(標示於圖1C)的背面110b上形成穿矽導通孔115及對應的線路層162(可以被稱為：第二線路層)。 In this embodiment, a thinning process may be performed on the silicon substrate 111' (indicated in FIG. 1B ) of the wafer 119 ′, and then the silicon substrate 111 (indicated in FIG. 1C ) is thinned from the backside 110b TSVs 115 and the corresponding circuit layer 162 (which may be referred to as a second circuit layer) are formed.

舉例而言，可以先對矽基材111’(標示於圖1B)進行薄化製程。然後，可以藉由蝕刻或其他適宜的方式，從薄化後的矽基材111(標示於圖1C)的背面110b形成暴露出晶片連接墊112 的開口。然後，可以藉由沉積、蝕刻及/或其他適宜的方式，以形成對應的絕緣層115e。絕緣層115e可以覆蓋基材111的背面110b以及開口的側壁，且絕緣層115e可以暴露出晶片連接墊112。然後，可以藉由沉積、鍍覆、蝕刻及/或其他適宜的方式，以形成對應的導電層115f、162f。導電層115f、162f例如包括對應的種子層及對應的鍍覆層，但本發明不限於此。位於開口內的部分導電層115f及對應的絕緣層115e可以被稱為穿矽導通孔115。位於基材111的背面110b上的部分導電層162f可以被稱為線路層162。也就是說，穿矽導通孔115中可以導電的一部分及線路層162中可以導電的一部分可以為相同的膜層。另外，線路層162中的線路佈局(layout design)可以依據設計上的需求而加以調整，於本發明並不加以限定。 For example, the silicon substrate 111' (shown in FIG. 1B ) can be thinned first. Then, the exposed die connection pads 112 can be formed from the backside 110b of the thinned silicon substrate 111 (shown in FIG. 1C ) by etching or other suitable methods. opening. Then, the corresponding insulating layer 115e may be formed by deposition, etching and/or other suitable methods. The insulating layer 115e can cover the back surface 110b of the substrate 111 and the sidewalls of the opening, and the insulating layer 115e can expose the die connection pads 112 . Then, the corresponding conductive layers 115f, 162f may be formed by deposition, plating, etching and/or other suitable methods. The conductive layers 115f and 162f include, for example, a corresponding seed layer and a corresponding plating layer, but the invention is not limited thereto. The portion of the conductive layer 115 f and the corresponding insulating layer 115 e located in the opening may be referred to as a TSV 115 . Part of the conductive layer 162f on the back surface 110b of the substrate 111 may be referred to as a wiring layer 162 . That is to say, the conductive part of the TSV 115 and the conductive part of the circuit layer 162 can be the same film layer. In addition, the circuit layout (layout design) in the circuit layer 162 can be adjusted according to design requirements, which is not limited in the present invention.

在本實施例中，絕緣層115e及導電層115f未完全地填滿暴露出晶片連接墊112的開口。 In this embodiment, the insulating layer 115e and the conductive layer 115f do not completely fill the opening exposing the die connection pad 112 .

請參照圖1C至圖1D，形成介電層150。介電層150可以覆蓋穿矽導通孔115且暴露出部分的線路層162。在本實施例中，可以藉由塗佈的方式於基材111的背面110b上形成對應的有機介電材(如：聚醯亞胺(Polyimide；PI)，但不限)。然後，可以藉由適當的固化方式(如：照光、加熱及/或靜置一段時間)，以使前述的有機介電材形成圖案化的介電層150。 Referring to FIG. 1C to FIG. 1D , a dielectric layer 150 is formed. The dielectric layer 150 may cover the TSV 115 and expose a portion of the wiring layer 162 . In this embodiment, a corresponding organic dielectric material (such as polyimide (PI), but not limited) can be formed on the back surface 110 b of the substrate 111 by coating. Then, the aforesaid organic dielectric material can be formed into a patterned dielectric layer 150 by a suitable curing method (such as light irradiation, heating and/or standing for a period of time).

在本實施例中，圖案化的介電層150可以部分地填入且未完全地填滿基材111的開口。也就是說，至少一氣隙(gas gap) 116嵌於穿矽導通孔115內。舉例而言，形成覆蓋穿矽導通孔115的介電層150的步驟(如：於基材的背面上形成有機介電材的步驟)可以於第二環境氣壓下進行，且第二環境氣壓例如為室壓(如：約一大氣壓)。如此一來，可以較為容易且/或快速地形成介電層150。也就是說，藉由上述的方式，氣隙116的壓力也大致上約為第二環境氣壓。 In this embodiment, the patterned dielectric layer 150 may partially but not completely fill the opening of the substrate 111 . That is, at least one gas gap 116 is embedded in the TSV 115 . For example, the step of forming the dielectric layer 150 covering the TSV 115 (such as the step of forming an organic dielectric material on the backside of the substrate) can be performed under a second ambient pressure, and the second ambient pressure is, for example, Is the room pressure (eg: about one atmosphere). In this way, the dielectric layer 150 can be formed relatively easily and/or quickly. That is to say, by the above method, the pressure of the air gap 116 is also approximately the second ambient pressure.

在一實施例中，用於形成介電層150的有機介電材可能被溶於適宜的溶劑中；或是，於適宜的溶劑中進行適當的反應(如：縮合聚合)而成。前述的溶劑例如為二甲基甲醯胺(Dimethylformamide)、二甲基亞碸(Dimethyl sulfoxide；DMSO)或其他適宜的有機溶劑。因此，在形成介電層150的過程中(如：進行前述的固化步驟時)，部分的有機溶劑分子可能會留存於氣隙116內。 In one embodiment, the organic dielectric material used to form the dielectric layer 150 may be dissolved in a suitable solvent; or, it may be formed by performing a suitable reaction (such as condensation polymerization) in a suitable solvent. The aforementioned solvent is, for example, dimethylformamide (Dimethylformamide), dimethylsulfoxide (DMSO) or other suitable organic solvents. Therefore, during the process of forming the dielectric layer 150 (eg, during the aforementioned curing step), some organic solvent molecules may remain in the air gap 116 .

在一實施例中，介電層150可以被稱為鈍化層(passivation layer)，但本發明不限於此。 In one embodiment, the dielectric layer 150 may be called a passivation layer, but the invention is not limited thereto.

請繼續參照圖1D，於介電層150上形成導電連接件136。導電連接件136可以電性連接於線路層162中對應的線路。 Please continue to refer to FIG. 1D , a conductive connection 136 is formed on the dielectric layer 150 . The conductive connector 136 can be electrically connected to the corresponding circuit in the circuit layer 162 .

在一實施例中，導電連接件136可以藉由適宜的方式(如：曝光顯影及鍍覆，但不限)形成，但本發明不限於此。在一實施例中，導電連接件136可以是預先成形(pre-formed)的導電件。 In one embodiment, the conductive connecting member 136 can be formed by a suitable method (such as exposure, development and plating, but not limited), but the invention is not limited thereto. In one embodiment, the conductive connector 136 may be a pre-formed conductive member.

請參照圖1E，於介電層150上配置第二晶片120。在本 實施例中，第二晶片120可以包括矽基材121、多個晶片連接墊122、晶片絕緣層123以及多個晶片連接件124。矽基材121的一側具有元件區(未繪示)，而元件區所位於的表面可以被稱為第二主動面120a。相對於第二主動面120a的表面可以被稱為第二背面120b。第二晶片120以其第二背面120b面向晶圓119的方式配置。晶片連接墊122可以位於第二主動面120a上。晶片連接件124例如是金屬凸塊(metal bumps)，但本發明不限於此。晶片連接件124位於對應的晶片連接墊122上且與其電性連接。晶片絕緣層123可以覆蓋晶片連接墊122，且晶片絕緣層123暴露出晶片連接墊122的一部分。在晶片設計中，元件區內的元件(如：第二晶片120的元件區內的元件)可以藉由對應的後段金屬內連線電性連接於對應的晶片連接墊(如：第二晶片120的部分晶片連接墊122)。 Referring to FIG. 1E , the second chip 120 is disposed on the dielectric layer 150 . in this In an embodiment, the second chip 120 may include a silicon substrate 121 , a plurality of die connection pads 122 , a die insulation layer 123 and a plurality of die connection members 124 . One side of the silicon substrate 121 has a device region (not shown), and the surface on which the device region is located may be referred to as the second active surface 120a. The surface opposite to the second active surface 120a may be referred to as a second back surface 120b. The second wafer 120 is arranged such that its second back surface 120 b faces the wafer 119 . The die attach pad 122 may be located on the second active surface 120a. The chip connectors 124 are, for example, metal bumps, but the invention is not limited thereto. The chip connection elements 124 are located on the corresponding chip connection pads 122 and are electrically connected thereto. The die insulation layer 123 may cover the die connection pads 122 , and the die insulation layer 123 exposes a part of the die connection pads 122 . In the chip design, the components in the device region (such as: the components in the device region of the second chip 120) can be electrically connected to the corresponding chip connection pads (such as: the second chip 120 part of the die attach pad 122).

在一實施例中，第二晶片120可以包括圖像訊號處理器(image signal processor；ISP)，但本發明不限於此。 In one embodiment, the second chip 120 may include an image signal processor (ISP), but the invention is not limited thereto.

值得注意的是，在所繪示的實施例中，是先於介電層150上形成導電連接件136，然後，於介電層150上配置第二晶片120，但本發明不限於此。在一未繪示的實施例中，可以先於介電層150上配置第二晶片120，然後，於介電層150上形成導電連接件136。 It should be noted that, in the illustrated embodiment, the conductive connectors 136 are formed on the dielectric layer 150 first, and then the second chip 120 is disposed on the dielectric layer 150, but the invention is not limited thereto. In an unillustrated embodiment, the second chip 120 may be disposed on the dielectric layer 150 first, and then the conductive connection member 136 is formed on the dielectric layer 150 .

在一實施例中，第二晶片120的第二背面120b上可以具有黏著材181。黏著材181可以包括晶粒黏著膜(die attached film；DAF)，但本發明不限於此。 In one embodiment, the second wafer 120 may have an adhesive material 181 on the second back surface 120b. The adhesive material 181 may include a die attached film (DAF), but the invention is not limited thereto.

請參照圖1E至圖1F，於介電層150上形成模封體130。 模封體130可以覆蓋第二晶片120。 Referring to FIG. 1E to FIG. 1F , the molding body 130 is formed on the dielectric layer 150 . The molding body 130 may cover the second wafer 120 .

在一實施例中，可以於介電層150上形成模封材料(molding material；未繪示)。並且，在將模封材料固化之後，可以進行平整化製程，以形成模封體130。平整化製程例如可以是研磨(grinding)、拋光(polishing)或其他適宜的平整化步驟。模封體130可以暴露出第二晶片120的晶片連接件124的上表面124a。也就是說，模封體130的模封面130b可以與第二晶片120的晶片連接件124的上表面124a共面(coplanar)。 In one embodiment, a molding material (not shown) may be formed on the dielectric layer 150 . Moreover, after the molding material is solidified, a planarization process may be performed to form the molding body 130 . The planarization process can be, for example, grinding (grinding), polishing (polishing) or other suitable planarization steps. The molding body 130 may expose the upper surface 124 a of the die attach member 124 of the second die 120 . That is to say, the mold surface 130 b of the molding body 130 may be coplanar with the upper surface 124 a of the die attach member 124 of the second die 120 .

在一實施例中，由於第二晶片120的第二主動面120a上具有晶片連接件124，因此，在進行前述平整化步驟時可以降低對第二晶片120的第二主動面120a造成損傷的可能。 In one embodiment, since the second active surface 120a of the second wafer 120 has the wafer connector 124, the possibility of damage to the second active surface 120a of the second wafer 120 can be reduced during the aforementioned planarization step. .

請參照圖1F至圖1G，於模封體130上形成重佈線路結構170。重佈線路結構170包括對應的導電層171(可以被稱為第一線路層)及對應的絕緣層175。貫穿部分絕緣層175的部分導電層171可以被稱為導電孔(conductive via)。導電層171所構成的線路的線路佈局(layout design)可以依據設計上的需求而加以調整，於本發明並不加以限定。晶圓119中的元件與第二晶片120之間可以藉由重佈線路結構170中對應的線路、對應的導電連接件136及第一線路層171中對應的線路而電性連接。 Referring to FIG. 1F to FIG. 1G , a redistribution circuit structure 170 is formed on the molding body 130 . The redistribution wiring structure 170 includes a corresponding conductive layer 171 (which may be called a first wiring layer) and a corresponding insulating layer 175 . Portions of the conductive layer 171 penetrating through portions of the insulating layer 175 may be referred to as conductive vias. The circuit layout (layout design) of the circuit formed by the conductive layer 171 can be adjusted according to the design requirement, which is not limited in the present invention. The components in the wafer 119 and the second chip 120 can be electrically connected by corresponding circuits in the redistribution circuit structure 170 , corresponding conductive connectors 136 and corresponding circuits in the first circuit layer 171 .

請參照圖1G至圖1H，形成導電端子186於第一線路層171上且與第一線路層171中對應的線路電性連接。導電端子186 可以包括焊球，但本發明不限於此。 Referring to FIG. 1G to FIG. 1H , the conductive terminals 186 are formed on the first circuit layer 171 and are electrically connected to corresponding circuits in the first circuit layer 171 . Conductive terminal 186 Solder balls may be included, but the invention is not limited thereto.

請繼續參照圖1G至圖1H，可以進行單一化(singulation)製程，以獲得多個第一晶片110。切單製程例如包括以旋轉刀片或雷射光束對晶圓119(標示於圖1G)進行切割。在一實施例中，前述的單一化製程更可以對重佈線路結構170、模封體130、阻擋結構145及/或透光片146進行。 Please continue to refer to FIG. 1G to FIG. 1H , a singulation process may be performed to obtain a plurality of first wafers 110 . The singulation process includes, for example, dicing the wafer 119 (shown in FIG. 1G ) with a rotary blade or a laser beam. In one embodiment, the aforementioned singulation process can be further performed on the redistribution wiring structure 170 , the molding body 130 , the barrier structure 145 and/or the light-transmitting sheet 146 .

值得注意的是，在進行單一化製程之後，相似的元件符號將用於單一化後的元件。舉例而言，晶圓119中對應的結構(如圖1G中的感測區110d、矽導通孔115、氣隙116或其他類似物)於單體化後可以為多個第一晶片110中對應的結構(如圖1H中的感測區110d、矽導通孔115、氣隙116或其他類似物)，第二晶片120(如圖1G所示)於單體化後可以為多個第二晶片120(如圖1H所示)，模封體130(如圖1G所示)於單體化後可以為多個模封體130(如圖1H所示)，阻擋結構145(如圖1G所示)於單體化後可以為多個阻擋結構145(如圖1H所示)，透光片146(如圖1G所示)於單體化後可以為多個透光片146(如圖1H所示)，諸如此類。其他單體化後的元件將依循上述相同的元件符號規則，於此不加以贅述。另外，為求清楚表示，於圖1H中並未一一地標示所有的元件。 It is worth noting that after the singulation process, similar device symbols will be used for the singulated components. For example, the corresponding structures in the wafer 119 (such as the sensing region 110d, silicon vias 115, air gaps 116 or the like in FIG. 1G ) can be corresponding in multiple first wafers 110 after singulation. structure (sensing region 110d, silicon via 115, air gap 116 or other similar in FIG. 1H ), the second chip 120 (as shown in FIG. 1G ) can be a plurality of second chips after singulation 120 (as shown in Figure 1H), the molded body 130 (as shown in Figure 1G) can be a plurality of molded bodies 130 (as shown in Figure 1H) after singulation, and the blocking structure 145 (as shown in Figure 1G ) can be a plurality of blocking structures 145 (as shown in FIG. 1H ) after being singulated, and the light-transmitting sheet 146 (as shown in FIG. 1G ) can be a plurality of light-transmitting sheets 146 (as shown in FIG. 1H ) after being singulated. shown), and so on. Other singulated components will follow the same component notation rules as above, and will not be repeated here. In addition, for the sake of clarity, not all components are marked one by one in FIG. 1H .

值得注意的是，在所繪示的實施例中，是先形成導電端子186，然後，進行前述的單一化製程，但本發明不限於此。在一未繪示的實施例中，可以先進行前述的單一化製程，然後，形成 導電端子186。 It should be noted that in the illustrated embodiment, the conductive terminals 186 are formed first, and then the aforementioned singulation process is performed, but the present invention is not limited thereto. In an unillustrated embodiment, the aforementioned singulation process can be performed first, and then, the formation Conductive terminal 186 .

請參照圖1H，經過上述製程後即可大致上完成本實施例之封裝結構100的製作。封裝結構100包括第一晶片110、第二晶片120、模封體130、阻擋結構145、透光片146、導電連接件136、第一線路層171以及導電端子186。第一晶片110包括第一主動面110a、第一背面110b以及第一側面110c。第一背面110b相對於第一主動面110a。第一側面110c連接第一主動面110a及第一背面110b。第一主動面110a具有感測區110d。第二晶片120包括第二主動面120a、第二背面120b以及第二側面120c。第二背面120b相對於第二主動面120a。第二側面120c連接第二主動面120a及第二背面120b。第二晶片120以其第二背面120b面向第一晶片110的第一背面110b的方式配置。模封體130覆蓋第二晶片120的第二側面120c及/或部分的第二主動面120a。模封體130具有第一模封面130a及相對於第一模封面130a的第二模封面130b。阻擋結構145位於第一模封面130a上，或是，更位於第一晶片110的第一主動面110a上。阻擋結構145暴露出第一晶片110的感測區110d。透光片146位於阻擋結構145上。導電連接件136貫穿模封體130。第一線路層171位於第二模封面130b上。第一晶片110藉由導電連接件136及第一線路層171電性連接第二晶片120。導電端子186，配置於第一線路層171上。 Please refer to FIG. 1H , the fabrication of the packaging structure 100 of this embodiment can be substantially completed after the above-mentioned manufacturing process. The packaging structure 100 includes a first chip 110 , a second chip 120 , a molding body 130 , a barrier structure 145 , a light-transmitting sheet 146 , a conductive connector 136 , a first circuit layer 171 and a conductive terminal 186 . The first wafer 110 includes a first active surface 110a, a first back surface 110b, and a first side surface 110c. The first back surface 110b is opposite to the first active surface 110a. The first side surface 110c connects the first active surface 110a and the first back surface 110b. The first active surface 110a has a sensing region 110d. The second wafer 120 includes a second active surface 120a, a second back surface 120b, and a second side surface 120c. The second back surface 120b is opposite to the second active surface 120a. The second side surface 120c is connected to the second active surface 120a and the second back surface 120b. The second wafer 120 is arranged such that the second back surface 120b thereof faces the first back surface 110b of the first wafer 110 . The molding body 130 covers the second side surface 120c and/or part of the second active surface 120a of the second chip 120 . The molding body 130 has a first mold surface 130a and a second mold surface 130b opposite to the first mold surface 130a. The blocking structure 145 is located on the first mold surface 130 a , or is further located on the first active surface 110 a of the first chip 110 . The barrier structure 145 exposes the sensing region 110d of the first wafer 110 . The transparent sheet 146 is located on the blocking structure 145 . The conductive connector 136 penetrates through the molding body 130 . The first circuit layer 171 is located on the second mold surface 130b. The first chip 110 is electrically connected to the second chip 120 through the conductive connector 136 and the first circuit layer 171 . The conductive terminal 186 is disposed on the first circuit layer 171 .

在本實施例中，第二晶片120的第二主動面120a上更具有晶片連接件124。晶片連接件124的表面124a與第二模封面130b 共面。 In this embodiment, the second active surface 120 a of the second chip 120 further has a chip connection part 124 . The surface 124a of the die attach member 124 and the second mold surface 130b Coplanar.

在本實施例中，封裝結構100更包括第二線路層162。第二線路層162位於第一模封面130a上。第一晶片110藉由第二線路層162、導電連接件136及第一線路層171電性連接第二晶片120。 In this embodiment, the packaging structure 100 further includes a second circuit layer 162 . The second circuit layer 162 is located on the first mold surface 130a. The first chip 110 is electrically connected to the second chip 120 through the second circuit layer 162 , the conductive connector 136 and the first circuit layer 171 .

在本實施例中，第一晶片110更包括穿矽導通孔115，且第一晶片110的穿矽導通孔115電性連接於第二線路層162。 In this embodiment, the first chip 110 further includes a TSV 115 , and the TSV 115 of the first chip 110 is electrically connected to the second circuit layer 162 .

在本實施例中，第二線路層162更位於第一晶片110及第二晶片120之間。 In this embodiment, the second circuit layer 162 is further located between the first chip 110 and the second chip 120 .

在本實施例中，封裝結構100更包括介電層150。介電層150位於第二線路層162上且覆蓋穿矽導通孔115。至少一氣隙116嵌於穿矽導通孔115內。在一實施例中，位於不同的穿矽導通孔115內的氣隙116可以具有不同的大小及/或形貌。 In this embodiment, the package structure 100 further includes a dielectric layer 150 . The dielectric layer 150 is located on the second circuit layer 162 and covers the TSV 115 . At least one air gap 116 is embedded in the TSV 115 . In one embodiment, the air gaps 116 in different TSVs 115 may have different sizes and/or shapes.

在本實施例中，第一晶片110、阻擋結構145及透光片146構成封閉空間R1。在一實施例中，氣隙116內的氣壓大於或等於一封閉空間R1內的氣壓。在一實施例中，封閉空間R1內的氣壓小於一大氣壓。 In this embodiment, the first chip 110 , the blocking structure 145 and the transparent sheet 146 form a closed space R1 . In one embodiment, the air pressure in the air gap 116 is greater than or equal to the air pressure in a closed space R1. In one embodiment, the air pressure in the enclosed space R1 is less than one atmosphere.

圖2A至圖2H是依照本發明的第二實施例的一種封裝結構的製造方法的部分剖視示意圖。 2A to 2H are partial cross-sectional schematic views of a manufacturing method of a packaging structure according to a second embodiment of the present invention.

請參照圖2A，提供第一載板91。本發明對於第一載板91並無特別的限制，只要第一載板91可以適於承載形成於其上膜層或配置於其上的元件即可。 Referring to FIG. 2A , a first carrier 91 is provided. The present invention has no special limitation on the first carrier 91 , as long as the first carrier 91 is suitable for carrying the film layer formed thereon or the components arranged thereon.

在本實施例中，第一載板91上可以具有離型層92，但本發明不限於此。離型層92例如是光熱轉換(light to heat conversion；LTHC)黏著層或其他類似的膜層，但本發明不限於此。 In this embodiment, the release layer 92 may be provided on the first carrier 91 , but the present invention is not limited thereto. The release layer 92 is, for example, a light to heat conversion (LTHC) adhesive layer or other similar film layers, but the invention is not limited thereto.

請繼續參照圖2A，於第一載板91上形成導電連接件136。 Please continue to refer to FIG. 2A , a conductive connecting member 136 is formed on the first carrier 91 .

請繼續參照圖2A，於第一載板91上配置第一晶片210。第一晶片210包括第一主動面210a以及相對於第一主動面210a的第一背面210b。第一主動面210a具有感測區210d。第一晶片210可以包括矽基材211以及多個晶片連接墊212。晶片連接墊212可以位於主動面210a上。第一晶片210以其第一主動面210a面向第一載板91的方式配置。 Please continue to refer to FIG. 2A , the first chip 210 is disposed on the first carrier 91 . The first wafer 210 includes a first active surface 210a and a first back surface 210b opposite to the first active surface 210a. The first active surface 210a has a sensing area 210d. The first chip 210 may include a silicon substrate 211 and a plurality of chip connection pads 212 . Die attach pads 212 may be located on the active surface 210a. The first wafer 210 is configured such that its first active surface 210 a faces the first carrier 91 .

值得注意的是，本發明並未限定形成導電連接件136的步驟及配置第一晶片210的步驟的先後順序。 It should be noted that the present invention does not limit the sequence of the step of forming the conductive connection member 136 and the step of disposing the first chip 210 .

請參照圖2A至圖2B，於第一晶片210上配置第二晶片120。第二晶片120以其第二背面120b面向第一晶片210的第一背面210b的方式配置。 Referring to FIG. 2A to FIG. 2B , the second chip 120 is disposed on the first chip 210 . The second wafer 120 is arranged such that the second back surface 120b thereof faces the first back surface 210b of the first wafer 210 .

在一實施例中，第一晶片210的第一背面210b與第二晶片120的第二背面120b之間可以具有黏著材281。黏著材281可以包括晶粒黏著膜，但本發明不限於此。 In one embodiment, there may be an adhesive material 281 between the first back surface 210 b of the first chip 210 and the second back surface 120 b of the second chip 120 . The adhesive material 281 may include a die attach film, but the invention is not limited thereto.

值得注意的是，本發明並未限定形成導電連接件136的步驟及配置第二晶片120的步驟的先後順序。 It should be noted that the present invention does not limit the sequence of the step of forming the conductive connection member 136 and the step of disposing the second chip 120 .

值得注意的是，在所繪示的實施例中，是先形成導電連 接件136，然後，於第一晶片210上配置第二晶片120，但本發明不限於此。在一未繪示的實施例中，可以先於於第一晶片210上配置第二晶片120，然後，於形成導電連接件136。 It is worth noting that in the illustrated embodiment, the conductive connections are formed first Then, the second chip 120 is disposed on the first chip 210, but the invention is not limited thereto. In an unillustrated embodiment, the second chip 120 may be disposed on the first chip 210 first, and then the conductive connection member 136 is formed.

請參照圖2B至圖2C，於第一載板91上形成模封體130，其覆蓋第一晶片210及第二晶片120。模封體130可以暴露出第二晶片120的晶片連接件124的上表面124a。 Referring to FIG. 2B to FIG. 2C , a molding body 130 is formed on the first carrier 91 to cover the first chip 210 and the second chip 120 . The molding body 130 may expose the upper surface 124 a of the die attach member 124 of the second die 120 .

值得注意的是，在所繪示的實施例中，是先形成導電連接件136，然後，形成覆蓋第一晶片210及第二晶片120的模封體130，但本發明不限於此。在一未繪示的實施例中，可以先形成覆蓋第一晶片210及第二晶片120的模封體130，然後，例如藉由鑽孔/蝕刻以及鍍覆的方式形成貫穿模封體130的導電連接件136。 It should be noted that, in the illustrated embodiment, the conductive connectors 136 are formed first, and then the molding body 130 covering the first chip 210 and the second chip 120 is formed, but the invention is not limited thereto. In an unillustrated embodiment, the molding body 130 covering the first chip 210 and the second chip 120 can be formed first, and then, for example, forming holes through the molding body 130 by drilling/etching and plating. Conductive connector 136 .

請參照圖2C至圖2D，於模封體130上形成重佈線路結構170。重佈線路結構170中對應的線路可以電性連接於對應的導電連接件136及/或第二晶片120。 Referring to FIG. 2C to FIG. 2D , a redistribution circuit structure 170 is formed on the molding body 130 . The corresponding circuits in the redistributed circuit structure 170 can be electrically connected to the corresponding conductive connectors 136 and/or the second chip 120 .

請參照圖2D至圖2E，於形成模封體130之後，可以不限順序地將圖2D所繪示的結構上下翻轉及置於第二載板93(標示於圖2E)上，然後，使第一載板91(標示於圖2D)與第一晶片210分離，以暴露出第一晶片210的第一主動面210a，而構成如圖2E所繪示的結構。 Please refer to FIG. 2D to FIG. 2E , after the molding body 130 is formed, the structure shown in FIG. 2D can be turned upside down and placed on the second carrier 93 (marked in FIG. 2E ) in any order, and then, use The first carrier 91 (marked in FIG. 2D ) is separated from the first chip 210 to expose the first active surface 210 a of the first chip 210 to form the structure shown in FIG. 2E .

本發明對於第二載板93並無特別的限制，只要第二載板93可以適於承載形成於其上膜層或配置於其上的元件即可。在本實施例中，第二載板93上可以具有離型層94，但本發明不限於此。 The present invention has no special limitation on the second carrier 93 , as long as the second carrier 93 is suitable for supporting the film layer formed thereon or the components arranged thereon. In this embodiment, the second carrier 93 may have a release layer 94 , but the invention is not limited thereto.

請繼續參照圖2E，於模封體130上形成第二線路層262。第二線路層262的對應線路可以電性連接於對應的晶片連接墊212。因此，第一晶片210及第二晶片120之間可以藉由重佈線路結構170中對應的線路、導電連接件136及第二線路層262而電性連接。 Please continue to refer to FIG. 2E , the second circuit layer 262 is formed on the molding body 130 . Corresponding circuits of the second circuit layer 262 can be electrically connected to corresponding die connection pads 212 . Therefore, the first chip 210 and the second chip 120 can be electrically connected through the corresponding circuits in the redistribution circuit structure 170 , the conductive connectors 136 and the second circuit layer 262 .

請參照圖2E至圖2F，於模封體130上形成阻擋結構145。阻擋結構145暴露出第一主動面210a中的感測區210d。 Referring to FIG. 2E to FIG. 2F , a blocking structure 145 is formed on the molding body 130 . The blocking structure 145 exposes the sensing region 210d in the first active surface 210a.

請參照圖2F至圖2G，配置透光片146於阻擋結構145上，然後，使第二載板93與重佈線路結構分離。 Referring to FIG. 2F to FIG. 2G , the transparent sheet 146 is disposed on the blocking structure 145 , and then the second carrier 93 is separated from the redistribution circuit structure.

值得注意的是，在所繪示的實施例中，是先將透光片146配置於阻擋結構145上，然後，使第二載板93與重佈線路結構分離，但本發明不限於此。 It should be noted that in the illustrated embodiment, the transparent sheet 146 is disposed on the blocking structure 145 first, and then the second carrier 93 is separated from the redistribution circuit structure, but the present invention is not limited thereto.

請參照圖2G至圖2H，形成導電端子186於第一線路層171上且與第一線路層171中對應的線路電性連接。 Referring to FIG. 2G to FIG. 2H , the conductive terminals 186 are formed on the first circuit layer 171 and are electrically connected to corresponding circuits in the first circuit layer 171 .

請參照圖2G至圖2H，可以至少對圖2G所繪示的結構進行單一化製程。值得注意的是，在進行單一化製程之後，相似的元件符號將用於單一化後的元件，於此不加以贅述。另外，為求清楚表示，於圖2H中並未一一地標示所有的元件。 Referring to FIGS. 2G to 2H , at least the structure shown in FIG. 2G can be singulated. It should be noted that after the singulation process is performed, similar component symbols will be used for the singulated components, which will not be repeated here. In addition, for the sake of clarity, not all components are marked one by one in FIG. 2H .

值得注意的是，本發明並未限定形成導電端子186的步驟及進行單一化製程的先後順序。 It should be noted that the present invention does not limit the steps of forming the conductive terminals 186 and the sequence of the singulation process.

值得注意的是，在所繪示的實施例中，可以是先使第二載板93與重佈線路結構分離，然後，進行單一化製程，但本發明 不限於此。在一未繪示的實施例中，可以先進行單一化製程，然後，使第二載板93與單一化後的多個結構分離。 It should be noted that, in the illustrated embodiment, the second carrier 93 may be separated from the redistribution circuit structure first, and then the singulation process is performed, but the present invention Not limited to this. In an unillustrated embodiment, the singulation process may be performed first, and then the second carrier 93 is separated from the singulated structures.

請參照圖2H，經過上述製程後即可大致上完成本實施例之封裝結構200的製作。封裝結構200包括第一晶片210、第二晶片120、模封體130、阻擋結構145、透光片146、導電連接件136、第一線路層171以及導電端子186。第一晶片210包括第一主動面210a、第一背面210b以及第一側面210c。第一背面210b相對於第一主動面210a。第一側面210c連接第一主動面210a及第一背面210b。第一主動面210a具有感測區210d。第二晶片120以其第二背面120b面向第一晶片210的第一背面210b的方式配置。模封體130覆蓋第一晶片210及第二晶片120。阻擋結構145暴露出第一晶片210的感測區210d。第一晶片210藉由導電連接件136及第一線路層171電性連接第二晶片120。導電端子186，配置於第一線路層171上。 Please refer to FIG. 2H , the fabrication of the packaging structure 200 of this embodiment can be substantially completed after the above-mentioned manufacturing process. The packaging structure 200 includes a first chip 210 , a second chip 120 , a molding body 130 , a barrier structure 145 , a light-transmitting sheet 146 , a conductive connector 136 , a first circuit layer 171 and a conductive terminal 186 . The first wafer 210 includes a first active surface 210a, a first back surface 210b, and a first side surface 210c. The first back surface 210b is opposite to the first active surface 210a. The first side surface 210c connects the first active surface 210a and the first back surface 210b. The first active surface 210a has a sensing area 210d. The second wafer 120 is arranged such that the second back surface 120b thereof faces the first back surface 210b of the first wafer 210 . The molding body 130 covers the first chip 210 and the second chip 120 . The barrier structure 145 exposes the sensing region 210d of the first wafer 210 . The first chip 210 is electrically connected to the second chip 120 through the conductive connector 136 and the first circuit layer 171 . The conductive terminal 186 is disposed on the first circuit layer 171 .

在本實施例中，封裝結構200更包括第二線路層262。第二線路層262位於第一模封面130a上。阻擋結構145可以更暴露出第二線路層262。第一晶片210藉由第二線路層262、導電連接件136及第一線路層171電性連接所述第二晶片120。第一晶片210、第二線路層262、阻擋結構145及透光片146構成封閉空間R2。 In this embodiment, the packaging structure 200 further includes a second circuit layer 262 . The second circuit layer 262 is located on the first mold surface 130a. The blocking structure 145 may further expose the second wiring layer 262 . The first chip 210 is electrically connected to the second chip 120 through the second circuit layer 262 , the conductive connector 136 and the first circuit layer 171 . The first chip 210 , the second circuit layer 262 , the blocking structure 145 and the transparent sheet 146 form a closed space R2 .

綜上所述，本發明的製造方法及對應的結構可以將適於感測的第一晶片及適於數據處理的第二晶片整合於一封裝結構 中。如此一來，可以提升封裝結構的感測處理效能。 In summary, the manufacturing method and corresponding structure of the present invention can integrate the first chip suitable for sensing and the second chip suitable for data processing into a package structure middle. In this way, the sensing processing performance of the package structure can be improved.

100:封裝結構100: Package structure

110、120:晶片110, 120: chip

110a、110b、110c、120a、120b、120c:面110a, 110b, 110c, 120a, 120b, 120c: surface

110d:感測區110d: Sensing area

111:基材111: Substrate

112:晶片連接墊112: chip connection pad

124:晶片連接件124: chip connector

124a:表面124a: surface

115:穿矽導通孔115:Through silicon via

116:氣隙116: air gap

130:模封體130: mold sealing body

130a、130b:模封面130a, 130b: mold cover

136:導電連接件136: Conductive connector

145:阻擋結構145: Blocking structure

146:透光片146: Translucent film

150:介電層150: dielectric layer

170:重佈線路結構170:Redistribute the circuit structure

171:線路層或導電層171: circuit layer or conductive layer

175:絕緣層175: insulation layer

162:線路層162: line layer

186:導電端子186: Conductive terminal

R1:封閉空間R1: closed space

Claims (5)

一種封裝結構，包括：第一晶片，包括第一主動面以及相對於所述第一主動面的第一背面，其中所述第一主動面具有感測區；第二晶片，包括第二主動面以及相對於所述第二主動面的第二背面，且所述第二晶片以其所述第二背面面向所述第一晶片的所述第一背面的方式配置；模封體，覆蓋所述第二晶片且具有第一模封面及相對於所述第一模封面的第二模封面；阻擋結構，位於所述第一模封面上且暴露出所述第一晶片的所述感測區；透光片，位於所述阻擋結構上；導電連接件，貫穿所述模封體；第一線路層，位於所述第二模封面上，且所述第一晶片藉由所述導電連接件及所述第一線路層電性連接所述第二晶片；導電端子，配置於所述第一線路層上；第二線路層，位於所述第一模封面上，其中所述第一晶片更包括穿矽導通孔，且所述第一晶片的所述穿矽導通孔藉由所述第二線路層、所述導電連接件及所述第一線路層電性連接所述第二晶片；以及介電層，位於所述第二線路層上且覆蓋所述穿矽導通孔，以使至少一氣隙嵌於所述穿矽導通孔內，其中所述第一晶片、所述 阻擋結構及所述透光片構成封閉空間，且所述氣隙內的氣壓大於或等於所述封閉空間內的氣壓。 A packaging structure, comprising: a first chip comprising a first active surface and a first back surface opposite to the first active surface, wherein the first active surface has a sensing region; a second chip comprising a second active surface And the second back side relative to the second active surface, and the second chip is configured in such a way that the second back side faces the first back side of the first chip; a molded body covering the The second chip has a first mold surface and a second mold surface relative to the first mold surface; a blocking structure is located on the first mold surface and exposes the sensing area of the first chip; The light-transmitting sheet is located on the barrier structure; the conductive connector runs through the molding body; the first circuit layer is located on the second mold cover, and the first chip is connected by the conductive connector and The first circuit layer is electrically connected to the second chip; the conductive terminal is configured on the first circuit layer; the second circuit layer is located on the first mold cover, wherein the first chip further includes TSVs, and the TSVs of the first chip are electrically connected to the second chip through the second circuit layer, the conductive connector and the first circuit layer; and An electrical layer, located on the second circuit layer and covering the TSV, so that at least one air gap is embedded in the TSV, wherein the first chip, the The blocking structure and the transparent sheet form a closed space, and the air pressure in the air gap is greater than or equal to the air pressure in the closed space. 如請求項1所述的封裝結構，其中：所述封閉空間的氣壓小於一大氣壓。 The packaging structure according to claim 1, wherein: the air pressure in the enclosed space is less than one atmosphere. 如請求項1所述的封裝結構，其中所述第二線路層更位於所述第一晶片及所述第二晶片之間。 The package structure according to claim 1, wherein the second circuit layer is further located between the first chip and the second chip. 如請求項1所述的封裝結構，其中所述第二晶片的所述第二主動面上更具有晶片連接件，且所述晶片連接件的表面與所述第二模封面共面。 The package structure according to claim 1, wherein the second active surface of the second chip further has a chip connector, and the surface of the chip connector is coplanar with the second mold surface. 一種封裝結構的製造方法，包括：提供晶圓，其包括主動面，其中所述主動面具有感測區；形成阻擋結構於所述晶圓的所述主動面上；配置透光片於所述阻擋結構上；對所述晶圓形成穿矽導通孔，且於所述晶圓相對於所述主動面的背面上形成電性連接所述穿矽導通孔的線路層；形成覆蓋所述穿矽導通孔的介電層；於所述介電層上形成導電連接件；於所述介電層上配置第二晶片；於所述介電層上形成覆蓋所述第二晶片的模封體；於所述模封體上形成第一線路層，且所述晶圓藉由所述導電連接件及所述第一線路層電性連接所述第二晶片；以及形成導電端子於所述第一線路層上。A method for manufacturing a packaging structure, comprising: providing a wafer, which includes an active surface, wherein the active surface has a sensing area; forming a barrier structure on the active surface of the wafer; configuring a light-transmitting sheet on the On the barrier structure; form a through-silicon via hole on the wafer, and form a circuit layer electrically connected to the through-silicon via hole on the back side of the wafer opposite to the active surface; form a through-silicon via hole covering the A dielectric layer for via holes; forming a conductive connector on the dielectric layer; disposing a second chip on the dielectric layer; forming a molding body covering the second chip on the dielectric layer; Forming a first circuit layer on the molding body, and the wafer is electrically connected to the second chip through the conductive connector and the first circuit layer; and forming a conductive terminal on the first on the line layer.

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