TWI787323B - Measuring device, measurement method, and plasma processing device - Google Patents
Measuring device, measurement method, and plasma processing device Download PDFInfo
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Abstract
Description
本發明係關於一種測定裝置、測定方法及電漿處理裝置。 The invention relates to a measuring device, a measuring method and a plasma processing device.
於在電漿處理裝置內進行之蝕刻或成膜等電漿處理中，為了控制蝕刻速率或成膜速率，關鍵在於掌握電漿之狀態。因此，為了測定電漿之狀態而提出有測定自給偏壓電壓Vdc之方法(例如，參照專利文獻1、2)。
In the plasma treatment such as etching or film formation in the plasma treatment equipment, in order to control the etching rate or film formation rate, the key is to grasp the state of the plasma. Therefore, a method of measuring the self-bias voltage Vdc has been proposed in order to measure the state of the plasma (for example, refer to
專利文獻1中，藉由不與電漿直接接觸之器件間接地測定自給偏壓電壓Vdc。於專利文獻1中，器件係設置於處理容器壁內，測定對器件內之由介電體絕緣之電極施加之電壓，根據該測定電壓考慮各寄生電容而算出自給偏壓電壓Vdc。
In
專利文獻2中，將自給偏壓電壓Vdc之測定電路組入至匹配器，並將測定電路之輸入電阻設為充分地大於簇射頭之電阻值之值，藉由測定電路進行自給偏壓電壓Vdc之測定。
In
[專利文獻1]日本專利特開2001-148374號公報 [Patent Document 1] Japanese Patent Laid-Open No. 2001-148374
[專利文獻2]日本專利特開2006-93342號公報 [Patent Document 2] Japanese Patent Laid-Open No. 2006-93342
然而，上述方法必須變更裝置或電路之設計，無法簡易地進行自給偏壓電壓Vdc之測定。例如，於專利文獻1中，為了將器件設置於處理容器壁內而對處理容器壁進行機械加工。又，由於測定用探針位於遠離作為測定對象之電漿之位置，故而測定之感度及精度降低。於專利文獻2中，必須將自給偏壓電壓Vdc之測定電路組入至匹配器，而必須變更電漿處理裝置之設計。
However, the above-mentioned method needs to change the design of the device or the circuit, and cannot easily measure the self-sufficient bias voltage Vdc. For example, in
根據上述情況，於專利文獻1、2中，為了將用以進行自給偏壓電壓Vdc之測定之探針或測定電路組入，必須進行電漿處理裝置之機械設計之變更、高頻電路(匹配器)之變更，存在缺乏測定之通用性及簡易性之情形。
In view of the above, in
針對上述問題，於一態樣中，本發明之目的在於簡易地進行電漿之自給偏壓電壓Vdc之測定。 In view of the above problems, in one aspect, the purpose of the present invention is to simply measure the plasma self-bias voltage Vdc.
為了解決上述問題，根據一態樣，提供一種測定裝置，其包含：切換部，其係配置於電漿處理裝置內之靜電吸盤內之電極，且切換被施加直流電壓之上述電極之連接；具有靜電電容之構件，其連接於上述切換部；及測定部，其測定相當於上述具有靜電電容之構件所儲存之電荷量之值。 In order to solve the above problems, according to one aspect, a measurement device is provided, which includes: a switching unit, which is an electrode disposed in an electrostatic chuck in a plasma processing device, and switches the connection of the electrode to which a DC voltage is applied; A member with electrostatic capacitance connected to the switching unit; and a measurement unit for measuring a value corresponding to the amount of charge stored in the member with electrostatic capacitance.
根據一態樣，可簡易地進行電漿之自給偏壓電壓Vdc之測定。 According to one aspect, the measurement of the plasma self-bias voltage Vdc can be easily performed.
1:氣體簇射頭 1: Gas shower head
1a:氣體導入口 1a: Gas inlet
1b:擴散室 1b: Diffusion chamber
1c:供給孔 1c: Supply hole
2:載台 2: carrier
2a:靜電吸盤 2a: Electrostatic Chuck
2b:基台 2b: Abutment
3:第1高頻電源 3: The first high-frequency power supply
3a:匹配器 3a: Matcher
4:第2高頻電源 4: The second high-frequency power supply
4a:匹配器 4a: Matcher
5:氣體供給部 5: Gas supply part
6:繼電器箱 6: Relay box
6a:開關 6a: switch
7:直流電源 7: DC power supply
8:聚焦環 8: Focus ring
9:排氣裝置 9: Exhaust device
10:測定裝置 10: Measuring device
11:濾波器 11: filter
12:銅圓板 12: Copper round plate
13:銅板 13: copper plate
14:丙烯酸系樹脂板 14: Acrylic resin board
15:探針 15: Probe
16:表面電位計 16: Surface potentiometer
17:信號記錄裝置 17: Signal recording device
18:電位測定系統 18: Potential measurement system
21:吸附電極 21: Adsorption electrode
22:介電層 22: Dielectric layer
22a:凸部 22a: convex part
100:電漿處理裝置 100: Plasma treatment device
200:控制部 200: control department
205:CPU 205:CPU
210:ROM 210:ROM
215:RAM 215: RAM
A:電極 A: electrode
bdot:面積 b dot : area
ddot:高度 d dot : height
C:處理容器 C: process container
C1:靜電電容 C 1 : Electrostatic capacitance
C2:靜電電容 C 2 : Electrostatic capacitance
C3:靜電電容 C 3 : Electrostatic capacitance
C11:靜電電容 C 11 : Electrostatic capacitance
C12:靜電電容 C 12 : Electrostatic capacitance
C13:靜電電容 C 13 : Electrostatic capacitance
CB:隔直流電容器 C B : DC blocking capacitor
G:閘閥 G: gate valve
HF:第1高頻電力 HF: 1st high frequency power
K:電極 K: electrode
LF:第2高頻電力 LF: 2nd high frequency power
q1:電荷 q 1 : charge
q2:電荷 q 2 : charge
q3:電荷 q 3 : charge
R:沈積物 R: sediment
RF:高頻電源 RF: High frequency power supply
S1~S6:步驟 S1~S6: steps
S10~S20:步驟 S10~S20: steps
T:高度 T: height
Th1:閾值 Th 1 : Threshold
Th2:閾值 Th 2 : Threshold
V1:電壓 V 1 : Voltage
V2:電壓 V 2 : voltage
Vdc:自給偏壓電壓 V dc : Self-sufficient bias voltage
W:晶圓 W: Wafer
圖1(a)、(b)係用以說明自給偏壓電壓之圖。 Fig. 1(a), (b) are diagrams used to illustrate the self-sufficient bias voltage.
圖2係表示一實施形態之電漿處理裝置及測定裝置之一例之圖。 Fig. 2 is a diagram showing an example of a plasma processing device and a measuring device according to an embodiment.
圖3係用以對一實施形態之自給偏壓電壓之測定時機進行說明之圖。 Fig. 3 is a diagram for explaining the timing of measuring the self-bias voltage in one embodiment.
圖4(a)、(b)係表示一實施形態之自給偏壓電壓之測定序列之一例之圖。 4( a ), ( b ) are diagrams showing an example of a measurement sequence of a self-bias voltage in one embodiment.
圖5(a)~(c)係表示一實施形態之自給偏壓電壓之測定序列之一例之圖。 5( a ) to ( c ) are diagrams showing an example of the measurement sequence of the self-bias voltage in one embodiment.
圖6係表示一實施形態之自給偏壓電壓之計算所使用之模型之一例之圖。 FIG. 6 is a diagram showing an example of a model used for calculation of self-bias voltage in one embodiment.
圖7係表示一實施形態之模型之等效電路之一例之圖。 Fig. 7 is a diagram showing an example of an equivalent circuit of a model of an embodiment.
圖8係表示一實施形態之自給偏壓電壓之測定結果之一例之圖。 Fig. 8 is a diagram showing an example of the measurement results of the self-bias voltage in one embodiment.
圖9係表示一實施形態之自給偏壓電壓與沈積時間之相關資訊之一例之圖。 FIG. 9 is a diagram showing an example of information related to self-bias voltage and deposition time in one embodiment.
圖10(a)~(i)係表示為了收集圖9之相關資訊而預先執行之測定之一例之圖。 FIGS. 10( a ) to ( i ) are diagrams showing examples of measurements performed in advance to collect the relevant information in FIG. 9 .
圖11係表示一實施形態之測定方法之一例之流程圖。 Fig. 11 is a flow chart showing an example of a measuring method in one embodiment.
以下，參照圖式對用以實施本發明之形態進行說明。再者，於本說明書及圖式中，對於實質上相同之構成，藉由標註相同符號而省略重複之說明。 Hereinafter, modes for implementing the present invention will be described with reference to the drawings. In addition, in this specification and drawing, about the structure which is substantially the same, the description which overlaps is abbreviate|omitted by attaching the same code|symbol.
首先，一面參照圖1，一面對電漿之直流自給偏壓電壓(以下，稱為「自給偏壓電壓Vdc」)進行說明。圖1(a)中模式性地表示將電極A與電極K對向地配置而成之對向電極之一部分。電極A係接地之接地電極，電極K係經由隔直流電容器CB連接於高頻電源(RF(Radio Frequency，射頻)電源)之高頻電極。又，電極K之面積小於電極A之面積。 First, the DC self-bias voltage (hereinafter referred to as "self-bias voltage Vdc") of plasma will be described with reference to FIG. 1 . FIG. 1( a ) schematically shows a part of the counter electrode in which the electrode A and the electrode K are arranged to face each other. Electrode A is a ground electrode that is grounded, and electrode K is a high-frequency electrode that is connected to a high-frequency power supply (RF (Radio Frequency, radio frequency) power supply) via a DC blocking capacitor C B . Also, the area of the electrode K is smaller than the area of the electrode A.
對電極K施加高頻電力RF而使氣體游離及解離，從而產生電漿。由於對電極K施加正弦曲線之正負對稱之高頻電力RF，故電極K之電位總計為零。自所產生之電漿產生電子及陽離子，且如圖1(b)所示，於電極K相對於電漿處於正電位時，電子流入至電極K，處於負電位時，陽離子流入至電極K。 A high-frequency electric power RF is applied to the electrode K to dissociate and dissociate the gas, thereby generating plasma. Since the sinusoidal positive and negative symmetrical high-frequency power RF is applied to the electrode K, the potential of the electrode K is zero in total. Electrons and cations are generated from the generated plasma, and as shown in FIG. 1( b ), electrons flow into the electrode K when the electrode K is at a positive potential relative to the plasma, and cations flow into the electrode K when it is at a negative potential.
此時，電子由於質量較小，故而可追隨電極K之高速之電位變動。其 結果，電子流入至電極K。另一方面，陽離子由於質量較大，故而無法追隨電極K之高速之電位變動，於平均電場中遵循慣性定律而移動。因此，離子向電極K之流入量固定且極小。 At this time, electrons can follow the high-speed potential change of the electrode K due to their small mass. That As a result, electrons flow into the electrode K. On the other hand, the positive ions cannot follow the high-speed potential change of the electrode K due to their large mass, and move in the average electric field according to the law of inertia. Therefore, the inflow of ions to the electrode K is constant and extremely small.
由於電極K藉由隔直流電容器CB而自接地浮動，故而流入至電極K之電子不流動於接地。由此，於電極K之表面相對於電漿處於正電位之週期(半循環)中，電子流入並儲存於電極K。然而，電極K之表面因所儲存之電子而帶負電，從而對電漿產生負偏壓。由於該負偏壓，陽離子流入至電極K之表面。藉此，於電極K之表面形成鞘層。 Since the electrode K is floating from the ground by the DC blocking capacitor C B , the electrons flowing into the electrode K do not flow to the ground. Thus, electrons flow into and are stored in the electrode K during the period (half cycle) in which the surface of the electrode K is at a positive potential relative to the plasma. However, the surface of electrode K is negatively charged by the stored electrons, thereby negatively biasing the plasma. Due to the negative bias, cations flow into the surface of the electrode K. Thereby, a sheath layer is formed on the surface of the electrode K.
最終，電極K之表面以1個循環中之非常短之時間相對於電漿成為正電位。此時流入之電子與因負偏壓而穩定地流入之陽離子達到平衡時之電極K之電位差之DC(Direct Current，直流)成分為自給偏壓電壓Vdc。 Finally, the surface of the electrode K becomes a positive potential with respect to the plasma in a very short time in one cycle. At this time, the DC (Direct Current) component of the potential difference of the electrode K when the electrons flowing in and the positive ions stably flowing in due to the negative bias are in balance is the self-bias voltage Vdc.
為了控制表示電漿處理之特性之蝕刻速率或成膜速率等，必須掌握電漿之狀態。因此，於本實施形態中，為了掌握電漿處理裝置100內之電漿之狀態而測定自給偏壓電壓Vdc。
In order to control the etching rate or film formation rate, etc., which represent the characteristics of plasma processing, it is necessary to grasp the state of the plasma. Therefore, in this embodiment, in order to grasp the state of the plasma in the
圖2所示之本實施形態之電漿處理裝置100具有裝置本體、繼電器箱6及測定裝置10。測定裝置10對配置於電漿處理裝置100之處理容器C內之靜電吸盤2a內之吸附電極21之電壓進行測定。繼電器箱6於直流電源7與測定裝置10之間切換吸附電極21之連接目標。若將吸附電極21與測定裝
置10連接，則測定裝置10測定銅圓板12與銅板13之間之電壓V2作為靜電吸盤2a之吸附電極21之電位差之DC成分，並基於測定結果算出自給偏壓電壓Vdc，上述電壓V2表示相當於夾持於銅圓板12與銅板13之間之丙烯酸系樹脂板14中儲存之電荷量之值。藉此，於本實施形態中，藉由對既有之電漿處理裝置100附加繼電器箱6及測定裝置10便可簡易且精度良好地進行自給偏壓電壓Vdc之測定。以下，對本實施形態之電漿處理裝置100及測定裝置10之構成之一例進行說明。
The
本實施形態之電漿處理裝置100係電容耦合型平行平板電漿處理裝置，且具有大致圓筒形之處理容器C。對處理容器C之內面實施氧化鋁膜處理(陽極氧化處理)。處理容器C之內部成為藉由電漿進行蝕刻處理或成膜處理等電漿處理之處理室。於處理容器C內設置有載台2。
The
載台2中，於基台2b上設置有用以對晶圓W進行靜電吸附之靜電吸盤2a。基台2b例如由鋁(Al)或鈦(Ti)、碳化矽(SiC)等形成。載台2亦作為下部電極發揮功能。
In the
靜電吸盤2a成為於介電層22內具有吸附電極21之構造。於靜電吸盤2a之表面形成有點狀之凸部22a。吸附電極21連接於繼電器箱6。若將繼電器箱6之開關6a切換至直流電源7，自直流電源7向吸附電極21供給直流電壓，則作為基板之一例之晶圓W由庫侖力吸附並保持於靜電吸盤2a。
The
於靜電吸盤2a之外周側之上部，以包圍晶圓W之外緣部之方式載置有圓環狀之聚焦環8。聚焦環8例如由矽形成，且以使電漿朝向晶圓W之表面收斂而提高電漿處理效率之方式發揮功能。
An
對於載台2，自第1高頻電源3施加第1頻率之電漿產生用之第1高頻電力(HF)，且自第2高頻電源4施加作為較第1頻率低之頻率之第2頻率的偏壓電壓產生用之第2高頻電力(LF)。第1高頻電源3經由匹配器3a電性連接於載台2。第2高頻電源4經由匹配器4a電性連接於載台2。第1高頻電源3例如對載台2施加40MHz之高頻電力HF。第2高頻電源4例如對載台2施加13.56MHz之高頻電力LF。再者，於本實施形態中，將第1高頻電力施加至載台2，但第1高頻電力亦可施加至氣體簇射頭1。
To the
匹配器3a使負載阻抗與第1高頻電源3之內部(或輸出)阻抗匹配。匹配器4a使負載阻抗與第2高頻電源4之內部(或輸出)阻抗匹配。
The
氣體簇射頭1係以經由被覆其外緣部之屏蔽環封閉處理容器C之頂壁部開口之方式進行安裝。氣體簇射頭1接地。氣體簇射頭1可由矽形成。氣體簇射頭1作為與載台2(下部電極)對向之對向電極(上部電極)發揮功能。
The
於氣體簇射頭1形成有導入氣體之氣體導入口1a。於氣體簇射頭1之內部設置有用以使氣體擴散之擴散室1b。自氣體供給部5輸出之氣體經由氣體導入口1a供給至擴散室1b，並於擴散室1b內擴散而自多個氣體供給孔1c導入至處理容器C內。
In the
於處理容器C之底面形成有排氣口，藉由連接於排氣口之排氣裝置9對處理容器C內進行排氣。藉此，可將處理容器C內維持於特定之真空度。於處理容器C之側壁設置有閘閥G。閘閥G於自處理容器C進行晶圓W之搬入及搬出時開閉。
An exhaust port is formed on the bottom surface of the processing container C, and the inside of the processing container C is exhausted by an
若自氣體供給部5向處理容器C內供給處理氣體並自第1高頻電源3及第2高頻電源4對載台2施加第1及第2高頻電力，則產生電漿，對晶圓W實施特定之電漿處理。尤其是，若自第2高頻電源4對載台2施加第2高頻電力，則電漿中之離子被引向晶圓W側。
When the processing gas is supplied from the
電漿處理後，自直流電源7對吸附電極21供給正負與晶圓W之吸附時相反之直流電壓，從而去除晶圓W之電荷。藉此，晶圓W自靜電吸盤2a剝落，並自閘閥G搬出至處理容器C之外部。
After the plasma treatment, the
於電漿處理裝置100設置有控制裝置整體之動作之控制部200。控制部200具有CPU(Central Processing Unit，中央處理單元)205、ROM(Read Only Memory，唯讀記憶體)210及RAM(Random Access Memory，隨機存取記憶體)215。CPU205依據RAM215等記憶區域中儲存之製程配方執行蝕刻等所需處理。製程配方中設定有對程序條件之裝置之控制資訊即程序時間、壓力(氣體之排氣)、高頻電力或電壓、各種氣體流量、處理容器內溫度(上部電極溫度、處理容器之側壁溫度、晶圓W溫度、靜電吸盤溫度等)、冷媒之溫度等。
The
又，控制部200於特定之時機切換繼電器箱6之開關6a，將吸附電極21連接至測定裝置10。測定裝置10所測定之電壓V2被發送至控制部200，藉此，控制部200基於電壓V2算出自給偏壓電壓Vdc。
In addition, the
再者，表示用以執行該等動作之程式或處理條件之製程配方亦可記憶於硬碟或半導體記憶體。又，製程配方亦可以收容於CD-ROM(compact disc read only memory，唯讀記憶光碟)、DVD(Digital Versatile Disc，數位多功能光碟)等可攜性之可由電腦讀取之記憶媒體的狀態設置於特定位置並被讀出。 Furthermore, a recipe representing a program or processing conditions for executing these operations can also be stored in a hard disk or a semiconductor memory. In addition, the process recipe can also be stored in CD-ROM (compact disc read only memory, CD-ROM), DVD (Digital Versatile Disc, digital versatile disc) and other portable storage media that can be read by the computer. at a specific location and read out.
其次，對測定裝置10之構成之一例進行說明。測定裝置10具有濾波器11、銅圓板12、銅板13、丙烯酸系樹脂板14、探針15、表面電位計16及信號記錄裝置17。探針15及表面電位計16構成電位測定系統18。
Next, an example of the configuration of the
又，於圖2中，為了便於說明，繼電器箱6係與測定裝置10分開地進行圖示，但測定裝置10具有繼電器箱6。繼電器箱6於直流電源7與測定裝置10之具有靜電電容之構件之間切換吸附電極21之連接。繼電器箱6於測定自給偏壓電壓Vdc之時機將繼電器箱6之開關6a連接至測定裝置10。繼電器箱6係將被施加高頻電力之吸附電極21之連接切換至具有靜電電容之構件的切換部之一例。具有將丙烯酸系樹脂板14夾於銅圓板12與銅板13之間之構成之構件係具有靜電電容之構件之一例。具有靜電電容之構件並
不限於銅圓板12、銅板13及丙烯酸系樹脂板14之構成，可由經絕緣之導體構成。
In addition, in FIG. 2 , for convenience of description, the
於電位測定系統18中，使用與銅圓板12之表面非接觸地設置之探針15藉由表面電位計16測定產生於銅圓板12與銅板13之間之丙烯酸系樹脂板14之電位。電位測定系統18係測定相當於具有靜電電容之構件中儲存之電荷量之值的測定部之一例。只要可測定銅圓板12與銅板13之間之電位差，則探針15可與銅圓板12接觸，亦可不接觸。
In the
於繼電器箱6與具有靜電電容之構件之間設置有去除高頻電力之濾波器11，防止高頻電力傳播至測定裝置10側。若繼電器箱6之開關6a自與直流電源7連接之一側切換至與測定裝置10之具有靜電電容之構件連接之一側，則可進行產生於具有靜電電容之構件之電壓V2之測定、即浮動狀態之吸附電極21之電壓V2之測定。
A
具體而言，銅板13接地，使用與銅圓板12之表面非接觸地設置之探針15藉由表面電位計16測定出之電位成為浮動狀態之吸附電極21之電壓V2。再者，銅圓板12之直徑例如可為100mm左右，但並不限於此。
Specifically, the
藉由表面電位計16測定出之電壓V2係保存於連接於表面電位計16之信號記錄裝置17。信號記錄裝置17可為PC(Personal Computer，個人電腦)或平板終端等具有記憶體之電子機器，亦可為設置於雲端上之雲電腦。信號記錄裝置17所記錄之測定電壓V2被發送至控制部200，由控制部
200使用於電漿處理裝置100之蝕刻速率或成膜速率等之控制。
The voltage V 2 measured by the
具有靜電電容之構件所儲存之電荷量會因水分而受到影響。因此，銅圓板12、銅板13、丙烯酸系樹脂板14及探針15較佳為設置於真空容器內。藉由將銅圓板12、銅板13、丙烯酸系樹脂板14及探針15置於真空環境下，可不受環境之干擾之影響而精度良好地測定電壓V2。
The amount of charge stored in components with electrostatic capacitance will be affected by moisture. Therefore, the
圖3表示於電漿處理裝置100中對晶圓W進行處理之處理循環之一例。當處理開始時，首先，將晶圓W自電漿處理裝置100之閘閥G搬入(步驟S1)。其次，自直流電源7對吸附電極21供給特定之直流電壓，使晶圓W靜電吸附於靜電吸盤2a(步驟S2)。其次，對載台2(吸附電極21)施加高頻電力，將自氣體供給部5供給之程序氣體電漿化，從而對晶圓W進行蝕刻處理等電漿處理(步驟S3)。蝕刻處理係利用電漿進行之基板處理之一例。高頻電力可為自第1高頻電源3輸出之高頻電力HF或自第2高頻電源4輸出之高頻電力LF之任一者，亦可為兩者。
FIG. 3 shows an example of a processing cycle for processing a wafer W in the
其次，對吸附電極21供給與步驟S2中施加至吸附電極21之直流電壓正負相反且大小相同之直流電壓，使晶圓W自靜電吸盤2a脫離(步驟S4)，且將晶圓W自電漿處理裝置100之閘閥G搬出(步驟S5)。其次，進行清洗處理(步驟S6)。
Next, supply the DC voltage opposite to the DC voltage applied to the
於該時間點，一個晶圓W之處理結束，完成一個處理循環。再次開
始下一晶圓W之處理循環時，進行靜電吸盤2a之表面處理(處理劑等之清洗)(步驟S6)，搬入下一晶圓W(步驟S1)，重複步驟S1之後之處理。
At this point in time, the processing of one wafer W ends, and one processing cycle is completed. open again
When the processing cycle of the next wafer W is started, the surface treatment of the
於以上循環之(1)清洗處理(S6)及(2)蝕刻處理(S3)中，繼電器箱6將吸附電極21之連接切換至測定裝置10。即，繼電器箱6於執行利用電漿之晶圓W之處理或清洗處理之過程中之時機，將吸附電極21之連接切換至測定裝置10，於電位測定系統18中測定浮動狀態之吸附電極21之電壓V2。
In the above cycle (1) cleaning treatment ( S6 ) and (2) etching treatment ( S3 ), the
其次，一面參照圖4及圖5之測定序列圖，一面對(1)清洗處理及(2)蝕刻處理之測定序列之一例進行說明。圖4表示清洗處理之測定序列之一例。圖5表示蝕刻處理之測定序列之一例。清洗處理及蝕刻處理之測定序列之控制係由控制部200進行。
Next, an example of the measurement sequence of (1) cleaning treatment and (2) etching treatment will be described with reference to the measurement sequence diagrams of FIGS. 4 and 5 . Fig. 4 shows an example of a measurement sequence for cleaning treatment. FIG. 5 shows an example of a measurement sequence of etching processing. Control of the measurement sequence of the cleaning process and the etching process is performed by the
圖4所示之清洗處理之測定序列係於無晶圓乾洗(WLDC)或無晶圓處理(WLT)中進行。開始本測定序列時，吸附電極21為斷開、即未連接於直流電源7而連接於接地(基準電位)之狀態。
The measured sequence of cleaning processes shown in FIG. 4 was performed in either wafer-less dry cleaning (WLDC) or wafer-less processing (WLT). At the start of this measurement sequence, the
於該狀態下於圖4之I開始測定序列，於II將繼電器箱6之開關6a切換至與測定裝置10連接之側。藉此，將吸附電極21之連接切換至測定裝置10，吸附電極21成為浮動狀態。
In this state, the measurement sequence is started at I in FIG. 4 , and the
其後，於III接通高頻電力，於電位測定系統18中使用探針15藉由表面電位計16測定銅圓板12之電壓V2，並記錄於信號記錄裝置17。其次，於IV斷開高頻電力，於V將繼電器箱6之開關6a切換至與直流電源7連接之側，結束測定序列。重複進行以上之測定序列。
Afterwards, turn on the high-frequency power in III, use the
圖5所示之蝕刻處理之測定序列係將晶圓W載置於靜電吸盤2a，於蝕刻等電漿處理中進行。開始本測定序列時，吸附電極21為接通、即連接於直流電源7之狀態。
The measurement sequence of the etching process shown in FIG. 5 is performed by placing the wafer W on the
於該狀態下於圖5之I開始測定序列，於II將繼電器箱6之開關6a切換至與測定裝置10連接之側。藉此，將吸附電極21之連接切換至測定裝置10，吸附電極21成為浮動狀態。
In this state, the measurement sequence is started at I in FIG. 5 , and the
其後，於III接通高頻電力，於電位測定系統18中使用探針15藉由表面電位計16測定銅圓板12之電壓V2，並記錄於信號記錄裝置17。其次，於IV斷開高頻電力，並於V將繼電器箱6之開關6a切換至與直流電源7連接之一側，而測定序列結束。重複進行以上之測定序列時，若處於電漿處理中，則於VI對吸附電極21施加直流電壓HV，使晶圓W靜電吸附於載台2，其後執行VII~XI之測定序列，並於XII截止對吸附電極21施加直流電壓HV，從而停止晶圓W之吸附。VII~XI之測定序列與上述說明之II~V之測定序列相同。
Afterwards, turn on the high-frequency power at III, use the
如此，繼電器箱6於直流電源7與測定裝置10之間切換吸附電極21之連接。若將繼電器箱6之開關6a切換至測定裝置10，則吸附電極21成為浮動狀態，其後，施加高頻電力，氣體於電漿處理裝置100之電漿處理空間內電漿化。
In this way, the
施加高頻電力之後，表面電位計16使用探針15測定銅圓板12之電壓V2，控制部200基於測定出之電壓V2算出自給偏壓電壓Vdc。以下，對基於測定出之電壓V2算出自給偏壓Vdc之方法進行說明。
After the high-frequency power is applied, the
將本實施形態之自給偏壓Vdc之計算所使用之模型之一例示於圖6。如圖6之靜電吸盤2a之表面之一部分之放大圖所示，將形成於靜電吸盤2a之表面之點狀凸部22a之上表面之面積設為bdot，且將凸部22a之高度設為ddot。又，將吸附電極21至點之上表面之高度設為T，且將凸部22a之上表面之面積相對於靜電吸盤2a之表面之面積的面積比設為ael。
An example of the model used for the calculation of the self-bias voltage Vdc of this embodiment is shown in FIG. 6 . As shown in the enlarged view of a part of the surface of the electrostatic chuck 2a in FIG. d dot . Also, let T be the height from the
將靜電吸盤2a之點狀凸部22a間之空間部分之靜電電容設為C11，將凸部22a間之空間下方與吸附電極21之間之靜電電容設為C12，且將凸部22a之上表面與吸附電極21之間之靜電電容設為C13。
Let the electrostatic capacitance of the space between the point-shaped
靜電電容C11係由以下之(1)式算出。 The capacitance C11 is calculated by the following formula ( 1 ).
[數式1]
靜電電容C12係由以下之(2)式算出。 The capacitance C12 is calculated by the following formula (2).
靜電電容C13係由以下之(3)式算出。 The capacitance C13 is calculated by the following formula (3).
於(1)式~(3)式中，ε0表示真空之介電常數，εr表示比介電常數、即靜電吸盤2a之介電層22之介電常數ε與真空之介電常數ε0之比(=ε/ε0)，且S表示吸附電極21之面積。
In formulas (1) to (3), ε 0 represents the dielectric constant of vacuum, and ε r represents the specific permittivity, that is, the dielectric constant ε of the
由於靜電電容C11、C12、C13為根據設計參數求出之固定值，故靜電吸盤2a之靜電電容C1係藉由將靜電電容C11、C12、C13代入至以下之(4)式而以固定值之形式算出。
Since the electrostatic capacitances C 11 , C 12 , and C 13 are fixed values obtained according to the design parameters, the electrostatic capacitance C 1 of the
[數式4]
使用所算出之靜電吸盤2a之靜電電容C1、對作為圖6之模型之等效電路之圖7所示之靜電吸盤2a所施加之電壓V1及儲存於靜電吸盤2a之電荷q1，根據庫侖定律，以下之(5)式之關係成立。
Using the calculated electrostatic capacitance C 1 of the
C1V1=q1‧‧‧(5) C 1 V 1 =q 1 ‧‧‧(5)
將銅圓板12與銅板13(接地)之間之靜電電容設為C2，將濾波器11之靜電電容設為C3，且將施加至銅圓板12與銅板13之間及濾波器11之電壓設為V2。又，若將分別儲存於銅圓板12與銅板13之間及濾波器11之電荷設為q2、q3，則根據庫侖定律，以下之(6)式之關係成立。
Set the electrostatic capacitance between the
再者，靜電電容C2係由銅圓板12、銅板13與丙烯酸系樹脂板14之構成所決定之根據設計參數求出之固定值。同樣，靜電電容C3係由濾波器11之構成所決定之根據設計參數求出之固定值。再者，靜電電容C1、C2、C3不僅可為由設計參數決定之固定值，當然亦可由測定所得之實測值決定。
Furthermore, the electrostatic capacitance C2 is a fixed value determined by the configuration of the
(C2+C3)V2=q2+q3‧‧‧(6) (C 2 +C 3 )V 2 =q 2 +q 3 ‧‧‧(6)
對於儲存於靜電吸盤2a之電荷q1、儲存於銅圓板12與銅板13之間之電荷q2、及儲存於濾波器11之電荷q3，以下之(7)式之關係成立。
For the
q1-(q2+q3)=0‧‧‧(7) q 1 -(q 2 +q 3 )=0‧‧‧(7)
若對式(7)進行變形，則 q1=(q2+q3)‧‧‧(8) If the formula (7) is transformed, then q 1 =(q 2 +q 3 )‧‧‧(8)
若將(5)式及(6)式代入至(8)式中，則C1V1=(C2+C3)V2‧‧‧(9) If formula (5) and formula (6) are substituted into formula (8), then C 1 V 1 =(C 2 +C 3 )V 2 ‧‧‧(9)
若對(9)式進行變形，則V1=V2×(C2+C3)/C1‧‧‧(10) If formula (9) is transformed, then V 1 =V 2 ×(C 2 +C 3 )/C 1 ‧‧‧(10)
V2=V1×C1/(C2+C3)‧‧‧(11) V 2 =V 1 ×C 1 /(C 2 +C 3 )‧‧‧(11)
圖7之自給偏壓電壓Vdc係根據(10)式及(11)式藉由(12)式算出。 The self-sufficient bias voltage V dc in Fig. 7 is calculated by formula (12) according to formula (10) and formula (11).
Vdc=V1+V2‧‧‧(12) V dc =V 1 +V 2 ‧‧‧(12)
若將(10)式代入至(12)式，則Vdc=V2×(C2+C3)/C1+V2‧‧‧(13) If formula (10) is substituted into formula (12), then V dc =V 2 ×(C 2 +C 3 )/C 1 +V 2 ‧‧‧(13)
若將利用測定裝置10測定出之電壓V2、及固定值之靜電電容C1、C2、C3代入至(13)式，則算出自給偏壓電壓Vdc。靜電電容C1為由(4)式求出之C11、C12、C13之合成電容值。靜電電容C1、C2、C3係由設計參數決定之固定值。
By substituting the voltage V 2 measured by the measuring
如以上所說明般，根據本實施形態之測定方法，自給偏壓電壓Vdc可基於(13)式由表面電位計16之測定值即電壓V2、靜電吸盤2a之靜電電容C1、具有靜電電容之構件之靜電電容C2、及濾波器11之靜電電容C3簡易且精度良好地導出。
As explained above, according to the measurement method of this embodiment, the self-sufficient bias voltage V dc can be based on the formula (13) from the measured value of the
圖8表示本實施形態之測定裝置10所得之電壓V2之測定結果、及由電壓V2算出之自給偏壓電壓Vdc之一例。圖8之橫軸表示電漿處理裝置100之
處理容器C內之壓力。於圖8中，將使處理容器C內之壓力變化並藉由測定裝置10測定出之電壓V2表示為測定值。又，將基於(13)式由靜電電容C1、C2、C3及測定值之電壓V2換算而得之自給偏壓電壓Vdc表示為換算值。
FIG. 8 shows the measurement results of the voltage V2 obtained by the
藉此，無論處理容器C內之壓力如何變化，3點之測定值與換算值均一對一地對應。即，明白可藉由電位測定系統18使用具有靜電電容之構件測定浮動狀態之吸附電極21之電壓，並使用測定出之電壓V2精度良好地算出自給偏壓電壓Vdc。又，根據(13)式，具有靜電電容之構件之靜電電容C2及濾波器11之靜電電容C3越小，測定出之電壓V2(測定值)與自給偏壓電壓Vdc(換算值)越接近。
Thereby, no matter how the pressure in the processing container C changes, the measured values at the three points correspond to the converted values in a one-to-one correspondence. That is, it is understood that the
如以上所說明般，根據本實施形態，無須變更電漿處理裝置之設計，僅藉由將切換部及測定裝置設置於電漿處理裝置便可簡易地進行電漿之自給偏壓電壓Vdc之測定。 As explained above, according to this embodiment, the self-bias voltage V dc of the plasma can be easily adjusted by simply installing the switching unit and the measuring device in the plasma processing apparatus without changing the design of the plasma processing apparatus. Determination.
晶圓W之偏移或破裂係由殘留於靜電吸盤2a之表面之電荷所引起。可藉由上述測定裝置10測定電壓V2並基於(13)式算出自給偏壓電壓Vdc，上述電壓V2表示導致該晶圓W之偏移或破裂之靜電吸盤2a表面之殘留吸附狀態、即電荷之儲存容易度或帶電狀態。
The deflection or cracking of the wafer W is caused by the charge remaining on the surface of the
該電壓V2之測定及自給偏壓電壓Vdc之算出係於搬入晶圓W前之靜電吸盤2a之狀態下進行。而且，根據算出之自給偏壓電壓Vdc，判斷該時間
點之靜電吸盤2a表面之殘留吸附狀態，控制靜電吸盤2a之清洗處理時間或控制是否執行打開處理容器C而進行之靜電吸盤2a之維護等。以此方式，藉由不載置晶圓W而基於算出之自給偏壓電壓Vdc預先判定靜電吸盤2a表面之殘留吸附狀態，可消除因搬出晶圓W時之推桿銷之上升而導致晶圓W破裂之風險。
The measurement of the voltage V 2 and the calculation of the self-bias voltage V dc are performed in the state of the
即，先前係觀察於搬出晶圓W時使推桿銷上升時之銷轉矩之大小而確認殘留吸附，或者將探針或感測器***而測定靜電吸盤2a之表面電位。相對於此，根據上述測定方法，可防止晶圓W破裂之風險，並且根據自給偏壓電壓Vdc之值判斷靜電吸盤2a表面之殘留吸附狀態而判定是否執行維護。藉此，可基於判定結果，根據自給偏壓電壓Vdc獲得所執行之清洗之頻度或清洗處理時間、其他維護之執行時機等運用方法之最佳化及運用改善之方針。
That is, conventionally, the magnitude of the pin torque when the pusher pin is raised when the wafer W is unloaded was checked to confirm the residual suction, or a probe or a sensor was inserted to measure the surface potential of the
例如，參照圖9~圖11，對包含上述判定之一實施形態之測定方法之一例進行說明。圖9係表示一實施形態之自給偏壓電壓Vdc與沈積時間之相關資訊之一例之曲線圖。圖10係表示為了收集圖9之曲線圖中示出一例之相關資訊而預先進行之製程之一例之圖。圖11係表示一實施形態之測定方法之一例之流程圖。 For example, an example of a measurement method including an embodiment of the above determination will be described with reference to FIGS. 9 to 11 . FIG. 9 is a graph showing an example of information related to self-bias voltage V dc and deposition time in one embodiment. FIG. 10 is a diagram showing an example of a preliminarily performed process for collecting information related to an example shown in the graph of FIG. 9 . Fig. 11 is a flow chart showing an example of a measuring method in one embodiment.
圖9係基於測定出之銅圓板12與銅板13之間之電壓V2導出橫軸之沈積時間之累積值與縱軸之自給偏壓電壓Vdc之相關資訊。橫軸之沈積物之沈積時間之累積值與供給沈積性氣體而施加之高頻電力之施加時間之累積值
相等，且與沈積於靜電吸盤2a表面之沈積物之厚度成比例。橫軸之沈積時間之累積值係表示靜電吸盤2a之殘留吸附狀態之值之一例。但是，表示靜電吸盤2a之殘留吸附狀態之值並不限於沈積時間之累積值，亦可為靜電吸盤2a上之沈積物之厚度之測定值，還可為高頻電力之施加時間之累積值。
FIG. 9 is based on the measured voltage V 2 between the
又，縱軸之自給偏壓電壓Vdc係相當於測定出之上述電荷量之值之一例。相當於測定出之上述電荷量之值並不限於由電壓V2算出之自給偏壓電壓Vdc，亦可為測定出之電壓V2。 In addition, the self-bias voltage V dc on the vertical axis is an example of a value corresponding to the above-mentioned measured charge amount. The value corresponding to the measured charge amount is not limited to the self-bias voltage V dc calculated from the voltage V 2 , and may be the measured voltage V 2 .
於本實施形態中，藉由圖10之(a)~(i)之製程導出圖9之沈積時間之累積值與自我偏壓電壓Vdc之相關資訊。但是，表示相當於測定出之上述電荷量之值與表示靜電吸盤2a之殘留吸附狀態之值的相關關係之曲線並不限於直線。
In this embodiment, the accumulation value of the deposition time in FIG. 9 and the relevant information of the self-bias voltage V dc are derived from the process of (a) to (i) in FIG. 10 . However, the curve representing the correlation between the value corresponding to the measured charge amount and the value representing the residual adsorption state of the
例如，於圖10(a)之製程中，測定裝置10將晶圓W載置於表面不存在沈積物之狀態(即沈積時間0秒)之靜電吸盤2a上，產生氧氣之電漿，並測定銅圓板12與銅板13之間之電壓V2。繼而，基於(13)式，由測定結果之電壓V2算出表示初始時之靜電吸盤2a表面之殘留吸附狀態之自給偏壓電壓Vdc。此時之資料係圖9之沈積時間為0(s)時之Vdc(=-70V)，將該資料記憶於控制部200之RAM215等記憶部。
For example, in the process shown in Figure 10(a), the
其次，於圖10(b)之製程中，將晶圓W搬出後，藉由一面供給作為沈積性氣體之一例之CF系氣體、一面以特定時間(本實施形態中為30秒)施加
高頻電力而產生CF系氣體之電漿，使CF系之聚合物即沈積物R沈積於靜電吸盤2a之表面。
Next, in the process of FIG. 10(b), after the wafer W is unloaded, a CF-based gas as an example of a deposition gas is supplied and applied for a predetermined time (30 seconds in this embodiment) while the wafer W is unloaded.
The high-frequency power generates the plasma of the CF-based gas, so that the CF-based polymer, that is, the deposit R, is deposited on the surface of the
其次，於圖10(c)之製程中，將晶圓W載置於靜電吸盤2a上，產生氧氣之電漿，並測定銅圓板12與銅板13之間之電壓V2。繼而，基於(13)式，由測定結果之電壓V2算出表示該時間點之靜電吸盤2a表面之殘留吸附狀態之自給偏壓電壓Vdc。此時之資料係圖9之沈積時間為30秒時之Vdc(=-68V)，將該資料記憶於控制部200之RAM215等記憶部。
Next, in the manufacturing process of FIG. 10(c), the wafer W is placed on the
其次，於圖10(d)之製程中，搬出晶圓W後，藉由一面供給CF系氣體一面以特定時間(本實施形態中為進而30秒)施加高頻電力而產生CF系氣體之電漿，使CF系之聚合物之沈積物R進而沈積於靜電吸盤2a之表面。
Next, in the process shown in FIG. 10( d ), after unloading the wafer W, the CF-based gas is generated by applying high-frequency power for a specific period of time (30 seconds in this embodiment) while supplying the CF-based gas. slurry, so that the deposit R of the CF-based polymer is further deposited on the surface of the
其次，於圖10(e)之製程中，將晶圓W載置於靜電吸盤2a上，產生氧氣之電漿，並測定銅圓板12與銅板13之間之電壓V2。繼而，基於(13)式，由測定結果之電壓V2算出表示該時間點之靜電吸盤2a表面之殘留吸附狀態之自給偏壓電壓Vdc(=-66V)。此時之資料係圖9之沈積時間為60秒(=30+30)時之Vdc，將該資料記憶於控制部200之RAM215等記憶部。
Next, in the manufacturing process of FIG. 10( e ), the wafer W is placed on the
於圖10(f)及(g)、圖10(h)及(i)之製程中，將與圖10(c)及圖10(d)之製程相同之動作重複進行2次。即，於圖10(g)之測定中，算出圖9之沈積時間為90秒時之Vdc(=-64V)，於圖10(h)之測定中，算出圖9之沈積時間為120秒時之Vdc(=-62V)，將該等資料記憶於控制部200之RAM215等記憶
部。
In the process of Fig. 10(f) and (g), Fig. 10(h) and (i), the same operation as that of Fig. 10(c) and Fig. 10(d) is repeated twice. That is, in the measurement of Fig. 10(g), the V dc (=-64V) when the deposition time of Fig. 9 is calculated as 90 seconds, and in the measurement of Fig. 10(h), the deposition time of Fig. 9 is calculated as 120 seconds When V dc (=-62V), these data are memorized in memory parts such as RAM215 of the
藉由預先進行該測定，於記憶部中儲存於圖9中示出一例之表示沈積時間與自給偏壓電壓Vdc之相關關係的相關資訊。再者，圖9之表示沈積時間與自給偏壓電壓Vdc之相關關係之相關資訊為表示相當於預先測定之電荷量之值與表示靜電吸盤2a之殘留吸附狀態之值之相關關係的相關資訊之一例。
By performing this measurement in advance, relevant information showing the correlation between the deposition time and the self-bias voltage V dc shown as an example in FIG. 9 is stored in the memory unit. Furthermore, the relevant information showing the correlation between the deposition time and the self-bias voltage V dc in FIG. 9 is the relevant information showing the correlation between the value corresponding to the amount of charge measured in advance and the value showing the residual adsorption state of the
以此方式儲存之圖9之相關資訊係供圖11所示之一實施形態之測定方法參照。圖11所示之測定方法係於搬入晶圓W前由控制部200執行，包含是否執行清洗處理等維護之判定製程。藉此，根據本實施形態之測定方法，由於在特定之情形時於搬入晶圓W前執行清洗處理等維護，故而可防止靜電吸盤2a表面之殘留吸附所導致之晶圓W之偏移或破裂。
The relevant information in FIG. 9 stored in this way is for reference by the measurement method of an embodiment shown in FIG. 11 . The measurement method shown in FIG. 11 is executed by the
當圖11之處理開始時，控制部200切換繼電器箱6之開關6a，將吸附電極21連接至測定裝置10。測定裝置10測定電壓V2(步驟S10)。將測定出之電壓V2發送至控制部200，藉此，控制部200基於電壓V2算出自給偏壓電壓Vdc(步驟S12)。
When the process in FIG. 11 starts, the
其次，控制部200判定算出之自給偏壓電壓Vdc之絕對值是否超過預先規定之閾值Th1(步驟S14)。控制部200若判定算出之Vdc之絕對值未超過預先規定之閾值Th1，則判定靜電吸盤2a之殘留吸附狀態並非於晶圓W之去靜電及搬出時產生晶圓之破裂之程度，從而結束本處理。
Next, the
另一方面，若於步驟S14中，控制部200判定算出之自給偏壓電壓Vdc之絕對值超過預先規定之閾值Th1，則判定自給偏壓電壓Vdc之絕對值是否超過預先規定之閾值Th2(步驟S16)。
On the other hand, if in step S14, the
例如，如圖11所示，閾值Th1及閾值Th2具有閾值Th1之絕對值小於閾值Th2之絕對值之關係。例如，閾值Th1係表示如下情況之指標之一例，即，於自給偏壓電壓Vdc之絕對值大於閾值Th1時，推桿銷之銷轉矩提高，處於去靜電時有時會於晶圓W產生破裂之程度之殘留吸附狀態。 For example, as shown in FIG. 11 , the threshold Th1 and the threshold Th2 have a relationship in which the absolute value of the threshold Th1 is smaller than the absolute value of the threshold Th2. For example, the threshold Th1 is an example of an index indicating that when the absolute value of the self-supplied bias voltage V dc is greater than the threshold Th1, the pin torque of the push rod pin is increased, and the crystal may sometimes be damaged during destaticization. Circle W is the residual adsorption state to the extent that rupture occurs.
又，例如，閾值Th2係表示如下情況之指標之一例，即，於自給偏壓電壓Vdc之絕對值大於閾值Th2時，處於去靜電時於晶圓W產生破裂之可能性較高之殘留吸附狀態，必須打開處理容器C進行維護。 Also, for example, the threshold value Th2 is an example of an index indicating that when the absolute value of the self - bias voltage Vdc is greater than the threshold value Th2, there is a high possibility of cracks occurring on the wafer W during destaticization. The adsorption state remains, and the processing container C must be opened for maintenance.
由此，若於步驟S16中，控制部200判定自給偏壓電壓Vdc之絕對值超過預先規定之閾值Th2，則以打開處理容器C對靜電吸盤2a之表面進行醇擦拭等維護之方式進行控制，並結束本處理。
Therefore, if in step S16, the
另一方面，若於步驟S16中，控制部200判定自給偏壓電壓Vdc之絕對值未超過預先規定之閾值Th2，則以使清洗處理時間較通常情況長而進行無晶圓乾洗之方式進行控制，並結束本處理。作為使清洗處理時間較通常情況長之一例，例如可列舉於通常之清洗處理時間為20秒之情形時延長至80秒左右之控制。
On the other hand, if in step S16, the
藉此，參照記憶有自給偏壓電壓Vdc與沈積時間之相關資訊之記憶部，基於由測定出之電壓V2算出之自給偏壓電壓Vdc執行判定靜電吸盤2a表面之殘留吸附狀態之判定製程。繼而，於判定製程中，參照上述記憶部，測定出之算出之自給偏壓電壓Vdc之絕對值超過預先規定之閾值Th1或閾值Th2之至少一者時，控制部200判定執行靜電吸盤2a或處理容器C內之清洗處理或其他維護。再者，於判定製程中，亦可基於測定出之電壓V2判定靜電吸盤2a表面之殘留吸附狀態。
In this way, the determination of the residual adsorption state on the surface of the
藉此，可根據算出之自給偏壓電壓Vdc，獲得清洗之頻度或清洗時間、是否為執行靜電吸盤2a之維護等之時機等運用方法之最佳化及運用改善之方針。
In this way, based on the calculated self-bias voltage V dc , guidelines for optimizing and improving the operation method can be obtained, such as cleaning frequency or cleaning time, whether it is the timing for performing maintenance of the
以上，藉由上述實施形態對測定裝置、測定方法及電漿處理裝置進行了說明，但本發明之測定裝置、測定方法及電漿處理裝置並不限定於上述實施形態，可於本發明之範圍內進行各種變化及改良。上述複數個實施形態中記載之事項可於不矛盾之範圍內進行組合。 Above, the measuring device, measuring method and plasma processing device have been described by the above-mentioned embodiment, but the measuring device, measuring method and plasma processing device of the present invention are not limited to the above-mentioned embodiment, and can be used within the scope of the present invention. Various changes and improvements have been made. The matters described in the above-mentioned plural embodiments can be combined within the range that does not contradict.
本發明之基板處理裝置可應用於電容耦合電漿(CCP，Capacitively Coupled Plasma)、感應耦合電漿(ICP，Inductively Coupled Plasma)、放射狀線槽孔天線、電子迴旋共振式電漿(ECR，Electron Cyclotron Resonance Plasma)、螺旋微波電漿(HWP，Helicon Wave Plasma)之任一類型。 The substrate processing device of the present invention can be applied to capacitively coupled plasma (CCP, Capacitively Coupled Plasma), inductively coupled plasma (ICP, Inductively Coupled Plasma), radial line slot antenna, electron cyclotron resonance plasma (ECR, Electron Any type of Cyclotron Resonance Plasma), Helicon Microwave Plasma (HWP, Helicon Wave Plasma).
於本說明書中，列舉晶圓W作為基板之一例而進行了說明。然而，基板並不限於此，亦可為用於LCD(Liquid Crystal Display，液晶顯示器)、FPD(Flat Panel Display，平板顯示器)之各種基板、或光罩、CD(Compact Disc，光碟)基板、印刷基板等。 In this specification, a wafer W has been described as an example of a substrate. However, the substrate is not limited thereto, and may also be various substrates for LCD (Liquid Crystal Display), FPD (Flat Panel Display, flat panel display), or a photomask, CD (Compact Disc, optical disc) substrate, printed Substrate etc.
1‧‧‧氣體簇射頭 1‧‧‧Gas shower head
1a‧‧‧氣體導入口 1a‧‧‧Gas inlet
1b‧‧‧擴散室 1b‧‧‧diffusion chamber
1c‧‧‧供給孔 1c‧‧‧Supply hole
2‧‧‧載台 2‧‧‧carrier
2a‧‧‧靜電吸盤 2a‧‧‧Electrostatic chuck
2b‧‧‧基台 2b‧‧‧abutment
3‧‧‧第1高頻電源 3‧‧‧The first high-frequency power supply
3a‧‧‧匹配器 3a‧‧‧Matcher
4‧‧‧第2高頻電源 4‧‧‧The second high frequency power supply
4a‧‧‧匹配器 4a‧‧‧Matcher
5‧‧‧氣體供給部 5‧‧‧Gas Supply Unit
6‧‧‧繼電器箱 6‧‧‧Relay box
6a‧‧‧開關 6a‧‧‧Switch
7‧‧‧直流電源 7‧‧‧DC power supply
8‧‧‧聚焦環 8‧‧‧Focus ring
9‧‧‧排氣裝置 9‧‧‧exhaust device
10‧‧‧測定裝置 10‧‧‧measurement device
11‧‧‧濾波器 11‧‧‧Filter
12‧‧‧銅圓板 12‧‧‧copper round plate
13‧‧‧銅板 13‧‧‧copper plate
14‧‧‧丙烯酸系樹脂板 14‧‧‧Acrylic resin board
15‧‧‧探針 15‧‧‧Probe
16‧‧‧表面電位計 16‧‧‧Surface potentiometer
17‧‧‧信號記錄裝置 17‧‧‧Signal recording device
18‧‧‧電位測定系統 18‧‧‧potential measurement system
21‧‧‧吸附電極 21‧‧‧Adsorption electrode
22‧‧‧介電層 22‧‧‧dielectric layer
22a‧‧‧凸部 22a‧‧‧convex part
100‧‧‧電漿處理裝置 100‧‧‧plasma treatment device
200‧‧‧控制部 200‧‧‧Control Department
205‧‧‧CPU 205‧‧‧CPU
210‧‧‧ROM 210‧‧‧ROM
215‧‧‧RAM 215‧‧‧RAM
C‧‧‧處理容器 C‧‧‧Disposal container
G‧‧‧閘閥 G‧‧‧gate valve
HF‧‧‧第1高頻電力 HF‧‧‧The first high-frequency power
LF‧‧‧第2高頻電力 LF‧‧‧The second high-frequency power
V2‧‧‧電壓 V 2 ‧‧‧voltage
W‧‧‧晶圓 W‧‧‧Wafer
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| JP2018129302A JP7138497B2 (en) | 2017-08-23 | 2018-07-06 | Measuring device, measuring method and plasma processing device |
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| TWI755664B (en) * | 2019-12-19 | 2022-02-21 | 日商日本真空技術服務股份有限公司 | Power supply device and substrate management method for electrostatic chuck |
| JP7482657B2 (en) * | 2020-03-17 | 2024-05-14 | 東京エレクトロン株式会社 | CLEANING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD |
| JP7519877B2 (en) | 2020-10-29 | 2024-07-22 | 東京エレクトロン株式会社 | Plasma processing method and plasma processing apparatus |
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| TW293231B (en) * | 1994-04-27 | 1996-12-11 | Aneruba Kk | |
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- 2018-07-06 JP JP2018129302A patent/JP7138497B2/en active Active
- 2018-08-13 TW TW107128150A patent/TWI787323B/en active
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| TW334609B (en) * | 1996-09-19 | 1998-06-21 | Hitachi Ltd | Electrostatic chuck, method and device for processing sanyle use the same |
| TW201349339A (en) * | 2012-02-03 | 2013-12-01 | Tokyo Electron Ltd | Release control method, and control device for plasma processing device |
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| US20140375299A1 (en) * | 2013-06-25 | 2014-12-25 | Sergey G. BELOSTOTSKIY | Non-intrusive measurement of a wafer dc self-bias in semiconductor processing equipment |
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| TW201921417A (en) | 2019-06-01 |
| JP7138497B2 (en) | 2022-09-16 |
| KR102613181B1 (en) | 2023-12-12 |
| JP2019040853A (en) | 2019-03-14 |
| KR20190022339A (en) | 2019-03-06 |
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