TWI786548B - Semiconductor devices and methods of formation - Google Patents

Semiconductor devices and methods of formation Download PDF

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TWI786548B
TWI786548B TW110106284A TW110106284A TWI786548B TW I786548 B TWI786548 B TW I786548B TW 110106284 A TW110106284 A TW 110106284A TW 110106284 A TW110106284 A TW 110106284A TW I786548 B TWI786548 B TW I786548B
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dummy gate
spacer
fin
gate electrode
layer
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TW202133277A (en
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林士堯
高魁佑
陳振平
林志翰
張銘慶
陳昭成
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台灣積體電路製造股份有限公司
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
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    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract

Semiconductor devices and methods of forming are described herein. The methods include depositing a dummy gate material layer over a fin etched into a substrate. A gate mask is then formed over the dummy gate material layer in a channel region of the fin. A dummy gate electrode is etched into the dummy gate material using the gate mask. A top spacer is then deposited over the gate mask and along sidewalls of a top portion of the dummy gate electrode. An opening is then etched through the remainder of the dummy gate material and through the fin. A bottom spacer is then formed along a sidewall of the opening and separates a bottom portion of the dummy gate electrode from the opening. A source/drain region is then formed in the opening and the dummy gate electrode is replaced with a metal gate stack.

Description

半導體裝置及其形成方法Semiconductor device and method of forming the same

本發明實施例是關於半導體裝置及其形成方法，特別是關於能夠提升積體密度的半導體裝置及其形成方法。Embodiments of the present invention relate to a semiconductor device and a method for forming the same, in particular to a semiconductor device capable of increasing bulk density and a method for forming the same.

半導體裝置用於各種電子應用，諸如：舉例而言個人電腦、行動電話、數位相機及其他電子設備。通常藉由在半導體基板之上按順序地沉積絕緣或介電層、導電層及半導體層的材料，並使用微影使各種材料層圖案化，以形成電路組件及元件在半導體基板上而製造出半導體裝置。Semiconductor devices are used in various electronic applications such as, for example, personal computers, mobile phones, digital cameras, and other electronic equipment. It is usually manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and components on a semiconductor substrate. semiconductor device.

半導體產業藉由不斷地縮減最小部件(feature)的尺寸，而持續改善了各種電子組件(例如：電晶體、二極體、電阻器、電容器等)的積體密度，這使得更多的組件可以被整合至指定的面積內。然而，隨著最小部件的尺寸縮減，需要解決其所衍生出的其他問題。The semiconductor industry continues to improve the bulk density of various electronic components (such as: transistors, diodes, resistors, capacitors, etc.) by continuously reducing the size of the smallest feature (feature), which allows more components to be integrated into the specified area. However, as the size of the smallest components shrinks, other issues that arise need to be addressed.

一實施例是關於一種形成方法。所述形成方法包括：形成鰭片於半導體基板之上。沉積虛設閘極材料層於鰭片之上。藉由使虛設閘極材料層圖案化，來形成虛設閘極電極的頂部。沿著虛設閘極電極的頂部的側壁形成頂部間隔物。藉由蝕刻穿過虛設閘極材料層且穿過鰭片的開口，形成虛設閘極電極的底部。沿著開口的側壁形成底部間隔物。形成源極/汲極區域在開口中。移除虛設閘極電極。沉積閘極堆疊物於鰭片之上。One embodiment relates to a forming method. The forming method includes: forming fins on the semiconductor substrate. A layer of dummy gate material is deposited over the fins. The top of the dummy gate electrode is formed by patterning the layer of dummy gate material. A top spacer is formed along the sidewall of the top of the dummy gate electrode. The bottom of the dummy gate electrode is formed by etching through the dummy gate material layer and through the opening of the fin. A bottom spacer is formed along sidewalls of the opening. Source/drain regions are formed in the openings. Remove the dummy gate electrodes. A gate stack is deposited over the fins.

另一實施例是關於一種形成方法。所述形成方法包括：形成鰭片於半導體基板之上。沉積虛設閘極材料層於鰭片之上。蝕刻虛設閘極材料層至第一深度。在蝕刻虛設閘極材料層之後，沉積第一間隔物於虛設閘極材料層之上。在沉積第一間隔物之後，蝕刻穿過虛設閘極材料層的開口，以形成虛設閘極電極。沉積第二間隔物於第一間隔物之上且沿著開口的側壁。形成源極/汲極區域於開口中，第二間隔物使虛設閘極電極與源極/汲極區域分離(separating。移除虛設閘極電極。沉積閘極堆疊物於鰭片之上。Another embodiment relates to a method of forming. The forming method includes: forming fins on the semiconductor substrate. A layer of dummy gate material is deposited over the fins. The layer of dummy gate material is etched to a first depth. After etching the dummy gate material layer, a first spacer is deposited on the dummy gate material layer. After depositing the first spacers, openings are etched through the layer of dummy gate material to form dummy gate electrodes. A second spacer is deposited over the first spacer and along sidewalls of the opening. Forming source/drain regions in openings, second spacers separating dummy gate electrodes from source/drain regions. Remove dummy gate electrodes. Deposit gate stacks over fins.

又另一實施例是關於一種半導體裝置。所述半導體裝置包括鰭片、閘極電極堆疊物、第一頂部間隔物、第一底部間隔物及第一源極/汲極區域。鰭片位於基板之上。閘極電極堆疊物位於鰭片之上。第一頂部間隔物相鄰於閘極電極堆疊物。第一底部間隔物位於第一頂部間隔物之下。第一源極/汲極區域相鄰於鰭片且藉由第一底部間隔物與閘極電極堆疊物獨立(isolated)。Yet another embodiment relates to a semiconductor device. The semiconductor device includes a fin, a gate electrode stack, a first top spacer, a first bottom spacer, and a first source/drain region. The fins are on the substrate. A gate electrode stack is over the fin. The first top spacer is adjacent to the gate electrode stack. The first bottom spacer is located below the first top spacer. A first source/drain region is adjacent to the fin and is isolated from the gate electrode stack by a first bottom spacer.

以下的揭露內容提供許多不同的實施例或範例，以實施本揭露之不同部件(features)。以下敘述組件及排列方式的特定範例，以簡化本揭露。當然，這些特定的範例僅為示例，而非用以限定。舉例而言，若是本揭露書敘述了將一第一部件形成於一第二部件之上(over)或上(on)，即表示其可能包括上述第一部件與上述第二部件是直接接觸(in direct contact)的實施例，且亦可能包括了將其他部件形成於上述第一部件與上述第二部件之間，而使上述第一部件與第二部件可能未直接接觸的實施例。另外，本揭露不同範例可能重複使用相同的元件符號及/或標記。這些重複是為了簡化與清晰的目的，並非用以限定所討論的不同實施例及/或配置之間有特定的關係。The following disclosure provides many different embodiments or examples for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these specific examples are only examples, not limitations. For example, if the disclosure describes forming a first component over or on a second component, it may include that the first component is in direct contact with the second component ( in direct contact), and may also include an embodiment in which other components are formed between the first component and the second component, so that the first component and the second component may not be in direct contact. In addition, different examples of the present disclosure may reuse the same reference numerals and/or symbols. These repetitions are for simplicity and clarity and are not intended to limit a particular relationship between the different embodiments and/or configurations discussed.

再者，在本文中所用的空間相關用詞，諸如「在…下方(beneath)」、「之下(below)」、「較低的(lower)」、「上方(above)」、「較高的(upper)」及類似的用詞，是為了便於描述圖式中一個元件(element)或部件與另一個(些)元件或部件之間的關係。除了在圖式中繪示的方位外，這些空間相關用詞意欲包括使用中或操作中的裝置之不同方位。設備可能被轉向不同方位(旋轉90度或其他方位)，則在本文中使用的空間相關用詞也可依此相同解釋。Furthermore, space-related terms used in this text, such as "beneath", "below", "lower", "above", "higher "upper" and similar terms are used to describe the relationship between one element or component and another element or component in the drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be turned in different orientations (rotated 90 degrees or other orientations), and spatially relative terms used herein may be interpreted accordingly.

現在參照第1A圖，顯示半導體裝置100的形成的透視圖，半導體裝置100具有至少部分地形成在基板101之上的鰭式場效電晶體(fin field effect transistor，FinFET)107。半導體裝置100可以位於核心(core)區域或輸入/輸出(input/output，I/O)區域中，且可以包括邏輯裝置、記憶體裝置、其組合或其類似物的一部分，前述邏輯裝置、記憶體裝置、其組合或其類似物用於執行半導體裝置100的所需功能，或者用於傳輸且接收半導體裝置100輸入及輸出的訊號。然而，可以利用任何合適的區域及任何合適的功能。Referring now to FIG. 1A , there is shown a perspective view of the formation of a semiconductor device 100 having a fin field effect transistor (FinFET) 107 at least partially formed over a substrate 101 . The semiconductor device 100 may be located in a core (core) area or an input/output (input/output, I/O) area, and may include a part of a logic device, a memory device, a combination thereof, or the like, the aforementioned logic device, memory A bulk device, a combination thereof, or the like is used to perform required functions of the semiconductor device 100, or to transmit and receive signals input and output from the semiconductor device 100. However, any suitable region and any suitable function may be utilized.

基板101可以是矽(silicon)基板，但是也可以使用其他基板，諸如絕緣層上覆半導體(semiconductor-on-insulator，SOI)、應變的絕緣層上覆半導體(strained SOI)及絕緣層上覆矽鍺(silicon germanium on insulator)。基板101可以是p型半導體，儘管在其他實施例中，基板101可以是n型半導體。The substrate 101 may be a silicon substrate, but other substrates such as semiconductor-on-insulator (SOI), strained SOI, and silicon-on-insulator may also be used. Germanium (silicon germanium on insulator). Substrate 101 may be a p-type semiconductor, although in other embodiments, substrate 101 may be an n-type semiconductor.

在其他實施例中，可以選擇基板101為將特定地提高(boost)由基板101形成的裝置的性能(例如，提高載子遷移率)的材料。舉例而言，在一些實施例中，可以選擇基板101的材料為磊晶生長的半導體材料層，諸如磊晶生長的矽鍺，前述磊晶生長的矽鍺有助於提高由磊晶生長的矽鍺形成的裝置的一些性能量測。然而，使用這些材料可能能夠提高裝置的一些性能特性的同時，使用這些相同的材料可能會影響裝置的其他性能特性。In other embodiments, substrate 101 may be selected to be a material that will specifically boost the performance of devices formed from substrate 101 (eg, increase carrier mobility). For example, in some embodiments, the material of the substrate 101 can be selected to be an epitaxially grown semiconductor material layer, such as epitaxially grown silicon germanium, the aforementioned epitaxially grown silicon germanium helps to improve the epitaxially grown silicon germanium Some performance measurements of devices formed from germanium. However, while the use of these materials may be able to enhance some performance characteristics of the device, the use of these same materials may affect other performance characteristics of the device.

在半導體裝置100的核心區域及/或I/O區域內，形成複數個鰭式場效電晶體(FinFET)107，為清楚起見，在第1A圖中僅顯示一個這樣的裝置。在形成在核心區域中的裝置中，可以實施較少的鰭片以形成相應的電晶體，且介於鄰近閘極之間的間隔(spacing)(因此，居間的(intervening)源極/汲極區域的寬度)可以小於其他區域(例如，I/O區域)。In the core region and/or the I/O region of the semiconductor device 100, a plurality of fin field effect transistors (FinFETs) 107 are formed, only one such device is shown in FIG. 1A for clarity. In devices formed in the core region, fewer fins can be implemented to form the corresponding transistors, with spacing between adjacent gates (thus, intervening source/drain area) may be smaller than other areas (eg, I/O area).

可以在最終形成隔離區域111中，移除基板101的一部分作為初始步驟。可以使用遮罩層(第1A圖中未單獨顯示)以及合適的蝕刻製程移除基板101的一部分。舉例而言，遮罩層可以是包括藉由諸如化學氣相沉積(chemical vapor deposition，CVD)的製程形成的氮化矽(silicon nitride)的硬遮罩，儘管可以使用其他材料，諸如氧化物(oxides)、氧氮化物(oxynitrides)、碳化矽(silicon carbide)、其組合或其類似物以及其他製程，諸如電漿輔助化學氣相沉積(plasma enhanced chemical vapor deposition，PECVD)、低壓化學氣相沉積(low pressure chemical vapor deposition，LPCVD)或甚至形成氧化矽然後執行氮化製程(nitridation)的方法。一旦經形成，就可以藉由合適的光微影(photolithographic)製程對遮罩層進行圖案化，以暴露將被移除的基板101的那些部分。A portion of the substrate 101 may be removed as an initial step in finally forming the isolation region 111 . A portion of the substrate 101 may be removed using a mask layer (not shown separately in FIG. 1A ) and a suitable etching process. For example, the mask layer may be a hard mask comprising silicon nitride formed by a process such as chemical vapor deposition (CVD), although other materials such as oxide ( oxides), oxynitrides, silicon carbide, their combinations or their analogs, and other processes, such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (low pressure chemical vapor deposition, LPCVD) or even the method of forming silicon oxide and then performing nitridation. Once formed, the masking layer may be patterned by a suitable photolithographic process to expose those portions of the substrate 101 to be removed.

然而，如所屬技術領域中具有通常知識者將認識到的是，前述用於形成遮罩層的製程及材料並不是可用於保護基板101的一部分並同時暴露基板101的其他部分的唯一方法。可以使用任何合適製程，諸如經圖案化且經顯影的光阻劑，以暴露基板101的要被移除的一部分。所有這樣的方法完全旨在包括在本實施例的範圍內。However, as one of ordinary skill in the art will recognize, the foregoing processes and materials for forming the mask layer are not the only methods that may be used to protect a portion of the substrate 101 while exposing other portions of the substrate 101 . Any suitable process may be used, such as a patterned and developed photoresist, to expose a portion of the substrate 101 to be removed. All such methods are fully intended to be included within the scope of this embodiment.

一旦已經形成並圖案化遮罩層，可以移除基板101的一部分。儘管可以使用任何合適的製程，可以藉由諸如反應性離子蝕刻(reactive ion etching，RIE)的合適製程，來移除經暴露的基板101，以移除基板101的一部分。在一實施例中，可以移除基板101的一部分至第一深度，前述第一深度是從基板101的表面小於大約5,000 Å。Once the mask layer has been formed and patterned, a portion of the substrate 101 may be removed. Although any suitable process may be used, the exposed substrate 101 may be removed by a suitable process such as reactive ion etching (RIE) to remove a portion of the substrate 101 . In one embodiment, a portion of the substrate 101 may be removed to a first depth that is less than about 5,000 Å from the surface of the substrate 101 .

然而，如所屬技術領域中具有通常知識者將認識到的是，前述製程僅僅是一個潛在的製程，並且並不意味著是唯一的實施例。而是，可以利用藉由其可以移除基板101的一部分的任何合適的製程，並且可以使用包括任何數量的遮罩及移除步驟的任何合適的製程。However, as one of ordinary skill in the art will recognize, the foregoing process is only one potential process and is not meant to be the only embodiment. Rather, any suitable process by which a portion of substrate 101 may be removed may be utilized, and any suitable process including any number of masking and removal steps may be used.

另外，遮罩及蝕刻製程附加地(additionally)從基板101留下的那些未移除的部分形成鰭片113。為方便起見，鰭片113在圖式中顯示為與基板101分離(separated)，儘管分離的物理指示(physical indication)可以存在或不存在。如下所述，這些鰭片113可用於形成多閘極FinFET電晶體(multiple-gate FinFET transistors)的通道區域。儘管第1A圖僅顯示由基板101形成的鰭片113之一者，但是可以使用任何數量的鰭片113。In addition, the masking and etching process additionally forms the fins 113 from those portions of the substrate 101 that are left unremoved. For convenience, the fins 113 are shown separated from the substrate 101 in the drawings, although a physical indication of separation may or may not be present. These fins 113 may be used to form channel regions for multiple-gate FinFET transistors, as described below. Although FIG. 1A shows only one of the fins 113 formed from the substrate 101, any number of fins 113 may be used.

可以形成鰭片113，使得鰭片113在基板101的表面處(at)具有在介於大約5 nm與大約80 nm之間的寬度。此外，儘管已經描述形成鰭片113的特定製程，但是可以藉由任何合適的方法使鰭片113圖案化。舉例而言，可以使用一或多種光微影製程來使鰭片113圖案化，前述光微影製程包括雙重圖案化(double-patterning)或多重圖案化(multi-patterning)製程。一般而言，雙重圖案化或多重圖案化製程與光微影及自對準(self-aligned)製程結合，從而允許創造具有舉例而言，間距(pitches)小於使用單一且直接的光微影法可獲得的其他間距的圖案。舉例而言，在一實施例中，形成犧牲層在基板之上，並使用光微影製程使犧牲層圖案化。使用自對準製程在經圖案化的犧牲層旁邊(alongside)形成間隔物。然後移除犧牲層，然後可以使用剩餘的間隔物來使鰭片113圖案化。The fin 113 may be formed such that the fin 113 has a width at (at) the surface of the substrate 101 of between about 5 nm and about 80 nm. Furthermore, although a specific process for forming fins 113 has been described, fins 113 may be patterned by any suitable method. For example, one or more photolithography processes may be used to pattern the fins 113, including double-patterning or multi-patterning processes. In general, double patterning or multi-patterning processes are combined with photolithography and self-aligned processes, allowing the creation of, for example, pitches smaller than using a single, direct photolithography method. Other pitch patterns available. For example, in one embodiment, a sacrificial layer is formed on the substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 113 .

一旦已經形成鰭片113，可以沉積介電材料且可以使介電材料凹入(recessed)以形成隔離區域111。介電材料可以是氧化物材料、高密度電漿(high-density plasma，HDP)氧化物或其類似物。在可選擇的(optional)清洗(cleaning)及形成襯層(lining)的步驟之後，可以使用化學氣相沉積(CVD)方法(例如，高深寬比(high-aspect ratio process，HARP)製程)、高密度電漿CVD(high density plasma CVD)方法、或本領域已知的其他合適的形成方法來形成介電材料。Once the fins 113 have been formed, a dielectric material may be deposited and recessed to form isolation regions 111 . The dielectric material may be an oxide material, a high-density plasma (HDP) oxide, or the like. After the optional cleaning and lining steps, a chemical vapor deposition (CVD) method (for example, a high-aspect ratio process (HARP) process), High density plasma CVD (high density plasma CVD) method, or other suitable forming methods known in the art to form the dielectric material.

沉積製程可以填充(fill)或過度填充(overfill)鰭片113周圍的區域，然後可以藉由諸如化學機械拋光(chemical mechanical polishing，CMP)、蝕刻、其組合或其類似物的合適的製程，從鰭片113之上移除過量的材料。在一實施例中，移除製程亦移除位於鰭片113之上的任何介電材料，使得介電材料的移除製程將使鰭片113的表面暴露於進一步的製程步驟。The deposition process may fill (fill) or overfill (overfill) the area around the fin 113, which may then be removed by a suitable process such as chemical mechanical polishing (CMP), etching, a combination thereof, or the like. Excess material is removed over the fins 113 . In one embodiment, the removal process also removes any dielectric material overlying the fins 113 such that the removal process of the dielectric material will expose the surface of the fins 113 to further processing steps.

一旦經平坦化，然後可以使介電材料遠離(away from)鰭片113的表面凹入。可以執行凹入，以暴露與鰭片113的頂表面相鄰的鰭片113的側壁的至少一部分。可以藉由將鰭片113的頂表面浸入至(dipping into)諸如HF的蝕刻劑中，而使用濕式蝕刻使介電材料凹入，但是可以使用諸如H2 之其他蝕刻劑，以及諸如反應性離子蝕刻、使用諸如NH3 /NF3 的乾式蝕刻、化學氧化物移除(chemical oxide remova)或乾式化學清洗(dry chemical clean)之其他方法。可以使介電材料凹入到與鰭片113的表面相距為介於大約50 Å至大約500 Å之間的距離。此外，凹入也可以移除任何位於鰭片113之上的留下的(leftover)介電材料，以確保暴露鰭片113來用於進一步製程。Once planarized, the dielectric material may then be recessed away from the surface of the fin 113 . Recessing may be performed to expose at least a portion of a sidewall of the fin 113 adjacent to the top surface of the fin 113 . Wet etching can be used to recess the dielectric material by dipping the top surface of the fin 113 into an etchant such as HF, but other etchants such as H2 can be used, as well as reactive Ion etching, other methods using dry etching such as NH 3 /NF 3 , chemical oxide removal or dry chemical clean. The dielectric material may be recessed to a distance between about 50 Å to about 500 Å from the surface of the fin 113 . In addition, the recessing also removes any leftover dielectric material over the fins 113 to ensure that the fins 113 are exposed for further processing.

然而，如所屬技術領域中具有通常知識者將認識到的是，前述步驟可能僅是用於填充介電材料及使介電材料凹入的整個製程流程的一部分。舉例而言，也可以使用形成襯層的步驟、清洗步驟、退火步驟、間隙填充(gap filling)步驟、其組合或其類似物。所有潛在的製程步驟完全旨在包括在本實施例的範圍內。However, as one of ordinary skill in the art will recognize, the foregoing steps may only be part of the overall process flow for filling and recessing the dielectric material. For example, a liner forming step, a cleaning step, an annealing step, a gap filling step, a combination thereof, or the like may also be used. All potential process steps are fully intended to be included within the scope of this embodiment.

在已經形成隔離區域111之後，可以在每個鰭片113之上形成虛設閘極介電質115及虛設閘極電極117。在一實施例中，虛設閘極介電質115可以藉由熱氧化、化學氣相沉積、濺射(sputtering)或本領域中已知且用於形成閘極介電質的任何其他方法來形成。取決於形成閘極介電質的技術，在鰭片113的頂部上的虛設閘極介電質115的厚度可以與在鰭片113的側壁上的閘極介電質的厚度不同。After the isolation region 111 has been formed, a dummy gate dielectric 115 and a dummy gate electrode 117 may be formed over each fin 113 . In one embodiment, dummy gate dielectric 115 may be formed by thermal oxidation, chemical vapor deposition, sputtering, or any other method known in the art for forming gate dielectrics. . Depending on the technique used to form the gate dielectric, the thickness of the dummy gate dielectric 115 on the top of the fin 113 may be different from the thickness of the gate dielectric on the sidewalls of the fin 113 .

虛設閘極介電質115可以包括諸如二氧化矽(silicon dioxide)或氮氧化矽的材料，其厚度範圍從介於大約3 Å到大約100 Å。虛設閘極介電質115可以由高介電常數(高k，high permittivity，high-k)的材料來形成，諸如氧化鑭(lanthanum oxide，La2 O3 )、氧化鋁(aluminum oxide，Al2 O3 )、氧化鉿(hafnium oxide，HfO2 )、氧氮化鉿(hafnium oxynitride，HfON)、氧化鋯(zirconium oxide，ZrO2 )或其組合，且具有介於大約0.5 Å至大約100 Å的等效氧化物厚度(equivalent oxide thickness)。另外，二氧化矽、氧氮化矽及/或高k材料的任何組合也可以用於虛設閘極介電質115。The dummy gate dielectric 115 may include a material such as silicon dioxide or silicon oxynitride, and its thickness ranges from about 3 Å to about 100 Å. The dummy gate dielectric 115 may be formed of a high-k (high permittivity, high-k) material, such as lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), hafnium oxynitride (HfON), zirconium oxide (zirconium oxide, ZrO 2 ), or combinations thereof, and have a range of about 0.5 Å to about 100 Å Equivalent oxide thickness. Alternatively, any combination of silicon dioxide, silicon oxynitride, and/or high-k materials may be used for the dummy gate dielectric 115 .

根據一些實施例，在形成虛設閘極介電質115之前，可以形成閘極氧化物(例如，氧化物襯層)在鰭片113之上。如上所述，一旦已經形成閘極氧化物，則可以形成虛設閘極介電質115在鰭片113及閘極氧化物之上，且可以使虛設閘極介電質115圖案化。According to some embodiments, a gate oxide (eg, an oxide liner) may be formed over the fin 113 before forming the dummy gate dielectric 115 . As described above, once the gate oxide has been formed, a dummy gate dielectric 115 can be formed over the fins 113 and the gate oxide, and the dummy gate dielectric 115 can be patterned.

虛設閘極電極117可以包括導電材料或非導電材料，且可以是矽基(silicon-based)的材料，諸如矽、SiGe、SiN、SiC、SiON、其組合或其類似物，但是可以使用諸如多晶矽的任何合適的材料。根據一些實施例，可以使用複合(complex)虛設閘極材料層125(例如，參照第1B及1C圖)來形成虛設閘極電極117，前述複合虛設閘極材料層125包括：包含第一虛設閘極材料119的底層以及包含第二虛設閘極材料119的頂層，且第二虛設閘極材料119與第一虛設閘極材料119不同。The dummy gate electrode 117 may comprise a conductive material or a non-conductive material, and may be a silicon-based material such as silicon, SiGe, SiN, SiC, SiON, combinations thereof, or the like, but may use materials such as polysilicon any suitable material. According to some embodiments, the dummy gate electrode 117 may be formed using a complex dummy gate material layer 125 (eg, see FIGS. 1B and 1C ), which includes a first dummy gate The bottom layer of the electrode material 119 and the top layer include the second dummy gate material 119 , and the second dummy gate material 119 is different from the first dummy gate material 119 .

在一些實施例中，可以選擇第一虛設閘極材料119為具有大於鰭片113的蝕刻速率。如下面更詳細描述的，選擇具有不同蝕刻速率的第一虛設閘極材料119、第二虛設閘極材料121及鰭片113的材料有助於使虛設閘極電極117圖案化。舉例而言，在使用矽(Si)形成鰭片113的實施例中，可以使用矽鍺(SiGe)形成第一虛設閘極材料119，並且可以使用矽(Si)形成第二虛設閘極材料121。如此一來，第一虛設閘極材料119的蝕刻速率可以大於鰭片113的蝕刻速率。在鰭片113是諸如矽鍺的材料的其他實施例中，第一虛設閘極材料119也可以是矽鍺，但是為了產生不同的蝕刻速率，第一虛設閘極材料119可具有更高濃度的鍺。In some embodiments, the first dummy gate material 119 may be selected to have a greater etch rate than the fin 113 . As described in more detail below, selecting first dummy gate material 119 , second dummy gate material 121 , and fin 113 materials having different etch rates facilitates patterning dummy gate electrode 117 . For example, in embodiments where silicon (Si) is used to form the fin 113, the first dummy gate material 119 may be formed using silicon germanium (SiGe), and the second dummy gate material 121 may be formed using silicon (Si). . In this way, the etching rate of the first dummy gate material 119 can be greater than the etching rate of the fin 113 . In other embodiments where the fin 113 is a material such as silicon germanium, the first dummy gate material 119 may also be silicon germanium, but in order to produce a different etch rate, the first dummy gate material 119 may have a higher concentration of germanium.

根據一些實施例，可以藉由諸如化學氣相沉積(CVD)、物理氣相沉積(physical vapor deposition，PVD)、電漿輔助化學氣相沉積(PECVD)、原子層沉積(atomic layer deposition)、濺射沉積(sputter deposition)、磊晶生長或本領域已知且用於沉積材料的其他技術的一或多種製程，來沉積複合虛設閘極材料層125的材料。根據一些實施例，儘管可以使用任何合適的厚度，複合虛設閘極材料層125的厚度可以在介於大約5 Å至大約200 Å的範圍內。複合虛設閘極材料層125的頂表面可以具有非平坦(non-planar)頂表面，且可以使用，舉例而言，在使複合虛設閘極材料層125圖案化之前的化學機械平坦化(chemical mechanical planarization，CMP)製程來平坦化。此時，可以或可以不將離子引入到複合虛設閘極材料層125中。舉例而言，可以藉由離子植入技術引入離子。According to some embodiments, by means such as chemical vapor deposition (CVD), physical vapor deposition (physical vapor deposition, PVD), plasma-assisted chemical vapor deposition (PECVD), atomic layer deposition (atomic layer deposition), sputtering The material of the composite dummy gate material layer 125 is deposited by one or more processes of sputter deposition, epitaxial growth, or other techniques known in the art for depositing materials. According to some embodiments, the thickness of the composite dummy gate material layer 125 may range from about 5 Å to about 200 Å, although any suitable thickness may be used. The top surface of the composite dummy gate material layer 125 may have a non-planar top surface, and may use, for example, chemical mechanical planarization prior to patterning the composite dummy gate material layer 125. planarization, CMP) process to planarize. At this time, ions may or may not be introduced into the composite dummy gate material layer 125 . For example, ions can be introduced by ion implantation technology.

一旦已經形成複合虛設閘極材料層125，可以使虛設閘極電極117圖案化。虛設閘極電極117可以定義(define)單一通道或者可以定義位於虛設閘極介電質115之下的鰭片113內的多個通道區域。可以藉由舉例而言，使用本領域已知的沉積及光微影技術，來初始沉積並圖案化閘極遮罩123於虛設閘極材料層上，來形成虛設閘極電極117。閘極遮罩123可以結合常用的遮罩及犧牲材料，諸如(但不限於)氧化矽、氮氧化矽、SiCON、SiC、SiOC及/或氮化矽，並且可以沉積到介於大約5 Å及200 Å之間的厚度。可以使用乾式蝕刻製程來蝕刻閘極遮罩123的材料，以形成閘極遮罩123。Once the layer of composite dummy gate material 125 has been formed, the dummy gate electrode 117 may be patterned. The dummy gate electrode 117 may define a single channel or may define multiple channel regions within the fin 113 under the dummy gate dielectric 115 . The dummy gate electrode 117 may be formed by, for example, initially depositing and patterning a gate mask 123 on the dummy gate material layer using deposition and photolithography techniques known in the art. Gate mask 123 may incorporate commonly used mask and sacrificial materials such as, but not limited to, silicon oxide, silicon oxynitride, SiCON, SiC, SiOC, and/or silicon nitride, and may be deposited to between about 5 Å and Thickness between 200 Å. The material of the gate mask 123 may be etched using a dry etching process to form the gate mask 123 .

第1A圖進一步顯示穿過半導體裝置100的幾條切割線，且將在以下的討論中以及其餘的圖式中參考這些切割線。具體而言，第1A圖顯示穿過在鰭片113中的垂直部分的第一切割線AA(例如，鰭片上切割(cut-on-fin)視圖)以及穿過相鄰於鰭片113的垂直部分的第二切割線BB(例如，鰭片外切割(cut-without-fin)視圖)。FIG. 1A further shows several dicing lines through the semiconductor device 100 , and these dicing lines will be referenced in the following discussion and in the remaining figures. Specifically, FIG. 1A shows a first cut line AA through a vertical portion in fin 113 (eg, a cut-on-fin view) and through a vertical portion adjacent to fin 113. Partial second cut line BB (eg, cut-without-fin view).

第1B及1C圖根據一些實施例，顯示在形成FinFET 107的中間步驟中，沿著第一切割線AA(例如，鰭片上切割(cut-on-fin)視圖)以及第二切割線BB(例如，鰭片外切割(cut-without-fin)視圖)的剖面圖。根據一些實施例，中間步驟包括將虛設閘極材料層形成為複合虛設閘極材料層125，以及在複合虛設閘極材料層125之上形成兩個閘極遮罩123。Figures 1B and 1C show, in an intermediate step of forming FinFET 107, along a first cut line AA (eg, a cut-on-fin view) and a second cut line BB (eg, , cut-without-fin view of the fin). According to some embodiments, the intermediate steps include forming the dummy gate material layer into a composite dummy gate material layer 125 and forming two gate masks 123 over the composite dummy gate material layer 125 .

第2A及2B圖根據一些實施例，顯示沿著第一切割線AA及第二切割線BB的剖面圖，且附加顯示在形成FinFET 107的中間步驟中的第一圖案化步驟以形成虛設閘極電極117的頂部203。根據一些實施例，一旦已經形成閘極遮罩123，可以使用乾式蝕刻製程在第二虛設閘極材料121(例如，矽(Si))中及/或至第一虛設閘極材料119(例如，矽鍺(SiGe))中形成開口201。然而，可以使用任何合適的蝕刻製程來形成開口201。如此一來，虛設閘極電極117的頂部203形成在複合虛設閘極材料層125中。Figures 2A and 2B show cross-sectional views along first cut line AA and second cut line BB, and additionally show a first patterning step in an intermediate step of forming FinFET 107 to form a dummy gate, according to some embodiments. The top 203 of the electrode 117 . According to some embodiments, once the gate mask 123 has been formed, a dry etch process may be used in the second dummy gate material 121 (eg, silicon (Si)) and/or to the first dummy gate material 119 (eg, The opening 201 is formed in silicon germanium (SiGe). However, any suitable etching process may be used to form opening 201 . In this way, the top 203 of the dummy gate electrode 117 is formed in the composite dummy gate material layer 125 .

在一些實施例中，虛設閘極電極117的頂部203包括單一材料(例如，第二虛設閘極材料121)。在其他實施例中，頂部203包括多種材料(例如，第二虛設閘極材料121及第一虛設閘極材料119)。根據一些實施例，開口201可以形成為在介於大約5 nm與大約300 nm之間的第一深度D1。但是，可以使用任何合適的深度。In some embodiments, the top 203 of the dummy gate electrode 117 includes a single material (eg, the second dummy gate material 121 ). In other embodiments, the top portion 203 includes multiple materials (eg, the second dummy gate material 121 and the first dummy gate material 119 ). According to some embodiments, the opening 201 may be formed to a first depth D1 between about 5 nm and about 300 nm. However, any suitable depth can be used.

第3A及3B圖顯示沿著第一切割線AA及第二切割線BB的剖面圖，並且附加顯示與閘極遮罩123及虛設閘極電極117相鄰並在第一虛設閘極材料119的經暴露表面之上的頂部間隔物301的初始形成。頂部間隔物301的材料可以包括一個材料層(例如，單層膜)，或者可以包括多個材料層(例如，多層膜)，諸如兩層膜、三層膜、或者甚至多達十層膜。根據一些實施例，頂部間隔物301的材料可以包括第一介電材料，諸如矽基材料，且前述矽基材料諸如SiN、SiON、SiOCN、SiC、SiOC及SiO2 。根據一些實施例，可以毯覆式沉積(blanket deposition)來形成頂部間隔物301為具有在介於大約5 Å及大約500 Å之間的厚度。在一實施例中，可以藉由初始使用諸如化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)、電漿輔助化學氣相沉積(PECVD)的沉積製程；諸如氧化法的處理、其組合或其類似製程來形成頂部間隔物301的材料。然而，可以使用任何合適的材料、厚度及形成方法。3A and 3B show cross-sectional views along the first cut line AA and the second cut line BB, and additionally show the gate mask 123 and the dummy gate electrode 117 adjacent to the first dummy gate material 119. Initial formation of a top spacer 301 over the exposed surface. The material of the top spacer 301 may include one layer of material (eg, a single-layer film), or may include multiple layers of material (eg, a multi-layer film), such as two-layer films, three-layer films, or even up to ten-layer films. According to some embodiments, the material of the top spacer 301 may include a first dielectric material, such as a silicon-based material, and the aforementioned silicon-based materials such as SiN, SiON, SiOCN, SiC, SiOC, and SiO 2 . According to some embodiments, top spacer 301 may be formed by blanket deposition to have a thickness between about 5 Å and about 500 Å. In one embodiment, a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma assisted chemical vapor deposition (PECVD) may be used initially; such as The material of the top spacer 301 is formed by an oxidation treatment, a combination thereof or similar processes. However, any suitable material, thickness and method of formation may be used.

第4A及4B圖顯示沿著第一切割線AA及第二切割線BB的剖面圖，並且附加顯示圖案化步驟。根據一些實施例，圖案化步驟包括蝕刻頂部間隔物301。一旦形成，可以使頂部間隔物301的材料圖案化以形成頂部間隔物301。在一實施例中，使用諸如反應性離子蝕刻(reactive ion etches)的一或多種非等向性(anisotropic)蝕刻製程，使頂部間隔物301的材料圖案化，以從結構的至少一些水平表面(horizontal surfaces)移除頂部間隔物301的材料。Figures 4A and 4B show cross-sectional views along the first cut line AA and the second cut line BB, and additionally show the patterning step. According to some embodiments, the patterning step includes etching the top spacer 301 . Once formed, the material of top spacer 301 may be patterned to form top spacer 301 . In one embodiment, the material of the top spacer 301 is patterned using one or more anisotropic etch processes, such as reactive ion etches, to remove from at least some of the horizontal surfaces of the structure ( horizontal surfaces) remove the material of the top spacer 301.

舉例而言，在一些實施例中，可以從結構的每個水平表面移除頂部間隔物301的材料。在其他實施例中，可以從基板101及隔離區域111的水平表面移除頂部間隔物301的材料，且同時移除在諸如閘極遮罩123的其他水平表面或接近(nearly)水平的表面之上的頂部間隔物301的材料，僅僅減薄(thinned)頂部間隔物301的材料，且移除頂部間隔物301的材料不足以暴露下層的(underlying)結構。可以利用任何合適的圖案化製程。For example, in some embodiments, top spacer 301 material may be removed from each horizontal surface of the structure. In other embodiments, the top spacer 301 material may be removed from the horizontal surfaces of the substrate 101 and isolation region 111, and at the same time removed between other horizontal or nearly horizontal surfaces such as the gate mask 123. The material of the top spacer 301 is only thinned, and the removal of the material of the top spacer 301 is not enough to expose the underlying structure. Any suitable patterning process can be utilized.

圖案化步驟進一步包括使開口201延伸穿過複合虛設閘極材料層125的剩餘部分(例如，第一虛設閘極材料119)，且延伸穿過鰭片113的下層材料(例如，通道蝕刻(channel etch))。在圖案化步驟期間，閘極遮罩123及頂部間隔物301保護虛設閘極電極117的頂部203。如此一來，虛設閘極電極117的底部401由複合虛設閘極材料層125的剩餘材料形成。在一些實施例中，虛設閘極電極117的底部401包括多種材料(例如，第二虛設閘極材料121及第一虛設閘極材料119)。在其他實施例中，底部401包括單一材料(例如，第一虛設閘極材料119)。The patterning step further includes extending the opening 201 through the remainder of the composite dummy gate material layer 125 (eg, first dummy gate material 119 ), and through the underlying material of the fin 113 (eg, channel etch (channel etch). etch)). The gate mask 123 and top spacer 301 protect the top 203 of the dummy gate electrode 117 during the patterning step. In this way, the bottom 401 of the dummy gate electrode 117 is formed by the remaining material of the composite dummy gate material layer 125 . In some embodiments, the bottom 401 of the dummy gate electrode 117 includes multiple materials (eg, the second dummy gate material 121 and the first dummy gate material 119 ). In other embodiments, bottom 401 includes a single material (eg, first dummy gate material 119 ).

可以藉由使用閘極遮罩123、虛設閘極電極117及頂部間隔物301作為硬遮罩的反應性離子蝕刻(RIE)，或者藉由任何其他合適的移除製程，來執行第一虛設閘極材料119的暴露部分的經暴露部分以及來自那些未被保護的區域中的鰭片113的下層材料的移除。可以繼續移除，直到鰭片113與隔離區域111的表面為平坦(planar with)或在隔離區域111的表面之下。在圖案化步驟中以第一虛設閘極材料119蝕刻鰭片113的經暴露部分時，對介於鰭片113之間的間隔(space)沒有限制(例如，通道至通道的間隔(channel to channel space))，這允許較大的蝕刻能力(etching capability)。此外，藉由選擇第一虛設閘極材料119的材料為不同於鰭片113的材料(例如，通道區域)，可以使用蝕刻條件調整，來執行圖案化步驟，以最小化及/或防止切割穿過(cutting through)鰭片113時，對通道區域的頂部的損壞。The first dummy gate can be performed by reactive ion etching (RIE) using gate mask 123, dummy gate electrode 117 and top spacer 301 as a hard mask, or by any other suitable removal process. The exposed portions of the exposed portions of the pole material 119 and the underlying material from the fin 113 in those unprotected areas are removed. The removal may continue until the surface of the fin 113 and the isolation region 111 is planar with or below the surface of the isolation region 111 . When etching the exposed portions of the fins 113 with the first dummy gate material 119 in the patterning step, there is no restriction on the space between the fins 113 (eg, channel to channel spacing). space)), which allows for greater etching capability. Furthermore, by selecting the material of the first dummy gate material 119 to be different from the material of the fin 113 (eg, the channel region), the patterning step can be performed using etching condition adjustments to minimize and/or prevent cutting through Damage to the top of the channel area when cutting through the fins 113 .

根據一些實施例，開口201延伸到鰭片113的基底(base)，前述鰭片113的基底停止在基板101上(第4A圖中未顯示)，且鰭片113的外部停止在隔離區域111上。在其他實施例中，開口201可以在鰭片113的基底之下延伸，並延伸到基板101中，且在鰭片113的外部延伸到隔離區域111中。根據一些實施例，開口201在虛設閘極電極117的頂部203之下延伸第二深度D2，前述第二深度D2在介於大約10 nm至大約300 nm之間。然而，可以使用任何合適的深度。According to some embodiments, the opening 201 extends to the base of the fin 113 that stops on the substrate 101 (not shown in FIG. 4A ) and the exterior of the fin 113 stops on the isolation region 111. . In other embodiments, the opening 201 may extend below the base of the fin 113 , into the substrate 101 , and into the isolation region 111 outside of the fin 113 . According to some embodiments, the opening 201 extends below the top 203 of the dummy gate electrode 117 to a second depth D2 between about 10 nm and about 300 nm. However, any suitable depth may be used.

第4C圖顯示在已經執行圖案化步驟之後，在通道之下的俯視圖(在進入及離開第4A及4B圖的紙面的方向上)。具體而言，第4C圖顯示穿過兩個鰭片113的開口201的形成。鰭片113可以具有介於大約0.5 nm與大約20 nm之間的第一寬度W1。在一些實施例中，鰭片113可以彼此分離為介於大約1 nm至大約300 nm之間的第一距離Dist1。第4C圖進一步顯示的是，形成開口201使第一虛設閘極材料119分離成如第4A及4B圖所顯示之虛設閘極電極117的兩個底部401，且亦將每個鰭片113切割成兩個分離的通道區域。根據一些實施例，介於兩個底部401之間的間隔(separation)及介於鰭片113的通道區域之間的間隔可以是介於大約5 nm及大約1000 nm之間的第二距離Dist2。然而，任何合適的距離可以用於第二距離Dist2。Figure 4C shows a top view below the channel (in a direction into and out of the paper of Figures 4A and 4B) after the patterning step has been performed. Specifically, FIG. 4C shows the formation of openings 201 through two fins 113 . The fin 113 may have a first width W1 between about 0.5 nm and about 20 nm. In some embodiments, the fins 113 may be separated from each other by a first distance Dist1 between about 1 nm and about 300 nm. Figure 4C further shows that opening 201 is formed to separate first dummy gate material 119 into two bottoms 401 of dummy gate electrode 117 as shown in Figures 4A and 4B, and each fin 113 is also cut into two separate channel regions. According to some embodiments, the separation between the two bottoms 401 and the separation between the channel regions of the fins 113 may be a second distance Dist2 between about 5 nm and about 1000 nm. However, any suitable distance may be used for the second distance Dist2.

第5A至5C圖顯示執行蝕刻拉回(etch pull-back)製程，以使虛設閘極電極117的底部401凹入。在蝕刻拉回製程期間，暴露底部401且藉由頂部間隔物301及閘極遮罩123保護頂部203。此外，經選擇來用於蝕刻拉回製程的前驅物對虛設閘極電極117的經暴露材料具有高選擇比，而對鰭片113的材料(例如，通道區域)具有較低的選擇比。舉例而言，對於所使用的蝕刻劑，虛設閘極電極117的蝕刻速率大於鰭片113的通道材料的蝕刻速率。如此一來，虛設閘極電極117的底部401可以從側壁凹入第三距離Dist3，且使鰭片113很少或沒有凹入。根據一些實施例，第三距離Dist3可以是介於大約0.3 nm及大約50 nm之間的距離。然而，可以使用任何合適的距離。FIGS. 5A-5C show that an etch pull-back process is performed to recess the bottom 401 of the dummy gate electrode 117 . During the etch pullback process, the bottom 401 is exposed and the top 203 is protected by the top spacer 301 and the gate mask 123 . Furthermore, the precursor selected for the etch pullback process has a high selectivity to the exposed material of the dummy gate electrode 117 and a low selectivity to the material of the fin 113 (eg, the channel region). For example, for the etchant used, the etch rate of the dummy gate electrode 117 is greater than the etch rate of the channel material of the fin 113 . In this way, the bottom 401 of the dummy gate electrode 117 can be recessed from the sidewall by the third distance Dist3, and the fin 113 is slightly or not recessed. According to some embodiments, the third distance Dist3 may be a distance between about 0.3 nm and about 50 nm. However, any suitable distance may be used.

根據一些實施例，可以使用電漿蝕刻(plasma etch)、遠程電漿蝕刻(remote plasma etch)、自由基蝕刻(radical etch)、其組合或其類似物來執行蝕刻拉回製程。蝕刻拉回製程可以使用第一前驅物(例如，主氣體(main gas))、第二前驅物(例如，鈍化氣體(passivation gas))及/或第三前驅物(例如，稀釋氣體(dilute gas))。根據一些實施例，第一前驅物包括但不限於諸如Cl2 、HBr、CF4 、CHF3 、CH2 F2 、CH3 F、C4 F6 、BCl3 、SF6 、H2 或其類似物的氣體。第二前驅物可以在蝕刻拉回製程中用於調整蝕刻選擇比，並且包括諸如N2 、O2 、CO2 、SO2 、CO、SiCl4 或其類似物的氣體。第三前驅物包括但不限於諸如Ar、He、Ne或其類似物的氣體。可以基於第一虛設閘極材料119(例如，SiGe)及/或鰭片113的材料(例如，Si)所需的材料選擇比，來選擇第一前驅物、第二前驅物及第三前驅物的濃度。According to some embodiments, the etch pullback process may be performed using plasma etch, remote plasma etch, radical etch, combinations thereof, or the like. The etch pullback process may use a first precursor (eg, main gas), a second precursor (eg, passivation gas) and/or a third precursor (eg, dilute gas) )). According to some embodiments, the first precursor includes, but is not limited to, such as Cl 2 , HBr, CF 4 , CHF 3 , CH 2 F 2 , CH 3 F, C 4 F 6 , BCl 3 , SF 6 , H 2 , or the like gas of matter. The second precursor may be used in the etch pull-back process to adjust etch selectivity, and includes gases such as N2 , O2 , CO2 , SO2, CO , SiCl4 , or the like. The third precursor includes, but is not limited to, gases such as Ar, He, Ne, or the like. The first, second, and third precursors may be selected based on a desired material selectivity ratio for the first dummy gate material 119 (eg, SiGe) and/or the material of the fin 113 (eg, Si). concentration.

根據一些實施例，可以使用介於大約10 W及大約3,000 W之間的電漿源功率(plasma source power)(控制離子/自由基比(ion/radical ratio))來執行拉回製程。然而，可以利用任何合適的電漿源功率。此外，可以使用大約0 W至大約3,000 W之間的電漿偏置功率(plasma bias power)來執行蝕刻拉回製程。然而，可以使用任何合適的電漿偏置功率。可以控制電漿蝕刻的方向。電漿蝕刻可以是等向性蝕刻或非等向性蝕刻。根據一些實施例，可以在介於大約1 mTorr與大約800 mTorr之間的製程壓力下，執行蝕刻拉回製程。然而，可以利用任何合適的壓力。在一些實施例中，可以使用在介於大約1 每分鐘標準立方公分(Standard cubic centimeters per minute，sccm)與大約5,000 sccm之間的製程流量(process flow)之蝕刻氣體，來執行蝕刻拉回製程。但是，可以利用任何合適的製程流程。According to some embodiments, the pullback process may be performed using a plasma source power (controlling the ion/radical ratio) between about 10 W and about 3,000 W. However, any suitable plasma source power may be utilized. In addition, the etch pullback process may be performed using a plasma bias power between about 0 W and about 3,000 W. However, any suitable plasma bias power may be used. The direction of plasma etching can be controlled. Plasma etching can be isotropic or anisotropic. According to some embodiments, the etch pullback process may be performed at a process pressure between about 1 mTorr and about 800 mTorr. However, any suitable pressure may be utilized. In some embodiments, the etch pullback process may be performed using an etch gas at a process flow between about 1 standard cubic centimeters per minute (sccm) and about 5,000 sccm . However, any suitable process flow can be utilized.

根據其他實施例，蝕刻拉回製程包括濕式清洗蝕刻(wet clean etch)。可以使用諸如氫氟酸(hydrofluoric acid，HF)、氟(fluorine，F2)、其組合或其類似物的第一蝕刻劑(例如，主要化學品)來執行濕式清洗蝕刻。根據一些實施例，可以添加反應物以輔助特定材料的化學蝕刻，且反應物可以用於選擇性調整濕式清洗蝕刻。反應物包括但不限於諸如H2 SO4 、HCl、HBr、NH3 、其組合或其類似物的化合物。在一些實施例中，可以使用溶劑來提供蝕刻劑作為用於濕式清洗蝕刻的溶液。溶劑包括但不限於去離子水(de-ionized water)(例如，DI水)、醇(alcohol)、丙酮(acetone)、其組合或其類似物。According to other embodiments, the etch pullback process includes a wet clean etch. The wet clean etch may be performed using a first etchant (eg, primary chemical) such as hydrofluoric acid (HF), fluorine (F2), combinations thereof, or the like. According to some embodiments, reactants may be added to assist in the chemical etching of certain materials, and the reactants may be used to selectively tune the wet clean etch. Reactants include, but are not limited to, compounds such as H2SO4 , HCl, HBr, NH3 , combinations thereof, or the like. In some embodiments, a solvent may be used to provide the etchant as a solution for wet clean etching. Solvents include, but are not limited to, de-ionized water (eg, DI water), alcohol, acetone, combinations thereof, or the like.

第5C圖以俯視圖顯示蝕刻拉回製程。具體而言，第5C圖顯示在第一虛設閘極材料119中形成的凹部(recess)的第三距離Dist3。開口201的形成及蝕刻拉回製程允許用於將被形成的源極/汲極區域的較大間隔，且沒有通道-通道限制(channel-channel restrictions)，從而增加虛設閘極殘留缺陷(dummy gate residue defect)的裕度(window)。如此一來，由於留下虛設閘極材料的殘留物，較大的虛設閘極殘留缺陷裕度能夠提升蝕刻能力，且具有較小的缺陷風險(例如，金屬閘極短路)。Figure 5C shows the etch pullback process in top view. Specifically, FIG. 5C shows a third distance Dist3 of a recess formed in the first dummy gate material 119 . The formation of the opening 201 and the etch pullback process allows a larger separation for the source/drain regions to be formed without channel-channel restrictions that increase dummy gate residual defects. residue defect) margin (window). As such, a larger dummy gate residual defect margin can improve etch capability with less risk of defects (eg, metal gate shorts) due to leaving residues of dummy gate material.

轉到第6A及6B圖，這些圖顯示沿著第一切割線AA及第二切割線BB的剖面圖，並且附加顯示相鄰於頂部間隔物301、第一虛設閘極材料119及鰭片113，且在基板101(第6A及6B圖中未顯示)及隔離區域111的經暴露表面之上的底部間隔物601的初始形成。底部間隔物601可以包括一個材料層(例如，單層膜)，或者可以包括多個材料層(例如多層膜)，諸如兩層膜、三層膜、甚至多達十層膜。可以使用適合於形成頂部間隔物301的任何材料及任何製程來形成底部間隔物601。在一些實施例中，為底部間隔物601選擇的材料不同於為頂部間隔物301選擇的材料，但是材料也可以為相同。舉例而言，在頂部間隔物301是氮化矽(SiN)的實施例中，底部間隔物601可以是氮氧化矽(SiON)。然而，可以使用任何合適的材料。Turning to Figures 6A and 6B, these figures show cross-sectional views along first cut line AA and second cut line BB, and additionally show adjacent top spacer 301, first dummy gate material 119, and fin 113. , and the initial formation of the bottom spacer 601 over the exposed surface of the substrate 101 (not shown in FIGS. 6A and 6B ) and the isolation region 111 . The bottom spacer 601 may include one material layer (eg, a single-layer film), or may include multiple material layers (eg, multi-layer films), such as two-layer films, three-layer films, or even up to ten-layer films. Bottom spacers 601 may be formed using any material and any process suitable for forming top spacers 301 . In some embodiments, the material chosen for the bottom spacer 601 is different than the material chosen for the top spacer 301, but the material could also be the same. For example, in embodiments where the top spacer 301 is silicon nitride (SiN), the bottom spacer 601 may be silicon oxynitride (SiON). However, any suitable material may be used.

在沉積期間，底部間隔物601的材料填充在虛設閘極電極117的底部401處的凹部中。根據一些實施例，底部間隔物601的材料可以在頂部間隔物301之上形成為介於大約5 Å至大約500 Å之間的第一厚度Th1，且可以在凹部內形成為介於大約8 Å至大約1000 Å之間的第二厚度Th2。然而，可以使用任何合適的材料、厚度及形成方法。During deposition, the material of the bottom spacer 601 fills in the recess at the bottom 401 of the dummy gate electrode 117 . According to some embodiments, the material of the bottom spacer 601 may be formed to a first thickness Th1 of between about 5 Å to about 500 Å over the top spacer 301 and may be formed within the recess to be between about 8 Å. to a second thickness Th2 of about 1000 Å. However, any suitable material, thickness and method of formation may be used.

第7A及7B圖顯示沿著第一切割線AA及第二切割線BB的剖面圖，且附加顯示對底部間隔物601、隔離區域111及/或基板101(第7A及7B圖中未顯示)的材料的蝕刻。一旦已經形成用於底部間隔物601的材料，可以使底部間隔物601的材料圖案化，以形成底部間隔物601。在一實施例中，使用一或多種非等向性蝕刻製程，諸如反應性離子蝕刻製程，使底部間隔物601的材料圖案化，以從結構的水平表面移除底部間隔物601。然而，可以利用任何合適的圖案化製程。Figures 7A and 7B show cross-sectional views along the first cutting line AA and the second cutting line BB, and additionally show the bottom spacer 601, the isolation region 111 and/or the substrate 101 (not shown in Figures 7A and 7B) material for etching. Once the material for bottom spacers 601 has been formed, the material for bottom spacers 601 may be patterned to form bottom spacers 601 . In one embodiment, the material of the bottom spacers 601 is patterned using one or more anisotropic etching processes, such as a reactive ion etching process, to remove the bottom spacers 601 from the horizontal surfaces of the structures. However, any suitable patterning process may be utilized.

根據一些實施例，可以使底部間隔物601圖案化為在鰭片113之上具有第一高度H1及第一寬度W1。在一些實施例中，第一高度H1可以在介於大約3 Å與大約2,000 Å之間，且第一寬度W1可以在介於大約3 Å至大約500 Å之間。然而，可以使用任何合適的高度及寬度。此外，根據一些實施例，可以使底部間隔物601圖案化為在隔離區域111之上具有第二高度H2及第二寬度W2。在一些實施例中，第二高度H2可以在介於大約3 Å與大約2,000 Å之間，且第二寬度W2可以在介於大約3 Å及大約500 Å之間。然而，可以使用任何合適的高度及寬度。According to some embodiments, the bottom spacer 601 may be patterned to have a first height H1 and a first width W1 above the fins 113 . In some embodiments, the first height H1 may be between about 3 Å and about 2,000 Å, and the first width W1 may be between about 3 Å and about 500 Å. However, any suitable height and width may be used. Furthermore, according to some embodiments, the bottom spacer 601 may be patterned to have a second height H2 and a second width W2 above the isolation region 111 . In some embodiments, the second height H2 may be between about 3 Å and about 2,000 Å, and the second width W2 may be between about 3 Å and about 500 Å. However, any suitable height and width may be used.

在一實施例中，用於從結構的水平表面移除底部間隔物601的一或多個非等向性蝕刻製程的圖案化製程，還可用於使藉由圖案化製程暴露的隔離區域111的一部分凹入。如此一來，可以使虛設閘極電極117及底部間隔物601未覆蓋的隔離區域111凹入至第三深度D3，前述第三深度D3位於經覆蓋的隔離區域111的一部分之下，從而將開口201延伸到隔離區域111。根據一些實施例，可以使隔離區域111凹入到介於大約0.5 nm至大約50 nm之間的第三深度D3。然而，在其他實施例中，沒有使隔離區域111凹入，且隔離區域111的任何合適的圖案完全旨在包括在實施例的範圍內。In one embodiment, the patterning process of one or more anisotropic etch processes used to remove the bottom spacers 601 from the horizontal surfaces of the structure may also be used to make the isolation regions 111 exposed by the patterning process A part is dented. In this way, the isolation region 111 not covered by the dummy gate electrode 117 and the bottom spacer 601 can be recessed to a third depth D3, the third depth D3 being located below a part of the covered isolation region 111, thereby opening 201 extends to the isolation region 111 . According to some embodiments, the isolation region 111 may be recessed to a third depth D3 between about 0.5 nm and about 50 nm. However, in other embodiments, isolation regions 111 are not recessed, and any suitable pattern of isolation regions 111 is fully intended to be included within the scope of embodiments.

第8A及8B圖根據一些實施例，顯示沿著第一切割線AA及第二切割線BB的剖面圖，且附加顯示源極/汲極區域801的形成。一旦已經延伸開口201以移除鰭片113的一部分，可以形成與每個鰭片113接觸的源極/汲極區域801。在一實施例中，可以形成源極/汲極區域801，且在一些實施例中，可以形成源極/汲極區域801以形成應力源(stressor)，前述應力源將向位於虛設閘極電極117之下的鰭片113的通道區域施加應力。在一實施例中，其中鰭片113包括矽並且FinFET為p-型裝置，可以藉由以諸如矽或其他具有與通道區域不同的晶格常數(lattice constant)的材料，諸如矽鍺(silicon germanium)的材料，來進行選擇性(selective)磊晶製程而形成源極/汲極區域801。磊晶生長製程可以使用諸如矽烷(silane)、二氯矽烷(dichlorosilane)、鍺烷(germane)或其類似物的前驅物，且可以持續介於大約5分鐘至大約120分鐘。Figures 8A and 8B show cross-sectional views along the first cut line AA and the second cut line BB, and additionally show the formation of source/drain regions 801, according to some embodiments. Once openings 201 have been extended to remove a portion of fins 113 , source/drain regions 801 in contact with each fin 113 may be formed. In one embodiment, a source/drain region 801 may be formed, and in some embodiments, the source/drain region 801 may be formed to form a stressor, which will be directed towards the dummy gate electrode. The channel area of the fin 113 below 117 applies stress. In an embodiment, where the fin 113 comprises silicon and the FinFET is a p-type device, it can be achieved by using a material such as silicon or another material with a different lattice constant than the channel region, such as silicon germanium. ) material to perform a selective epitaxy process to form the source/drain region 801 . The epitaxial growth process may use precursors such as silane, dichlorosilane, germane or the like, and may last from about 5 minutes to about 120 minutes.

在一實施例中，可以形成源極/汲極區域801為具有在介於大約5 Å及大約1000 Å之間的第三高度H3。此外，根據一些實施例，可以形成源極/汲極區域801為具有在介於大約50 Å與大約10,000 Å之間的第三寬度W3。然而，可以使用任何合適的高度及寬度。雖然經顯示的實施例顯示的是，源極/汲極區域801的頂部在底部間隔物601的頂部之下，但是源極/汲極區域801也可以在底部間隔物601的頂部之上，且這樣的實施例完全旨在包括在本實施例的範圍中。In one embodiment, the source/drain region 801 may be formed to have a third height H3 between about 5 Å and about 1000 Å. Furthermore, according to some embodiments, the source/drain region 801 may be formed to have a third width W3 between about 50 Å and about 10,000 Å. However, any suitable height and width may be used. Although the illustrated embodiment shows that the top of the source/drain region 801 is below the top of the bottom spacer 601, the source/drain region 801 may also be above the top of the bottom spacer 601, and Such embodiments are fully intended to be included within the scope of the present embodiments.

一旦形成源極/汲極區域801，可以藉由植入合適的摻質來使摻質植入到源極/汲極區域801中，以補充鰭片113中的摻質來。舉例而言，可以植入諸如硼(boron)、鎵(gallium)、銦(indium)或其類似物的p型摻質以形成p型金屬氧化物半導體場效電晶體(p-type Metal Oxide Semiconductor Field Effect Transistor，PMOS)裝置。可替代地(alternatively)，可以植入諸如磷(phosphorous)、砷(arsenic)、銻(antimony)或其類似物的n型摻質以形成n型金屬氧化物半導體場效電晶體(n-type Metal Oxide Semiconductor Field Effect Transistor，NMOS)裝置。可以使用虛設閘極電極117、頂部間隔物301及底部間隔物601作為遮罩來植入這些摻質。應當注意的是，所屬技術領域中具有通常知識者將認識到的是，可以使用許多其他製程、步驟或其類似方法來植入摻質。舉例而言，所屬技術領域中具有通常知識者將認識到的是，可以使用間隔物及襯層的各種組合來執行複述個植入，或者甚至在形成期間原位植入以形成具有適用於特定目的之特定形狀或特性的源極/汲極區域。這些製程中的任何一種都可以用於植入摻質，且以上描述並不意味著將本發明的實施例限於前述步驟。Once the source/drain regions 801 are formed, dopants can be implanted into the source/drain regions 801 by implanting suitable dopants to supplement the dopants in the fins 113 . For example, p-type dopants such as boron, gallium, indium, or the like can be implanted to form a p-type Metal Oxide Semiconductor Field Effect Transistor (p-type Metal Oxide Semiconductor Field Effect Transistor, PMOS) device. Alternatively (alternatively), n-type dopants such as phosphorus (phosphorous), arsenic (arsenic), antimony (antimony) or the like can be implanted to form n-type metal oxide semiconductor field effect transistors (n-type Metal Oxide Semiconductor Field Effect Transistor, NMOS) device. These dopants can be implanted using dummy gate electrode 117, top spacer 301 and bottom spacer 601 as a mask. It should be noted that one of ordinary skill in the art will recognize that many other processes, steps, or the like may be used to implant dopants. For example, those of ordinary skill in the art will recognize that various combinations of spacers and liners can be used to perform repeat implants, or even in situ implants during formation to form features suitable for particular applications. Source/drain regions of specific shape or characteristics of interest. Any of these processes may be used to implant dopants, and the above description is not meant to limit embodiments of the present invention to the foregoing steps.

第8C及8D圖分別顯示沿著第一切割線AA及第二切割線BB的剖面圖，且進一步顯示層間介電層901的形成以及用閘極堆疊物903替換虛設閘極電極117，其中第8C圖對應於第8A圖的結構，且第8D圖對應於第8B圖的結構。一旦已經形成源極/汲極區域801，在第8A及8B圖中的結構的源極/汲極區域801、底部間隔物601、頂部間隔物301及隔離區域111的經暴露表面之上，形成接觸蝕刻停止層(未顯示)的毯覆式沉積。接觸蝕刻停止層是用來從藉由進一步製程引起的損害來保護下層結構，並提供用於進一步的蝕刻製程的控制點。在一實施例中，雖然可以可替代地使用其他材料諸如氮化物、氮氧化物、碳化物(carbide)、硼化物(boride)、其組合或其類似物，且可以可替代地使用形成接觸蝕刻停止層的替代技術，諸如低壓CVD(LPCVD)、PVD或其類似製程，接觸蝕刻停止層可以使用電漿輔助化學氣相沉積(PECVD)由氮化矽來形成。接觸蝕刻停止層可以具有介於大約50 Å與大約2000 Å之間的厚度。Figures 8C and 8D show cross-sectional views along the first cutting line AA and the second cutting line BB, respectively, and further show the formation of the interlayer dielectric layer 901 and the replacement of the dummy gate electrode 117 with the gate stack 903, wherein the first Figure 8C corresponds to the structure of Figure 8A, and Figure 8D corresponds to the structure of Figure 8B. Once the source/drain regions 801 have been formed, over the exposed surfaces of the source/drain regions 801, bottom spacers 601, top spacers 301, and isolation regions 111 of the structures in FIGS. 8A and 8B, formed Blanket deposition of a contact etch stop layer (not shown). The contact etch stop layer is used to protect the underlying structure from damage caused by further processes and to provide a control point for further etch processes. In one embodiment, although other materials such as nitrides, oxynitrides, carbides, borides, combinations thereof, or the like may alternatively be used, and may alternatively be used to form a contact etch Alternative techniques for the stop layer, such as low pressure CVD (LPCVD), PVD or similar processes, the contact etch stop layer can be formed from silicon nitride using plasma assisted chemical vapor deposition (PECVD). The contact etch stop layer may have a thickness between about 50 Å and about 2000 Å.

根據一些實施例，一旦已經形成接觸蝕刻停止層，沉積層間介電層901在接觸蝕刻停止層之上。儘管可以使用任何合適的介電，層間介電層901可以包括諸如硼磷矽酸鹽玻璃(boron phosphorous silicate glass，BPSG)的材料。雖然可以可替代地使用諸如LPCVD的其他製程，可以使用諸如PECVD的製程來形成層間介電層901。層間介電層901可以形成為在介於大約100 Å到大約3,000 Å之間的厚度。然而，可以使用任何合適的厚度。According to some embodiments, once the contact etch stop layer has been formed, an interlayer dielectric layer 901 is deposited over the contact etch stop layer. The interlayer dielectric layer 901 may comprise a material such as boron phosphorous silicate glass (BPSG), although any suitable dielectric may be used. The interlayer dielectric layer 901 may be formed using a process such as PECVD, although other processes such as LPCVD may alternatively be used. The interlayer dielectric layer 901 may be formed to have a thickness between about 100 Å to about 3,000 Å. However, any suitable thickness may be used.

一旦形成，層間介電層901及接觸蝕刻停止層可以與頂部間隔物301及虛設閘極電極117一起平坦化。在一實施例中，雖然可以使用任何合適的製程，可以使用舉例而言，諸如化學機械研磨(chemical mechanical polishing)製程的平坦化製程來使層間介電層901、接觸蝕刻停止層及頂部間隔物301平坦化。在一些實施例中，可以利用平坦化製程來移除閘極遮罩123並暴露虛設閘極電極117。Once formed, the ILD layer 901 and contact etch stop layer may be planarized along with the top spacer 301 and the dummy gate electrode 117 . In one embodiment, the ILD layer 901, the contact etch stop layer, and the top spacer may be formed using, for example, a planarization process such as a chemical mechanical polishing process, although any suitable process may be used. 301 planarization. In some embodiments, a planarization process may be used to remove the gate mask 123 and expose the dummy gate electrode 117 .

第9A及9B圖顯示的是，一旦已經暴露虛設閘極電極117，可以移除虛設閘極電極117及下層的虛設閘極介電質115。根據一些實施例，使用例如一或多種濕式或乾式蝕刻製程來移除虛設閘極電極117及虛設閘極介電質115，前述濕式或乾式蝕刻製程利用對虛設閘極電極117及/或虛設閘極介電質115的材料具有選擇比的蝕刻劑，而不是利用對於下層的鰭片113的材料(例如，通道區域)具有選擇比的蝕刻劑。然而，可以使用任何合適的移除製程或其他製程。Figures 9A and 9B show that once the dummy gate electrode 117 has been exposed, the dummy gate electrode 117 and the underlying dummy gate dielectric 115 can be removed. According to some embodiments, dummy gate electrode 117 and dummy gate dielectric 115 are removed using, for example, one or more wet or dry etch processes utilizing Instead of using an etchant that is selective to the material of the underlying fin 113 (eg, the channel region), the dummy gate dielectric 115 material has an etchant selectivity. However, any suitable removal or other process may be used.

在移除虛設閘極電極117期間，或者舉例而言，在移除虛設閘極電極117之後的閘極氧化物移除步驟中，蝕刻製程可以移除頂部間隔物301及/或底部間隔物601的一些材料。如此一來，頂部間隔物301及/或底部間隔物601的厚度可以從頂部間隔物301及/或底部間隔物601的原始厚度(例如，第三距離Dist3)減小。此外，基於介於頂部間隔物301及底部間隔物601的材料之間的蝕刻速率的差異，且基於用於移除虛設閘極電極117的蝕刻劑的選擇比，可以相較於底部間隔物601的厚度進一步減小頂部間隔物301的厚度。然而，在其他實施例中，亦可以相較於頂部間隔物301的厚度進一步減小底部間隔物601的厚度，可以以相同的量來減小厚度，或者可以不從頂部間隔物301及/或底部間隔物601的原始厚度(例如，如第5C圖所示的第三距離Dist3)來減小厚度。根據第9A至9E圖所顯示的實施例，頂部間隔物301及底部間隔物601的厚度並未從其原始厚度(例如，第三距離Dist3)減小。During removal of dummy gate electrode 117 , or, for example, in a gate oxide removal step after removal of dummy gate electrode 117 , the etch process may remove top spacer 301 and/or bottom spacer 601 some materials. In this way, the thickness of the top spacer 301 and/or the bottom spacer 601 can be reduced from the original thickness (eg, the third distance Dist3 ) of the top spacer 301 and/or the bottom spacer 601 . Furthermore, based on the difference in etch rates between the materials of the top spacer 301 and the bottom spacer 601 , and based on the selectivity of the etchant used to remove the dummy gate electrode 117 , compared to the bottom spacer 601 The thickness of the top spacer 301 is further reduced. However, in other embodiments, the thickness of the bottom spacer 601 may be further reduced compared to the thickness of the top spacer 301, the thickness may be reduced by the same amount, or the thickness of the top spacer 301 and/or may not be reduced. The original thickness of the bottom spacer 601 (for example, the third distance Dist3 as shown in FIG. 5C ) is reduced in thickness. According to the embodiment shown in FIGS. 9A-9E , the thickness of the top spacer 301 and the bottom spacer 601 are not reduced from their original thickness (eg, third distance Dist3 ).

一旦已經暴露鰭片113的通道區域，可以形成閘極堆疊物903。在一實施例中，可以藉由先沉積一系列層來形成閘極堆疊物903。在一實施例中，前述一系列層可以包括界面(interfacial)層、第一閘極介電材料、第一金屬材料及第一p型金屬功函數層(為清楚起見，在第9A及9B圖中未分別顯示每個層)。Once the channel region of the fin 113 has been exposed, a gate stack 903 may be formed. In one embodiment, gate stack 903 may be formed by first depositing a series of layers. In one embodiment, the foregoing series of layers may include an interfacial layer, a first gate dielectric material, a first metal material, and a first p-type metal work function layer (for clarity, in 9A and 9B Each layer is not shown separately in the figure).

可選擇地(optionally)，可以在形成第一閘極介電材料之前形成界面層。在一實施例中，界面層可以是藉由諸如原位蒸氣產生(in situ steam generation，ISSG)的製程，或者諸如化學氣相沉積或原子層沉積的沉積製程來形成的諸如二氧化矽(silicon dioxide)的材料。在另一實施例中，界面層可以是高k材料，諸如HfO2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、LaO、ZrO、Ta2 O5 、其組合或其類似物，且界面層可以具有介於大約5 Å及大約20 Å之間的第一厚度。在利用沉積製程的實施例中，可以共形地(conformably)形成界面層，而在利用ISSG的實施例中，可以沿開口的底部而不沿著側壁延伸地形成界面層。Optionally, an interfacial layer may be formed before forming the first gate dielectric material. In one embodiment, the interfacial layer can be formed by a process such as in situ steam generation (ISSG), or a deposition process such as chemical vapor deposition or atomic layer deposition, such as silicon dioxide (silicon dioxide). Dioxide) material. In another embodiment, the interfacial layer can be a high-k material, such as HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, Ta 2 O 5 , combinations thereof, or the like, and the interfacial layer can have A first thickness between about 5 Å and about 20 Å. In embodiments utilizing a deposition process, the interfacial layer may be conformably formed, while in embodiments utilizing ISSG, the interfacial layer may be formed extending along the bottom of the opening and not along the sidewalls.

一旦形成界面層，可以在界面層之上使第一閘極介電材料形成為蓋層。在一實施例中，第一閘極介電材料是藉由諸如原子層沉積、化學氣相沉積或其類似製程的製程來沉積的高k材料，諸如HfO2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、LaO、ZrO、Ta2 O5 、其組合或其類似物。雖然可以使用任何合適的材料及厚度，可以使第一閘極介電材料沉積到介於大約5 Å及大約200 Å之間的第二厚度。Once the interfacial layer is formed, a first gate dielectric material may be formed as a capping layer over the interfacial layer. In one embodiment, the first gate dielectric material is a high-k material, such as HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, Ta 2 O 5 , combinations thereof, or the like. The first gate dielectric material can be deposited to a second thickness of between about 5 Å and about 200 Å, although any suitable material and thickness can be used.

可選地，第一金屬材料或金屬閘極蓋層可以與第一閘極介電材料相鄰地形成(formed adjacent)為阻障層，且可以由諸如TaN、Ti、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、Ru、Mo、WN、其他金屬氧化物(metal oxides)、金屬氮化物(metal nitrides)、金屬矽酸鹽(metal silicates)、過渡金屬氧化物(transition metal-oxides)、過渡金屬氮化物(transition metal-nitrides)、過渡金屬矽酸鹽(transition metal-silicates)、金屬的氮氧化物(oxynitrides of metals)、金屬鋁酸鹽(metal aluminates)、矽酸鋯(zirconium silicate)、鋁酸鋯(zirconium aluminate)、其組合或其類似物。雖然可以使用任何合適的沉積製程或厚度，可以使用諸如原子層沉積、化學氣相沉積、濺射或其類似製程的沉積製程，使第一金屬材料沉積至介於大約5 Å至大約200 Å之間的第三厚度。Optionally, the first metal material or metal gate capping layer can be formed adjacent to the first gate dielectric material as a barrier layer, and can be made of materials such as TaN, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal-oxides , transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium silicate ), zirconium aluminate, combinations thereof, or the like. While any suitable deposition process or thickness can be used, the first metal material can be deposited to a thickness between about 5 Å to about 200 Å using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, or the like. Between the third thickness.

第一p型金屬功函數層可以相鄰於第一金屬材料形成，且在特定實施例中，可以類似於第一金屬材料。舉例而言，第一p型金屬功函數層可以由諸如W、Al、Cu、TiN、Ti、TiAlN、Ta、TaN、Co、Ni、TaC、TaCN、TaSiN、TaSi2、NiSi2、Mn、Zr、ZrSi2、TaN、Ru、AlCu、Mo、MoSi2、WN、其它金屬氧化物、金屬氮化物、金屬矽酸鹽、過渡金屬氧化物、過渡金屬氮化物，過渡金屬矽酸鹽、金屬的氮氧化物、金屬鋁酸鹽、矽酸鋯、鋁酸鋯、其組合或其類似物的金屬材料形成。另外，雖然可以使用任何合適的沉積製程或厚度，第一p型金屬功函數層可以使用諸如原子層沉積、化學氣相沉積、濺射或其類似製程的沉積製程來沉積至介於大約5 Å至大約500 Å之間的第四厚度。The first p-type metal work function layer can be formed adjacent to the first metal material, and in certain embodiments, can be similar to the first metal material. For example, the first p-type metal work function layer can be made of such as W, Al, Cu, TiN, Ti, TiAlN, Ta, TaN, Co, Ni, TaC, TaCN, TaSiN, TaSi2, NiSi2, Mn, Zr, ZrSi2 , TaN, Ru, AlCu, Mo, MoSi2, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal Aluminate, zirconium silicate, zirconium aluminate, combinations thereof or the like are formed of metallic materials. Additionally, although any suitable deposition process or thickness can be used, the first p-type metal work function layer can be deposited to between about 5 Å using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, or the like. to a fourth thickness between approximately 500 Å.

一旦已經形成第一p型金屬功函數層，可以沉積第一n型金屬功函數層。在一實施例中，第一n型金屬功函數層可以是諸如W、Cu、AlCu、TiAlC、TiAlN、Ti、TiN、Ta、TaN、Co、Ni、Ag、Al、TaAl、TaAlC、TaC、TaCN、TaSiN、Mn、Zr、其他合適的n型功函數材料或其組合。舉例而言，可以利用原子層沉積(ALD)製程、CVD製程或其類似製程，使第一n型金屬功函數層沉積至介於大約5 Å至大約5000 Å之間的第六厚度。然而，可以利用任何合適的材料及製程來形成第一n型金屬功函數層。Once the first p-type metal work function layer has been formed, a first n-type metal work function layer can be deposited. In one embodiment, the first n-type metal work function layer can be such as W, Cu, AlCu, TiAlC, TiAlN, Ti, TiN, Ta, TaN, Co, Ni, Ag, Al, TaAl, TaAlC, TaC, TaCN , TaSiN, Mn, Zr, other suitable n-type work function materials or combinations thereof. For example, the first n-type metal work function layer may be deposited to a sixth thickness ranging from about 5 Å to about 5000 Å using an atomic layer deposition (ALD) process, a CVD process, or the like. However, any suitable material and process can be used to form the first n-type metal work function layer.

在閘極堆疊物903內，亦沉積黏膠層及填充材料。一旦已經形成第一n型金屬功函數層，可以形成黏膠層，以助於使上層的填充材料與下層的第一n型金屬功函數層黏著，並提供用於形成填充材料的成核層。在一實施例中，黏膠層可以是諸如氮化鈦(titanium nitride)的材料，或者可以是與第一n型金屬功函數層相似的材料，並且可以使用諸如ALD的類似製程，來使黏膠層形成為介於大約10 Å至大約100 Å之間的第七厚度。然而，可以使用任何合適的材料及製程。Inside the gate stack 903, an adhesive layer and a fill material are also deposited. Once the first n-type metal work function layer has been formed, an adhesive layer may be formed to facilitate adhesion of the overlying filler material to the underlying first n-type metal work function layer and to provide a nucleation layer for forming the filler material . In one embodiment, the adhesive layer may be a material such as titanium nitride, or may be a material similar to the first n-type metal work function layer, and a similar process such as ALD may be used to make the adhesive The bondline is formed to a seventh thickness between about 10 Å to about 100 Å. However, any suitable materials and processes may be used.

一旦已經形成黏膠層，使用黏膠層沉積填充材料以填充開口的剩餘部分。在一實施例中，填充材料可以是諸如鎢、Al、Cu、AlCui、Ti、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、Ta、TaN、Co、Ni、其組合或其類似物的材料，且可以使用諸如鍍膜(plating)、化學氣相沉積、原子層沉積、物理氣相沉積、其組合或其類似物的沉積製程來形成。另外，可以將填充材料沉積到藉於大約1000 Å到大約2000 Å之間的厚度。然而，可以使用任何合適的材料。Once the adhesive layer has been formed, a fill material is deposited using the adhesive layer to fill the remainder of the opening. In one embodiment, the filling material can be such as tungsten, Al, Cu, AlCui, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations thereof or the like materials and may be formed using deposition processes such as plating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations thereof, or the like. Additionally, the fill material may be deposited to a thickness between about 1000 Å to about 2000 Å. However, any suitable material may be used.

第9A及9B圖進一步顯示的是，在已經沉積填充材料以填充及過度填充(overfill)開口之後，可以將材料平坦化以形成閘極堆疊物903。在一實施例中，雖然可以使用任何合適的製程，諸如研磨(grinding)或蝕刻，可以使用例如化學機械拋光來使材料平坦化。儘管為清楚起見沒有明確顯示，但是界面層可以沿著閘極堆疊物903的底表面為平坦(planar)；且第一閘極介電材料、第一金屬材料、第一p型金屬功函數層、第一n型金屬功函數層、黏膠層及填充材料可以填充閘極堆疊物903的剩餘空間。第9A圖進一步突顯出沿著第一切割線AA的結構的第一部分905，且第9B圖進一步突顯出沿著第二切割線BB的結構的第二部分907。在下面關於第9D及9E圖的討論中引用前述第一部分905及第二部分907。FIGS. 9A and 9B further show that after the fill material has been deposited to fill and overfill the openings, the material can be planarized to form the gate stack 903 . In one embodiment, the material may be planarized using, for example, chemical mechanical polishing, although any suitable process may be used, such as grinding or etching. Although not explicitly shown for clarity, the interfacial layer may be planar along the bottom surface of the gate stack 903; and the first gate dielectric material, the first metal material, the first p-type metal work function layer, the first n-type metal work function layer, the adhesive layer and the filling material may fill the remaining space of the gate stack 903 . Figure 9A further highlights a first portion 905 of the structure along the first cut line AA, and Figure 9B further highlights a second portion 907 of the structure along the second cut line BB. Reference is made to the aforementioned first portion 905 and second portion 907 in the discussion below with respect to Figures 9D and 9E.

第9A至9C圖進一步說明閘極堆疊物903的底部臨界尺寸(bottom portion critical dimension)CDB 及頂部臨界尺寸(top portion critical dimension)CDT 。底部臨界尺寸CDB 是由閘極堆疊物903分隔的(separated)底部間隔物601之間的距離，且頂部臨界尺寸CDT是由閘極堆疊物903分隔的頂部間隔物301之間的距離。根據一些實施例，頂部臨界尺寸CDT 可以是與底部臨界尺寸CDB 大約相同的距離，諸如在介於大約1 nm至大約500 nm之間的距離。然而，可以使用任何合適的距離。第9C圖以俯視圖顯示閘極堆疊物903的形成。具體而言，第9C圖顯示在兩個相鄰的鰭片113之間且在底部間隔物601之間的閘極堆疊物903的形成。FIGS. 9A-9C further illustrate the bottom portion critical dimension CD B and the top portion critical dimension CD T of the gate stack 903 . The bottom CD B is the distance between the bottom spacers 601 separated by the gate stacks 903 , and the top CDT is the distance between the top spacers 301 separated by the gate stacks 903 . According to some embodiments, the top CD T may be about the same distance as the bottom CD B , such as between about 1 nm to about 500 nm. However, any suitable distance may be used. FIG. 9C shows the formation of the gate stack 903 in a top view. Specifically, FIG. 9C shows the formation of gate stacks 903 between two adjacent fins 113 and between bottom spacers 601 .

第9D圖顯示在第9A圖中突顯出的第一部分905的放大圖，且第9E圖顯示在第9B圖中突顯示的第二部分907的放大圖。具體而言，第9D及9E圖進一步顯示的是，在閘極堆疊物903的頂部臨界尺寸CDT 及底部臨界尺寸CDB 為大約相等的距離的實施例中，閘極堆疊物903、頂部間隔物301及底部間隔物601的一些部件。Figure 9D shows an enlarged view of the first portion 905 highlighted in Figure 9A, and Figure 9E shows an enlarged view of the second portion 907 highlighted in Figure 9B. Specifically, Figures 9D and 9E further show that in embodiments where the top critical dimension CD T and the bottom critical dimension CD B of the gate stack 903 are approximately equal distances apart, the gate stack 903, top spacer Object 301 and some parts of bottom spacer 601.

根據一些實施例，在間隔物界面909處頂部間隔物301與底部間隔物601相交(intersect)。根據一些實施例，間隔物界面909具有大約等於第三距離Dist3的長度。在一些實施例中，雖然間隔物界面909也可以位於源極/汲極區域801的頂部的水平面處或水平面之下，間隔物界面909位於源極/汲極區域801的頂部的水平面(level)之上。According to some embodiments, top spacer 301 intersects bottom spacer 601 at spacer interface 909 . According to some embodiments, the spacer interface 909 has a length approximately equal to the third distance Dist3. In some embodiments, the spacer interface 909 is located at the level of the top of the source/drain region 801, although the spacer interface 909 may also be located at or below the level of the top of the source/drain region 801. above.

第9D圖進一步顯示的是，底部間隔物601位於與閘極堆疊物903相鄰且與通道區域(例如，鰭片113)的頂部相鄰。在介於底部間隔物601及閘極堆疊物903之間的界面及底部間隔物601及通道區域之間的界面形成第一角度θ’。根據一些實施例，第一角度θ’為大約90°，諸如在介於大約60°與大約120°之間的範圍內。FIG. 9D further shows that bottom spacer 601 is located adjacent to gate stack 903 and adjacent to the top of the channel region (eg, fin 113 ). A first angle θ' is formed between the interface between the bottom spacer 601 and the gate stack 903 and the interface between the bottom spacer 601 and the channel region. According to some embodiments, the first angle θ' is about 90°, such as in a range between about 60° and about 120°.

轉為參照第10A及10B圖，根據一些其他實施例，這些圖式分別顯示在第9A圖中突顯出的第一部分905及在第9B圖中突顯出的第二部分907的放大圖。具體而言，第10A及10B圖顯示另一實施例的閘極堆疊物903、頂部間隔物301及底部間隔物601的一些部件，其中閘極堆疊物903的頂部臨界尺寸CDT 大於閘極堆疊物903的底部臨界尺寸CDB 。Turning to FIGS. 10A and 10B , these figures show enlarged views of the first portion 905 highlighted in FIG. 9A and the second portion 907 highlighted in FIG. 9B , respectively, according to some other embodiments. Specifically, FIGS. 10A and 10B show some components of gate stack 903 , top spacer 301 , and bottom spacer 601 in another embodiment, wherein gate stack 903 has a top critical dimension CD T greater than that of the gate stack. Bottom critical dimension CD B of object 903 .

根據一些實施例，頂部間隔物301包括第一介電材料(例如，SiN)的單層膜，且底部間隔物601包括第二介電材料的單層膜，且前述第二介電材料可以是前述關於第一介電材料的任何材料(例如，SiON)，且其中第一介電材料的第一蝕刻速率大於第二介電材料的第二蝕刻速率。在移除虛設閘極電極117及/或移除虛設閘極介電質115的製程期間中，頂部間隔物301的厚度減小到介於大約0.3 nm及大約49.8 nm之間的第三厚度Th3，且底部間隔物601的厚度不從其初始厚度(例如：第三距離Dist3)減小，或者底部間隔物601的厚度僅最小地減少。如此一來，閘極堆疊物903的頂部臨界尺寸CDT 大於閘極堆疊物903的底部臨界尺寸CDB 。根據一些實施例，頂部臨界尺寸CDT 可以在介於大約1.4 nm與1000 nm之間，且底部臨界尺寸CDB 可以在介於大約1 nm與大約1000 nm之間。然而而，可以使用任何合適的尺寸。此外，間隔物界面909的長度減小到第三厚度Th3，且底部間隔物601的頂部與頂部間隔物301及閘極堆疊物903之兩者接合(interface)。According to some embodiments, the top spacer 301 includes a single-layer film of a first dielectric material (eg, SiN), and the bottom spacer 601 includes a single-layer film of a second dielectric material, and the aforementioned second dielectric material may be Any of the foregoing with respect to the first dielectric material (eg, SiON), and wherein the first etch rate of the first dielectric material is greater than the second etch rate of the second dielectric material. During the process of removing the dummy gate electrode 117 and/or removing the dummy gate dielectric 115, the thickness of the top spacer 301 is reduced to a third thickness Th3 between about 0.3 nm and about 49.8 nm. , and the thickness of the bottom spacer 601 is not reduced from its initial thickness (for example: the third distance Dist3), or the thickness of the bottom spacer 601 is only minimally reduced. Thus, the top critical dimension CD T of the gate stack 903 is larger than the bottom critical dimension CD B of the gate stack 903 . According to some embodiments, the top CD T may be between about 1.4 nm and 1000 nm, and the bottom CD B may be between about 1 nm and about 1000 nm. However, any suitable size may be used. Furthermore, the length of the spacer interface 909 is reduced to a third thickness Th3, and the top of the bottom spacer 601 interfaces with both the top spacer 301 and the gate stack 903 .

繼續第11A及11B圖，根據又一其他實施例，這些圖分別顯示在第9A圖中突顯出的第一部分905及在第9B圖中突顯出的第二部分907的放大圖。具體而言，第11A及11B圖顯示又一實施例的閘極堆疊物903、頂部間隔物301及底部間隔物601的一些部件，其中閘極堆疊物903的底部臨界尺寸CDB 大於閘極堆疊物903的頂部臨界尺寸CDT 。Continuing with FIGS. 11A and 11B , these figures show enlarged views of the first portion 905 highlighted in FIG. 9A and the second portion 907 highlighted in FIG. 9B , respectively, according to yet other embodiments. Specifically, FIGS. 11A and 11B show some components of gate stack 903 , top spacer 301 , and bottom spacer 601 according to yet another embodiment, wherein gate stack 903 has a bottom critical dimension CD B that is larger than the gate stack. The top critical dimension CD T of object 903 .

根據一些實施例，頂部間隔物301包括第一介電材料(例如，SiOCN)的單層膜，且底部間隔物601包括第二介電材料(例如，SiC)的單膜，其中第二介電材料的第四蝕刻速率大於第一介電材料的第三蝕刻速率。在移除虛設閘極電極117及/或移除虛設閘極介電質115的製程期間中，底部間隔物601的厚度減小到介於大約0.3 nm及大約49.8 nm之間的第四厚度Th4，且頂部間隔物301的厚度不從其初始厚度(例如：第三距離Dist3)減小，或者頂部間隔物301的厚度僅最小地減少。如此一來，閘極堆疊物903的底部臨界尺寸CDB 大於閘極堆疊物903的頂部臨界尺寸CDT 。根據一些實施例，底部臨界尺寸CDB 可以在介於大約1.4 nm至1000 nm之間，且頂部臨界尺寸CDT 可以在介於大約1 nm與大約1000 nm之間。然而，可以使用任何合適的尺寸。此外，間隔物界面909的長度減小到第四厚度Th4，且頂部間隔物301的底部與底部間隔物601及閘極堆疊物903之兩者接合。According to some embodiments, the top spacer 301 comprises a single film of a first dielectric material (eg, SiOCN), and the bottom spacer 601 comprises a single film of a second dielectric material (eg, SiC), wherein the second dielectric material The fourth etch rate of the material is greater than the third etch rate of the first dielectric material. During the process of removing the dummy gate electrode 117 and/or removing the dummy gate dielectric 115, the thickness of the bottom spacer 601 is reduced to a fourth thickness Th4 between about 0.3 nm and about 49.8 nm. , and the thickness of the top spacer 301 does not decrease from its initial thickness (for example: the third distance Dist3), or the thickness of the top spacer 301 decreases only minimally. As a result, the bottom CD B of the gate stack 903 is larger than the top CD T of the gate stack 903 . According to some embodiments, the bottom CD B may be between about 1.4 nm and 1000 nm, and the top CD T may be between about 1 nm and about 1000 nm. However, any suitable size can be used. Furthermore, the length of the spacer interface 909 is reduced to a fourth thickness Th4, and the bottom of the top spacer 301 is bonded to both the bottom spacer 601 and the gate stack 903 .

，現在參照第12A及12B圖，根據一些其他實施例，這些圖式分別顯示在第9A圖中突顯出的第一部分905及在第9B圖中突顯出的第二部分907的放大圖。具體而言，第12A及12B圖顯示又一實施例的閘極堆疊物903、頂部間隔物301及底部間隔物601的一些部件，其中在蝕刻製程期間中(例如，參照第6A、6B、7A及7B圖)保留(retained)用於形成底部間隔物601的間隔物材料的一部分以與頂部間隔物301的外側壁及鰭片113的側壁相鄰。Referring now to Figures 12A and 12B, these figures show enlarged views of the first portion 905 highlighted in Figure 9A and the second portion 907 highlighted in Figure 9B, respectively, according to some other embodiments. Specifically, FIGS. 12A and 12B show some components of gate stack 903 , top spacer 301 , and bottom spacer 601 according to yet another embodiment, wherein during the etch process (see, for example, FIGS. 6A, 6B, and 7A 7B ) retains a portion of the spacer material used to form the bottom spacer 601 to be adjacent to the outer sidewalls of the top spacer 301 and the sidewalls of the fins 113 .

根據一些實施例，如關於第6A、6B、7A及7B圖所討論的是，底部間隔物601的材料可以從頂部間隔物301、基板101及隔離區域111的水平表面移除。然而，在這些圖式中沿著垂直表面形成的底部間隔物601的材料可以以較小的程度移除。如此一來，底部間隔物601的材料的剩餘部分可以沿著側壁從初始厚度減小，從第一厚度Th1(在第6A及6B圖中顯示)至第五厚度Th5。此外，底部間隔物601的材料可以在虛設閘極電極117的底部401的凹部中從第二厚度Th2(在第6A及6B圖中所顯示)減小到第六厚度Th6。根據一些實施例，第五厚度Th5可以在介於大約0.3 nm與大約50 nm之間，且第六厚度Th6可以在介於大約0.6 nm與大約100nm之間。然而，可以使用任何合適的厚度。According to some embodiments, material of the bottom spacer 601 may be removed from the horizontal surfaces of the top spacer 301 , substrate 101 , and isolation region 111 as discussed with respect to FIGS. 6A , 6B, 7A, and 7B. However, the material of the bottom spacers 601 formed along the vertical surfaces in these figures can be removed to a lesser extent. As such, the remainder of the material of the bottom spacer 601 may decrease from the initial thickness along the sidewalls, from a first thickness Th1 (shown in Figures 6A and 6B ) to a fifth thickness Th5. Furthermore, the material of the bottom spacer 601 may be reduced from the second thickness Th2 (shown in FIGS. 6A and 6B ) to a sixth thickness Th6 in the recess of the bottom 401 of the dummy gate electrode 117 . According to some embodiments, the fifth thickness Th5 may be between about 0.3 nm and about 50 nm, and the sixth thickness Th6 may be between about 0.6 nm and about 100 nm. However, any suitable thickness may be used.

第12A及12B圖進一步顯示的是，介於底部間隔物601及頂部間隔物301之間的間隔物界面909沿著頂部間隔物301的底表面及外側壁表面形成反向(backwards)「L形(L-shape)」。底部間隔物601亦可與鰭片113形成界面，前述界面沿著鰭片113的頂表面及外側壁形成為上下顛倒(upside down)的反向「L形」。Figures 12A and 12B further show that the spacer interface 909 between the bottom spacer 601 and the top spacer 301 forms a backwards "L" shape along the bottom surface and the outer sidewall surface of the top spacer 301. (L-shape)". The bottom spacer 601 can also form an interface with the fin 113 , and the aforementioned interface is formed in an upside down reverse "L shape" along the top surface and the outer sidewall of the fin 113 .

轉為參照第13A及13B圖，根據又一實施例，這些圖式分別顯示類似於第12A及12B圖的第一部分905及第二部分907的放大圖。具體而言，第13A及13B圖顯示又一實施例的閘極堆疊物903、頂部間隔物301及底部間隔物601的一些部件，其中頂部間隔物301包括多層膜。Turning to Figures 13A and 13B, these Figures show enlarged views of the first portion 905 and the second portion 907, respectively, similar to those of Figures 12A and 12B, according to yet another embodiment. Specifically, FIGS. 13A and 13B show some components of gate stack 903 , top spacer 301 , and bottom spacer 601 according to yet another embodiment, wherein top spacer 301 includes a multilayer film.

根據一些實施例，頂部間隔物301包括第一介電膜1301及第二介電膜1303。第一介電膜1301可以包括第一介電材料(例如，SiN)，且第二介電膜1303可以包括第二介電材料(例如，SiOCN)。根據一些實施例，可以使第一介電膜1301沉積到介於大約0.3 nm及大約50 nm之間的第七厚度Th7，且可以使第二介電膜1303沉積在第一介電膜1301之上。然而，可以使用任何合適的厚度。According to some embodiments, the top spacer 301 includes a first dielectric film 1301 and a second dielectric film 1303 . The first dielectric film 1301 may include a first dielectric material (eg, SiN), and the second dielectric film 1303 may include a second dielectric material (eg, SiOCN). According to some embodiments, the first dielectric film 1301 may be deposited to a seventh thickness Th7 between about 0.3 nm and about 50 nm, and the second dielectric film 1303 may be deposited on the first dielectric film 1301 superior. However, any suitable thickness may be used.

一旦已經沉積第二介電膜1303，則如以上關於第4A至4C圖所討論的是，可以藉由頂部間隔物301、第一虛設閘極材料119及鰭片113延伸開口201。如此一來，可以將第一介電膜1301形成為具有(with)間隔物界面909，第一介電膜1301可以背向(face away)閘極堆疊物903形成「L形」；且第二介電膜1303可以形成為「I形(I-shape)」。另外，可以使第二介電膜1303圖案化為具有在介於大約0.3 nm及大約50 nm之間的第八厚度Th8。然而，可以使用任何合適的厚度。Once the second dielectric film 1303 has been deposited, the opening 201 may be extended by the top spacer 301 , the first dummy gate material 119 and the fin 113 as discussed above with respect to FIGS. 4A-4C . In this way, the first dielectric film 1301 can be formed to have (with) the spacer interface 909, and the first dielectric film 1301 can form an "L shape" facing away from the gate stack 903; and the second The dielectric film 1303 may be formed in an "I-shape". In addition, the second dielectric film 1303 may be patterned to have an eighth thickness Th8 between about 0.3 nm and about 50 nm. However, any suitable thickness may be used.

轉為參照第14A及14B圖，根據又一實施例，這些圖式分別顯示類似於第13A及13B圖的第一部分905及第二部分907的放大圖。具體而言，第14A及14B圖顯示又一實施例的閘極堆疊物903、頂部間隔物301及底部間隔物601的一些部件，其中頂部間隔物301包括多個介電膜。Turning to Figures 14A and 14B, these Figures show enlarged views of the first portion 905 and the second portion 907, respectively, similar to those of Figures 13A and 13B, according to yet another embodiment. Specifically, FIGS. 14A and 14B show some components of gate stack 903 , top spacer 301 , and bottom spacer 601 according to yet another embodiment, wherein top spacer 301 includes a plurality of dielectric films.

根據一些實施例，頂部間隔物301包括第一介電膜1301、第二介電膜1303及第三介電膜1401。第三介電膜1401可以包括第一介電材料(例如，SiC)。如第3A及3B圖所示，可以使用上述用於形成頂部間隔物301的任何材料及製程使第三介電膜1401毯覆式沉積在第二介電膜1303之上。根據一些實施例，可以使第一介電膜1301沉積至介於大約0.3 nm至大約50 nm之間的第九厚度Th9，且可以使第二介電膜1303沉積至介於大約0.3 nm至大約50 nm之間的第十厚度Th10。According to some embodiments, the top spacer 301 includes a first dielectric film 1301 , a second dielectric film 1303 and a third dielectric film 1401 . The third dielectric film 1401 may include a first dielectric material (eg, SiC). As shown in FIGS. 3A and 3B , the third dielectric film 1401 may be blanket deposited on the second dielectric film 1303 using any of the materials and processes described above for forming the top spacer 301 . According to some embodiments, the first dielectric film 1301 may be deposited to a ninth thickness Th9 between about 0.3 nm and about 50 nm, and the second dielectric film 1303 may be deposited to a ninth thickness Th9 between about 0.3 nm and about 50 nm. Tenth thickness Th10 between 50 nm.

一旦已經沉積第三介電膜1401，則如以上關於第4A至4C圖所討論的是，可以藉由頂部間隔物301、第一虛設閘極材料119及鰭片113延伸開口201。如此一來，可以將第一介電膜1301形成為具有間隔物界面909。另外，第一介電膜1301及第二介電膜1303之兩者都可以形成為背向閘極堆疊物903的「L形」，且第三介電膜1401可以形成為「I形」。另外，一旦已經沉積第三介電膜1401並使第三介電膜1401圖案化，則第三介電膜1401可以具有在介於大約0.3 nm與大約50 nm之間的第十一厚度Th11。然而，可以使用任何合適的厚度。Once the third dielectric film 1401 has been deposited, openings 201 may be extended by top spacers 301 , first dummy gate material 119 and fins 113 as discussed above with respect to FIGS. 4A-4C . In this way, the first dielectric film 1301 can be formed to have the spacer interface 909 . In addition, both the first dielectric film 1301 and the second dielectric film 1303 may be formed in an "L shape" facing away from the gate stack 903, and the third dielectric film 1401 may be formed in an "I shape". In addition, once the third dielectric film 1401 has been deposited and patterned, the third dielectric film 1401 may have an eleventh thickness Th11 of between about 0.3 nm and about 50 nm. However, any suitable thickness may be used.

轉為參照第15A及15B圖，根據又一實施例，這些圖式分別顯示類似於第12A及12B圖的第一部分905及第二部分907的放大圖。具體而言，第15A及15B圖顯示又一實施例的閘極堆疊物903、頂部間隔物301及底部間隔物601的一些部件，其中用於形成底部間隔物601的間隔物材料的一部分包括多層，且保留前述間隔物材料的一部分以與頂部間隔物301的外側壁及鰭片113的側壁相鄰。Turning to Figures 15A and 15B, these Figures show enlarged views of the first portion 905 and the second portion 907, respectively, similar to those of Figures 12A and 12B, according to yet another embodiment. Specifically, Figures 15A and 15B show some components of gate stack 903, top spacer 301, and bottom spacer 601 in yet another embodiment, wherein a portion of the spacer material used to form bottom spacer 601 includes multiple layers , and retain a portion of the aforementioned spacer material to be adjacent to the outer sidewalls of the top spacer 301 and the sidewalls of the fins 113 .

根據一些實施例，底部間隔物601包括第一介電層1501及第二介電層1503。第一介電層1501可以包括第一介電材料(例如，SiON)，且第二介電層1503可以包括第二介電材料(例如，SiOC)。如第6A及6B圖所顯示，可以使用上述用於形成底部間隔物601的任何材料及製程，使第一介電層1501毯覆式沉積在結構之上，且可以使第二介電層1503毯覆式沉積在第一介電層1501之上。根據一些實施例，如上所述，可以使第一介電層1501沉積到第五厚度Th5。According to some embodiments, the bottom spacer 601 includes a first dielectric layer 1501 and a second dielectric layer 1503 . The first dielectric layer 1501 may include a first dielectric material (eg, SiON), and the second dielectric layer 1503 may include a second dielectric material (eg, SiOC). As shown in Figures 6A and 6B, any of the materials and processes described above for forming the bottom spacer 601 can be used to blanket deposit the first dielectric layer 1501 over the structure and the second dielectric layer 1503 Blanket deposition is over the first dielectric layer 1501 . According to some embodiments, as described above, the first dielectric layer 1501 may be deposited to a fifth thickness Th5.

一旦已經沉積第二介電層1503，可相對於第6A、6B、7A及7B圖所討論的是，可以從頂部間隔物301、基板101及隔離區域111的水平表面移除底部間隔物601的材料。然而，沿著結構的垂直表面形成的底部間隔物601的材料可以以較小的程度移除。第15A及15B圖進一步顯示的是，間隔物界面909在介於頂部間隔物301的底表面與外側壁表面及第一介電層1501之間形成反向「L形」。第一介電層1501亦可以與鰭片113形成界面，前述界面沿著鰭片113的頂表面及外側壁形成為上下顛倒的反向「L形」的形狀。此外，根據一些實施例，第二介電層1503將層間介電層901及源極/汲極區域801從第一介電層1501分離。最後，根據一些實施例，在圖案化之後，第二介電層1503可以具有介於大約0.3 nm與大約50 nm之間的第十二厚度Th12。然而，可以使用任何合適的厚度。Once the second dielectric layer 1503 has been deposited, as discussed with respect to FIGS. 6A, 6B, 7A, and 7B, the bottom spacers 601 can be removed from the horizontal surfaces of the top spacers 301, substrate 101, and isolation regions 111. Material. However, the material of the bottom spacers 601 formed along the vertical surfaces of the structure may be removed to a lesser extent. FIGS. 15A and 15B further show that the spacer interface 909 forms an inverted "L-shape" between the bottom and outer sidewall surfaces of the top spacer 301 and the first dielectric layer 1501 . The first dielectric layer 1501 can also form an interface with the fin 113 , and the aforementioned interface is formed in an upside-down reverse “L-shape” shape along the top surface and the outer sidewall of the fin 113 . Furthermore, according to some embodiments, the second dielectric layer 1503 separates the interlayer dielectric layer 901 and the source/drain regions 801 from the first dielectric layer 1501 . Finally, according to some embodiments, after patterning, the second dielectric layer 1503 may have a twelfth thickness Th12 of between about 0.3 nm and about 50 nm. However, any suitable thickness may be used.

繼續參照第16A及16B圖，根據又一實施例，這些圖式分別顯示類似於第15A及15B圖的第一部分905及第二部分907的放大圖。具體而言，第16A及16B圖顯示又一實施例的閘極堆疊物903、頂部間隔物301及底部間隔物601的一些部件，其中用於形成底部間隔物601的間隔物材料的一部分包括多層，且保留前述間隔物材料的一部分以與頂部間隔物301的外側壁及鰭片113的側壁相鄰。Continuing to refer to Figures 16A and 16B, these Figures show enlarged views of the first portion 905 and the second portion 907 similar to those of Figures 15A and 15B, respectively, according to yet another embodiment. Specifically, Figures 16A and 16B show some components of gate stack 903, top spacer 301, and bottom spacer 601 in yet another embodiment, wherein a portion of the spacer material used to form bottom spacer 601 includes multiple layers , and retain a portion of the aforementioned spacer material to be adjacent to the outer sidewalls of the top spacer 301 and the sidewalls of the fins 113 .

在一些實施例中，底部間隔物601包括第一介電層1501、第二介電層1503及第三介電層1601。如第6A及6B圖所示，可以使用上述用於形成底部間隔物601的任何材料及製程使第三介電層1601毯覆式沉積在第二介電層1503之上。根據一些實施例，可以使用第一介電材料(例如，SiO2 )來沉積第三介電層1601。In some embodiments, the bottom spacer 601 includes a first dielectric layer 1501 , a second dielectric layer 1503 and a third dielectric layer 1601 . As shown in FIGS. 6A and 6B , the third dielectric layer 1601 may be blanket deposited on the second dielectric layer 1503 using any of the materials and processes described above for forming the bottom spacer 601 . According to some embodiments, the third dielectric layer 1601 may be deposited using a first dielectric material (eg, SiO 2 ).

一旦已經沉積第三介電層1601，則如關於第6A、6B、7A及7B圖所討論的是，可以從頂部間隔物301、基板101及隔離區域111的水平表面移除底部間隔物601的材料。然而，沿著結構的垂直表面形成的底部間隔物601的材料可以以較小的程度移除。第16A及16B圖進一步顯示的是，間隔物界面909在介於頂部間隔物301的底表面與外側壁表面及第一介電層1501之間形成反向「L形」。第一介電層1501亦可以與鰭片113形成界面，前述界面沿著鰭片113的頂表面及外側壁形成為上下顛倒的反向「L形」的形狀。此外，根據一些實施例，第三介電層1601將層間介電層901及源極/汲極區域801從第二介電層1503分離。根據一些實施例，一旦圖案化，第三介電層1601可以具有在介於大約0.3 nm與大約50 nm之間的第十三厚度Th13。然而，可以使用任何合適的厚度。Once the third dielectric layer 1601 has been deposited, as discussed with respect to FIGS. 6A, 6B, 7A, and 7B, the bottom spacers 601 can be removed from the horizontal surfaces of the top spacers 301, substrate 101, and isolation regions 111. Material. However, the material of the bottom spacers 601 formed along the vertical surfaces of the structure may be removed to a lesser extent. FIGS. 16A and 16B further show that the spacer interface 909 forms an inverted "L-shape" between the bottom and outer sidewall surfaces of the top spacer 301 and the first dielectric layer 1501 . The first dielectric layer 1501 can also form an interface with the fin 113 , and the aforementioned interface is formed in an upside-down reverse “L-shape” shape along the top surface and the outer sidewall of the fin 113 . Furthermore, according to some embodiments, the third dielectric layer 1601 separates the interlayer dielectric layer 901 and the source/drain regions 801 from the second dielectric layer 1503 . According to some embodiments, once patterned, the third dielectric layer 1601 may have a thirteenth thickness Th13 of between about 0.3 nm and about 50 nm. However, any suitable thickness may be used.

上述先進的微影製程、方法及材料可用於許多應用，前述應用包括鰭式場效電晶體(FinFET)。舉例而言，可以使鰭片圖案化，以在介於部件之間產生相對緊密的間隔，這些間隔非常適合用於前述揭露內容。另外，可以根據以上揭露內容來製造用於形成FinFET的鰭片的間隔物，且前述間隔物也稱為心軸(mandrels)。The advanced lithography processes, methods and materials described above can be used in many applications including fin field effect transistors (FinFETs). For example, fins can be patterned to create relatively tight spacing between intervening features, which are well suited for use in the foregoing disclosure. In addition, the spacers used to form the fins of FinFETs can be fabricated according to the above disclosure, and the aforementioned spacers are also called mandrels.

另外，雖然已經描述了關於形成FinFET裝置的上述實施例，但是本文描述的材料及製程可以等效地應用於其他半導體裝置且完全包括在實施例的範圍內，前述其他半導體裝置諸如：括梯度通道(gradient-channel)裝置、多通道(multi-channel)裝置、其組合或其類似物。舉例而言，鰭片113的形成可以指向從組合(compound)材料層堆疊物(例如，漸變組合材料(gradient compound materials)、奈米片或其類似物)圖案化鰭片。如此一來，梯度通道裝置及/或多通道裝置(例如，奈米片FET(nanosheet FET，NSFET)、全繞式閘極FET(gate-all-around FET，GAAFET)或其類似物)也可以使用前述技術及製程來形成，且完全包括在實施例的範圍內。Additionally, while the above embodiments have been described with respect to forming FinFET devices, the materials and processes described herein are equally applicable to and are fully within the scope of other semiconductor devices, such as: (gradient-channel) devices, multi-channel (multi-channel) devices, combinations thereof, or the like. For example, the formation of the fins 113 may refer to patterning the fins from a stack of compound material layers (eg, gradient compound materials, nanosheets, or the like). In this way, gradient channel devices and/or multi-channel devices (eg, nanosheet FETs (nanosheet FETs, NSFETs), all-around gate FETs (gate-all-around FETs, GAAFETs) or the like) can also be Formed using the aforementioned techniques and processes, and are fully within the scope of the embodiments.

根據一些實施例，FinFET裝置可以形成有梯度通道。鰭片113可以由在基板101之上形成的梯度材料層形成為梯度通道。梯度材料層可以包括第一矽基梯度化合物(silicon-based gradient compound)(例如，SiGe( 低 Ge%) (SiGe(low Ge%) ))，且在梯度材料層中，相對於的矽的百分比濃度而言，前述第一矽基梯度化合物具有相對低的鍺的百分比濃度。可以使用前述技術來使鰭片113圖案化，且在介於鰭片113之間形成隔離區域111。一旦已經在介於鰭片113之間形成隔離區域111，就在鰭片113及隔離區域111之上形成複合(complex)虛設閘極材料層125。可以使用前述技術使鰭片113圖案化，且在鰭片113之上形成複合虛設閘極材料層125。根據一些實施例，複合虛設閘極材料層125的第一虛設閘極材料119包括第二矽基梯度化合物，前述第二矽基梯度化合物的蝕刻速率大於鰭片113的蝕刻速率。在一些實施例中，第二矽基梯度化合物包括相對於的矽的百分比濃度而言，具有相對高的鍺的百分比濃度的材料(例如，SiGe( 高 Ge%) (SiGe(high Ge%) ))。在一些實施例中，複合虛設閘極材料層125的第二虛設閘極材料121包括另一矽基材料(例如，Si)，且先圖案化至虛設閘極電極117的頂部203中，然後由頂部間隔物301保護。如此一來，前述用於延伸開口201以使虛設閘極電極117的底部401圖案化並蝕刻穿過(etch through)鰭片113的技術可以等效地應用於這些實施例。利用介於第一虛設閘極材料119及鰭片113的材料之間的蝕刻速率的差異，在使虛設閘極電極117圖案化及蝕刻穿過鰭片113期間中，防止鰭片113的頂部受到損壞。According to some embodiments, FinFET devices may be formed with gradient channels. The fins 113 may be formed as gradient channels from a gradient material layer formed over the substrate 101 . The gradient material layer may include a first silicon-based gradient compound (for example, SiGe ( low Ge%) (SiGe (low Ge%) )), and in the gradient material layer, relative to the percentage of silicon In terms of concentration, the aforementioned first silicon-based gradient compound has a relatively low percentage concentration of germanium. The aforementioned techniques may be used to pattern the fins 113 and form isolation regions 111 between the fins 113 . Once the isolation regions 111 have been formed between the fins 113 , a complex dummy gate material layer 125 is formed over the fins 113 and the isolation regions 111 . The fins 113 may be patterned using the techniques previously described, and a layer of composite dummy gate material 125 formed over the fins 113 . According to some embodiments, the first dummy gate material 119 of the composite dummy gate material layer 125 includes a second silicon-based gradient compound, and the etching rate of the second silicon-based gradient compound is greater than the etching rate of the fin 113 . In some embodiments, the second silicon-based gradient compound includes a material having a relatively high percentage concentration of germanium relative to the percentage concentration of silicon (e.g., SiGe ( high Ge%) (SiGe (high Ge%) ) ). In some embodiments, the second dummy gate material 121 of the composite dummy gate material layer 125 includes another silicon-based material (eg, Si) and is first patterned into the top 203 of the dummy gate electrode 117 and then formed by Top spacer 301 protection. As such, the aforementioned techniques for extending the opening 201 to pattern the bottom 401 of the dummy gate electrode 117 and etch through the fin 113 are equally applicable to these embodiments. Utilizing the difference in etch rate between the first dummy gate material 119 and the material of the fin 113 protects the top of the fin 113 from damage during patterning of the dummy gate electrode 117 and etching through the fin 113. damage.

在又一實施例中，多通道FET裝置(例如，奈米片FET(NSFET)、全繞閘極FET(GAAFET)或其類似物)由形成在基板101之上的半導體材料的多層堆疊物來形成。根據一些實施例，多層堆疊物包括第一奈米片材料層(例如，SiGe)及第二奈米片材料層(例如，Si)的交錯奈米片(alternating nanosheets)。第一奈米片材料層也可以稱為犧牲通道層。初始使用上述的圖案化技術使鰭片113形成為多層堆疊物。一旦已經使鰭片113圖案化，就在介於鰭片113之間形成隔離區域111，且在鰭片113及隔離區域111之上形成複合虛設閘極材料層125。複合虛設閘極材料層125包括第一虛設閘極材料119及第二虛設閘極材料121。根據一些實施例，第一虛設閘極材料119包括第一矽基材料(例如，SiGe)，且第二虛設閘極材料121包括第二矽基材料(例如，Si)。一旦已經形成複合虛設閘極材料層125，就使用上述技術使虛設閘極電極117的頂部203圖案化為第二虛設閘極材料121，然後由頂部間隔物301來保護。上述的用於延伸開口201以使虛設閘極電極117的底部401圖案化並蝕刻穿過鰭片113的技術可以等效地應用於這些實施例。根據一些實施例，前述用於使第一虛設閘極材料119凹入的蝕刻拉回技術也可以應用於這些實施例，且可以進一步用於使第一奈米片材料層(例如，SiGe)在通道區域內凹入。一旦凹入，沉積以形成底部間隔物601的材料也可以用於在第二奈米片材料層的凹部中形成內間隔物(inner spacers)。一旦開口201已經延伸穿過鰭片113，就可以在開口201中形成源極/汲極區域801。根據一些實施例，選擇第一虛設閘極材料119(例如，SiGe)為用於鰭片113的犧牲通道層(例如，SiGe)相同的材料，且犧牲通道層(例如，SiGe)的蝕刻速率大於第二奈米片材料層(例如，Si)的蝕刻速率。如此一來，在用於移除虛設閘極電極117的第一虛設閘極材料119的製程中，移除在鰭片113的通道區域中的第一奈米片材料層(例如，SiGe)(例如，藉由奈米線釋放(wire-release)技術)。第二奈米片材料層(例如，Si)的剩餘材料形成在通道區域內的被內間隔物分離的奈米結構。一旦已經形成奈米結構，就可以在通道區域內圍繞奈米結構形成閘極介電質及閘極電極。In yet another embodiment, a multi-channel FET device (e.g., a nanosheet FET (NSFET), an all-around gate FET (GAAFET), or the like) is formed from a multilayer stack of semiconductor materials formed on a substrate 101. form. According to some embodiments, the multilayer stack includes alternating nanosheets of a first layer of nanosheet material (eg, SiGe) and a second layer of nanosheet material (eg, Si). The first nanosheet material layer may also be referred to as a sacrificial channel layer. Fins 113 are initially formed as a multilayer stack using the patterning techniques described above. Once the fins 113 have been patterned, isolation regions 111 are formed between the fins 113 and a composite dummy gate material layer 125 is formed over the fins 113 and isolation regions 111 . The composite dummy gate material layer 125 includes a first dummy gate material 119 and a second dummy gate material 121 . According to some embodiments, the first dummy gate material 119 includes a first silicon-based material (eg, SiGe), and the second dummy gate material 121 includes a second silicon-based material (eg, Si). Once the composite dummy gate material layer 125 has been formed, the top 203 of the dummy gate electrode 117 is patterned into a second dummy gate material 121 using the techniques described above and then protected by the top spacer 301 . The techniques described above for extending the opening 201 to pattern the bottom 401 of the dummy gate electrode 117 and etch through the fin 113 are equally applicable to these embodiments. According to some embodiments, the aforementioned etch pull-back technique for recessing the first dummy gate material 119 can also be applied to these embodiments, and can be further used to make the first nanosheet material layer (eg, SiGe) in the Recessed in channel area. Once recessed, the material deposited to form the bottom spacers 601 may also be used to form inner spacers in the recesses of the second nanosheet material layer. Once opening 201 has been extended through fin 113 , source/drain region 801 may be formed in opening 201 . According to some embodiments, the first dummy gate material 119 (eg, SiGe) is selected to be the same material used for the sacrificial channel layer (eg, SiGe) of the fin 113, and the etching rate of the sacrificial channel layer (eg, SiGe) is greater than The etch rate of the second nanosheet material layer (eg, Si). Thus, in the process for removing the first dummy gate material 119 of the dummy gate electrode 117, the first nanosheet material layer (eg, SiGe) in the channel region of the fin 113 is removed ( For example, by nanowire release (wire-release) technology). The remaining material of the second nanosheet material layer (eg, Si) forms nanostructures separated by inner spacers within the channel region. Once the nanostructures have been formed, a gate dielectric and gate electrode can be formed around the nanostructures in the channel region.

本文揭露半導體裝置及形成諸如FinFET、NSFET及GAA裝置的此些裝置的方法的實施例。所揭露的實施例的一些部件提供包括大的裝置生產良率的益處，並且如下實現裝置性能。Embodiments of semiconductor devices and methods of forming such devices, such as FinFET, NSFET and GAA devices, are disclosed herein. Some features of the disclosed embodiments provide benefits including large device production yield, and device performance is achieved as follows.

本文揭露的方法及裝置提供以下一或多個優點及益處。在複合虛設閘極材料層125上使用的兩步驟(two-step)蝕刻製程允許形成虛設閘極電極117，且前述虛設閘極電極117具有包括第一材料的頂部203及包括第二材料的底部401。在對虛設閘極電極117的底部401進行圖案化的期間中，頂部間隔物301形成在虛設閘極電極117的頂部203之上並保護虛設閘極電極117的頂部203。此外，在相同的蝕刻步驟中，使虛設閘極電極117的底部及用於源極/汲極區域801的開口圖案化。如此一來，在形成虛設閘極電極117的底部401以及在源極/汲極區域801中形成開口的製程期間中，鰭片113的頂部受到保護，這最小化或完全消除通道頂部(channel-top)的損傷、虛設閘極殘留物缺陷(dummy gate residue defects)以及通道-通道之間空間的限制(channel-channel space restrictions)。一旦形成，底部間隔物601與鰭片113的頂部形成第一界面，且與閘極堆疊物903形成第二界面，介於第一界面及第二界面之間的角度為大約90°。此外，可以藉由頂部間隔物301及/或底部間隔物601的成形(shaping)，在很大程度上控制金屬閘極電極的臨界尺寸。這些部件在具有高裝置性能的半導體裝置的製造期間中提供高良率。The methods and devices disclosed herein provide one or more of the following advantages and benefits. The use of a two-step etch process on the composite dummy gate material layer 125 allows the formation of a dummy gate electrode 117 having a top 203 comprising a first material and a bottom comprising a second material 401. During patterning the bottom 401 of the dummy gate electrode 117 , the top spacer 301 is formed over and protects the top 203 of the dummy gate electrode 117 . Furthermore, in the same etching step, the bottom of the dummy gate electrode 117 and the opening for the source/drain region 801 are patterned. In this way, the top of the fin 113 is protected during the process of forming the bottom 401 of the dummy gate electrode 117 and forming the opening in the source/drain region 801, which minimizes or completely eliminates the channel-top (channel- top), dummy gate residue defects, and channel-channel space restrictions. Once formed, the bottom spacer 601 forms a first interface with the top of the fin 113 and a second interface with the gate stack 903, the angle between the first interface and the second interface being approximately 90°. Furthermore, the CD of the metal gate electrode can be largely controlled by the shaping of the top spacer 301 and/or the bottom spacer 601 . These components provide high yields during the manufacture of semiconductor devices with high device performance.

根據一些實施例，方法包括：形成鰭片於半導體基板之上。沉積虛設閘極材料層於鰭片之上。對虛設閘極材料層圖案化來形成虛設閘極電極的頂部。沿著虛設閘極電極的頂部的側壁形成頂部間隔物。蝕刻穿過虛設閘極材料層且穿過鰭片的開口，以形成虛設閘極電極的底部。沿著開口的側壁形成底部間隔物。形成源極/汲極區域在開口中。移除虛設閘極電極。沉積閘極堆疊物於鰭片之上。在一實施例中，前述方法包括沉積第一虛設閘極材料於鰭片之上，以及沉積第二虛設閘極材料於第一虛設閘極材料之上，第二虛設閘極材料不同於第一虛設閘極材料。在一實施例中，第二虛設閘極材料具有不同於第一虛設閘極材料的蝕刻選擇比。在前述方法的一實施例中，第一虛設閘極材料具有第一蝕刻選擇比，且鰭片具有第二蝕刻選擇比，第一蝕刻選擇比不同於第二蝕刻選擇比。在一實施例中，形成頂部間隔物包括沉積多層膜。在一實施例中，前述方法進一步包括在形成底部間隔物之前，使虛設閘極電極的底部凹入(recessing)。在前述方法的一實施例中，形成底部間隔物以藉由第二間隔物材料來填充藉由使底部凹入而留下的間隔。在一實施例中，前述方法進一步包括使頂部間隔物相較於底部間隔物更加凹入。在一實施例中，前述方法進一步包括使底部間隔物相較於頂部間隔物更加凹入。According to some embodiments, a method includes: forming a fin on a semiconductor substrate. A layer of dummy gate material is deposited over the fins. The dummy gate material layer is patterned to form the top of the dummy gate electrode. A top spacer is formed along the sidewall of the top of the dummy gate electrode. Etching through the layer of dummy gate material and through the opening of the fin forms the bottom of the dummy gate electrode. A bottom spacer is formed along sidewalls of the opening. Source/drain regions are formed in the openings. Remove the dummy gate electrodes. A gate stack is deposited over the fins. In one embodiment, the aforementioned method includes depositing a first dummy gate material on the fin, and depositing a second dummy gate material on the first dummy gate material, the second dummy gate material being different from the first dummy gate material. dummy gate material. In one embodiment, the second dummy gate material has a different etch selectivity than the first dummy gate material. In an embodiment of the foregoing method, the first dummy gate material has a first etch selectivity, and the fin has a second etch selectivity, the first etch selectivity being different from the second etch selectivity. In one embodiment, forming the top spacer includes depositing a multi-layer film. In one embodiment, the aforementioned method further includes recessing the bottom of the dummy gate electrode prior to forming the bottom spacer. In an embodiment of the foregoing method, the bottom spacer is formed to fill the space left by recessing the bottom with the second spacer material. In one embodiment, the aforementioned method further includes making the top spacer more concave than the bottom spacer. In one embodiment, the aforementioned method further includes making the bottom spacer more concave than the top spacer.

根據一些實施例，方法包括：形成鰭片於半導體基板之上。沉積虛設閘極材料層於鰭片之上。蝕刻虛設閘極材料層至第一深度。在蝕刻虛設閘極材料層之後，沉積第一間隔物於虛設閘極材料層之上。在沉積第一間隔物之後，蝕刻穿過虛設閘極材料層的開口，以形成虛設閘極電極。沉積第二間隔物於第一間隔物之上且沿著開口的側壁。形成源極/汲極區域於開口中，第二間隔物使虛設閘極電極與源極/汲極區域分離(separating)。移除虛設閘極電極。沉積閘極堆疊物於鰭片之上。在前述方法的一實施例中，蝕刻開口進一步包括形成第一凹部在介於鰭片及第一間隔物之間的虛設閘極電極的側壁中；以及沉積第二間隔物進一步包括以第二間隔物填充第一凹部。在前述方法的一實施例中，移除虛設閘極電極進一步包括使第二間隔物凹入第一距離。在前述方法的一實施例中，移除虛設閘極電極進一步包括使第一間隔物凹入第二距離，且第二距離小於第一距離。在前述方法的一實施例中，移除虛設閘極電極進一步包括使第一間隔物凹入第二距離，且第二距離大於第一距離。在前述方法的一實施例中，沉積第一間隔物包括沉積介電膜的多層。在前述方法的一實施例中，沉積第二間隔物包括沉積介電膜的多層。According to some embodiments, a method includes: forming a fin on a semiconductor substrate. A layer of dummy gate material is deposited over the fins. The layer of dummy gate material is etched to a first depth. After etching the dummy gate material layer, a first spacer is deposited on the dummy gate material layer. After depositing the first spacers, openings are etched through the layer of dummy gate material to form dummy gate electrodes. A second spacer is deposited over the first spacer and along sidewalls of the opening. A source/drain region is formed in the opening, and a second spacer separates the dummy gate electrode from the source/drain region. Remove the dummy gate electrodes. A gate stack is deposited over the fins. In an embodiment of the foregoing method, etching the opening further includes forming a first recess in a sidewall of the dummy gate electrode between the fin and the first spacer; and depositing the second spacer further includes forming the second spacer material to fill the first recess. In an embodiment of the foregoing method, removing the dummy gate electrode further includes recessing the second spacer by the first distance. In an embodiment of the foregoing method, removing the dummy gate electrode further includes recessing the first spacer by a second distance, and the second distance is less than the first distance. In an embodiment of the aforementioned method, removing the dummy gate electrode further includes recessing the first spacer by a second distance, and the second distance is greater than the first distance. In an embodiment of the foregoing method, depositing the first spacer includes depositing multiple layers of a dielectric film. In an embodiment of the foregoing method, depositing the second spacer includes depositing multiple layers of a dielectric film.

根據一些實施例，半導體裝置包括：鰭片、閘極電極堆疊物、第一頂部間隔物、第一底部間隔物以及第一源極/汲極區域。鰭片位於基板之上。閘極電極堆疊物位於鰭片之上。第一頂部間隔物相鄰於閘極電極堆疊物。閘極電極堆疊物具有相鄰於第一頂部間隔物的第一寬度。第一底部間隔物位於第一頂部間隔物之下。閘極電極堆疊物具有相鄰於第一底部間隔物的第二寬度。第二寬度不同於第一寬度。第一源極/汲極區域相鄰於鰭片且藉由第一底部間隔物與閘極電極堆疊物獨立(isolated)。在半導體裝置的一實施例中，第一頂部間隔物包括具有L形(L-shape)形狀的多層膜。在半導體裝置的一實施例中，第一底部間隔物包括具有倒L形(backwards L-shape)形狀的多層膜。在半導體裝置的一實施例中，第一寬度大於第二寬度。在半導體裝置的一實施例中，第一寬度小於第二寬度。在半導體裝置的一實施例中，第一頂部間隔物包括第一材料，且第二底部間隔物包括不同於第一材料的第二材料。According to some embodiments, a semiconductor device includes: a fin, a gate electrode stack, a first top spacer, a first bottom spacer, and a first source/drain region. The fins are on the substrate. A gate electrode stack is over the fin. The first top spacer is adjacent to the gate electrode stack. The gate electrode stack has a first width adjacent to the first top spacer. The first bottom spacer is located below the first top spacer. The gate electrode stack has a second width adjacent to the first bottom spacer. The second width is different from the first width. A first source/drain region is adjacent to the fin and is isolated from the gate electrode stack by a first bottom spacer. In an embodiment of the semiconductor device, the first top spacer includes a multilayer film having an L-shape. In an embodiment of the semiconductor device, the first bottom spacer includes a multilayer film having a backwards L-shape. In an embodiment of the semiconductor device, the first width is greater than the second width. In an embodiment of the semiconductor device, the first width is smaller than the second width. In an embodiment of the semiconductor device, the first top spacer includes a first material, and the second bottom spacer includes a second material different from the first material.

前述內文概述了各種實施例的部件，使所屬技術領域中具有通常知識者可以從各個方面更佳地了解本揭露。所屬技術領域中具有通常知識者應可理解的是，他們可輕易地以本揭露為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在本文中介紹的各種實施例相同之優點。所屬技術領域中具有通常知識者也應理解的是，這些等效的構型並未背離本揭露的發明精神與範圍，且在不背離本揭露的發明精神與範圍之前提下，可對本揭露進行各種改變、置換或修改。The foregoing text summarizes components of various embodiments, so that those skilled in the art can better understand the present disclosure from various aspects. It should be understood by those skilled in the art that they can easily design or modify other processes and structures based on the present disclosure, so as to achieve the same purpose and/or achieve the various Embodiments have the same advantages. It should also be understood by those skilled in the art that these equivalent configurations do not depart from the inventive spirit and scope of the present disclosure, and that the present disclosure can be modified without departing from the inventive spirit and scope of the present disclosure. various changes, substitutions or modifications.

100:半導體裝置 101:基板 111:隔離區域 113:鰭片 115:虛設閘極介電質 117:虛設閘極電極 119:第一虛設閘極材料 121:第二虛設閘極材料 123:閘極遮罩 125:複合虛設閘極材料層 201:開口 203:頂部 301:頂部間隔物 401:底部 601:底部間隔物 801:源極/汲極區域 901:層間介電層 903:閘極堆疊物 905:第一部分 907:第二部分 909:間隔物界面 1301:第一介電膜 1303:第二介電膜 1401:第三介電膜 1501:第一介電層 1503:第二介電層 1601:第三介電層 CDT :頂部臨界尺寸 CDB :底部臨界尺寸 D1:第一深度 D2:第二深度 D3:第三深度 Dist1:第一距離 Dist2:第二距離 Dist3:第三距離 H1:第一高度 H2:第二高度 Th1:第一厚度 Th2:第二厚度 Th3:第三厚度 Th4:第四厚度 Th5:第五厚度 Th6:第六厚度 Th7:第七厚度 Th8:第八厚度 Th9:第九厚度 Th10:第十厚度 Th11:第十一厚度 Th12:第十二厚度 Th13:第十三厚度 W1:第一寬度 W2:第二寬度 W3:第三寬度 θ’:第一角度100: semiconductor device 101: substrate 111: isolation region 113: fin 115: dummy gate dielectric 117: dummy gate electrode 119: first dummy gate material 121: second dummy gate material 123: gate shield Cap 125: composite dummy gate material layer 201: opening 203: top 301: top spacer 401: bottom 601: bottom spacer 801: source/drain region 901: interlayer dielectric layer 903: gate stack 905: First part 907: second part 909: spacer interface 1301: first dielectric film 1303: second dielectric film 1401: third dielectric film 1501: first dielectric layer 1503: second dielectric layer 1601: first Three dielectric layers CD T : top critical dimension CD B : bottom critical dimension D1: first depth D2: second depth D3: third depth Dist1: first distance Dist2: second distance Dist3: third distance H1: first Height H2: second height Th1: first thickness Th2: second thickness Th3: third thickness Th4: fourth thickness Th5: fifth thickness Th6: sixth thickness Th7: seventh thickness Th8: eighth thickness Th9: ninth Thickness Th10: Tenth Thickness Th11: Eleventh Thickness Th12: Twelfth Thickness Th13: Thirteenth Thickness W1: First Width W2: Second Width W3: Third Width θ': First Angle

根據以下的詳細說明並配合所附圖式閱讀，能夠最好的理解本揭露的所有態樣。應注意的是，根據本產業的標準作業，各種部件並未必按照比例繪製。事實上，可能任意的放大或縮小各種部件的尺寸，以做清楚的說明。 第1A圖是根據一些實施例，描繪半導體裝置的透視圖； 第1B、1C、2A、2B、3A及3B圖是根據一些實施例，描繪在形成半導體裝置的中間步驟中，形成在基板中的鰭片、形成在介於鰭片之間的隔離區域以及形成在鰭片之上的虛設閘極電極的剖面圖。 第4A至4C圖是根據一些實施例，描繪形成穿過虛設閘極材料的剩餘部分且穿過鰭片的開口。 第5A至5C圖是根據一些實施例，描繪執行蝕刻拉回(pull-back)製程以使虛設閘極電極的底部凹入。 第6A、6B、7A、7B、8A、8B、8C及8D圖是根據一些實施例，描繪在虛設閘極電極的凹部中形成底部間隔物以及在穿過鰭片的開口中形成源極/汲極區域。 第9A至9E圖是根據一些實施例，描繪移除虛設閘極電極以及形成取代虛設閘極電極的閘極電極堆疊物。 第10A、10B、11A及11B圖是根據一些其他實施例，描繪使頂部間隔物凹入及/或使底部間隔物凹入，且進一步描繪形成閘極電極堆疊物。 第12A、12B、13A、13B、14A、14B、15A、15B、16A及16B圖是根據又一些其他實施例，描繪頂部間隔物及底部間隔物。All aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with the standard practice in the industry, various features have not necessarily been drawn to scale. In fact, the dimensions of the various features may be arbitrarily expanded or reduced for clarity of illustration. FIG. 1A is a perspective view depicting a semiconductor device, according to some embodiments; Figures 1B, 1C, 2A, 2B, 3A, and 3B depict fins formed in a substrate, isolation regions formed between the fins, and formation of fins in intermediate steps of forming a semiconductor device, according to some embodiments. Cross-sectional view of a dummy gate electrode above a fin. Figures 4A-4C depict openings formed through the remainder of the dummy gate material and through the fins, according to some embodiments. Figures 5A-5C depict performing an etch pull-back process to recess the bottom of the dummy gate electrode, according to some embodiments. Figures 6A, 6B, 7A, 7B, 8A, 8B, 8C, and 8D depict formation of bottom spacers in recesses of dummy gate electrodes and source/drain formations in through-fin openings, according to some embodiments. polar region. 9A-9E depict removal of dummy gate electrodes and formation of gate electrode stacks replacing the dummy gate electrodes, according to some embodiments. Figures 10A, 10B, 11A, and 11B depict recessing the top spacers and/or recessing the bottom spacers, and further depict forming gate electrode stacks, according to some other embodiments. Figures 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A, and 16B depict top spacers and bottom spacers, according to yet other embodiments.

113:鰭片 113: fins

301:頂部間隔物 301: top spacer

601:底部間隔物 601: Bottom spacer

801:源極/汲極區域 801: source/drain region

901:層間介電層 901: interlayer dielectric layer

903:閘極堆疊物 903:Gate stack

905:第一部分 905: Part I

CDT:頂部臨界尺寸 CD T : top critical dimension

CDB:底部臨界尺寸 CD B : bottom critical dimension

W3:第三寬度 W3: third width

Claims (9)

一種半導體裝置的形成方法，其包括：形成一鰭片於一半導體基板之上；沉積一虛設閘極材料層於該鰭片之上；藉由使該虛設閘極材料層圖案化，來形成一虛設閘極電極的一頂部；沿著該虛設閘極電極的該頂部的側壁形成一頂部間隔物；藉由蝕刻穿過該虛設閘極材料層且穿過該鰭片的一開口，形成該虛設閘極電極的一底部；沿著該開口的側壁形成一底部間隔物；形成一源極/汲極區域在該開口中；移除該虛設閘極電極；以及沉積一閘極堆疊物於該鰭片之上。 A method for forming a semiconductor device, comprising: forming a fin on a semiconductor substrate; depositing a dummy gate material layer on the fin; and forming a dummy gate material layer by patterning the dummy gate material layer. a top of the dummy gate electrode; forming a top spacer along sidewalls of the top of the dummy gate electrode; forming the dummy by etching an opening through the dummy gate material layer and through the fin forming a bottom spacer along sidewalls of the opening; forming a source/drain region in the opening; removing the dummy gate electrode; and depositing a gate stack on the fin on top of the slice. 如請求項1所述的形成方法，其中沉積該虛設閘極材料層包括沉積一第一虛設閘極材料於該鰭片之上，以及沉積一第二虛設閘極材料於該第一虛設閘極材料之上，該第二虛設閘極材料具有不同於該第一虛設閘極材料的蝕刻選擇比。 The forming method according to claim 1, wherein depositing the dummy gate material layer comprises depositing a first dummy gate material on the fin, and depositing a second dummy gate material on the first dummy gate material, the second dummy gate material has a different etch selectivity than the first dummy gate material. 如請求項1所述的形成方法，其進一步包括在形成該底部間隔物之前，使該虛設閘極電極的該底部凹入(recessing)。 The forming method of claim 1, further comprising recessing the bottom of the dummy gate electrode before forming the bottom spacer. 如請求項3所述的形成方法，其中形成該底部間隔物以藉由一第二間隔物材料來填充一間隔(space)，前述間隔是藉由使該底部凹入而留下。 The forming method of claim 3, wherein the bottom spacer is formed to fill a space left by recessing the bottom with a second spacer material. 如請求項4所述的形成方法，其中移除該虛設閘極電極進一步包括使該頂部間隔物相較於該底部間隔物更加凹入，或者使該底部間隔物相較於 該頂部間隔物更加凹入。 The forming method according to claim 4, wherein removing the dummy gate electrode further comprises making the top spacer more concave than the bottom spacer, or making the bottom spacer more concave than the bottom spacer The top spacer is more concave. 一種半導體裝置的形成方法，其包括：形成一鰭片於一半導體基板之上；沉積一虛設閘極材料層於該鰭片之上；蝕刻該虛設閘極材料層至一第一深度；在蝕刻該虛設閘極材料層之後，沉積一第一間隔物於該虛設閘極材料層之上；在沉積該第一間隔物之後，蝕刻穿過該虛設閘極材料層的一開口，以形成一虛設閘極電極；沉積一第二間隔物於該第一間隔物之上且沿著該開口的側壁；形成一源極/汲極區域於該開口中，該第二間隔物使該虛設閘極電極與該源極/汲極區域分離(separating)；移除該虛設閘極電極；以及沉積一閘極堆疊物於該鰭片之上。 A method for forming a semiconductor device, comprising: forming a fin on a semiconductor substrate; depositing a dummy gate material layer on the fin; etching the dummy gate material layer to a first depth; After the dummy gate material layer, a first spacer is deposited on the dummy gate material layer; after depositing the first spacer, an opening through the dummy gate material layer is etched to form a dummy gate electrode; depositing a second spacer on the first spacer and along the sidewall of the opening; forming a source/drain region in the opening, the second spacer enabling the dummy gate electrode separating from the source/drain region; removing the dummy gate electrode; and depositing a gate stack over the fin. 如請求項6所述的形成方法，其中：蝕刻該開口進一步包括形成一第一凹部在介於該鰭片及該第一間隔物之間的該虛設閘極電極的側壁中；以及沉積該第二間隔物進一步包括以第二間隔物填充該第一凹部。 The forming method according to claim 6, wherein: etching the opening further comprises forming a first recess in the sidewall of the dummy gate electrode between the fin and the first spacer; and depositing the first The second spacer further includes filling the first recess with a second spacer. 一種半導體裝置，其包括：一鰭片，位於一基板之上；一閘極電極堆疊物，位於該鰭片之上；一第一頂部間隔物，相鄰於該閘極電極堆疊物； 一第一底部間隔物，位於該第一頂部間隔物之下；以及一第一源極/汲極區域，相鄰於該鰭片且藉由該第一底部間隔物與該閘極電極堆疊物獨立(isolated)，其中該閘極電極堆疊物具有一第一寬度及一第二寬度，該第一寬度相鄰於該第一頂部間隔物，該第二寬度相鄰於該第一底部間隔物，且該第一寬度大於或小於該第二寬度。 A semiconductor device comprising: a fin on a substrate; a gate electrode stack on the fin; a first top spacer adjacent to the gate electrode stack; a first bottom spacer under the first top spacer; and a first source/drain region adjacent to the fin by the first bottom spacer and the gate electrode stack isolated, wherein the gate electrode stack has a first width and a second width, the first width is adjacent to the first top spacer, and the second width is adjacent to the first bottom spacer , and the first width is larger or smaller than the second width. 如請求項8所述的半導體裝置，其中該第一頂部間隔物包括具有L形(L-shape)形狀的一多層膜，且該第一底部間隔物包括具有反向L形(backwards L-shape)形狀的一多層膜。 The semiconductor device as claimed in claim 8, wherein the first top spacer comprises a multilayer film having an L-shape, and the first bottom spacer comprises a film having a backwards L-shape. shape) shape of a multilayer film.
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