TWI785371B - Electronic packaging and manufacturing method thereof - Google Patents

Electronic packaging and manufacturing method thereof Download PDF

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Publication number
TWI785371B
TWI785371B TW109128936A TW109128936A TWI785371B TW I785371 B TWI785371 B TW I785371B TW 109128936 A TW109128936 A TW 109128936A TW 109128936 A TW109128936 A TW 109128936A TW I785371 B TWI785371 B TW I785371B
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electronic component
electronic
package
layer
manufacturing
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TW109128936A
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Chinese (zh)
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TW202209507A (en
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董正彪
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矽品精密工業股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Containers And Plastic Fillers For Packaging (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

This invention provides an electronic package which arranges an electronic component on a carrying structure, and then forms an encapsulation layer on a part of a surface of the carrying structure to cover the electronic component, so as to regulate a stress distribution of the carrying structure and avoid a problem of cracking of the electronic component due to stress concentration.

Description

電子封裝件及其製法 Electronic package and its manufacturing method

本發明係有關一種半導體裝置，尤指一種可提升產品可靠度之電子封裝件及其製法。 The present invention relates to a semiconductor device, especially an electronic package that can improve product reliability and its manufacturing method.

隨著科技的演進，電子產品需求趨勢朝向異質整合邁進，為此，多晶片封裝模組(multi-chip module,MCM)/(multi-chip package,MCP)逐漸興起。 With the evolution of technology, the demand trend of electronic products is moving towards heterogeneous integration. For this reason, multi-chip module (multi-chip module, MCM) / (multi-chip package, MCP) is gradually emerging.

如圖1所示之封裝結構1，係將複數半導體晶片11藉由複數銲錫凸塊13結合至一封裝基板10上，再形成包覆該複數半導體晶片11之封裝層14。俾藉由將多顆半導體晶片封裝成單一結構的特性，使其具有較多的I/O數，且可以大幅增加處理器的運算能力，減少訊號傳遞的延遲時間，以應用於高密度線路/高傳輸速度/高疊層數/大尺寸設計之高階產品。 The package structure 1 shown in FIG. 1 is to combine a plurality of semiconductor chips 11 onto a package substrate 10 via a plurality of solder bumps 13 , and then form a package layer 14 covering the plurality of semiconductor chips 11 . By packaging multiple semiconductor chips into a single structure, it has a large number of I/Os, and can greatly increase the computing power of the processor and reduce the delay time of signal transmission, so it can be applied to high-density circuits/ High-end products with high transmission speed/high stack count/large size design.

惟，習知封裝結構1於封裝過程中，該封裝基板10係為整版面(即量產尺寸)，其於溫度循環(temperature cycle)或應力變化時，如通過回銲爐、或經歷落摔等製程或測試時，該封裝基板10與該半導體晶片11(或封裝層14)之間容易因熱膨脹係數(Coefficient of thermal expansion，簡稱CTE)差異(Mismatch)，而使該封裝基板10發生翹曲(warpage)(如圖1所示之虛線態樣)，故於翹曲的情 況下，容易造成該半導體晶片11與該封裝層14之間發生裂縫k，甚至造成該半導體晶片11碎裂，導致產品良率降低。 However, in the packaging process of the conventional packaging structure 1, the packaging substrate 10 is the entire layout (ie, mass production size), and when the temperature cycle (temperature cycle) or stress changes, such as passing through a reflow oven, or experiencing drop During the manufacturing process or testing, the package substrate 10 is likely to be warped due to the Coefficient of Thermal Expansion (CTE) difference (Mismatch) between the package substrate 10 and the semiconductor chip 11 (or package layer 14 ). (warpage) (as shown in the dotted line in Figure 1), so in the case of warpage Under such circumstances, it is easy to cause a crack k to occur between the semiconductor wafer 11 and the encapsulation layer 14, and even cause the semiconductor wafer 11 to break, resulting in a decrease in product yield.

因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。 Therefore, how to overcome the various problems of the above-mentioned conventional technologies has become an urgent problem to be solved at present.

鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：承載結構；電子元件，係設於該承載結構上，其中，該電子元件上係形成有複數導電凸塊，使該電子元件藉由該導電凸塊電性連接該承載結構；以及封裝層，係形成於該承載結構之部分表面上，以包覆該電子元件。 In view of the various deficiencies of the above-mentioned conventional technologies, the present invention provides an electronic package, which includes: a carrying structure; The electronic component is electrically connected to the carrying structure through the conductive bump; and an encapsulation layer is formed on a part of the surface of the carrying structure to cover the electronic component.

本發明復提供一種電子封裝件之製法，係包括：提供至少一電子元件，其上形成有複數導電凸塊；將該電子元件設於一承載結構上，其中，該電子元件係以該導電凸塊電性連接該承載結構；以及形成封裝層於該承載結構之部分表面上，以包覆該電子元件。 The present invention further provides a method for manufacturing an electronic package, which includes: providing at least one electronic component with a plurality of conductive bumps formed thereon; placing the electronic component on a carrier structure, wherein the electronic component is formed with the conductive bumps a block is electrically connected to the carrying structure; and an encapsulation layer is formed on a part of the surface of the carrying structure to cover the electronic component.

前述之電子封裝件及其製法中，該承載結構上係於水平方向排設複數該電子元件，以令任二相鄰之該電子元件之間形成有一間隙，使該封裝層填滿該間隙。例如，該間隙之間距係至多為300微米。 In the aforementioned electronic package and its manufacturing method, a plurality of the electronic components are arranged horizontally on the carrier structure, so that a gap is formed between any two adjacent electronic components, and the encapsulation layer fills up the gap. For example, the distance between the gaps is at most 300 microns.

前述之電子封裝件及其製法中，該電子元件之一表面係外露於該封裝層之一表面。進一步，該電子元件之該表面與該封裝層之該表面之間的交界處係形成有強化體，例如，該強化體係以點膠方式形成之絕緣塊。甚至於該電子元件之該表面、該強化體與該封裝層之該表面上形成有金屬層。 In the aforementioned electronic package and its manufacturing method, one surface of the electronic component is exposed on one surface of the package layer. Further, a reinforcement is formed at the junction between the surface of the electronic component and the surface of the encapsulation layer, for example, an insulating block formed by dispensing the reinforcement system. Even the metal layer is formed on the surface of the electronic component, the reinforcing body and the surface of the encapsulation layer.

前述之電子封裝件及其製法中，復包括於形成該封裝層後，粗糙化該電子元件之一表面，使其呈凹凸表面。 In the aforementioned electronic package and its manufacturing method, after forming the package layer, roughening a surface of the electronic component to make it a concave-convex surface.

前述之電子封裝件及其製法中，該封裝層之楊氏模數係至少為20GPa。 In the aforementioned electronic package and its manufacturing method, the Young's modulus of the package layer is at least 20 GPa.

前述之電子封裝件及其製法中，復包括於形成該封裝層後，粗糙化該封裝層之一表面，使其呈凹凸表面。 In the aforementioned electronic package and its manufacturing method, after forming the package layer, roughening a surface of the package layer to make it a concave-convex surface.

由上可知，本發明之電子封裝件及其製法中，主要藉由該強化體之設計，可強化該電子元件與該封裝層之間的交界處的強度，故於該承載結構發生翹曲時，仍可避免該電子元件與該封裝層之間發生裂縫，因而能避免該電子元件發生碎裂之問題。 It can be seen from the above that in the electronic package and its manufacturing method of the present invention, the strength of the junction between the electronic component and the packaging layer can be strengthened mainly through the design of the reinforcing body, so when the carrying structure warps , can still avoid the occurrence of cracks between the electronic component and the encapsulation layer, thus avoiding the problem of cracking of the electronic component.

1:封裝結構 1: Package structure

10:封裝基板 10: Package substrate

11:半導體晶片 11: Semiconductor wafer

13:銲錫凸塊 13: Solder bumps

14,24:封裝層 14,24: encapsulation layer

2:電子封裝件 2: Electronic package

2a:整版面基材結構 2a: Full-page substrate structure

20:承載結構 20: Bearing structure

200:線路層 200: line layer

21:電子元件 21: Electronic components

21a:作用面 21a: Action surface

21b:非作用面 21b: Non-active surface

210:電極墊 210: electrode pad

22:導電凸塊 22: Conductive bump

24b:上表面 24b: upper surface

25:強化體 25: Reinforcement body

26:金屬層 26: metal layer

k:裂縫 k: crack

L,S:切割路徑 L, S: cutting path

M:凹凸表面 M: uneven surface

t:間隙 t: gap

X:水平方向 X: horizontal direction

圖1係為習知封裝結構之剖面示意圖。 FIG. 1 is a schematic cross-sectional view of a conventional packaging structure.

圖2A至圖2E係為本發明之電子封裝件之製法的剖視示意圖。 2A to 2E are schematic cross-sectional views of the manufacturing method of the electronic package of the present invention.

圖3係為圖2E之另一態樣的局部放大剖視示意圖。 FIG. 3 is a partially enlarged cross-sectional schematic diagram of another aspect of FIG. 2E .

以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The implementation of the present invention is described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實 施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to match the content disclosed in the specification, for the understanding and reading of those familiar with this technology, and are not used to limit the implementation of the present invention Therefore, it has no technical substantive meaning. Any modification of structure, change of proportional relationship or adjustment of size shall still fall within the scope of this invention without affecting the effect and purpose of the present invention. The technical content disclosed by the invention must be within the scope covered. At the same time, terms such as "above" quoted in this specification are only for the convenience of description, and are not used to limit the practicality of the present invention. The scope of implementation, the change or adjustment of its relative relationship, without substantial change in technical content, should also be regarded as the scope of the present invention that can be implemented.

圖2A至圖2E係為本發明之電子封裝件2之製法之剖視示意圖。 2A to 2E are schematic cross-sectional views of the manufacturing method of the electronic package 2 of the present invention.

如圖2A所示，提供一整版面基材結構2a，其包含複數陣列排設之電子元件21，且各該電子元件21上佈設有複數導電凸塊22。 As shown in FIG. 2A , a full-page substrate structure 2 a is provided, which includes a plurality of electronic components 21 arranged in an array, and a plurality of conductive bumps 22 are arranged on each of the electronic components 21 .

該電子元件21可為主動元件、被動元件、封裝結構或其組合者，且該主動元件係如半導體晶片，而該被動元件係如電阻、電容及電感。於本實施例中，該電子元件21係為半導體晶片，並具有相對之作用面21a與非作用面21b，該作用面21a上具有複數電極墊210，於各該電極墊210上形成有導電凸塊22。 The electronic component 21 can be an active component, a passive component, a packaging structure or a combination thereof, and the active component is such as a semiconductor chip, and the passive component is such as a resistor, capacitor and inductor. In this embodiment, the electronic component 21 is a semiconductor chip, and has an opposite active surface 21a and a non-active surface 21b. There are a plurality of electrode pads 210 on the active surface 21a, and conductive bumps are formed on each of the electrode pads 210. Block 22.

再者，該導電凸塊22係為焊錫材、金屬柱(如銅柱)或其組合。 Furthermore, the conductive bump 22 is a solder material, a metal post (such as a copper post) or a combination thereof.

如圖2B所示，沿如圖2A所示之切割路徑L對該整版面基材結構2a進行切單製程，以分離各該電子元件21，再於一承載結構20上沿水平方向X上間隔佈設至少兩個電子元件21。 As shown in FIG. 2B, the full-page substrate structure 2a is subjected to a singulation process along the cutting path L shown in FIG. 2A to separate the electronic components 21, and then spaced on a carrier structure 20 along the horizontal direction X. At least two electronic components 21 are arranged.

所述之承載結構20可為具有核心層與線路結構之封裝基板(substrate)或無核心層(coreless)之線路構造，且其構成係於介電材上形成複數線路層200，如線路重佈層(redistribution layer，簡稱RDL)。 The carrying structure 20 can be a packaging substrate (substrate) with a core layer and a circuit structure or a circuit structure without a core layer (coreless), and its composition is to form a plurality of circuit layers 200 on a dielectric material, such as circuit redistribution Layer (redistribution layer, RDL for short).

於本實施例中，該承載結構20係無核心層(coreless)之線路構造。然而，於其它實施例中，該承載結構20亦可為具有複數導電矽穿孔(Through-silicon via，簡稱TSV)之半導體基板，以作為矽中介板(Through Silicon interposer，簡稱TSI)。應可理解地，該承載結構20亦可為其它可供承載如晶片等電子元件之承載單元，如導線架(lead frame)，但並不限於上述。 In this embodiment, the carrying structure 20 is a circuit structure without a core layer (coreless). However, in other embodiments, the carrier structure 20 can also be a semiconductor substrate with a plurality of conductive through-silicon vias (TSV for short), serving as a through silicon interposer (TSI for short). It should be understood that the carrying structure 20 can also be other carrying units capable of carrying electronic components such as chips, such as a lead frame, but is not limited to the above.

再者，當該電子元件21係以覆晶方式藉由該些導電凸塊22電性連接該承載結構20之線路層200。 Furthermore, when the electronic component 21 is flip-chip, the conductive bumps 22 are electrically connected to the circuit layer 200 of the carrying structure 20 .

另外，於本實施例中，該些電子元件21雖均為相同類型(即主動元件)，但其內部構造可相同或不相同。應可理解地，該些電子元件21亦可為不相同類型的電子元件。 In addition, in this embodiment, although the electronic components 21 are of the same type (ie active components), their internal structures may be the same or different. It should be understood that the electronic components 21 can also be different types of electronic components.

如圖2C所示，形成一封裝層24於該承載結構20之部分表面上，以包覆該些電子元件21與該些導電凸塊22。 As shown in FIG. 2C , an encapsulation layer 24 is formed on a part of the surface of the carrying structure 20 to cover the electronic components 21 and the conductive bumps 22 .

所述之封裝層24可為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)、模封化合物(molding compound)或其它適當材料。 The encapsulation layer 24 can be an insulating material, such as polyimide (PI for short), dry film, epoxy, molding compound or other suitable materials.

於本實施例中，該封裝層24係採用壓合(lamination)或模壓(molding)之方式形成於該承載結構20上，以令該封裝層24未填滿任二相鄰之該電子元件21之間，因而形成間隙t。 In this embodiment, the encapsulation layer 24 is formed on the carrying structure 20 by lamination or molding, so that the encapsulation layer 24 does not fill any two adjacent electronic components 21 Between, thus forming a gap t.

再者，該封裝層24之楊氏模數係為20GPa以上。 Furthermore, the Young's modulus of the encapsulation layer 24 is above 20 GPa.

又，可藉由整平製程或薄化製程，使該電子元件21之非作用面21b與該封裝層24之上表面24b共平面，以令該電子元件21之非作用面21b外露於該封裝層24。例如，當形成該封裝層24於該承載結構20上時，該封裝層24係覆蓋該電子元件21之非作用面21b，再以研磨或切割方式移除該封裝層24之部分材質(亦可依需求同時移除該電子元件21之非作用面21b之部分材質)，使該電子元件21之非作用面21b齊平於該封裝層24之上表面24b。 In addition, the non-active surface 21b of the electronic component 21 can be coplanar with the upper surface 24b of the packaging layer 24 through a flattening process or a thinning process, so that the non-active surface 21b of the electronic component 21 is exposed to the package Layer 24. For example, when forming the encapsulation layer 24 on the carrying structure 20, the encapsulation layer 24 covers the non-active surface 21b of the electronic component 21, and then removes part of the material of the encapsulation layer 24 by grinding or cutting (also can be At the same time, part of the material of the non-active surface 21b of the electronic component 21 is removed as required, so that the non-active surface 21b of the electronic component 21 is flush with the upper surface 24b of the encapsulation layer 24 .

如圖2D所示，於該電子元件21之非作用面21b與該封裝層24之間的交界處形成強化體25。 As shown in FIG. 2D , a reinforcement 25 is formed at the junction between the non-active surface 21 b of the electronic component 21 and the encapsulation layer 24 .

於本實施例中，該強化體25係以點膠方式形成之絕緣塊，以壓制於該電子元件21之非作用面21b與該封裝層24之間的交界處上。例如，復可於該電子元件21之非作用面21b、強化體25與該封裝層24之上表面24b上形成一如銅 材之金屬層26，以進一步壓制該電子元件21與該封裝層24。該金屬層26應可理解可做為晶片21的電磁干擾屏蔽(EMI shielding)。 In this embodiment, the reinforcing body 25 is an insulating block formed by dispensing glue, so as to be pressed on the junction between the non-active surface 21 b of the electronic component 21 and the encapsulation layer 24 . For example, a copper foil can be formed on the non-active surface 21b of the electronic component 21, the reinforcing body 25 and the upper surface 24b of the packaging layer 24. The metal layer 26 of the material is used to further suppress the electronic component 21 and the encapsulation layer 24 . The metal layer 26 can be understood as an EMI shielding for the chip 21 .

如圖2E所示，沿圖2D所示之切割路徑S(如間隙t)進行切單製程，以獲取該電子封裝件2。 As shown in FIG. 2E , a singulation process is performed along the cutting path S (such as the gap t) shown in FIG. 2D to obtain the electronic package 2 .

於本實施例中，可依需求先粗糙化該電子元件21之非作用面21b與該封裝層24之上表面24b，使該電子元件21之非作用面21b與該封裝層24之上表面24b形成凹凸表面M，如圖3所示，再形成該強化體25與該金屬層26，以增加該強化體25之接觸面積及該金屬層26之接觸面積，進而強化該強化體25之結合性及該金屬層26之結合性。 In this embodiment, the non-active surface 21b of the electronic component 21 and the upper surface 24b of the encapsulation layer 24 can be roughened first as required, so that the inactive surface 21b of the electronic component 21 and the upper surface 24b of the encapsulation layer 24 Form the concave-convex surface M, as shown in Figure 3, and then form the reinforcement 25 and the metal layer 26 to increase the contact area of the reinforcement 25 and the contact area of the metal layer 26, thereby strengthening the bonding of the reinforcement 25 And the combination of the metal layer 26.

於後續製程中(即形成該封裝層24後)，可於該承載結構20之下側(或植球側)上形成複數銲球(圖略)，以供該電子封裝件2接置於一如電路板之電子裝置(圖略)上。 In the subsequent process (that is, after the packaging layer 24 is formed), a plurality of solder balls (not shown) can be formed on the lower side (or ball-planting side) of the carrier structure 20 for the electronic package 2 to be connected to a Such as the electronic device on the circuit board (not shown).

因此，本發明之製法，主要藉由該封裝層24形成於該承載結構20之部分表面上，以調控該承載結構20上之應力分佈，故相較於習知技術，本發明之製法即使於該承載結構20發生翹曲的情況下，該電子元件21仍可分散其所受之應力，以避免該電子元件21因應力集中而發生破裂之問題，因而能提高該電子封裝件2之可靠度。 Therefore, the manufacturing method of the present invention mainly controls the stress distribution on the supporting structure 20 by forming the encapsulation layer 24 on a part of the surface of the supporting structure 20. Therefore, compared with the prior art, the manufacturing method of the present invention can be used in When the supporting structure 20 is warped, the electronic component 21 can still disperse the stress it receives, so as to avoid the cracking of the electronic component 21 due to stress concentration, thereby improving the reliability of the electronic package 2 .

再者，藉由該強化體25(及該金屬層26)之設計，以壓制該電子元件21之非作用面21b與該封裝層24之間的交界處，故當該承載結構20發生翹曲(warpage)時，能避免該電子元件21與該封裝層24之間發生裂縫，因而能避免該電子元件21發生碎裂之問題，以有效提高產品良率。 Moreover, by the design of the reinforcing body 25 (and the metal layer 26), to suppress the junction between the non-active surface 21b of the electronic component 21 and the encapsulation layer 24, so when the carrier structure 20 warps During warpage, cracks can be avoided between the electronic component 21 and the encapsulation layer 24, thereby avoiding the cracking of the electronic component 21, so as to effectively improve product yield.

本發明復提供一種電子封裝件2，係包括：一承載結構20、至少一電子元件21、以及一封裝層24。 The present invention further provides an electronic package 2 , which includes: a carrying structure 20 , at least one electronic component 21 , and a packaging layer 24 .

所述之電子元件21係設於該承載結構20上，其中，且該電子元件21係具有複數導電凸塊22，使該電子元件21以該導電凸塊22電性連接該承載結構20。 The electronic component 21 is disposed on the carrying structure 20 , wherein the electronic component 21 has a plurality of conductive bumps 22 , so that the electronic component 21 is electrically connected to the carrying structure 20 through the conductive bumps 22 .

所述之封裝層24係形成於該承載結構20之部分表面上，以包覆該電子元件21與導電凸塊22。 The encapsulation layer 24 is formed on a part of the surface of the carrying structure 20 to cover the electronic component 21 and the conductive bump 22 .

於一實施例中，該承載結構20上係於水平方向X排設複數該電子元件21，以令任二相鄰之該電子元件21之間形成有一間隙t，使該封裝層24未填滿該間隙t。例如，該間隙t之間距係至多為300微米。 In one embodiment, a plurality of electronic components 21 are arranged in the horizontal direction X on the carrier structure 20, so that a gap t is formed between any two adjacent electronic components 21, so that the encapsulation layer 24 is not filled The gap t. For example, the distance between the gaps t is at most 300 micrometers.

於一實施例中，該電子元件21之非作用面21b係外露於該封裝層24之上表面24b。進一步，該電子元件21之非作用面21b與該封裝層24之上表面24b之間的交界處係形成有強化體25，如絕緣塊，甚至於該電子元件21之非作用面21b、該強化體25與該封裝層24之上表面24b上形成有金屬層26。 In one embodiment, the non-active surface 21 b of the electronic component 21 is exposed on the upper surface 24 b of the encapsulation layer 24 . Further, the junction between the non-active surface 21b of the electronic component 21 and the upper surface 24b of the encapsulation layer 24 is formed with a reinforcement 25, such as an insulating block, and even the non-active surface 21b of the electronic component 21, the reinforced A metal layer 26 is formed on the body 25 and the upper surface 24 b of the encapsulation layer 24 .

於一實施例中，該電子元件21之非作用面21b係呈凹凸表面或粗糙化。 In one embodiment, the non-active surface 21b of the electronic component 21 is a concave-convex surface or roughened.

於一實施例中，該封裝層24之楊氏模數係至少為20GPa。 In one embodiment, the Young's modulus of the encapsulation layer 24 is at least 20 GPa.

於一實施例中，該封裝層24之上表面24b係呈凹凸表面或粗糙化。 In one embodiment, the upper surface 24b of the encapsulation layer 24 is a concave-convex surface or roughened.

綜上所述，本發明之電子封裝件及其製法，係藉由該強化體之設計，能強化該電子元件與該封裝層之間的交界處的強度，故於該承載結構發生翹曲時，能避免該電子元件與該封裝層之間發生裂縫，因而能避免該電子元件發生碎裂之問題。 In summary, the electronic package and its manufacturing method of the present invention can strengthen the strength of the junction between the electronic component and the packaging layer through the design of the reinforcing body, so when the carrying structure warps , can avoid cracks between the electronic component and the encapsulation layer, and thus can avoid the problem of cracking of the electronic component.

上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所 The above-mentioned embodiments are used to illustrate the principles and effects of the present invention, but not to limit the present invention. Any person skilled in the art can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the protection scope of the right of the present invention should be as stated in the scope of patent application mentioned later.

20:承載結構 20: Bearing structure

21:電子元件 21: Electronic components

21b:非作用面 21b: Non-active surface

22:導電凸塊 22: Conductive bump

24:封裝層 24: encapsulation layer

t:間隙 t: gap

Claims (14)

一種電子封裝件，係包括：承載結構；電子元件，係以覆晶方式設於該承載結構上，其中，該電子元件上係形成有複數導電凸塊，使該電子元件藉由該導電凸塊電性連接該承載結構；封裝層，係形成於該承載結構之部分表面上，以包覆該電子元件，其中，該電子元件之一表面係外露於該封裝層之一表面；以及強化體，係為絕緣塊，且僅形成於該電子元件之該表面與該封裝層之該表面之間的交界處。 An electronic package, comprising: a carrying structure; an electronic component is provided on the carrying structure in a flip-chip manner, wherein a plurality of conductive bumps are formed on the electronic component, so that the electronic component can pass through the conductive bump electrically connecting the carrying structure; an encapsulation layer formed on a part of the surface of the carrying structure to cover the electronic component, wherein one surface of the electronic component is exposed on one surface of the encapsulation layer; and a reinforcing body, An insulating block is formed only at the interface between the surface of the electronic component and the surface of the encapsulation layer. 如請求項1所述之電子封裝件，其中，該承載結構上水平排設有複數該電子元件，以令任二相鄰之該電子元件之間形成有一間隙，使該封裝層未填滿該間隙。 The electronic package as claimed in claim 1, wherein a plurality of electronic components are horizontally arranged on the supporting structure, so that a gap is formed between any two adjacent electronic components, so that the packaging layer does not fill the gap. 如請求項2所述之電子封裝件，其中，該間隙之間距係至多為300微米。 The electronic package as claimed in claim 2, wherein the distance between the gaps is at most 300 microns. 如請求項1所述之電子封裝件，其中，該電子元件之該表面、該強化體與該封裝層之該表面上形成有金屬層。 The electronic package as claimed in claim 1, wherein a metal layer is formed on the surface of the electronic component, the reinforcing body and the surface of the encapsulation layer. 如請求項1所述之電子封裝件，其中，該電子元件之一表面係呈凹凸表面。 The electronic package according to claim 1, wherein one surface of the electronic component is a concave-convex surface. 如請求項1所述之電子封裝件，其中，該封裝層之楊氏模數係至少為20GPa。 The electronic package as claimed in claim 1, wherein the Young's modulus of the packaging layer is at least 20 GPa. 如請求項1所述之電子封裝件，其中，該封裝層之一表面係呈凹凸表面。 The electronic package according to claim 1, wherein one surface of the packaging layer is a concave-convex surface. 一種電子封裝件之製法，係包括：提供至少一電子元件，其上形成有複數導電凸塊；將該電子元件以覆晶方式藉由該複數導電凸塊設於一承載結構上，其中，該電子元件係以該導電凸塊電性連接該承載結構；形成封裝層於該承載結構之部分表面上，以包覆該電子元件，且令該電子元件之一表面係外露於該封裝層之一表面；以及以點膠方式形成係為絕緣塊之強化體，且將該強化體僅形成於該電子元件之該表面與該封裝層之該表面之間的交界處。 A method for manufacturing an electronic package, comprising: providing at least one electronic component with a plurality of conductive bumps formed thereon; setting the electronic component on a carrier structure in a flip-chip manner through the plurality of conductive bumps, wherein the The electronic component is electrically connected to the carrying structure by the conductive bump; forming a packaging layer on a part of the surface of the carrying structure to cover the electronic component, and making one surface of the electronic component exposed on one of the packaging layers the surface; and forming a reinforcing body as an insulating block by dispensing, and forming the reinforcing body only at the junction between the surface of the electronic component and the surface of the encapsulation layer. 如請求項8所述之電子封裝件之製法，其中，該承載結構上水平排設有複數該電子元件，以令任二相鄰之該電子元件之間形成有一間隙，使該封裝層未填滿該間隙。 The method for manufacturing an electronic package as claimed in claim 8, wherein a plurality of the electronic components are horizontally arranged on the supporting structure, so that a gap is formed between any two adjacent electronic components, so that the packaging layer is not filled fill the gap. 如請求項9所述之電子封裝件之製法，其中，該間隙之間距係至多為300微米。 The method for manufacturing an electronic package as claimed in claim 9, wherein the distance between the gaps is at most 300 micrometers. 如請求項8所述之電子封裝件之製法，其中，該電子元件之該表面、該強化體與該封裝層之該表面上形成有金屬層。 The method for manufacturing an electronic package according to claim 8, wherein a metal layer is formed on the surface of the electronic component, the reinforcing body, and the surface of the packaging layer. 如請求項8所述之電子封裝件之製法，復包括於形成該封裝層後，粗糙化該電子元件之一表面。 The method for manufacturing an electronic package as claimed in claim 8 further includes roughening a surface of the electronic component after forming the packaging layer. 如請求項8所述之電子封裝件之製法，其中，該封裝層之楊氏模數係至少為20GPa。 The method for manufacturing an electronic package as claimed in claim 8, wherein the Young's modulus of the packaging layer is at least 20 GPa. 如請求項8所述之電子封裝件之製法，復包括於形成該封裝層後，粗糙化該封裝層之一表面。 The method for manufacturing an electronic package as claimed in claim 8 further includes roughening a surface of the package layer after forming the package layer.
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