TWI784089B - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

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TWI784089B
TWI784089B TW107142099A TW107142099A TWI784089B TW I784089 B TWI784089 B TW I784089B TW 107142099 A TW107142099 A TW 107142099A TW 107142099 A TW107142099 A TW 107142099A TW I784089 B TWI784089 B TW I784089B
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Taiwan
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resist
opening
aforementioned
electrode pad
semiconductor element
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TW107142099A
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TW201926741A (zh
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櫻井大輔
玉利健
越智正三
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日商松下知識產權經營股份有限公司
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Abstract

在半導體裝置之製造方法中，具備：抗蝕劑步驟，對於具有複數個電極墊之半導體元件的第1面，以覆蓋前述電極墊表面的方式來供給抗蝕劑；開口步驟，以使前述電極墊表面從前述抗蝕劑露出的方式來將前述電極墊表面上的前述抗蝕劑開口；硬化步驟，對前述抗蝕劑施加光或熱，將前述抗蝕劑硬化；鍍敷步驟，將鍍敷液填充至前述抗蝕劑的前述開口內，在前述電極墊表面上形成突起電極；及剝離步驟，將前述抗蝕劑從前述半導體元件的前述第1面剝離。

Description

半導體裝置之製造方法
發明領域
本發明是有關於一種半導體裝置之製造方法。特別是有關於一種使用了抗蝕劑(resist)的半導體裝置之製造方法。
發明背景
近年來，為了促進兼顧半導體元件的高密度化與電極端子的多接腳化，而在謀求半導體元件的電極端子的窄距化、面積縮小化。通常，在覆晶(flip chip)安裝中，是在系統LSI、記憶體、CPU等的半導體元件的電極端子上形成錫銲凸塊等的突起電極，並以倒裝(face down)方式來將其半導體元件相對於安裝基板的連接端子進行壓接、加熱而使凸塊連接，藉此進行安裝。
作為在半導體元件的電極端子上形成錫銲凸塊的方法，迄今採用了下述工法：以網版印刷或分配(dispense)或電解鍍敷將焊料形成於電極上後，以回焊爐加熱至焊料熔點以上，藉此形成突起狀的錫銲凸塊。
然而，近年來對電極間之窄距化的要求變得非常嚴格，故開始出現下述問題：在覆晶安裝時的加熱步驟中熔融之焊料變形，因焊料的表面張力而發生錫銲凸塊彼此連接的焊橋不良。
於是，有人提出一種使用例如由金或銅等所構成的漸縮之細微金屬凸塊，在倒裝安裝步驟中使前端塑性變形，並藉由固相擴散進行接合的工法。根據該方法，漸縮之細微金屬凸塊在覆晶時不會熔融，故可防止發生橋接，而可對應窄距化。
作為形成漸縮之細微金屬凸塊的方法，具有噴射微粒子與載氣(carrier gas)而堆積金屬微粒子的氣相沉積法。(例如，參照專利文獻1)。圖5是概念性顯示專利文獻1所記載之實施例的細微金屬凸塊形成方法的截面圖。
如圖5(a)所示，基板110上形成有電極112，且電極112受到由樹脂所構成的遮罩層130所覆蓋。在遮罩層130上，以電極112之既定處會露出的方式而形成有凹部134。該凹部134的開口形狀為圓形形狀。
接著，如圖5(b)所示，將基板110在已載置於金屬板上的狀態下載置於氣相沉積裝置的真空環境中，並在電極112的露出面上，藉由將使金屬蒸發而得之金屬微粒子與載氣一起從噴嘴125噴射而堆積於既定處的氣相沉積法，來形成細微的金屬凸塊。
若從噴嘴125持續噴射金屬微粒子，則如圖 5(c)及圖5(d)所示，會形成堆積於直線狀凹部134底面之電極112上的金屬凸塊114a，且堆積於遮罩層130上之金屬膜132的前端會從直線狀凹部134的開口緣突出而亦使得直線狀凹部134的開口部變窄。因此，堆積於電極112之露出面上的金屬微粒子量亦從直線狀凹部134的內周緣朝向中心遞減，而形成圓錐台狀的金屬凸塊114a。
此外，若持續噴射金屬微粒子，則如圖5(e)所示，直線狀凹部134的開口部會被堆積於遮罩層130上之金屬膜132的前端部完全封閉。此時，在直線狀凹部134之底面露出的電極112的露出面上，不與金屬膜132接觸而獨立形成有圓錐狀金屬凸塊114。
接著，停止從噴嘴125噴射金屬粒子與載氣，如圖5(f)所示，將基板110從氣相沉積裝置取出，在保持圓錐狀金屬凸塊114之形狀的狀態下，將遮罩層130及金屬膜132從基板110的一面側進行機械剝離。其結果，會沿著基板110的外周緣形成金屬凸塊114。
根據該實施形態，可提供一種細微金屬凸塊之形成方法，其可在形成於基板的一面側的金屬構件之既定處上，穩定且工業性地形成細微的金屬凸塊。
先前技術文獻 專利文獻
專利文獻1：日本專利第4826924號公報
發明概要
然而，以往的方法中，為了形成圓錐狀的金屬凸塊，必須針對每1個凸塊，將金屬微粒子與載氣從噴嘴噴射至電極部。要對多接腳且大口徑的晶圓形成大量凸塊，就必須掃描晶圓整個表面來進行金屬微粒子與載氣的噴射，故具有需要較長生產時間這樣的問題。此外，在晶圓整個表面的複數個開口部中，難以將噴射之氣體流量控制成相同，故具有凸塊的形狀有差異這樣的問題。
此外，已堆積之金屬膜132會與遮罩層130同時剝離，故必須將由金或鉑等的高價金屬所構成的金屬膜132廢棄或進行回收，而亦具有生產成本提高這樣的問題。
本發明鑒於上述問題，目的在於提供一種在邁向多接腳化、大口徑化的半導體元件中，能夠以較短生產時間確保穩定的形狀，並且進一步以低成本來製造的微小突起電極之形成方法。
本發明之一態樣中，半導體裝置之製造方法具備：抗蝕劑步驟，對於具有複數個電極墊之半導體元件的第1面，以覆蓋前述電極墊表面的方式來供給抗蝕劑；開口步驟，以使前述電極墊表面從前述抗蝕劑露出的方式來將前述電極墊表面上的前述抗蝕劑開口；硬化步驟，對前述抗蝕劑施加光或熱，將前述抗蝕劑硬化；鍍敷步驟，將鍍敷液填充至前述抗蝕劑的前述開口內，在前述電極墊 表面上形成突起電極；及剝離步驟，將前述抗蝕劑從前述半導體元件的前述第1面剝離。
本發明之另一態樣的半導體裝置之製造方法具備：抗蝕劑步驟，對於具有複數個電極墊之半導體元件的第1面，以使前述電極墊表面露出的方式來供給抗蝕劑，而在前述電極墊表面上形成前述抗蝕劑的開口；硬化步驟，對前述抗蝕劑施加光或熱，將前述抗蝕劑硬化；鍍敷步驟，將鍍敷液填充至前述抗蝕劑的前述開口內，在前述電極墊表面上形成突起電極；及剝離步驟，將前述抗蝕劑從前述半導體元件的前述第1面剝離。
根據本發明的半導體裝置之製造方法，在邁向多接腳化、大口徑化的半導體元件中，能夠以低成本來提供高產量且形狀穩定的微小突起電極。
1:半導體元件
2:電極墊
3:抗蝕劑
3a:開口部
3b:開口部
4:辨識標記
5:奈米壓印模
5a:突起部
5b:突起部
6:顯影液
7:晶種層
8:凸塊
8a:頭頂部
8b:台座部
10:揮發性樹脂層
13:抗蝕劑
13a:抗蝕劑
13b:抗蝕劑
14:辨識標記
110:基板
112:電極
114:金屬凸塊
114a:金屬凸塊
125:噴嘴
130:遮罩層
132:金屬膜
134:凹部
圖1(a)~(g)是說明本發明之實施形態1中的半導體裝置之製造方法的截面圖。
圖2(a)是概念性顯示實施形態1中的奈米壓印模的立體圖，圖2(b)是概念性顯示實施形態1中以奈米壓印模形成了複數個凸塊的半導體裝置的立體圖。
圖3(a)~(f)是顯示本發明之實施形態2中的半導體裝置之製造方法的截面圖。
圖4(a)~(j)是說明本發明之實施形態3中的半導體裝置之製造方法的截面圖。
圖5(a)~(f)是概念性顯示專利文獻1所記載之實施例的細微金屬凸塊形成方法的截面圖。
用以實施發明之形態
本發明之一態樣的半導體裝置之製造方法具備：抗蝕劑步驟，對於具有複數個電極墊之半導體元件的第1面，以覆蓋前述電極墊表面的方式來供給抗蝕劑；開口步驟，以使前述電極墊表面從前述抗蝕劑露出的方式來將前述電極墊表面上的前述抗蝕劑開口；硬化步驟，對前述抗蝕劑施加光或熱，將前述抗蝕劑硬化；鍍敷步驟，將鍍敷液填充至前述抗蝕劑的前述開口內，在前述電極墊表面上形成突起電極；及剝離步驟，將前述抗蝕劑從前述半導體元件的前述第1面剝離。
可構造成在前述開口步驟中，藉由將奈米壓印的轉印模加壓至前述抗蝕劑而形成前述開口。
可構造成在前述開口步驟中，以使前述抗蝕劑之前述開口中的底部部分比入口部分更寬的方式來形成前述開口。
可構造成在前述抗蝕劑步驟之前，具有在前述電極墊表面上形成樹脂層的步驟，在前述抗蝕劑步驟中，以覆蓋已形成於前述電極墊表面上之前述樹脂層的方式來對前述半導體元件的前述第1面供給前述抗蝕劑，在前述開口步驟中，以使前述電極墊表面露出的方式來將前述電極墊表面上的前述抗蝕劑及前述樹脂層去除，而形成 前述開口。
可構造成在前述開口步驟中，以使前述樹脂層露出的方式來將前述樹脂層上的前述抗蝕劑開口後，透過前述開口將前述樹脂層去除，而在前述電極墊表面上形成前述抗蝕劑的前述開口。
可構造成在前述開口步驟中，於前述抗蝕劑的前述開口內注入不超過前述開口之深度的量的溶解液，將前述抗蝕劑之前述開口的內壁溶解，而使前述抗蝕劑之前述開口中的底部部分比入口部分更寬。
本發明之另一態樣的半導體裝置之製造方法具備：抗蝕劑步驟，對於具有複數個電極墊之半導體元件的第1面，以使前述電極墊表面露出的方式來供給抗蝕劑，而在前述電極墊表面上形成前述抗蝕劑的開口；硬化步驟，對前述抗蝕劑施加光或熱，將前述抗蝕劑硬化；鍍敷步驟，將鍍敷液填充至前述抗蝕劑的前述開口內，在前述電極墊表面上形成突起電極；及剝離步驟，將前述抗蝕劑從前述半導體元件的前述第1面剝離。
可構造成在前述抗蝕劑步驟中，藉由奈米壓印的轉印將第1抗蝕劑層配置於前述半導體元件的前述第1面後，以積層在前述第1抗蝕劑層上的方式來配置第2抗蝕劑層，前述第1抗蝕劑層在與前述電極墊表面對應的部分具有第1開口，前述第2抗蝕劑層具有尺寸比前述第1抗蝕劑層之前述第1開口更小的第2開口。
以下，針對本發明之實施形態，一邊參照圖 式一邊進行說明。
(實施形態1)
圖1是本發明之實施形態1中的半導體裝置之製造方法。於以下進行說明。如圖1(a)所示，在半導體元件1之圖示上表面即第1面上，形成有複數個電極墊2。以覆蓋形成有電極墊2之第1面整體的方式來形成晶種層(seed layer)7後，在各個電極墊2上配置揮發性樹脂層10(樹脂層形成步驟)。
再者，晶種層7是作為用以形成電鍍的基底層來使用。材質可使用例如Ni、W、Cr、Cu、Co、Ti等，厚度可形成為0.02~2μm。
揮發性樹脂層10是藉由例如奈米壓印、噴墨、光刻、針式(needle)轉印、塗布、印刷等的方法而形成，之後，藉由光照射或加熱來進行硬化反應，直到表現出彈性體的特性。
接著，如圖1(b)所示，在半導體元件1的第1面上，以覆蓋各個電極墊2及樹脂層10的方式來配置抗蝕劑3(抗蝕劑步驟)。抗蝕劑3是使用例如旋塗、棒塗布裝置等，以使膜變得均勻的方式來形成。抗蝕劑3亦可使用感光型、熱硬化型、光熱併用型的抗蝕劑。較佳是實質上對半導體元件1的第1面整個表面供給抗蝕劑3。
之後，如圖1(c)所示，將奈米壓印模5和半導體元件1的電極墊2進行對位，前述奈米壓印模5是以與各個電極墊2相對的方式而設有複數個突起部5a。之後，將 奈米壓印模5的各個突起部5a壓附於抗蝕劑3，來將壓附著突起部5a之部分中的抗蝕劑3擠開，並將抗蝕劑3加壓，直到突起部5a與揮發性樹脂層10接觸。在藉由奈米壓印模5加壓抗蝕劑3的狀態下，藉由光照射或加熱來使抗蝕劑3硬化(硬化步驟)。
奈米壓印模5為奈米壓印的轉印模，可以是使用例如丙烯酸、聚矽氧、環氧等的樹脂而形成者。奈米壓印模5在加壓時會變形，藉此可吸收半導體元件1的翹曲、膨脹，而可在半導體元件1整個表面均勻地形成後述開口部。
接著，藉由將奈米壓印模5從半導體元件1剝離，如圖1(d)所示，在揮發性樹脂層10上方設置開口部3a。再者，可在奈米壓印模5的表面形成有脫模層。作為脫模層可使用例如聚矽氧、氟、丙烯酸等的樹脂或鎳等的金屬膜。藉由形成脫模層，可輕易將奈米壓印模5從抗蝕劑3及樹脂層10剝離。
之後，將半導體元件1浸漬於溶解液，以使液體進入半導體元件1的抗蝕劑3之開口部3a。藉此，在抗蝕劑3不溶解的狀態下，僅選擇性地溶解揮發性樹脂層10，透過開口部3a將樹脂層10去除。之後，以洗淨液將半導體元件1洗淨並使其乾燥。如圖1(e)所示，以使各個電極墊表面(電極墊2的表面)從抗蝕劑3露出的方式，形成已將電極墊表面上的抗蝕劑3去除的開口(開口步驟)。該開口是開口部3b與抗蝕劑3之開口部3a連通而構成，前述開口部 3b相當於之前存在過樹脂層10的部分，前述開口部3a是由奈米壓印模5的突起部5a所形成。沿著半導體元件1的第1面的方向上的開口部3b之尺寸是形成為比開口部3a之尺寸更大。又，抗蝕劑3之開口中的底部部分側相當於開口部3b，入口部分側相當於開口部3a。
接著，在將鍍敷液填充至抗蝕劑3之開口(開口部3a及3b)內的狀態下，將電極連接至晶種層7上，並實施電化學鍍敷。藉此，如圖1(f)所示，在抗蝕劑3之開口(開口部3a、3b)內，於電極墊2的表面上形成突起電極之一例的鍍敷凸塊8(鍍敷步驟)。
之後，將半導體元件1浸漬於抗蝕劑3的剝離液中，將抗蝕劑3從半導體元件1的第1面剝離(剝離步驟)。再來，將晶種層7從半導體元件1的第1面剝離。藉此，完成在半導體元件1的各個電極墊2上形成有鍍敷凸塊8的半導體裝置。此處，作為抗蝕劑3的剝離液可使用例如醇、乙醇、丙酮、純水等。晶種層7的剝離可使用例如以氫氟酸、鹽酸、硝酸等的剝離液所進行的濕蝕刻、或是灰化(ashing)等的乾蝕刻法。
鍍敷凸塊8具有頭頂部8a及台座部8b。頭頂部8a是由開口部3a的形狀，亦即奈米壓印模之突起部5a的形狀所決定。因此，在與半導體元件1的第1面平行的面上裁切時的各個頭頂部8a的截面，能夠以更均勻的形狀及尺寸來形成。例如，頭頂部8a的截面形狀為圓、四角形、六角形、八角形的情況下，會形成圓柱、四角柱、六角柱、 八角柱等的立體形狀。另一方面，台座部8b具有受開口部3b的形狀，亦即揮發性樹脂層10的形狀所支配的傾向，且成為具有一定的圓度或傾斜的形狀。此處，對於抗蝕劑3之開口部3a與開口部3b連接成的抗蝕劑3之開口填充鍍敷液，藉由鍍敷來形成鍍敷凸塊8。因此，頭頂部8a與台座部8b之間不存在接合界面，故鍍敷凸塊8可確保良好的強度。
頭頂部8a在沿著半導體元件1的第1面的方向上的尺寸(例如直徑)比台座部8b更細。因此，在半導體裝置的安裝步驟中，頭頂部8a會被壓縮而一邊在橫向上擴展一邊變形，藉此可吸收半導體元件1及基板(未圖示)的翹曲、膨脹，而具有確保鍍敷凸塊8與基板的電極接觸的功能。
此處，抗蝕劑3只要使用溶解參數(SP值)與揮發性樹脂層10差異1以上的材料即可。若不到1，則在揮發性樹脂層10溶解的同時，抗蝕劑3之開口部的內壁部亦開始溶解，而導致形狀不穩定。若為1以上，則實質上可選擇性地僅溶解揮發性樹脂層10。
再者，作為揮發性樹脂層10，可使用在抗蝕劑3之耐熱溫度以下會昇華的材料來代替選擇要溶解於溶解液的材料。根據該方法，在抗蝕劑3的硬化步驟中，可藉由使揮發性樹脂層10揮發，而形成如圖1(e)的抗蝕劑3之開口部3b。藉此，無需另外實施揮發性樹脂層10的溶解步驟，而可使揮發性樹脂層10的殘渣不易殘留。例如，在 形成細微、多接腳之凸塊的情況下，可確保穩定的凸塊形狀。此外，昇華的成分會附著於抗蝕劑3之開口部的內壁，而形成奈米級的親水膜。因此，即便像是入口部分窄，底部部分寬，且微小的開口部這種在形狀上難以讓液體進入的開口，鍍敷液仍會充分浸透，而可形成無孔洞的穩定之鍍敷凸塊。
再者，即便是不使用晶種層7的情況亦可。在圖1(a)之揮發性樹脂層10的形成步驟中，亦可將例如與揮發性樹脂層10的親水性比半導體元件1之電極墊2的附近部分更高的材料作為電極墊2來使用。藉此，即使對於半導體元件1的第1面全面供給液狀的揮發性樹脂層10，亦可在電極墊2上選擇性地形成揮發性樹脂層10。
根據該方法，即使對於具有細微且窄距之電極墊2的半導體元件1，亦可在各個電極墊2上穩定地形成揮發性樹脂層10。鍍敷步驟亦可藉由無電解鍍敷法來進行。即使無晶種層7，亦可形成鍍敷凸塊8。
圖2(a)、圖2(b)是概念性顯示本發明之實施形態1中的奈米壓印模5及半導體元件1的立體圖。如圖2(a)所示，在奈米壓印模5的表面上，以恆定間隔設有複數個例如八角柱形狀的突起部5a。
圖2(b)顯示使用圖2(a)的奈米壓印模5所形成的凸塊8。在半導體元件1上，以恆定間隔設有複數個例如由拱頂狀的台座部8b與八角柱狀的頭頂部8a所形成的凸塊8。將這種構成的半導體裝置安裝於基板(未圖示)的情 況下，細長的八角柱狀的頭頂部8a會一邊在橫向上擴展一邊被壓縮而引起塑性變形，進而與基板側的電極接合。即使壓縮變形，頭頂部8a亦為細長，故可在不與鄰接之凸塊發生短路不良的情況下進行接合。
接著，藉由實施形態1中的製造方法製作半導體裝置。使半導體元件1為1mm×1mm，並使電極墊2的間距為10μm、直徑為5μm。在電極墊2上形成直徑為4~6μm、高度為2μm的揮發性樹脂層10。使抗蝕劑3的厚度為6μm。使突起部5a的直徑為3μm、高度為5μm，藉由上述製造方法在抗蝕劑3上形成開口(開口部3a及3b)。以SEM觀察藉由截面研磨所形成之形狀的結果，確認抗蝕劑3之開口的底部部分即開口部3b的最大徑為6μm，入口部分即開口部3a的最大徑為3μm，且是以一樣的形狀來形成開口。使用Au作為鍍敷材料進行電鍍的結果，確認凸塊8的高度為6μm，且具有：八角柱的頭頂部8a、及具有圓度的台座部8b。
如上所述，根據本發明之實施形態1，即使是微小且多接腳的凸塊，亦可一邊確保高產量性，一邊輕易地穩定形成凸塊。
(實施形態2)
圖3是本發明之實施形態2中的半導體裝置之製造方法。於以下進行說明。首先，如圖3(a)所示，在半導體元件1之圖示上表面即第1面上，設有複數個電極墊2。例如，電極墊2的形狀可採取在平面視角下為四角形、八角形、 圓等各種形狀。
在奈米壓印之轉印模的第1奈米壓印模5上，以在相對於半導體元件1的第1面對向時，避開複數個電極墊2之形成位置的方式，設有突起部5a。亦即，以在第1奈米壓印模5與半導體元件1的第1面對向的狀態下，與包圍各個電極墊2的周圍區域對向的方式，在第1奈米壓印模5設有突起部5a。例如，像是在半導體元件1的第1面中，四角形狀的電極墊2配置成矩陣狀的情況下，突起部5a會具有與包圍各個電極墊2的網格狀周圍區域對應的形狀。
首先，轉印至半導體元件1的抗蝕劑在轉印用板材(未圖示)上形成為恆定的膜厚。接著，將奈米壓印模5壓附於該抗蝕劑上，以將第1抗蝕劑13a轉印至奈米壓印模5的突起部5a。之後，使奈米壓印模5與半導體元件1對向，以使突起部5a與包圍各個電極墊2的周圍區域對向的方式來進行對位。該對位亦可使用設於半導體元件1的第1面上的辨識標記4，藉由影像處理等的方式來進行。之後，使奈米壓印模5的突起部5a接近半導體元件1的第1面並進一步壓附，藉此將已轉印至奈米壓印模5之突起部5a的第1抗蝕劑13a轉印至半導體元件1的第1面。具體而言，將第1抗蝕劑13a轉印至半導體元件1的第1面上包圍各個電極墊2的周圍區域，形成第1抗蝕劑13a之層(第1抗蝕劑層)，前述第1抗蝕劑13a之層在與各個電極墊2的表面對應的部分具有第1開口(抗蝕劑步驟)。
接著，如圖3(b)所示，對轉印至半導體元件 1的第1抗蝕劑13a照射光，或是將第1抗蝕劑13a進行加熱，藉此使第1抗蝕劑13a硬化(硬化步驟)。
接著，如圖3(c)所示，使用設有突起部5b的奈米壓印模5，進一步進行抗蝕劑的轉印，前述突起部5b之截面積的寬度比突起部5a更大。在奈米壓印模5中，突起部5b實質上是以與突起部5a相同的配置所形成，但不同點在於突起部5b之截面積的寬度比突起部5a更大。使用這種構成的奈米壓印模5，以與突起部5a的情況相同的手法，將第2抗蝕劑13b轉印至突起部5b，並以積層在已配置於半導體元件1上之第1抗蝕劑13a上的方式來轉印第2抗蝕劑13b(抗蝕劑步驟)。第2抗蝕劑13b之層在與各個電極墊2的表面對應的部分具有第2開口，該第2開口成為比第1開口更小的開口。之後，進行光照射或熱硬化，如圖3(d)所示，形成開口尺寸不同的第1抗蝕劑13a之層與第2抗蝕劑13b之層在上下方向上積層的抗蝕劑13。
接著，如圖3(e)所示，將鍍敷液填充至藉由抗蝕劑13所形成之電極墊2上的開口內，藉由鍍敷而在電極墊2上形成鍍敷凸塊8(鍍敷步驟)。此處，鍍敷可使用無電解鍍敷法。又，作為電極墊2的材料可使用例如Al、Al-Cu、Al-Si-Cu、Cu、Au、P-Al等，鍍敷凸塊8的材料可使用例如Cu、Au、Co、W等。
最後，若將抗蝕劑13從半導體元件1的第1面剝離(剝離步驟)，則如圖3(f)所示，形成台座部(電極墊2側的部分)具有比頭頂部(前端側部分)更大之尺寸的突起 狀凸塊8。
此處，如圖3(d)所示，抗蝕劑13b中的第2開口的入口部分具有朝向上方擴展的形狀。因此，即使在第2開口具有微小尺寸的情況下，亦容易使鍍敷液沿著入口部分流入，而可在不具有孔洞部分的情況下填充鍍敷液。
再者，以上實施形態中，雖說明了以無電解鍍敷形成凸塊的方法，但並不限定於此。與實施形態1相同地，可藉由追加在抗蝕劑形成前預先進行的晶種層形成步驟、及在抗蝕劑剝離後進行的晶種層剝離步驟，而使用電鍍或電化學鍍敷。
如上所述，根據本發明之實施形態2，即使在比實施形態1更加多接腳且細微的半導體元件中，亦可一邊使形狀穩定，一邊形成凸塊。
(實施形態3)
圖4是本發明之實施形態3中的半導體裝置之製造方法。於以下進行說明。
如圖4(a)所示，以覆蓋半導體元件1之形成有電極墊2的第1面整體的方式來形成晶種層7後，在第1面上形成抗蝕劑3。例如，使用旋塗、棒塗布裝置、噴塗、噴射分配(jet dispense)法等，以使膜變得均勻的方式來形成。半導體元件1例如為圓盤狀的晶圓。
接著，如圖4(b)所示，將設於奈米壓印模5的辨識標記14與半導體元件1的辨識標記4進行對位。奈米壓印模5在平面視角下的外形尺寸比半導體元件1更大，例 如可為矩形形狀。
再來，如圖4(c)所示，將奈米壓印模5所具有之突起部5a壓附於抗蝕劑3，一邊在抗蝕劑3上形成開口，一邊使突起部5a與半導體元件1的電極墊2接觸(開口步驟)。此處，抗蝕劑3例如為凝膠狀且具有流動性。在奈米壓印模5上，以與電極墊2對向的方式，形成有複數個突起部5a。突起部5a的形狀可使用例如圓、四角形、八角形等的形狀。又，作為奈米壓印模5的加壓方式可使用例如輥壓法等。
之後，如圖4(d)所示，在將奈米壓印模5壓附於電極墊2的狀態下，使光線穿透奈米壓印模5而照射至抗蝕劑3後，進行加熱以使抗蝕劑3硬化(硬化步驟)。
接著，如圖4(e)所示，將奈米壓印模5拉起，藉此在抗蝕劑3中，於電極墊2上形成細微的開口部3a。
作為將奈米壓印模5拉起的方式可使用例如以下方法。以夾具保持矩形形狀之奈米壓印模5的一端後，在用壓板等壓住奈米壓印模5的狀態下，以恆定的張力拉動奈米壓印模5。再來，一邊使壓板的位置在水平方向上移動，一邊將奈米壓印模5的已保持之一端拉起，藉此可相對於半導體元件1將奈米壓印模5在垂直方向上拉起。此處，可藉由耐熱性脫模劑來對包含突起部5a之奈米壓印模5的表面實施脫模處理。加熱後會變得容易拉起。
之後，藉由在抗蝕劑3之開口部3a內注入顯影液6，將抗蝕劑3之開口部3a的內壁溶解，而擴展抗蝕劑 3之開口部3a。此處，若將顯影液6的液量進行管理，以不會超過抗蝕劑3之開口部3a之深度的方式來注入顯影液6，則接近半導體元件1的第1面的底部部分之抗蝕劑3就會因為重力而比抗蝕劑3的表層部分更容易溶解於顯影液6。因此，可形成具有底部部分比頭頂部更寬之錐狀開口部3a的抗蝕劑3。
接著，如圖4(g)所示，藉由洗淨液將進入抗蝕劑3之開口部3a的顯影液6、殘渣去除。例如，洗淨液可使用純水、醇、乙醇、丙酮等。
接著，如圖4(h)所示，將鍍敷液填充至抗蝕劑3之開口部3a內，藉由鍍敷來形成鍍敷凸塊8(鍍敷步驟)。鍍敷凸塊8可使用例如鹼性的倒置(bottom-up)型填充鍍敷。抗蝕劑的底部部分會因為鹼而比表層部分溶解更多，從而一邊使底部部分的擴展直徑進一步擴展，一邊使鍍敷以倒置方式來堆積。此處，抗蝕劑3之開口部3a的內壁的潤濕性提高，因此即使是微小尺寸的開口部3a，亦容易注入鍍敷液，從而以倒置方式來形成鍍敷。再來，如圖4(i)所示，將抗蝕劑3浸漬於抗蝕劑剝離液中，將抗蝕劑3從半導體元件1的第1面剝離(剝離步驟)。
最後，如圖4(j)所示，利用濕蝕刻或灰化處理將晶種層7去除，藉此形成具有錐狀台座部的凸塊8。
此處，在圖4(f)中，亦可不浸漬於大量的顯影液6，而是一邊旋轉半導體元件1，一邊滴下或噴射已計量過的顯影液6。可將填滿複數個開口部3a內之顯影液6的 量都保持定量，而可將溶解之抗蝕劑3的直徑穩定化。
又，從圖4(f)至圖4(g)的顯影方法亦可使用乾式法(dry process)。可減少步驟數，同時可將流入細微開口部之氣流的量穩定化，而可得到形狀穩定化的效果。
如上所述，使用實施形態3的話，將可穩定且高產量地形成更加微小且高縱橫比的細微鍍敷凸塊。
(在整體上)
上述實施形態可進行組合。特別是實施形態1與3可將一部分併入彼此。
產業上之可利用性
本發明是可穩定複數個細微突起狀凸塊形狀，並且高產量地生產的半導體裝置之製造方法及半導體裝置，在安裝邁向多接腳化、大口徑化的半導體元件的安裝領域中特別有用。
1:半導體元件
2:電極墊
3:抗蝕劑
3a:開口部
3b:開口部
5:奈米壓印模
5a:突起部
7:晶種層
8:凸塊
8a:頭頂部
8b:台座部
10:揮發性樹脂層

Claims (10)

  1. 一種半導體裝置之製造方法，具備：抗蝕劑步驟，對具有複數個電極墊之半導體元件的第1面，以覆蓋前述電極墊表面的方式來供給抗蝕劑；開口步驟，以使前述電極墊表面從前述抗蝕劑露出的方式來將前述電極墊表面上的前述抗蝕劑開口；硬化步驟，對前述抗蝕劑施加光或熱，將前述抗蝕劑硬化；鍍敷步驟，將鍍敷液填充至前述抗蝕劑的前述開口內，在前述電極墊表面上形成突起電極；及剝離步驟，將前述抗蝕劑從前述半導體元件的前述第1面剝離，在前述開口步驟中，將奈米壓印的轉印模加壓於前述抗蝕劑，前述轉印模會變形，而吸收前述半導體元件的翹曲、膨脹，藉此形成前述開口部。
  2. 如請求項1之半導體裝置之製造方法，其中前述奈米壓印是丙烯酸、聚矽氧、環氧之其中一者。
  3. 如請求項1或2之半導體裝置之製造方法，其中在前述開口步驟中，以使前述抗蝕劑之前述開口中的底部部分比入口部分更寬的方式來形成前述開口。
  4. 如請求項1或2之半導體裝置之製造方法，其中在前述抗蝕劑步驟之前，具有在前述電極墊表面上形成樹脂層的步驟，在前述抗蝕劑步驟中，以覆蓋已形成於前述電極墊表 面上之前述樹脂層的方式來對前述半導體元件的前述第1面供給前述抗蝕劑，在前述開口步驟中，以使前述電極墊表面露出的方式來將前述電極墊表面上的前述抗蝕劑及前述樹脂層去除，而形成前述開口。
  5. 如請求項4之半導體裝置之製造方法，其中在前述開口步驟中，以使前述樹脂層露出的方式來將前述樹脂層上的前述抗蝕劑開口後，透過前述開口將前述樹脂層去除，而在前述電極墊表面上形成前述抗蝕劑的前述開口。
  6. 如請求項1或2之半導體裝置之製造方法，其中在前述開口步驟中，於前述抗蝕劑的前述開口內注入不超過前述開口之深度的量的溶解液，將前述抗蝕劑之前述開口的內壁溶解，而使前述抗蝕劑之前述開口中的底部部分比入口部分更寬。
  7. 一種半導體裝置之製造方法，具備：抗蝕劑步驟，對具有複數個電極墊之半導體元件的第1面，在前述電極墊表面不塗布抗蝕劑，在前述電極墊間供給抗蝕劑，而在前述電極墊表面上形成前述抗蝕劑的開口；硬化步驟，對前述抗蝕劑施加光或熱，將前述抗蝕劑硬化；鍍敷步驟，將鍍敷液填充至前述抗蝕劑的前述開口內，在前述電極墊表面上形成突起電極；及 剝離步驟，將前述抗蝕劑從前述半導體元件的前述第1面剝離。
  8. 如請求項7之半導體裝置之製造方法，其中在前述抗蝕劑步驟中，藉由奈米壓印的轉印將第1抗蝕劑層配置於前述半導體元件的前述第1面後，以積層在前述第1抗蝕劑層上的方式來配置第2抗蝕劑層，前述第1抗蝕劑層在與前述電極墊表面對應的部分具有第1開口，前述第2抗蝕劑層具有尺寸比前述第1抗蝕劑層之前述第1開口更小的第2開口。
  9. 如請求項7之半導體裝置之製造方法，其中在前述抗蝕劑步驟中，只在奈米壓印之轉印模的突起塗上前述抗蝕劑，而供給前述抗蝕劑。
  10. 如請求項7之半導體裝置之製造方法，其中前述奈米壓印具有突起，且前述突起是包圍前述電極墊的形狀。
TW107142099A 2017-12-08 2018-11-26 半導體裝置之製造方法 TWI784089B (zh)

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JP7403083B2 (ja) * 2019-08-28 2023-12-22 パナソニックＩｐマネジメント株式会社 半導体装置、半導体装置の実装構造、及び半導体装置の製造方法
CN118103964A (zh) * 2021-10-14 2024-05-28 信越化学工业株式会社 受体基板、受体基板的制造方法、移载方法、led面板的制造方法和压模
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100029084A1 (en) * 2008-07-29 2010-02-04 Takeshi Koshiba Pattern forming method and pattern forming device
US20120040524A1 (en) * 2010-08-12 2012-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Process for making conductive post with footing profile
US20130341788A1 (en) * 2012-06-20 2013-12-26 Shinko Electric Industries Co., Ltd. Semiconductor device and method of manufacturing the same, and wiring substrate and method of manufacturing the same
US20140159235A1 (en) * 2012-12-06 2014-06-12 Fujitsu Limited Electronic component, electronic apparatus including the same, and manufacturing method of the electronic apparatus

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1805126C3 (de) 1968-10-25 1975-05-28 H. & E. Boergardts Kg, 3425 Walkenried Masse zur Herstellung von Arbeitsformen für die keramische Industrie
JPS5126485B2 (zh) 1971-08-12 1976-08-06
JP2000174048A (ja) * 1998-12-03 2000-06-23 Matsushita Electric Ind Co Ltd 突起電極形成方法および半導体装置
TW494548B (en) * 2000-08-25 2002-07-11 I-Ming Chen Semiconductor chip device and its package method
JP2002261111A (ja) * 2001-03-06 2002-09-13 Texas Instr Japan Ltd 半導体装置及びバンプ形成方法
JP4492330B2 (ja) * 2004-12-07 2010-06-30 パナソニック株式会社 電子部品実装構造体およびその製造方法
JP4716819B2 (ja) * 2005-08-22 2011-07-06 新光電気工業株式会社 インターポーザの製造方法
US7767574B2 (en) 2006-03-30 2010-08-03 Kabushiki Kaisha Mikuni Kogyo Method of forming micro metal bump
US9142533B2 (en) * 2010-05-20 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate interconnections having different sizes
US8823166B2 (en) * 2010-08-30 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar bumps and process for making same
US9425136B2 (en) * 2012-04-17 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US8994190B2 (en) * 2012-05-22 2015-03-31 Freescale Semiconductor, Inc. Low-temperature flip chip die attach
JP6130312B2 (ja) * 2014-02-10 2017-05-17 新光電気工業株式会社 半導体装置及びその製造方法
US9997482B2 (en) * 2014-03-13 2018-06-12 Taiwan Semiconductor Manufacturing Co., Ltd. Solder stud structure
US20150279793A1 (en) * 2014-03-27 2015-10-01 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
WO2017131831A2 (en) * 2015-11-05 2017-08-03 Massachusetts Institute Of Technology Qubit and coupler circuit structures and coupling techniques

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100029084A1 (en) * 2008-07-29 2010-02-04 Takeshi Koshiba Pattern forming method and pattern forming device
US20120040524A1 (en) * 2010-08-12 2012-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Process for making conductive post with footing profile
US20130341788A1 (en) * 2012-06-20 2013-12-26 Shinko Electric Industries Co., Ltd. Semiconductor device and method of manufacturing the same, and wiring substrate and method of manufacturing the same
US20140159235A1 (en) * 2012-12-06 2014-06-12 Fujitsu Limited Electronic component, electronic apparatus including the same, and manufacturing method of the electronic apparatus

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