TWI781846B

TWI781846B - Unbalanced plane management method, associated data storage device and controller thereof

Info

Publication number: TWI781846B
Application number: TW110145772A
Authority: TW
Inventors: 林翰宏
Original assignee: 慧榮科技股份有限公司
Priority date: 2019-03-04
Filing date: 2019-08-22
Publication date: 2022-10-21
Also published as: TW202213103A; TWI752784B; TW202034172A; TWI718635B; TW202125264A

Abstract

An unbalanced plane management method, an associated data storage device and the controller thereof are provided. The unbalanced plane management method may include: setting an unbalanced plane number; selecting at least one plane with a plane count obtained from subtracting the unbalanced plane number from a maximum plane number, and recording at least one set of blocks of the at least one plane to a block skip table; according to block numbers as indexes, combining blocks of unselected planes into super blocks, wherein said super blocks respectively correspond to said block numbers; and recording total capacity of all super blocks and the unbalanced plane number, to generate a latest record of records of multiple types of storage capacity, for further setting storage capacity configuration of the data storage device, wherein said all super blocks include said super blocks.

Description

非對稱型平面管理方法以及資料儲存裝置及其控制器 Asymmetric plane management method, data storage device and controller thereof

本發明係有關於快閃記憶體(Flash memory)之存取(access)，尤指一種非對稱型平面管理(Unbalanced Plane Management)方法以及資料儲存裝置及其控制器。 The present invention relates to flash memory (Flash memory) access, especially an asymmetric plane management (Unbalanced Plane Management) method, data storage device and its controller.

快閃記憶體可廣泛地應用於各種可攜式或非可攜式資料儲存裝置(例如：符合SD/MMC、CF、MS、XD或UFS標準之記憶卡；又例如：固態硬碟；又例如：符合UFS或EMMC規格之嵌入式(embedded)儲存裝置)中。以常用的NAND型快閃記憶體而言，最初有單階細胞(single level cell，SLC)、多階細胞(multiple level cell，MLC)等類型的快閃記憶體。由於記憶體的技術不斷地發展，較新的資料儲存裝置產品可採用三階細胞(triple level cell，TLC)快閃記憶體，甚至四階細胞(quadruple level cell，QLC)快閃記憶體。為了確保資料儲存裝置對快閃記憶體之存取控制能符合相關規範，快閃記憶體的控制器通常備有某些管理機制以妥善地管理其內部運作。 Flash memory can be widely used in various portable or non-portable data storage devices (for example: memory cards that meet SD/MMC, CF, MS, XD or UFS standards; another example: solid-state hard drives; another example : In an embedded storage device conforming to UFS or EMMC specifications). For the commonly used NAND flash memory, there are initially single level cell (SLC) and multiple level cell (MLC) types of flash memory. Due to the continuous development of memory technology, newer data storage device products can use triple level cell (TLC) flash memory, and even quadruple level cell (QLC) flash memory. In order to ensure that the access control of the data storage device to the flash memory complies with relevant regulations, the controller of the flash memory usually has some management mechanism to properly manage its internal operation.

依據相關技術，有了這些管理機制的資料儲存裝置還是有不足之處。舉例來說，多個快閃記憶體裸晶(Die)可被同時使用以提升存取效能。然而，某一個快閃記憶體裸晶的好區塊的數量可能限制這些快閃記憶體裸晶之各自的區塊的使用率。例如，在這些好區塊的數量很小、或者這些好區塊的分佈不平衡的情況下，無法得到需要的儲存容量。因此，需要一種新穎的方法及相關架構，以在沒有副作用或較不可能帶來副作用之狀況下實現具有可靠的管理機制之資料儲存裝置。 According to related technologies, the data storage devices with these management mechanisms still have deficiencies. For example, multiple flash memory Dies can be used simultaneously to improve access performance. However, the number of good blocks for a certain Flash die may limit the utilization of the respective blocks of the Flash die. For example, when the number of these good blocks is small, or the distribution of these good blocks is unbalanced, the required storage capacity cannot be obtained. Therefore, there is a need for a novel method and related framework to achieve reliable management with no side effects or less likely to cause side effects Mechanism data storage device.

本發明之一目的在於提供一種非對稱型平面管理方法以及相關之資料儲存裝置及其控制器，以解決上述問題。 An object of the present invention is to provide an asymmetric plane management method, a related data storage device and its controller, so as to solve the above problems.

本發明之另一目的在於提供一種非對稱型平面管理方法以及相關之資料儲存裝置及其控制器，以在沒有副作用或較不可能帶來副作用之狀況下將可靠的管理機制賦予資料儲存裝置。 Another object of the present invention is to provide an asymmetric planar management method and a related data storage device and its controller, so as to provide a reliable management mechanism to the data storage device without or less likely to cause side effects.

本發明之至少一實施例提供一種非對稱型平面管理方法，其中該非對稱型平面管理方法係應用於一資料儲存裝置，該資料儲存裝置包含一非揮發性記憶體(non-volatile memory，NV memory)，該非揮發性記憶體包含複數個非揮發性記憶體元件(NV memory element)，以及該複數個非揮發性記憶體元件包含複數個區塊。該非對稱型平面管理方法可包含：設定一非平衡平面數量(unbalanced plane number)，其中該非平衡平面數量小於一最大平面數量，且該最大平面數量代表該複數個非揮發性記憶體元件之各自的平面的數量的總和；選取該最大平面數量減去該非平衡平面數量的至少一平面，並將該至少一平面的至少一組區塊記錄至一區塊省略表(block skip table)；依據區塊編號為索引，將未選取的平面的區塊組成超級區塊，其中所述超級區塊分別對應於所述區塊編號；以及記錄全部超級區塊的總容量以及該非平衡平面數量，以產生多種儲存容量的記錄中的一最新的記錄，以供進一步設定該資料儲存裝置的儲存容量組態，其中所述全部超級區塊包含所述超級區塊。 At least one embodiment of the present invention provides an asymmetric plane management method, wherein the asymmetric plane management method is applied to a data storage device, and the data storage device includes a non-volatile memory (non-volatile memory, NV memory ), the non-volatile memory includes a plurality of non-volatile memory elements (NV memory elements), and the plurality of non-volatile memory elements includes a plurality of blocks. The asymmetric plane management method may include: setting an unbalanced plane number (unbalanced plane number), wherein the unbalanced plane number is less than a maximum plane number, and the maximum plane number represents each of the plurality of non-volatile memory elements The sum of the number of planes; selecting at least one plane of the maximum number of planes minus the number of unbalanced planes, and recording at least one group of blocks of the at least one plane into a block skip table; according to the block The number is used as an index, and the blocks of the unselected planes are composed into super blocks, wherein the super blocks correspond to the block numbers respectively; and the total capacity of all super blocks and the number of unbalanced planes are recorded to generate various A newest record among the records of storage capacity is used for further setting the storage capacity configuration of the data storage device, wherein all the superblocks include the superblock.

本發明之至少一實施例提供一種資料儲存裝置，其可包含：一非揮發性記憶體，用來儲存資訊，其中該非揮發性記憶體包含複數個非揮發性記憶體元件，以及該複數個非揮發性記憶體元件包含複數個區塊；以及一控制器，耦接至該非揮發性記憶體，用來控制該資料儲存裝置之操作。該控制器可包含一處理電路，其中該處理電路可依據來自一主機(host device)的複數個主機命令(host command)控制該控制器，以容許該主機透過該控制器存取該非揮發性記憶體。例如：該控制器設定一非平衡平面數量，其中該非平衡平面數量小於一最大平面數量，且該最大平面數量代表該複數個非揮發性記憶體元件之各自的平面的數量的總和；該控制器選取該最大平面數量減去該非平衡平面數量的至少一平面，並將該至少一平面的至少一組區塊記錄至一區塊省略表；該控制器依據區塊編號為索引，將未選取的平面的區塊組成超級區塊，其中所述超級區塊分別對應於所述區塊編號；以及該控制器記錄全部超級區塊的總容量以及該非平衡平面數量，以產生多種儲存容量的記錄中的一最新的記錄，以供進一步設定該資料儲存裝置的儲存容量組態，其中所述全部超級區塊包含所述超級區塊。 At least one embodiment of the present invention provides a data storage device, which may include: a non-volatile memory for storing information, wherein the non-volatile memory includes a plurality of non-volatile memory elements, and the plurality of non-volatile memory elements The volatile memory element includes a plurality of blocks; and a controller, Coupled to the non-volatile memory, used to control the operation of the data storage device. The controller can include a processing circuit, wherein the processing circuit can control the controller according to a plurality of host commands (host commands) from a host (host device), so as to allow the host to access the non-volatile memory through the controller body. For example: the controller sets an unbalanced plane number, wherein the unbalanced plane number is less than a maximum plane number, and the maximum plane number represents the sum of the respective plane numbers of the plurality of non-volatile memory elements; the controller Selecting at least one plane of the maximum number of planes minus the number of unbalanced planes, and recording at least one group of blocks of the at least one plane into a block omission table; the controller indexes the unselected Blocks of planes form super blocks, wherein the super blocks respectively correspond to the block numbers; and the controller records the total capacity of all super blocks and the number of unbalanced planes to generate records of various storage capacities A latest record for further setting the storage capacity configuration of the data storage device, wherein all the superblocks include the superblock.

本發明之至少一實施例提供一種資料儲存裝置之控制器，其中該資料儲存裝置包含該控制器與一非揮發性記憶體，該非揮發性記憶體包含複數個非揮發性記憶體元件，以及該複數個非揮發性記憶體元件包含複數個區塊。該控制器可包含一處理電路，其中該處理電路可依據來自一主機的複數個主機命令控制該控制器，以容許該主機透過該控制器存取該非揮發性記憶體。例如：該控制器設定一非平衡平面數量，其中該非平衡平面數量小於一最大平面數量，且該最大平面數量代表該複數個非揮發性記憶體元件之各自的平面的數量的總和；該控制器選取該最大平面數量減去該非平衡平面數量的至少一平面，並將該至少一平面的至少一組區塊記錄至一區塊省略表；該控制器依據區塊編號為索引，將未選取的平面的區塊組成超級區塊，其中所述超級區塊分別對應於所述區塊編號；以及該控制器記錄全部超級區塊的總容量以及該非平衡平面數量，以產生多種儲存容量的記錄中的一最新的記錄，以供進一步設定該資料儲存裝置的儲存容量組態，其中所述全部超級區塊包含所述超級區塊。 At least one embodiment of the present invention provides a controller for a data storage device, wherein the data storage device includes the controller and a non-volatile memory, the non-volatile memory includes a plurality of non-volatile memory elements, and the The plurality of non-volatile memory elements comprise a plurality of blocks. The controller can include a processing circuit, wherein the processing circuit can control the controller according to a plurality of host commands from a host to allow the host to access the non-volatile memory through the controller. For example: the controller sets an unbalanced plane number, wherein the unbalanced plane number is less than a maximum plane number, and the maximum plane number represents the sum of the respective plane numbers of the plurality of non-volatile memory elements; the controller Selecting at least one plane of the maximum number of planes minus the number of unbalanced planes, and recording at least one group of blocks of the at least one plane into a block omission table; the controller indexes the unselected Blocks of planes form super blocks, wherein the super blocks respectively correspond to the block numbers; and the controller records the total capacity of all super blocks and the number of unbalanced planes to generate records of various storage capacities An up-to-date record for further configuration of the data The storage capacity configuration of the storage device, wherein all the superblocks include the superblock.

本發明的好處之一是，透過仔細設計之管理機制，本發明能針對該控制器的運作進行妥善的控制，尤其，使資料儲存裝置能利用不平衡平面的方式，例如，使用在超級區塊(Super Block)內可更改的數量的平面而不是使用全部數量的平面。於是，本發明能打破關於NAND型快閃記憶體的好區塊的數量的限制，以整合出最大的容量；或是，在特定的容量需求下，有效地整合出充足的超級區塊，達到最佳化效能。另外，依據本發明之實施例來實施並不會增加許多額外的成本。因此，相關技術的問題可被解決，且整體成本不會增加太多。相較於傳統架構，本發明能在沒有副作用或較不可能帶來副作用之狀況下達到資料儲存裝置之最佳化效能。 One of the advantages of the present invention is that, through a carefully designed management mechanism, the present invention can properly control the operation of the controller, especially, enabling data storage devices to utilize unbalanced planes, for example, in superblocks Changeable number of planes within (Super Block) instead of using the full number of planes. Therefore, the present invention can break the restriction on the number of good blocks of NAND flash memory to integrate the maximum capacity; or, under a specific capacity requirement, effectively integrate enough super blocks to achieve Optimize performance. In addition, the implementation according to the embodiments of the present invention does not add much extra cost. Therefore, the problems of the related art can be solved without increasing the overall cost too much. Compared with the traditional structure, the present invention can achieve the optimal performance of the data storage device without or less likely to cause side effects.

50:主機 50: Host

100:資料儲存裝置 100: data storage device

110:記憶體控制器 110: Memory controller

112:微處理器 112: Microprocessor

112C:程式碼 112C: code

112M:唯讀記憶體 112M: read-only memory

114:控制邏輯電路 114: Control logic circuit

116:緩衝記憶體 116: buffer memory

118:傳輸介面電路 118: Transmission interface circuit

120:非揮發性記憶體 120: Non-volatile memory

122,122-1,122-2~122-N:非揮發性記憶體元件 122,122-1,122-2~122-N: non-volatile memory components

0-0~0-199,1-0~1-199,2-0~2-199,3-0~3-199,4-0~4-199,5-0~5-199,6-0~6-199,7-0~7-199:區塊索引 0-0~0-199,1-0~1-199,2-0~2-199,3-0~3-199,4-0~4-199,5-0~5-199,6- 0~6-199,7-0~7-199: block index

S10,S12,S14,S16,S18,S20,S22:步驟 S10, S12, S14, S16, S18, S20, S22: steps

ORPHAN_BLOCK_TABLE:孤兒區塊表 ORPHAN_BLOCK_TABLE: Orphan block table

BLOCKSKIPIDX:區塊省略索引 BLOCKSKIPIDX: block skip index

第1圖為依據本發明一實施例之一種資料儲存裝置與一主機(host device)的示意圖。 FIG. 1 is a schematic diagram of a data storage device and a host device according to an embodiment of the present invention.

第2圖繪示針對超級區塊的一管理方案的示意圖。 FIG. 2 shows a schematic diagram of a management scheme for superblocks.

第3圖繪示依據本發明一實施例之一超級區塊管理方案。 FIG. 3 illustrates a superblock management scheme according to an embodiment of the present invention.

第4圖繪示壞區塊分佈的一個例子。 Figure 4 shows an example of bad block distribution.

第5圖繪示依據本發明另一實施例之一超級區塊管理方案。 FIG. 5 illustrates a superblock management scheme according to another embodiment of the present invention.

第6圖繪示依據本發明一實施例之一種非對稱型平面管理方法的一工作流程。 FIG. 6 shows a workflow of an asymmetric plane management method according to an embodiment of the present invention.

請參考第1圖，第1圖為依據本發明一第一實施例之一種資料儲存裝置100與一主機(Host Device)50的示意圖。例如：資料儲存裝置100可為固態硬碟(Solid State Drive，SSD)。另外，主機50的例子可包含(但不限於)：多功能行動電話(Multifunctional Mobile Phone)、平板電腦(Tablet)、以及個人電腦(Personal Computer)諸如桌上型電腦與膝上型電腦。依據本實施例，資料儲存裝置100可包含一控制器諸如記憶體控制器110，且可另包含非揮發性(Non-Volatile)記憶體120，其中該控制器係用來存取(Access)非揮發性記憶體120，且非揮發性記憶體120係用來儲存資訊。 Please refer to FIG. 1 , which is a schematic diagram of a data storage device 100 and a host (Host Device) 50 according to a first embodiment of the present invention. For example: the data storage device 100 can be a solid state Hard disk (Solid State Drive, SSD). In addition, examples of the host 50 may include (but not limited to): multifunctional mobile phones, tablet computers, and personal computers such as desktop computers and laptop computers. According to this embodiment, the data storage device 100 may include a controller such as a memory controller 110, and may further include a non-volatile (Non-Volatile) memory 120, wherein the controller is used to access (Access) non-volatile The volatile memory 120 and the non-volatile memory 120 are used to store information.

非揮發性記憶體120可包含複數個非揮發性記憶體元件122-1、122-2、...與122-N，其中符號「N」可代表大於一的正整數。例如：非揮發性記憶體120可為快閃記憶體(Flash memory)，而非揮發性記憶體元件122-1、122-2、...與122-N可分別為複數個快閃記憶體晶片或複數個快閃記憶體裸晶，但本發明並不限於此。此外，資料儲存裝置100可以還包括揮發性記憶體元件以緩存資料，其中，揮發性記憶體元件較佳為動態隨機存取記憶體(Dynamic Random Access Memory，DRAM)。上述揮發性記憶體元件可提供適當的資料暫存空間以緩存資料，或是僅提供小量的資料暫存空間以緩存小量資料，此架構又稱為部分DRAM(Partial DRAM)。另外，揮發性記憶體元件為非必要元件。 The non-volatile memory 120 may include a plurality of non-volatile memory elements 122-1, 122-2, . . . and 122-N, wherein the symbol "N" may represent a positive integer greater than one. For example: the non-volatile memory 120 can be a flash memory (Flash memory), and the non-volatile memory elements 122-1, 122-2, . . . and 122-N can be a plurality of flash memories respectively. A wafer or a plurality of flash memory dies, but the invention is not limited thereto. In addition, the data storage device 100 may further include a volatile memory element for caching data, wherein the volatile memory element is preferably a Dynamic Random Access Memory (DRAM). The above-mentioned volatile memory components can provide appropriate temporary data storage space to cache data, or only provide a small amount of temporary data storage space to cache a small amount of data. This structure is also called partial DRAM (Partial DRAM). In addition, the volatile memory components are optional.

記憶體控制器110可包含處理電路諸如微處理器112、儲存器諸如唯讀記憶體(Read Only Memory，ROM)112M、控制邏輯電路114、緩衝記憶體116、與傳輸介面電路118，其中這些元件可透過匯流排彼此耦接。緩衝記憶體116較佳為靜態隨機存取記憶體(Static Random Access Memory，SRAM)。舉例來說，如果資料儲存裝置100更配置有上述DRAM，記憶體控制器110可利用緩衝記憶體116諸如SRAM作為第一層快取(Cache)，並利用DRAM作為第二層快取。DRAM的資料儲存量較佳大於緩衝記憶體116的資料儲存量，而緩衝記憶體116所緩衝處理的資料可源自於DRAM或非揮發性記憶體120。 The memory controller 110 may include a processing circuit such as a microprocessor 112, a storage such as a read-only memory (Read Only Memory, ROM) 112M, a control logic circuit 114, a buffer memory 116, and a transmission interface circuit 118, wherein these elements can be coupled to each other through bus bars. The buffer memory 116 is preferably a static random access memory (Static Random Access Memory, SRAM). For example, if the data storage device 100 is further configured with the above-mentioned DRAM, the memory controller 110 can use the buffer memory 116 such as SRAM as a first-level cache (Cache), and use DRAM as a second-level cache. The data storage capacity of the DRAM is preferably larger than the data storage capacity of the buffer memory 116 , and the data buffered by the buffer memory 116 can be derived from the DRAM or the non-volatile memory 120 .

本實施例之唯讀記憶體112M係用來儲存程式碼112C，而微處理器 112則用來執行程式碼112C以控制對非揮發性記憶體120之存取。請注意，程式碼112C亦得儲存在緩衝記憶體116或任何形式之記憶體內。此外，控制邏輯電路114可包含至少一錯誤更正碼(Error Correction Code，ECC)電路(未顯示)，以保護資料、及/或進行錯誤更正，而傳輸介面電路118可符合特定通訊標準(諸如串列高級技術附件(Serial Advanced Technology Attachment，SATA)標準、快捷外設互聯(Peripheral Component Interconnect Express，PCIE)標準或非揮發性記憶體快捷(Non-Volatile Memory Express，NVME)標準且可依據特定通訊標對主機50進行通訊。 The ROM 112M of the present embodiment is used to store the program code 112C, and the microprocessor 112 is used to execute program code 112C to control access to non-volatile memory 120 . Note that program code 112C may also be stored in cache memory 116 or any form of memory. In addition, the control logic circuit 114 may include at least one error correction code (Error Correction Code, ECC) circuit (not shown) to protect data and/or perform error correction, and the transmission interface circuit 118 may conform to a specific communication standard (such as serial Advanced Technology Attachment (Serial Advanced Technology Attachment, SATA) standard, Peripheral Component Interconnect Express (PCIE) standard or Non-Volatile Memory Express (Non-Volatile Memory Express, NVME) standard and can be based on specific communication standards communicate with the host computer 50 .

於本實施例中，主機50可傳送複數個主機命令(Host Command)至資料儲存裝置100，記憶體控制器110再依據主機命令而對非揮發性記憶體120進行存取(例如讀取或寫入資料)，其中上述資料較佳為源自於主機50之使用者資料。主機命令包括邏輯位址，例如：邏輯區塊位址(Logical Block Address，LBA)。記憶體控制器110可接收主機命令並將主機命令分別轉譯成記憶體操作命令(簡稱操作命令)，再以操作命令控制非揮發性記憶體120讀取、寫入(Write)/編程(Program)非揮發性記憶體120當中特定實體位址之頁面(Page)。 In this embodiment, the host 50 can send a plurality of host commands (Host Command) to the data storage device 100, and the memory controller 110 then accesses the non-volatile memory 120 according to the host command (such as reading or writing) input data), wherein the above-mentioned data is preferably derived from the user data of the host 50. The host command includes a logical address, such as a logical block address (Logical Block Address, LBA). The memory controller 110 can receive host commands and translate the host commands into memory operation commands (referred to as operation commands), and then use the operation commands to control the non-volatile memory 120 to read, write (Write)/program (Program) A page (Page) of a specific physical address in the non-volatile memory 120 .

記憶體控制器110將資料的邏輯位址與實體位址之間的映射關係記錄於邏輯對實體位址(Logical-to-Physical Address，L2P)映射表，其中，實體位址可由通道(Channel)編號、邏輯單元編號(Logical Unit Number，LUN)、平面(Plane)編號、區塊編號、頁面編號以及偏移量(Offset)所組成。於某些實施例中，實體位址的實施可予以變化。例如，實體位址可包含通道編號、邏輯單元編號、平面編號、區塊編號、頁面編號、及/或偏移量。 The memory controller 110 records the mapping relationship between the logical address and the physical address of the data in a logical-to-physical address (Logical-to-Physical Address, L2P) mapping table, wherein the physical address can be determined by a channel (Channel) Number, logical unit number (Logical Unit Number, LUN), plane (Plane) number, block number, page number, and offset (Offset). In some embodiments, the implementation of the physical address may vary. For example, physical addresses may include channel numbers, LUN numbers, plane numbers, block numbers, page numbers, and/or offsets.

L2P映射表可儲存於非揮發性記憶體120中之系統區塊中，且可分割成多個群組(Group)映射表，每一群組映射表記錄一段邏輯位址的映射關係。系統區塊較佳為加密區塊且以SLC模式進行資料的編程。記憶體控制器110可依緩衝記憶體116的容量大小而將該多個群組映射表中的一部分或全部群組映射表從非揮發性記憶體120載入緩衝記憶體116，以供快速參考，但本發明不限於此。當使用者資料更新時，記憶體控制器110可依據使用者資料的最新映射關係來更新群組映射表的內容。群組映射表的大小較佳不大於非揮發性記憶體元件122-n的一個頁面(Page)的大小，例如16KB(kilobytes；千位元組)，其中符號「n」可代表區間[1,N]中之任一正整數，但本發明不限於此。例如，群組映射表的大小可為4KB或1KB。 The L2P mapping table can be stored in the system block of the non-volatile memory 120, and can be divided into multiple group mapping tables, and each group mapping table records a mapping relationship of a logical address. The system block is preferably an encrypted block and data is programmed in SLC mode. The memory controller 110 can depend on According to the capacity of the buffer memory 116, some or all of the group mapping tables are loaded from the non-volatile memory 120 into the buffer memory 116 for quick reference, but the present invention is not limited thereto . When the user data is updated, the memory controller 110 can update the content of the group mapping table according to the latest mapping relationship of the user data. The size of the group mapping table is preferably not greater than the size of a page (Page) of the non-volatile memory element 122-n, such as 16KB (kilobytes; thousand bytes), wherein the symbol "n" can represent the interval [1, any positive integer in N], but the present invention is not limited thereto. For example, the size of the group mapping table can be 4KB or 1KB.

非揮發性記憶體元件122-n可包含多個平面(Planes)，諸如平面#0、#1、#2與#3，每一個平面包含多個區塊，每一區塊包含多個頁面。在此情況下，記憶體控制器110可將平面#0~#3之各自一個區塊組合成一個大區塊，則大區塊的大小等於一個區塊的大小的4倍。 The non-volatile memory device 122-n may include multiple planes, such as planes #0, #1, #2, and #3, each plane includes multiple blocks, and each block includes multiple pages. In this case, the memory controller 110 can combine each block of the planes #0-#3 into a large block, and the size of the large block is equal to 4 times the size of a block.

記憶體控制器110可將多個通道，例如2個通道CH#0與CH#1，中各自的一個非揮發性記憶體元件122-n之各自的一個大區塊可組合成一個超級區塊(Super Block，SB)，則超級區塊的大小等於一個區塊的大小的8倍，且此2個非揮發性記憶體元件122-n可由同一晶片啟用(Chip Enable，CE)訊號所控制，但本發明不限於此。例如，在通道數量等於4的設定下，諸如通道CH#0~CH#3，通道CH#0~CH#3中的各自的一個非揮發性記憶體元件之各自的一個大區塊亦可組成一個超級區塊，亦可由一個晶片啟用訊號所控制。 The memory controller 110 can combine a large block of a non-volatile memory element 122-n in multiple channels, such as two channels CH#0 and CH#1, into a super block (Super Block, SB), then the size of the super block is equal to 8 times the size of a block, and the two non-volatile memory elements 122-n can be controlled by the same chip enabling (Chip Enable, CE) signal, But the present invention is not limited thereto. For example, under the setting that the number of channels is equal to 4, such as channels CH#0~CH#3, each of a non-volatile memory element in channels CH#0~CH#3 can also be composed of a large block A super block can also be controlled by a chip enable signal.

第2圖繪示針對超級區塊的一管理方案的示意圖。非揮發性記憶體元件122-1、122-2、...與122-N可實施成複數個快閃記憶體裸晶，諸如裸晶#0與#1，其中裸晶#0與#1可作為上述2個通道CH#0與CH#1中各自的一個非揮發性記憶體元件122-n，並以此架構為例說明超級區塊的組成。裸晶#0可具有4個平面，因此，裸晶#0中的區塊可由4組區塊索引(Block Index)來表示，例如其區塊索引{0-0,0-1,...,0-199}、{1-0,1-1,...,1-199}、{2-0,2-1,...,2-199}與{3-0,3-1,...,3-199}。相仿地，裸晶#1亦可具有4個平面，因此，裸晶#1中的區塊亦可由4組區塊索引來表示，例如其區塊索引{0-0,0-1,...,0-199}、{1-0,1-1,...,1-199}、{2-0,2-1,...,2-199}與{3-0,3-1,...,3-199}。 FIG. 2 shows a schematic diagram of a management scheme for superblocks. The non-volatile memory elements 122-1, 122-2, . It can be used as a non-volatile memory element 122-n in each of the above two channels CH#0 and CH#1, and this structure is taken as an example to illustrate the composition of the super block. Die #0 can have 4 planes, therefore, the blocks in die #0 can be represented by 4 sets of block indexes (Block Index), for example, its block index {0-0,0-1,... ,0-199}, {1-0,1-1,...,1-199}, {2-0,2-1,...,2-199} and {3-0,3-1 ,...,3-199}. Similarly, Die #1 can also have 4 planes, therefore, blocks in Die #1 can also be represented by 4 sets of block indices, for example, its block indices {0-0,0-1, .. .,0-199}, {1-0,1-1,...,1-199}, {2-0,2-1,...,2-199} and {3-0,3- 1,...,3-199}.

當組成超級區塊時，裸晶#0~#1可分別置於通道CH#0與CH#1，如此一來，超級區塊中的區塊可由區塊索引來表示，例如具有區塊索引格式[Die#,PLN#,BLK#]的8組區塊索引{[0,0,0],[0,0,1],...,[0,0,199]}、{[0,1,0],[0,1,1],...,[0,1,199]}、{[0,2,0],[0,2,1],...,[0,2,149]}、{[0,3,0],[0,3,1],...,[0,3,199]}、{[1,4,0],[1,4,1],...,[1,4,199]}、{[1,5,0],[1,5,1],...,[1,5,199]}、{[1,6,0],[1,6,1],...,[1,6,199]}以及{[1,7,0],[1,7,1],...,[1,7,199]}，並且在區塊索引格式[Die#,PLN#,BLK#]中的Die#、PLN#與BLK#分別代表裸晶編號、平面編號與區塊編號，其中，裸晶編號與平面編號較佳為累進值(例如具有固定增量的一系列數值)，有時裸晶編號會以通道編號來替代。另外，在上述架構中，由於超級區塊中的區塊來自八個平面，此種超級區塊又可稱為八平面超級區塊或平衡平面架構。 When forming a super block, bare dies #0~#1 can be placed in channels CH#0 and CH#1 respectively, so that the blocks in the super block can be represented by block index, for example, have a block index 8 sets of block indexes {[0,0,0],[0,0,1],...,[0,0,199]}, {[0,1] in the format [Die#,PLN#,BLK#] ,0],[0,1,1],...,[0,1,199]}, {[0,2,0],[0,2,1],...,[0,2,149]} , {[0,3,0],[0,3,1],...,[0,3,199]}, {[1,4,0],[1,4,1],..., [1,4,199]}, {[1,5,0],[1,5,1],...,[1,5,199]}, {[1,6,0],[1,6,1 ],...,[1,6,199]} and {[1,7,0],[1,7,1],...,[1,7,199]}, and in block index format [Die# , PLN#, BLK#] in Die#, PLN# and BLK# represent die number, plane number and block number respectively, wherein, die number and plane number are preferably progressive values (for example, with a fixed increment A series of values), sometimes the die number is replaced by the channel number. In addition, in the above architecture, since the blocks in the super block come from eight planes, this kind of super block can also be called an eight-plane super block or balanced plane architecture.

假設在理想情況下，裸晶#0與#1之各自的平面#0~#3可具有相同數量的好區塊(Good Block)，例如200個好區塊，即區塊#0~#199都是好區塊，沒有一個是壞區塊(Bad Block)。於是，在理想情況下，記憶體控制器110可將裸晶#0與#1中的平面#0~#3之相同區塊編號的區塊組合成超級區塊，因此，可組合成200個超級區塊。由於所有的區塊都是好區塊，記憶體控制器110在此情況下可以組合最多數量的超級區塊，因此，資料儲存裝置100(例如SSD)可以提供理想的儲存容量。假設每一裸晶的儲存容量為64GB(Gigabytes；十億位元組)，，資料儲存裝置100可以提供128GB的儲存容量。由於裸晶中的區塊被組合成超級區塊，因此，資料儲存裝置100可以提供理想(較佳)的存取效能。 Assume that under ideal conditions, the respective planes #0~#3 of die #0 and #1 can have the same number of good blocks (Good Block), for example, 200 good blocks, that is, blocks #0~#199 All are good blocks, none of them are bad blocks. Therefore, in an ideal situation, the memory controller 110 can combine the blocks with the same block numbers of the planes #0~#3 in the die #0 and #1 into a super block, so 200 blocks can be combined super block. Since all the blocks are good blocks, the memory controller 110 can combine the maximum number of super blocks in this case, so the data storage device 100 (such as SSD) can provide ideal storage capacity. Assuming that the storage capacity of each die is 64GB (Gigabytes; one billion bytes), the data storage device 100 can provide a storage capacity of 128GB. Since the blocks in the die are combined into super blocks, the data storage device 100 can provide ideal (better) access performance.

然而，在真實情況下，裸晶通常包括一部分的壞區塊。例如，裸晶 #0的平面#2的區塊#150~#199都是壞區塊，如符號「X」所示。於是，在真實情況下，記憶體控制器110將裸晶#0與#1中的平面#0~#3之相同區塊編號的區塊組合成超級區塊，如第2圖下半部中的超級區塊索引(Super Block Index){0,1,...,149}所示，其中，第2圖左下角所示區塊索引{0-0,0-1,...,0-149}、{1-0,1-1,...,1-149}、{2-0,2-1,...,2-149}與{3-0,3-1,...,3-149}可代表裸晶#0的區塊索引{0-0,0-1,...,0-149}、{1-0,1-1,...,1-149}、{2-0,2-1,...,2-149}與{3-0,3-1,...,3-149}，而第2圖右下角所示區塊索引{4-0,4-1,...,4-149}、{5-0,5-1,...,5-149}、{6-0,6-1,...,6-149}與{7-0,7-1,...,7-149}可代表裸晶#1的區塊索引{0-0,0-1,...,0-149}、{1-0,1-1,...,1-149}、{2-0,2-1,...,2-149}與{3-0,3-1,...,3-149}。在真實情況下，記憶體控制器110僅能組合成150個超級區塊，資料儲存裝置100僅能提供96GB(例如(128*(150/200))=96)的儲存容量，至於未組合至超級區塊的剩餘區塊，例如：裸晶#0的平面#0、#1以及#3的區塊#150~#199，裸晶#1的平面#0~#3的區塊#150~#199，則作為預留空間(Over-provisioning)，無法成為資料儲存裝置100的儲存容量。 However, in a real situation, the die usually includes a portion of bad blocks. For example, bare die Blocks #150~#199 of plane #2 of #0 are all bad blocks, as indicated by the symbol "X". Therefore, in a real situation, the memory controller 110 combines the blocks with the same block numbers of the planes #0~#3 in the die #0 and #1 into a super block, as shown in the lower half of FIG. 2 The Super Block Index (Super Block Index) {0,1,...,149} shown in Figure 2, where the block index {0-0,0-1,...,0 shown in the lower left corner of Figure 2 -149}, {1-0,1-1,...,1-149}, {2-0,2-1,...,2-149} and {3-0,3-1,. ...,3-149} can represent the block index {0-0,0-1,...,0-149}, {1-0,1-1,...,1- 149}, {2-0,2-1,...,2-149} and {3-0,3-1,...,3-149}, and the block index shown in the lower right corner of Figure 2 {4-0,4-1,...,4-149}, {5-0,5-1,...,5-149}, {6-0,6-1,...,6 -149} and {7-0,7-1,...,7-149} can represent the block index {0-0,0-1,...,0-149}, { 1-0,1-1,...,1-149}, {2-0,2-1,...,2-149} and {3-0,3-1,...,3- 149}. In a real situation, the memory controller 110 can only be combined into 150 super blocks, and the data storage device 100 can only provide a storage capacity of 96GB (for example (128*(150/200))=96). The remaining blocks of the super block, for example: block #150~#199 of plane #0, #1 and #3 of die #0, block #150~ of plane #0~#3 of die #1 #199, as over-provisioning, cannot be used as the storage capacity of the data storage device 100 .

為了克服上述問題，本發明提供一種非對稱型平面管理(Unbalanced Plane Management)方法，其可在資料儲存裝置100進行儲存容量檢測而無法達到容量閾值，例如：100GB，的情況下，開發出不同的儲存容量，使資料儲存裝置100的儲存容量可以超過容量閾值，達到本發明的目的。而本發明非對稱型平面管理方法不局限於將每一平面之一個區塊整合至一個超級區塊中，尤其，可依據真實情況下的需求來彈性地調整超級區塊的組合，或是調整平面的個數以組成超級區塊。舉例來說，當使用本發明非對稱型平面管理方法來管理裸晶#0與#1時，超級區塊可由八個平面中的七個平面的區塊的組合來形成，如第3圖所示，其中，區塊索引{0-0,0-1,...,0-199}、{1-0,1-1,...,1-199}、{2-0,2-1,...,2-149}與{3-0,3-1,...,3-199}可代表裸晶#0的區塊索引{0-0,0-1,...,0-199}、{1-0,1-1,..., 1-199}、{2-0,2-1,...,2-149}與{3-0,3-1,...,3-199}，而區塊索引{4-0,4-1,...,4-199}、{5-0,5-1,...,5-199}、{6-0,6-1,...,6-199}與{7-0,7-1,...,7-199}可代表裸晶#1的區塊索引{0-0,0-1,...,0-199}、{1-0,1-1,...,1-199}、{2-0,2-1,...,2-199}與{3-0,3-1,...,3-199}。於是，可以產生較多的超級區塊，例如：由原本的150個超級區塊增加為200個超級區塊，且，可以增加資料儲存裝置100的儲存容量，例如：資料儲存裝置100的儲存容量從96GB增加為112GB(例如(128*(7/8))=112)，以成功地達成本發明的目的。 In order to overcome the above-mentioned problems, the present invention provides an asymmetric plane management (Unbalanced Plane Management) method, which can develop different planar management methods when the storage capacity of the data storage device 100 fails to reach the capacity threshold, such as 100GB. The storage capacity enables the storage capacity of the data storage device 100 to exceed a capacity threshold, thereby achieving the purpose of the present invention. However, the asymmetric plane management method of the present invention is not limited to integrating one block of each plane into a super block, especially, the combination of super blocks can be flexibly adjusted according to the actual needs, or the adjustment The number of planes to form a superblock. For example, when using the asymmetric plane management method of the present invention to manage die #0 and #1, the super block can be formed by combining blocks of seven planes out of eight planes, as shown in FIG. 3 , where block indices {0-0,0-1,...,0-199}, {1-0,1-1,...,1-199}, {2-0,2- 1,...,2-149} and {3-0,3-1,...,3-199} can represent the block index {0-0,0-1,... of die #0 ,0-199}, {1-0,1-1,..., 1-199}, {2-0,2-1,...,2-149} and {3-0,3-1,...,3-199}, while the block index {4-0, 4-1,...,4-199}, {5-0,5-1,...,5-199}, {6-0,6-1,...,6-199} and { 7-0,7-1,...,7-199} can represent block index {0-0,0-1,...,0-199}, {1-0,1 -1,...,1-199}, {2-0,2-1,...,2-199} and {3-0,3-1,...,3-199}. Thus, more super blocks can be generated, for example: from the original 150 super blocks to 200 super blocks, and the storage capacity of the data storage device 100 can be increased, for example: the storage capacity of the data storage device 100 Increase from 96GB to 112GB (eg (128*(7/8))=112), to successfully achieve the purpose of the present invention.

在另一個真實情況下，如第4圖所示，裸晶#0的平面#2的區塊#150~#199都是壞區塊，裸晶#1的平面#2的區塊#180~#199都是壞區塊，因此，資料儲存裝置100僅能提供96GB的儲存容量。當採用本發明一種非對稱型平面管理方法時，將超級區塊由八個平面中的七個平面的區塊來組合，如第5圖所示，其中，區塊索引{0-0,0-1,...,0-199}、{1-0,1-1,...,1-199}、{2-0,2-1,...,2-149}與{3-0,3-1,...,3-199}可代表裸晶#0的區塊索引{0-0,0-1,...,0-199}、{1-0,1-1,...,1-199}、{2-0,2-1,...,2-149}與{3-0,3-1,...,3-199}，而區塊索引{4-0,4-1,...,4-199}、{5-0,5-1,...,5-199}、{6-0,6-1,...,6-179}與{7-0,7-1,...,7-199}可代表裸晶#1的區塊索引{0-0,0-1,...,0-199}、{1-0,1-1,...,1-199}、{2-0,2-1,...,2-179}與{3-0,3-1,...,3-199}。屬於超級區塊#0~#179的一大部分區塊可由裸晶#0的平面#0、#1與#3以及裸晶#1的平面#0~#3之各自的區塊#0~#179所組成，而屬於超級區塊#180~#199的另一部分區塊可改由裸晶#0與#1之各自的平面#0、#1與#3之各自的區塊#180~#199以及裸晶#0的平面#2的區塊#0~#19(如虛線框所示)所組成，一樣可以組成200個超級區塊，使資料儲存裝置100的儲存容量從96GB增加為112GB，以成功地達成本發明的目的。 In another real situation, as shown in Figure 4, blocks #150~#199 of plane #2 of die #0 are all bad blocks, and blocks #180~#199 of plane #2 of die #1 #199 are all bad blocks, therefore, the data storage device 100 can only provide a storage capacity of 96GB. When using an asymmetric plane management method of the present invention, the super block is combined by blocks of seven planes in eight planes, as shown in Figure 5, wherein the block index {0-0,0 -1,...,0-199}, {1-0,1-1,...,1-199}, {2-0,2-1,...,2-149} and {3 -0,3-1,...,3-199} can represent the block index {0-0,0-1,...,0-199}, {1-0,1- 1,...,1-199}, {2-0,2-1,...,2-149} and {3-0,3-1,...,3-199}, while the block Index {4-0,4-1,...,4-199}, {5-0,5-1,...,5-199}, {6-0,6-1,..., 6-179} and {7-0,7-1,...,7-199} can represent the block index {0-0,0-1,...,0-199} of die #1, {1-0,1-1,...,1-199}, {2-0,2-1,...,2-179} and {3-0,3-1,...,3 -199}. A large portion of the blocks belonging to super blocks #0~#179 can be composed of planes #0, #1 and #3 of die #0 and the respective blocks #0~ of planes #0~#3 of die #1 Composed of #179, another part of the blocks belonging to the super block #180~#199 can be changed from the respective blocks #180~ of the respective planes #0, #1 and #3 of the bare die #0 and #1 #199 and block #0~#19 (as shown in the dotted line box) of plane #2 of bare crystal #0 are formed, and can also form 200 super blocks, so that the storage capacity of the data storage device 100 is increased from 96GB to 112GB, to successfully reach the purpose of the present invention.

第6圖繪示依據本發明一實施例之非對稱型平面管理方法的工作流程，本發明非對稱型平面管理方法可應用於資料儲存裝置100，並由資料儲存裝置100的記憶體控制器110所執行。另外，於執行本發明非對稱型平面管理方法以後，記憶體控制器110可能會產生多種儲存容量的記錄，其可分別對應於一平面數參數(plane count parameter)諸如一非平衡平面數量(unbalanced plane number)UNBAL_NUM的多個可能的值(例如多個候選值)，並且使用者可以依據其需求從上述多種儲存容量的記錄選擇對應於該多個可能的值中的某一可能的值(例如該多個候選值中的某一候選值)之一記錄，例如：選取儲存容量值為最大的記錄，或是選取儲存容量值為次佳但是非平衡平面數量UNBAL_NUM的值較小的記錄，而選取該所選擇的記錄所對應的非平衡平面數量UNBAL_NUM的值，使資料儲存裝置100能透過對應的儲存容量組態提供所需的儲存容量。 Figure 6 shows the workflow of the asymmetric plane management method according to an embodiment of the present invention. The asymmetric plane management method of the present invention can be applied to the data storage device 100, and the data storage device Executed by the memory controller 110 set to 100. In addition, after executing the asymmetric plane management method of the present invention, the memory controller 110 may generate records of various storage capacities, which may respectively correspond to a plane count parameter such as an unbalanced plane number (unbalanced plane number) UNBAL_NUM multiple possible values (such as multiple candidate values), and the user can select a possible value corresponding to the multiple possible values from the records of the above-mentioned multiple storage capacities according to his needs (such as One of the multiple candidate values), for example: select the record with the largest storage capacity value, or select the record with the second best storage capacity value but the value of the number of unbalanced planes UNBAL_NUM is small, and The value of the unbalanced plane number UNBAL_NUM corresponding to the selected record is selected so that the data storage device 100 can provide the required storage capacity through the corresponding storage capacity configuration.

於步驟S10中，記憶體控制器110設定非平衡平面數量UNBAL_NUM，其中，非平衡平面數量UNBAL_NUM小於一最大平面數量。該最大平面數量代表該複數個非揮發性記憶體元件122-1、122-2、...與122-N之各自的平面的數量的總和，尤其，該最大平面數量可等於裸晶數量(Die Count)DIE_COUNT乘以平面數量(Plane Number)PLANE_NUM，以前面所述實施例為例，資料儲存裝置100設置有裸晶#0與#1，則裸晶數量DIE_COUNT等於2。平面數量PLANE_NUM可代表每一裸晶所包含的平面的總數量，裸晶#0與#1分別具有其各自的平面#0~#3，則平面數量PLANE_NUM等於4，因此該最大平面數量等於8。非平衡平面數量UNBAL_NUM的初始值例如等於7，最小值例如等於2。 In step S10 , the memory controller 110 sets an unbalanced plane number UNBAL_NUM, wherein the unbalanced plane number UNBAL_NUM is smaller than a maximum plane number. The maximum number of planes represents the sum of the number of planes of the plurality of non-volatile memory elements 122-1, 122-2, ... and 122-N, especially, the maximum number of planes may be equal to the number of dies ( Die Count) (DIE_COUNT) is multiplied by the plane number (Plane Number) PLANE_NUM. Taking the aforementioned embodiment as an example, the data storage device 100 is provided with dies #0 and #1, and the die number DIE_COUNT is equal to 2. The number of planes PLANE_NUM can represent the total number of planes contained in each die. Dies #0 and #1 have their own planes #0~#3 respectively, so the number of planes PLANE_NUM is equal to 4, so the maximum number of planes is equal to 8 . The initial value of the number of unbalanced planes UNBAL_NUM is equal to 7, for example, and the minimum value is equal to 2, for example.

於步驟S12中，記憶體控制器110選取該最大平面數量減去非平衡平面數量UNBAL_NUM的至少一平面，並將選取的平面(諸如該至少一平面)的至少一組區塊(例如其區塊索引)記錄至一區塊省略表(block skip table)諸如對應於該至少一平面之至少一組區塊省略索引(block skip indexes)BLOCKSKIPIDX，其中該區塊省略表可包含該至少一組區塊省略索引 BLOCKSKIPIDX。該至少一組區塊省略索引BLOCKSKIPIDX較佳為一陣列，其可包含一或多個子陣列，而該陣列的該一或多個子陣列的一子陣列數(sub-array count)較佳等於該最大平面數量減去非平衡平面數量UNBAL_NUM的差值，並且該陣列的大小較佳等於該至少一組區塊的總數量。以第2圖上半部以及第4圖為例，最大平面數量等於8，非平衡平面數量UNBAL_NUM等於7，因此，記憶體控制器110將選取1個平面。由於裸晶#0的平面#2的好區塊的總數量最少，因此，記憶體控制器110選取裸晶#0的平面#2，並將裸晶#0的平面#2的區塊#0~#149(例如其區塊索引)記錄至區塊省略索引BLOCKSKIPIDX。假設非平衡平面數量UNBAL_NUM可予以變化，例如，當非平衡平面數量UNBAL_NUM等於6時，因為裸晶#0的平面#2以及裸晶#1的平面#2的好區塊的總數量最少，記憶體控制器110選取裸晶#0的平面#2以及裸晶#1的平面#2，並將裸晶#0的平面#2的區塊#0~#149以及裸晶#1的平面#2的區塊#0~#179(例如其區塊索引)記錄至區塊省略索引BLOCKSKIPIDX。另外，於某些實施例中，記憶體控制器110可選取好區塊的總數量最多的一或多個平面，並將該一或多個平面的區塊(例如其區塊索引)記錄至區塊省略索引BLOCKSKIPIDX，但本發明並不以此為限。 In step S12, the memory controller 110 selects at least one plane of the maximum plane number minus the unbalanced plane number UNBAL_NUM, and at least one group of blocks (for example, its blocks) of the selected plane (such as the at least one plane) index) to a block skip table (block skip table) such as at least one set of block skip indexes (block skip indexes) BLOCKSKIPIDX corresponding to the at least one plane, wherein the block skip table may include the at least one set of blocks omit index BLOCKSKIPIDX. The at least one block omission index BLOCKSKIPIDX is preferably an array, which may include one or more sub-arrays, and a sub-array count (sub-array count) of the one or more sub-arrays of the array is preferably equal to the maximum The difference between the number of planes minus the number of unbalanced planes UNBAL_NUM, and the size of the array is preferably equal to the total number of the at least one group of blocks. Taking the upper part of FIG. 2 and FIG. 4 as examples, the maximum number of planes is equal to 8, and the number of unbalanced planes UNBAL_NUM is equal to 7. Therefore, the memory controller 110 will select one plane. Since the total number of good blocks in plane #2 of die #0 is the least, memory controller 110 selects plane #2 of die #0 and assigns block #0 of plane #2 of die #0 ~#149 (eg its block index) records to the block omission index BLOCKSKIPIDX. Assume that the number of unbalanced planes UNBAL_NUM can be changed, for example, when the number of unbalanced planes UNBAL_NUM is equal to 6, because the total number of good blocks of plane #2 of die #0 and plane #2 of die #1 is the least, memory The bulk controller 110 selects plane #2 of die #0 and plane #2 of die #1, and assigns blocks #0 to #149 of plane #2 of die #0 and plane #2 of die #1 The blocks #0~#179 (such as their block index) are recorded in the block omission index BLOCKSKIPIDX. In addition, in some embodiments, the memory controller 110 may select one or more planes with the largest total number of good blocks, and record the blocks (such as the block index) of the one or more planes into The block omits the index BLOCKSKIPIDX, but the present invention is not limited thereto.

於步驟S14中，記憶體控制器110依據區塊編號為索引(例如：BLK#=0、BLK#=1...)，將未選取的平面的區塊組成超級區塊，尤其，逐一地(one by one)及/或依序地(sequentially)，以將這些平面之各自的區塊#0、#1等分別組成超級區塊#0、#1等，其中這些超級區塊分別對應於這些區塊編號。以第2圖上半部以及第4圖為例，未選取的平面可為裸晶#0的平面#0、#1、#3以及裸晶#1的平面#0~#3，記憶體控制器110依據區塊編號為索引，將未選取的平面的區塊(例如其區塊索引)記錄至孤兒區塊表ORPHAN_BLOCK_TABLE，如第3以及5圖所示，其中，孤兒區塊表ORPHAN_BLOCK_TABLE記錄每一超級區塊的區塊編號，例如，超級區塊#0由7個不同平面的區塊#0所組成，超級區塊#1由7個不同平面的區塊#1所組成，依此類推。此種架構的超級區塊又可稱為7平面超級區塊，或非平衡平面超級區塊。 In step S14, the memory controller 110 uses the block number as an index (for example: BLK#=0, BLK#=1 . (one by one) and/or sequentially (sequentially), so that the respective blocks #0, #1, etc. of these planes are respectively composed of super blocks #0, #1, etc., wherein these super blocks respectively correspond to These block numbers. Taking the upper part of Figure 2 and Figure 4 as an example, the unselected planes can be planes #0, #1, #3 of die #0 and planes #0~#3 of die #1, memory control The device 110 records the unselected planar blocks (for example, its block index) into the orphan block table ORPHAN_BLOCK_TABLE according to the block number as an index, as shown in Figures 3 and 5, wherein the orphan block table ORPHAN_BLOCK_TABLE records every The block number of a super block, for example, super block #0 is composed of 7 different plane blocks #0, and super block #1 is composed of 7 different Block #1 of the plane is composed, and so on. A super block with such a structure can also be called a 7-plane super block, or an unbalanced plane super block.

於步驟S16中，記憶體控制器110判斷步驟S14中的這些區塊編號是否小於一區塊閾值，以產生一判斷結果，尤其，透過將這些區塊編號所形成的一區塊編號序列中的最後一個區塊編號和該區塊閾值比較，以產生這個判斷結果，其中該最後一個區塊編號是這些區塊編號中的最大值。如果是(例如判斷結果為「真」(True))，則執行步驟S18；如果否(例如判斷結果為「偽」(False))，則執行步驟S20。該區塊閾值等於一預定值，且較佳等於全部可用的(available)區塊編號{BLK#}的最大值。以第2圖上半部以及第4圖為例，區塊閾值等於上述全部可用的區塊編號{BLK#}的最大值，即數值199。以第3圖為例，孤兒區塊表ORPHAN_BLOCK_TABLE可因應區塊編號BLK#的變化順利地從超級區塊#0建立至超級區塊#199，因此，當步驟S16的判斷為否時，這表示針對非平衡平面數量UNBAL_NUM的目前值之檢測已完成，可執行步驟S20，尤其，可另因應步驟S22的某一判斷結果執行步驟S10，以進行針對非平衡平面數量UNBAL_NUM的下一個值之檢測，例如，記憶體控制器110可在步驟S10中將非平衡平面數量UNBAL_NUM的下一個值(尤其，最新值)設定為非平衡平面數量UNBAL_NUM的目前值減1。 In step S16, the memory controller 110 judges whether the block numbers in step S14 are smaller than a block threshold to generate a judgment result, especially, by combining the block numbers in a block number sequence formed by these block numbers The last block number is compared with the block threshold to generate the judgment result, wherein the last block number is the maximum value among the block numbers. If yes (for example, the judgment result is "True"), then execute step S18; if not (for example, the judgment result is "False" (False)), then execute step S20. The block threshold is equal to a predetermined value, preferably equal to the maximum value of all available block numbers {BLK#}. Taking the upper half of Figure 2 and Figure 4 as examples, the block threshold is equal to the maximum value of all available block numbers {BLK#} above, which is 199. Taking Figure 3 as an example, the orphan block table ORPHAN_BLOCK_TABLE can be successfully established from super block #0 to super block #199 in response to the change of block number BLK#. Therefore, when the judgment of step S16 is negative, it means The detection of the current value of the number of unbalanced planes UNBAL_NUM has been completed, and step S20 can be executed. In particular, step S10 can be executed in response to a certain judgment result of step S22, so as to detect the next value of the number of unbalanced planes UNBAL_NUM, For example, the memory controller 110 may set the next value (especially, the latest value) of the unbalanced plane number UNBAL_NUM to the current value of the unbalanced plane number UNBAL_NUM minus 1 in step S10 .

於步驟S18中，記憶體控制器110繼續依據區塊編號為索引，尤其，依據上述全部可用的區塊編號{BLK#}中的剩餘的區塊編號(例如步驟S14中的上述區塊編號之後續區塊編號)為索引，將上述未選取的平面的其它區塊(例如對應於上述後續區塊編號之後續區塊)以及區塊省略索引BLOCKSKIPIDX所記錄的區塊組成其它超級區塊，諸如步驟S14中的上述超級區塊之後續超級區塊。以第4至5圖為例，孤兒區塊表ORPHAN_BLOCK_TABLE的表內容(例如其內的區塊索引所代表的超級區塊)可順利地建立至超級區塊#179，然而，在建立超級區塊#180時，只剩下6個不同平面的區塊#180，因此，記憶體控制器110選取區塊省略索引BLOCKSKIPIDX所記錄的裸晶#0的平面#2的區塊#0以及6個不同平面的區塊#180來建立超級區塊#180。接著，記憶體控制器110選取區塊省略索引BLOCKSKIPIDX所記錄的裸晶#0的平面#2的區塊#1以及6個不同平面的區塊#181來建立超級區塊#181，依此類推，直到完成超級區塊#199的建立，如第5圖所示。 In step S18, the memory controller 110 continues to index according to the block numbers, especially, according to the remaining block numbers in the above-mentioned all available block numbers {BLK#} (such as the above-mentioned block numbers in step S14 Subsequent block number) is an index, and other blocks of the above-mentioned unselected plane (for example, corresponding to the subsequent block of the above-mentioned subsequent block number) and blocks recorded by the block omission index BLOCKSKIPIDX form other super blocks, such as The above-mentioned super-block in step S14 is subsequent to the super-block. Taking Figures 4 to 5 as an example, the table contents of the orphan block table ORPHAN_BLOCK_TABLE (such as the super block represented by the block index in it) can be successfully established to the super block #179, however, the When the super block #180 is established, there are only 6 blocks #180 of different planes left, therefore, the memory controller 110 selects the block #0 of the plane #2 of the die #0 recorded by the block omission index BLOCKSKIPIDX And 6 blocks #180 of different planes to build super block #180. Next, the memory controller 110 selects the block #1 of the plane #2 of the die #0 recorded by the block omission index BLOCKSKIPIDX and the block #181 of six different planes to create a super block #181, and so on , until the establishment of super block #199 is completed, as shown in Figure 5.

於步驟S20中，記憶體控制器110記錄全部超級區塊的總容量以及非平衡平面數量UNBAL_NUM，以產生上述多種儲存容量的記錄中的一最新的記錄，以供進一步設定資料儲存裝置100的儲存容量組態，其中上述全部超級區塊可包含步驟S14中的上述超級區塊，尤其，可另包含步驟S18中的上述其它超級區塊(若步驟S18被執行)。於完成孤兒區塊表ORPHAN_BLOCK_TABLE的建立以後，記憶體控制器110可依據孤兒區塊表ORPHAN_BLOCK_TABLE而計算出超級區塊的總容量，例如：112GB，且記錄超級區塊的總容量以及非平衡平面數量UNBAL_NUM的目前值，例如：數值7。 In step S20, the memory controller 110 records the total capacity of all superblocks and the number of unbalanced planes UNBAL_NUM to generate the latest record among the records of the above-mentioned various storage capacities for further setting the storage capacity of the data storage device 100 Capacity configuration, wherein all the above superblocks may include the above superblock in step S14, especially, may additionally include the above other superblocks in step S18 (if step S18 is executed). After completing the establishment of the orphan block table ORPHAN_BLOCK_TABLE, the memory controller 110 can calculate the total capacity of the super block according to the orphan block table ORPHAN_BLOCK_TABLE, for example: 112GB, and record the total capacity of the super block and the number of unbalanced planes The current value of UNBAL_NUM, for example: the value 7.

於步驟S22中，記憶體控制器110判斷非平衡平面數量UNBAL_NUM是否等於平面閾值。如果否(例如判斷結果為「偽」)，則執行步驟S10；如果是(例如判斷結果為「真」)，則結束非對稱型平面管理方法的執行。在步驟S10，記憶體控制器110例如將非平衡平面數量UNBAL_NUM的下一個值(尤其，最新值)設定為非平衡平面數量UNBAL_NUM的目前值減1。另外，平面閾值可等於UNBAL_NUM的最小值，例如：數值2。 In step S22 , the memory controller 110 determines whether the unbalanced plane number UNBAL_NUM is equal to the plane threshold. If no (for example, the judgment result is "false"), execute step S10; if yes (for example, the judgment result is "true"), then end the execution of the asymmetric plane management method. In step S10 , the memory controller 110 sets, for example, the next value (especially, the latest value) of the unbalanced plane number UNBAL_NUM to the current value of the unbalanced plane number UNBAL_NUM minus 1. In addition, the plane threshold can be equal to the minimum value of UNBAL_NUM, for example: the value 2.

由於上述中可知，本發明至少一實施例之非對稱型平面管理方法能成功地將資料儲存裝置100的儲存容量從96GB增加為112GB，並使資料儲存裝置100具備基於超級區塊的高存取效能，而剩下未利用的區塊，例如：區塊省略索引BLOCKSKIPIDX所記錄的區塊則可作為預留空間(Over-provisioning)使用，達到本發明的目的。 As can be seen from the above, the asymmetric plane management method of at least one embodiment of the present invention can successfully increase the storage capacity of the data storage device 100 from 96GB to 112GB, and enable the data storage device 100 to have high access based on super blocks performance, and the remaining unused blocks, for example: the blocks recorded by the block omission index BLOCKSKIPIDX can be used as Over-provisioning, Reach the object of the present invention.

以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

S10,S12,S14,S16,S18,S20,S22:步驟 S10, S12, S14, S16, S18, S20, S22: steps

Claims

一種非對稱型平面管理方法，該非對稱型平面管理方法係應用於一資料儲存裝置，該資料儲存裝置包含一非揮發性記憶體(non-volatile memory,NV memory)，該非揮發性記憶體包含複數個非揮發性記憶體元件(NV memory element)，該複數個非揮發性記憶體元件包含複數個區塊(block)，該非對稱型平面管理方法包含有：依據區塊編號為索引，將該複數個非揮發性記憶體元件之各自的平面中之未選取的平面的區塊，而非被選取以供進行一先前處理之至少一平面的任何區塊，組成超級區塊，其中一非平衡平面數量(unbalanced plane number)指出所述未選取的平面之一平面數(plane count)，該至少一平面之一平面數加上該非平衡平面數量等於一最大平面數量，該最大平面數量代表該複數個非揮發性記憶體元件之所述各自的平面的數量的總和，且所述超級區塊分別對應於所述區塊編號，其中該先前處理包含將該至少一平面的至少一組區塊記錄至一區塊省略表(block skip table)；判斷所述區塊編號中的至少一者是否小於一區塊閾值，以產生一判斷結果，其中該區塊閾值等於全部可用的(available)區塊編號的最大值，且該判斷結果指出所述區塊編號中的該至少一者是否小於該區塊閾值；因應該判斷結果指出所述區塊編號中的該至少一者小於該區塊閾值，依據所述全部可用的區塊編號中的剩餘的區塊編號為索引，將所述未選取的平面的其它區塊以及該區塊省略表所記錄的區塊組成其它超級區塊；以及因應來自一主機(host device)的複數個主機命令(host command)中之至少一主機命令，為該主機存取(access)所述超級區塊中之至少一超級區塊。 An asymmetric plane management method, the asymmetric plane management method is applied to a data storage device, the data storage device includes a non-volatile memory (non-volatile memory, NV memory), the non-volatile memory includes a plurality of A non-volatile memory element (NV memory element), the plurality of non-volatile memory elements include a plurality of blocks (block), the asymmetric planar management method includes: according to the block number as an index, the plurality Blocks of non-selected planes in the respective planes of the non-volatile memory elements, other than any blocks of at least one plane selected for a previous process, constitute a super-block, wherein an unbalanced plane The number (unbalanced plane number) indicates a plane count (plane count) of the unselected plane, the plane count of the at least one plane plus the unbalanced plane number is equal to a maximum plane number, and the maximum plane number represents the complex number sum of numbers of said respective planes of non-volatile memory elements, and said superblocks respectively correspond to said block numbers, wherein said previous processing comprises recording at least one set of blocks of said at least one plane into A block skip table; judging whether at least one of the block numbers is less than a block threshold to generate a judgment result, wherein the block threshold is equal to all available (available) block numbers , and the judgment result indicates whether the at least one of the block numbers is smaller than the block threshold; because the judgment result indicates that the at least one of the block numbers is smaller than the block threshold, according to The remaining block numbers in all available block numbers are used as indexes to form other super blocks from other blocks of the unselected plane and the blocks recorded in the block omission table; One of a plurality of host commands (host command) of the host (host device) At least one host command is for the host to access at least one superblock in the superblocks.

如申請專利範圍第1項所述之非對稱型平面管理方法，其中該區塊省略表包含至少一組區塊省略索引(block skip indexes)；以及該至少一組區塊省略索引是一陣列，該陣列包含一或多個子陣列，且該陣列的該一或多個子陣列的一子陣列數(sub-array count)等於該最大平面數量減去該非平衡平面數量的差值，其中該陣列的大小等於該至少一組區塊的總數量。 The asymmetric plane management method as described in claim 1, wherein the block skip table includes at least one set of block skip indexes; and the at least one set of block skip indexes is an array, The array includes one or more sub-arrays, and a sub-array count (sub-array count) of the one or more sub-arrays of the array is equal to the difference between the maximum number of planes minus the number of unbalanced planes, wherein the size of the array equal to the total number of the at least one group of blocks.

如申請專利範圍第1項所述之非對稱型平面管理方法，其中所述剩餘的區塊編號包含所述區塊編號之後續區塊編號，所述未選取的平面的所述其它區塊包含對應於所述後續區塊編號之後續區塊，且所述其它超級區塊包含所述超級區塊之後續超級區塊。 The asymmetric plane management method described in claim 1 of the scope of the patent application, wherein the remaining block number includes the subsequent block number of the block number, and the other blocks of the unselected plane include A subsequent block corresponding to the subsequent block number, and the other super blocks include subsequent super blocks of the super block.

如申請專利範圍第1項所述之非對稱型平面管理方法，其中判斷所述區塊編號中的該至少一者是否小於該區塊閾值以產生該判斷結果之步驟包含：將所述區塊編號所形成的一區塊編號序列中的最後一個區塊編號和該區塊閾值比較，以產生該判斷結果，其中該最後一個區塊編號是所述區塊編號中的最大值。 According to the asymmetric plane management method described in item 1 of the scope of patent application, the step of judging whether at least one of the block numbers is smaller than the block threshold to generate the judging result includes: The last block number in a block number sequence formed by numbers is compared with the block threshold to generate the judgment result, wherein the last block number is the maximum value among the block numbers.

如申請專利範圍第1項所述之非對稱型平面管理方法，其中存取所述超級區塊中之該至少一超級區塊包含：將資料寫入該至少一超級區塊。 According to the asymmetric plane management method described in item 1 of the scope of the patent application, accessing the at least one super block in the super block includes: Write data into the at least one superblock.

如申請專利範圍第5項所述之非對稱型平面管理方法，其中存取所述超級區塊中之該至少一超級區塊另包含：從該至少一超級區塊讀取該資料中之至少一部分資料。 According to the asymmetric plane management method described in item 5 of the scope of patent application, wherein accessing the at least one super block in the super block further includes: reading at least one of the data from the at least one super block part of the data.

一種資料儲存裝置，包含有：一非揮發性記憶體(non-volatile memory，NV memory)，用來儲存資訊，其中該非揮發性記憶體包含複數個非揮發性記憶體元件(NV memory element)，以及該複數個非揮發性記憶體元件包含複數個區塊；以及一控制器，耦接至該非揮發性記憶體，用來控制該資料儲存裝置之操作，其中該控制器包含：一處理電路，用來依據來自一主機(host device)的複數個主機命令(host command)控制該控制器，以容許該主機透過該控制器存取(access)該非揮發性記憶體，其中：該控制器依據區塊編號為索引，將該複數個非揮發性記憶體元件之各自的平面中之未選取的平面的區塊，而非被選取以供進行一先前處理之至少一平面的任何區塊，組成超級區塊，其中一非平衡平面數量(unbalanced plane number)指出所述未選取的平面之一平面數(plane count)，該至少一平面之一平面數加上該非平衡平面數量等於一最大平面數量，該最大平面數量代表該複數個非揮發性記憶體元件之所述各自的平面的數量的總和，且所述超級區塊分別對應於所述區塊編號，其中該先前處理包含將該至少一平面的至少一組區塊記錄至一區塊省略表(block skip table)；該控制器判斷所述區塊編號中的至少一者是否小於一區塊閾值，以產生一判斷結果，其中該區塊閾值等於全部可用的(available)區塊編號的最大值，且該判斷結果指出所述區塊編號中的該至少一者是否小於該區塊閾值；因應該判斷結果指出所述區塊編號中的該至少一者小於該區塊閾值，該控制器依據所述全部可用的區塊編號中的剩餘的區塊編號為索引，將所述未選取的平面的其它區塊以及該區塊省略表所記錄的區塊組成其它超級區塊；以及因應來自該主機的該複數個主機命令中之至少一主機命令，該控制器為該主機存取所述超級區塊中之至少一超級區塊。 A data storage device includes: a non-volatile memory (non-volatile memory, NV memory) for storing information, wherein the non-volatile memory includes a plurality of non-volatile memory elements (NV memory element), And the plurality of non-volatile memory elements include a plurality of blocks; and a controller, coupled to the non-volatile memory, for controlling the operation of the data storage device, wherein the controller includes: a processing circuit, Used to control the controller according to a plurality of host commands (host command) from a host (host device), so as to allow the host to access (access) the non-volatile memory through the controller, wherein: the controller is based on the area The block number is used to index blocks of non-selected planes of the respective planes of the plurality of non-volatile memory elements, other than any blocks of at least one plane selected for a previous process, to form a super block, wherein an unbalanced plane number (unbalanced plane number) indicates a plane count (plane count) of the unselected plane, and the plane count of the at least one plane plus the unbalanced plane number equals a maximum plane count, The maximum number of planes represents the sum of the number of said respective planes of the plurality of non-volatile memory elements, and the super blocks respectively correspond to the block numbers, wherein the previous processing includes recording at least one group of blocks of the at least one plane into a block skip table; the controller determines that the whether at least one of the block numbers is less than a block threshold, wherein the block threshold is equal to the maximum value of all available (available) block numbers, and the judgment result indicates that the block number Whether the at least one of the block numbers is smaller than the block threshold; because the judgment result indicates that the at least one of the block numbers is smaller than the block threshold, the controller bases the remaining number of all available block numbers on the The block number of the block is used as an index to form other blocks of the unselected plane and blocks recorded in the block omission table into other super blocks; and in response to at least one of the plurality of host commands from the host Instructing the host, the controller accesses at least one of the superblocks for the host.

如申請專利範圍第7項所述之資料儲存裝置，其中該區塊省略表包含至少一組區塊省略索引(block skip indexes)；以及該至少一組區塊省略索引是一陣列，該陣列包含一或多個子陣列，且該陣列的該一或多個子陣列的一子陣列數(sub-array count)等於該最大平面數量減去該非平衡平面數量的差值，其中該陣列的大小等於該至少一組區塊的總數量。 The data storage device as described in item 7 of the scope of patent application, wherein the block skip table includes at least one set of block skip indexes; and the at least one set of block skip indexes is an array, and the array includes One or more sub-arrays, and a sub-array count (sub-array count) of the one or more sub-arrays of the array is equal to the difference between the maximum number of planes minus the number of unbalanced planes, wherein the size of the array is equal to the at least The total number of blocks in a set.

如申請專利範圍第7項所述之資料儲存裝置，其中所述剩餘的區塊編號包含所述區塊編號之後續區塊編號，所述未選取的平面的所述其它區塊包含對應於所述後續區塊編號之後續區塊，且所述其它超級區塊包含所述超級區塊之後續超級區塊。 The data storage device as described in item 7 of the scope of the patent application, wherein the remaining block numbers include the subsequent block numbers of the block numbers, and the other blocks of the unselected planes A block includes a subsequent block corresponding to the subsequent block number, and the other superblock includes a subsequent superblock of the superblock.

如申請專利範圍第7項所述之資料儲存裝置，其中該控制器將所述區塊編號所形成的一區塊編號序列中的最後一個區塊編號和該區塊閾值比較，以產生該判斷結果，其中該最後一個區塊編號是所述區塊編號中的最大值。 The data storage device as described in item 7 of the scope of the patent application, wherein the controller compares the last block number in a block number sequence formed by the block number with the block threshold to generate the judgment As a result, wherein the last block number is the maximum value among the block numbers.

如申請專利範圍第7項所述之資料儲存裝置，其中存取所述超級區塊中之該至少一超級區塊包含：將資料寫入該至少一超級區塊。 In the data storage device described in claim 7 of the patent application, accessing the at least one super block of the super blocks includes: writing data into the at least one super block.

如申請專利範圍第11項所述之資料儲存裝置，其中存取所述超級區塊中之該至少一超級區塊另包含：從該至少一超級區塊讀取該資料中之至少一部分資料。 The data storage device described in claim 11 of the patent application, wherein accessing the at least one super block in the super block further includes: reading at least a part of the data from the at least one super block.

一種資料儲存裝置之控制器，該資料儲存裝置包含該控制器與一非揮發性記憶體(non-volatile memory，NV memory)，該非揮發性記憶體包含複數個非揮發性記憶體元件(NV memory element)，該複數個非揮發性記憶體元件包含複數個區塊，該控制器包含有：一處理電路，用來依據來自一主機(host device)的複數個主機命令(host command)控制該控制器，以容許該主機透過該控制器存取(access)該非揮發性記憶體，其中：該控制器依據區塊編號為索引，將該複數個非揮發性記憶體元件之各自的平面中之未選取的平面的區塊，而非被選取以供進行一先前處理之至少一平面的任何區塊，組成超級區塊，其中一非平衡平面數量(unbalanced plane number)指出所述未選取的平面之一平面數(plane count)，該至少一平面之一平面數加上該非平衡平面數量等於一最大平面數量，該最大平面數量代表該複數個非揮發性記憶體元件之所述各自的平面的數量的總和，且所述超級區塊分別對應於所述區塊編號，其中該先前處理包含將該至少一平面的至少一組區塊記錄至一區塊省略表(block skip table)；該控制器判斷所述區塊編號中的至少一者是否小於一區塊閾值，以產生一判斷結果，其中該區塊閾值等於全部可用的(available)區塊編號的最大值，且該判斷結果指出所述區塊編號中的該至少一者是否小於該區塊閾值；因應該判斷結果指出所述區塊編號中的該至少一者小於該區塊閾值，該控制器依據所述全部可用的區塊編號中的剩餘的區塊編號為索引，將所述未選取的平面的其它區塊以及該區塊省略表所記錄的區塊組成其它超級區塊；以及因應來自該主機的該複數個主機命令中之至少一主機命令，該控制器為該主機存取所述超級區塊中之至少一超級區塊。 A controller of a data storage device, the data storage device includes the controller and a non-volatile memory (non-volatile memory, NV memory), and the non-volatile memory includes a plurality of non-volatile memory elements (NV memory element), the plurality of non-volatile memory elements include a plurality of blocks, and the controller includes: a processing circuit for controlling the control according to a plurality of host commands (host command) from a host (host device) device to allow the host to access the non-volatile memory through the controller, wherein: the controller indexes the plurality of non-volatile memory elements according to the block number Blocks of unselected planes in the respective planes, other than any blocks of at least one plane selected for a previous process, constitute superblocks, wherein an unbalanced plane number indicates the A plane count (plane count) of the unselected planes, the plane count of the at least one plane plus the unbalanced plane count equals a maximum plane count, and the maximum plane count represents the location of the plurality of non-volatile memory elements the sum of the numbers of the respective planes, and the super blocks respectively correspond to the block numbers, wherein the previous processing includes recording at least one group of blocks of the at least one plane into a block skip table (block skip table); the controller judges whether at least one of the block numbers is less than a block threshold to generate a judgment result, wherein the block threshold is equal to the maximum value of all available (available) block numbers, and The judgment result indicates whether the at least one of the block numbers is smaller than the block threshold; because the judgment result indicates that the at least one of the block numbers is smaller than the block threshold, the controller according to the The remaining block numbers in all available block numbers are used as indexes, and other blocks of the unselected plane and the blocks recorded in the block omission table are used to form other super blocks; and in response to the request from the host In accordance with at least one host command of the plurality of host commands, the controller accesses at least one of the super blocks for the host.

如申請專利範圍第13項所述之控制器，其中該區塊省略表包含至少一組區塊省略索引(block skip indexes)；以及該至少一組區塊省略索引是一陣列，該陣列包含一或多個子陣列，且該陣列的該一或多個子陣列的一子陣列數(sub-array count)等於該最大平面數量減去該非平衡平面數量的差值，其中該陣列的大小等於該至少一組區塊的總數量。 The controller as described in claim 13, wherein the block skip table includes at least one set of block skip indexes; and the at least one set of block skip indexes is an array, and the array includes a or more sub-arrays, and a sub-array count (sub-array count) of the one or more sub-arrays of the array is equal to the maximum number of planes minus the number of unbalanced planes , wherein the size of the array is equal to the total number of the at least one set of blocks.

如申請專利範圍第13項所述之控制器，其中所述剩餘的區塊編號包含所述區塊編號之後續區塊編號，所述未選取的平面的所述其它區塊包含對應於所述後續區塊編號之後續區塊，且所述其它超級區塊包含所述超級區塊之後續超級區塊。 The controller described in item 13 of the scope of patent application, wherein the remaining block number includes the subsequent block number of the block number, and the other blocks of the unselected plane include the blocks corresponding to the Subsequent blocks of subsequent block numbers, and the other super blocks include subsequent super blocks of the super block.

如申請專利範圍第13項所述之控制器，其中該控制器將所述區塊編號所形成的一區塊編號序列中的最後一個區塊編號和該區塊閾值比較，以產生該判斷結果，其中該最後一個區塊編號是所述區塊編號中的最大值。 The controller described in claim 13 of the scope of patent application, wherein the controller compares the last block number in a block number sequence formed by the block number with the block threshold to generate the judgment result , where the last block number is the largest of the block numbers.

如申請專利範圍第13項所述之控制器，其中存取所述超級區塊中之該至少一超級區塊包含：將資料寫入該至少一超級區塊。 The controller as described in claim 13, wherein accessing the at least one super block of the super blocks includes: writing data into the at least one super block.

如申請專利範圍第17項所述之控制器，其中存取所述超級區塊中之該至少一超級區塊另包含：從該至少一超級區塊讀取該資料中之至少一部分資料。 The controller described in claim 17 of the patent application, wherein accessing the at least one super block in the super block further includes: reading at least a part of the data from the at least one super block.