TWI781788B - Physical unclonable function circuit and associated chip and electronic device - Google Patents

Physical unclonable function circuit and associated chip and electronic device Download PDF

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TWI781788B
TWI781788B TW110138002A TW110138002A TWI781788B TW I781788 B TWI781788 B TW I781788B TW 110138002 A TW110138002 A TW 110138002A TW 110138002 A TW110138002 A TW 110138002A TW I781788 B TWI781788 B TW I781788B
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coupled
function circuit
node
voltage
type transistor
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TW202316302A (en
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林俊彥
邱志杰
陳鈞恒
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英屬維京群島商爍星有限公司
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Abstract

The present disclosure provides a physical unclonable function (PUF) circuit and an associated chip and electronic device. The PUF circuit includes a pattern generator and a programmable circuit. When the PUF circuit is powered on, the pattern generator is adapted to form a preference voltage value based on characteristics of inherent process mismatch and current ambient factors. The preference voltage value is volatilized when the PUF circuit is powered off. The programmable circuit, coupled to the pattern generator, arranged to be programmed according to the preference voltage value, in which a programmed result is not volatilized when the PUF circuit is powered off.

Description

物理不可複製函數電路及相關晶片和電子裝置Physically non-reproducible functional circuits and related chips and electronic devices

本發明係關於一種電路，尤其是關於一種物理不可複製函數電路及相關晶片和電子裝置。The present invention relates to a circuit, in particular to a physical non-reproducible function circuit and related chips and electronic devices.

許多加密協定都是基於物理不可複製函數（Physical Unclonable Functions, PUF）來進行加密。舉例來說，利用電晶體在積體電路製造過程中獨一無二的變異，產生出不可複製的密鑰。然而，除了半導體製程上的因素，電壓以及溫度等外在環境因子同樣也會影響物理不可複製函數電路偏好的行為，所以往往需要搭配複雜的錯誤更正電路來確保所產生的密鑰的穩定性，造成整體成本的上升。Many cryptographic protocols are based on Physical Unclonable Functions (PUF) for encryption. For example, unique variations in transistors during the fabrication of integrated circuits are used to generate non-replicable keys. However, in addition to semiconductor manufacturing factors, external environmental factors such as voltage and temperature will also affect the behavior of physical non-reproducible function circuits, so complex error correction circuits are often required to ensure the stability of the generated keys. lead to an increase in overall costs.

因此，如何改善物理不可複製函數電路的穩定性，已成為本領域亟需解決的問題之一。Therefore, how to improve the stability of a physically non-reproducible function circuit has become one of the urgent problems to be solved in this field.

本發明的目的在於提供一種物理不可複製函數電路，包括：圖案產生器以及可程式化電路；其中該物理不可複製函數電路上電時，該圖案產生器依據本身的製程不匹配特性及當下的環境因子形成偏好的電壓值，該偏好的電壓值在該物理不可複製函數電路下電時揮發佚失；該可程式化電路耦接該圖案產生器，用來依據該圖案產生器形成之該偏好的電壓值來被程式化，該可程式化電路被程式化的結果在該物理不可複製函數電路下電時不揮發佚失。The object of the present invention is to provide a physically non-reproducible function circuit, including: a pattern generator and a programmable circuit; wherein when the physically non-reproducible function circuit is powered on, the pattern generator will be automatically controlled according to its own process mismatch characteristics and the current environment The factor forms a preferred voltage value, and the preferred voltage value is volatile and lost when the physical non-replicable function circuit is powered off; the programmable circuit is coupled to the pattern generator, and is used to form the preferred voltage value according to the pattern generator The voltage value is programmed, and the programmed result of the programmable circuit is not volatile and lost when the physically non-reproducible function circuit is powered off.

本發明的目的在於提供一種晶片，包括上述的物理不可複製函數電路。The object of the present invention is to provide a chip including the above-mentioned physically non-replicable function circuit.

本發明的目的在於提供一種裝置，包括上述的晶片。The object of the present invention is to provide a device comprising the above-mentioned wafer.

本申請的物理不可複製函數電路及相關晶片和電子裝置可以在實現基於物理不可複製函數的認證機制時，提高穩定性及降低成本。The physical non-reproducible function circuit and related chips and electronic devices of the present application can improve the stability and reduce the cost when realizing the authentication mechanism based on the physical non-reproducible function.

圖1為本發明的物理不可複製函數電路的示意圖。物理不可複製函數電路100包含圖案產生器102以及可程式化電路104。圖案產生器102採用半導體製程。具體來說，圖案產生器102以互補式金屬氧化物半導體（CMOS）製程實現。因此，當物理不可複製函數電路100上電（power on）時，圖案產生器102會依據本身的製程不匹配特性形成偏好的電壓值Dp，又稱圖案（pattern），由於製造物理不可複製函數電路100時，圖案產生器102的製程不匹配特性具有獨特性和隨機性，因此該圖案也就具有獨特性和隨機性，而能用以產生不可複製的密鑰。應注意的是，偏好的電壓值Dp可以包含一個或多個電壓值。FIG. 1 is a schematic diagram of a physically non-clonable function circuit of the present invention. The physically non-clonable function circuit 100 includes a pattern generator 102 and a programmable circuit 104 . The pattern generator 102 adopts semiconductor process. Specifically, the pattern generator 102 is realized by a complementary metal oxide semiconductor (CMOS) process. Therefore, when the physical non-reproducible function circuit 100 is powered on, the pattern generator 102 will form a preferred voltage value Dp according to its own process mismatch characteristics, also known as a pattern (pattern). When 100, the process mismatch characteristic of the pattern generator 102 is unique and random, so the pattern also has uniqueness and randomness, and can be used to generate a non-replicable key. It should be noted that the preferred voltage value Dp may contain one or more voltage values.

然而，除了半導體製程上的因素，當下的環境因子也會影響偏好的電壓值Dp。舉例來說，該環境因子可以包含圖案產生器102所在的環境之溫度差異，及/或供應給圖案產生器102的供應電壓的電壓值的差異等。由於圖案產生器102所形成之偏好的電壓值Dp在物理不可複製函數電路100下電（power off）時即揮發佚失。而物理不可複製函數電路100下一次上電時，若圖案產生器102本身的製程不匹配特性不夠顯著，上述的環境因子可能會造成圖案產生器102所形成之偏好的電壓值Dp'和前一次的偏好的電壓值Dp不同。這種現象越容易發生，代表圖案產生器102的穩定性越低，對於密鑰的應用是越不利的。However, in addition to factors in the semiconductor manufacturing process, current environmental factors will also affect the preferred voltage value Dp. For example, the environmental factor may include a temperature difference of the environment where the pattern generator 102 is located, and/or a voltage value difference of the supply voltage supplied to the pattern generator 102 , and the like. The preferred voltage value Dp formed by the pattern generator 102 is volatilized and lost when the physically irreproducible function circuit 100 is powered off. When the physical non-reproducible function circuit 100 is powered on next time, if the process mismatch characteristic of the pattern generator 102 itself is not significant enough, the above-mentioned environmental factors may cause the preferred voltage value Dp' formed by the pattern generator 102 to be different from the previous one. The preferred voltage value Dp is different. The easier this phenomenon occurs, the lower the stability of the pattern generator 102 is, and the more unfavorable it is to the application of the key.

因此，本申請還利用可程式化（programmable）電路104來解決此問題。可程式化電路104耦接圖案產生器102，用來依據圖案產生器102形成之偏好的電壓值Dp來被程式化（programmed），可程式化電路104被程式化的結果在下電時不會揮發消失。Therefore, the present application also utilizes a programmable circuit 104 to solve this problem. The programmable circuit 104 is coupled to the pattern generator 102, and is used to be programmed according to the preferred voltage value Dp formed by the pattern generator 102. The programmed result of the programmable circuit 104 will not be volatile when the power is turned off. disappear.

具體來說，當物理不可複製函數電路100第一次上電時，會進入初始階段，這時圖案產生器102形成之偏好的電壓值Dp會被利用來程式化可程式化電路104。而在之後任何一次重新上電後，當物理不可複製函數電路100收到質詢（challenge）訊號Sc時，物理不可複製函數電路100會通過可程式化電路104將偏好的電壓值Dp，回應質詢訊號Sc。由於可程式化電路104所保存的內容是不揮發的（non-volatile），所以在下電之後，可程式化電路104被程式化的結果不會揮發佚失，因此在沒有被重新程式化之前，即使重新上電也不會改變其被程式化的結果。所以可以確保在可程式化電路104被重新程式化之前，物理不可複製函數電路100每次輸出的圖案，即偏好的電壓值Dp，都一致不變。Specifically, when the physical non-clonable function circuit 100 is powered on for the first time, it enters an initial stage, and at this time, the preferred voltage value Dp formed by the pattern generator 102 is used to program the programmable circuit 104 . After any subsequent power-on, when the physical non-reproducible function circuit 100 receives a challenge signal Sc, the physical non-reproducible function circuit 100 will respond to the challenge signal with the preferred voltage value Dp through the programmable circuit 104 Sc. Since the content stored in the programmable circuit 104 is non-volatile, after power off, the programmed result of the programmable circuit 104 will not be volatile and lost. Therefore, before it is reprogrammed, Even power cycle will not change its programmed result. Therefore, it can be ensured that before the programmable circuit 104 is reprogrammed, the output pattern of the physically non-reproducible function circuit 100 each time, that is, the preferred voltage value Dp, remains unchanged.

在本實施例中，質詢訊號Sc來自物理不可複製函數電路100外部的伺服器，但本申請不以此為限。又，在本實施例中，物理不可複製函數電路100僅在第一次上電時進入前述的初始階段。然而在某些實施例中，還可以通過重置物理不可複製函數電路100來使物理不可複製函數電路100重新進入初始階段，以重新程式化可程式化電路104。在某些實施例中，對於進入初始階段的時間點也可以有其他的變化。例如可以設定物理不可複製函數電路100在第一次收到質詢訊號Sc時（而非第一次上電時）進入初始階段。In this embodiment, the challenge signal Sc comes from a server outside the physically non-clonable function circuit 100 , but the application is not limited thereto. Also, in this embodiment, the physically non-clonable function circuit 100 enters the aforementioned initial stage only when it is powered on for the first time. However, in some embodiments, the physically non-clonable function circuit 100 can also be re-entered into an initial stage by resetting the physically non-clonable function circuit 100 to reprogram the programmable circuit 104 . In some embodiments, there may be other variations on the point of entry into the initial phase. For example, it can be set that the physical non-clonable function circuit 100 enters the initial stage when it receives the challenge signal Sc for the first time (not when it is powered on for the first time).

圖2為本發明的物理不可複製函數電路的第一實施例的示意圖。物理不可複製函數電路200中，以揮發性記憶體202來實現物理不可複製函數電路100中的圖案產生器102；以及使用非揮發性記憶體204來實現物理不可複製函數電路100中的可程式化電路104。揮發性記憶體202包含至少一揮發性記憶體胞元（cell），例如動態隨機存取記憶體（Dynamic Random Access Memory, DRAM）胞元或靜態隨機存取記憶體（Static Random Access Memory, SRAM）胞元等；非揮發性記憶體204包含至少一非揮發性記憶體胞元，例如快閃記憶體（flash memory）胞元、鐵電隨機存取記憶體（Ferroelectric RAM, FRAM）胞元、磁阻式隨機存取記憶體（Magnetoresistive RAM, MRAM）胞元、可程式化唯讀記憶體（Programmable read-only memory, PROM）胞元、電可改寫唯讀記憶體（Electrically alterable read only memory, EAROM）胞元、可抹除可程式化唯讀記憶體（Erasable programmable read only memory, EPROM）胞元或電可抹除可程式化唯讀記憶體（Electrically erasable programmable read only memory, EEPROM）胞元等。FIG. 2 is a schematic diagram of the first embodiment of the physically non-clonable function circuit of the present invention. In the physically non-reproducible function circuit 200, the pattern generator 102 in the physically non-reproducible function circuit 100 is implemented with a volatile memory 202; circuit 104. The volatile memory 202 includes at least one volatile memory cell (cell), such as a dynamic random access memory (Dynamic Random Access Memory, DRAM) cell or a static random access memory (Static Random Access Memory, SRAM) cells, etc.; the non-volatile memory 204 includes at least one non-volatile memory cell, such as a flash memory (flash memory) cell, a ferroelectric random access memory (Ferroelectric RAM, FRAM) cell, a magnetic Resistive random access memory (Magnetoresistive RAM, MRAM) cell, programmable read-only memory (Programmable read-only memory, PROM) cell, electrically rewritable read-only memory (Electrically alterable read only memory, EAROM) ) cell, erasable programmable read only memory (Erasable programmable read only memory, EPROM) cell or electrically erasable programmable read only memory (Electrically erasable programmable read only memory, EEPROM) cell, etc. .

當物理不可複製函數電路200進入初始階段時，揮發性記憶體202之中的至少一揮發性記憶體胞元上形成的偏好電壓值Dp被讀出後，再被儲存至非揮發性記憶體204之中的非揮發性記憶體胞元。而當物理不可複製函數電路200收到質詢訊號Sc時，物理不可複製函數電路200會根據非揮發性記憶體204之中的非揮發性記憶體胞元所儲存的偏好的電壓值Dp來輸出圖案，以回應質詢訊號Sc。When the physical non-replicable function circuit 200 enters the initial stage, the bias voltage value Dp formed on at least one volatile memory cell in the volatile memory 202 is read out and then stored in the non-volatile memory 204 Among the non-volatile memory cells. And when the physical non-clonable function circuit 200 receives the challenge signal Sc, the physical non-clonable function circuit 200 will output the pattern according to the preferred voltage value Dp stored in the non-volatile memory cell in the non-volatile memory 204 , in response to the challenge signal Sc.

圖3為本發明的物理不可複製函數電路的第二實施例的示意圖。物理不可複製函數電路300中，以揮發性記憶體302來實現物理不可複製函數電路100中的圖案產生器102；以及使用非揮發性記憶體304來實現物理不可複製函數電路100中的可程式化電路104。雖本申請不以此限，但為方便說明，後續以一個揮發性記憶體胞元以及對應的一個非揮發性記憶體胞元的工作方式來做說明。因此在圖3中，揮發性記憶體302中僅繪示了一個揮發性記憶體胞元，非揮發性記憶體304中僅繪示了一個非揮發性記憶體胞元。FIG. 3 is a schematic diagram of a second embodiment of the physically non-clonable function circuit of the present invention. In the physically non-reproducible function circuit 300, the pattern generator 102 in the physically non-reproducible function circuit 100 is implemented with a volatile memory 302; circuit 104. Although the present application is not limited thereto, for the convenience of description, a working method of a volatile memory cell and a corresponding non-volatile memory cell will be described later. Therefore, in FIG. 3 , only one volatile memory cell is shown in the volatile memory 302 , and only one non-volatile memory cell is shown in the non-volatile memory 304 .

揮發性記憶體胞元302包含電晶體3022、電晶體3024、電晶體3026以及電晶體3028。在本實施例中，電晶體3022和電晶體3024為P型電晶體；電晶體3026和電晶體3028為N型電晶體。電晶體3022的源極耦接至第一參考電壓V1，電晶體3022的汲極耦接至節點N，電晶體3022的閘極耦接至節點NB。電晶體3024的源極耦接至第一參考電壓V1，電晶體3024的汲極耦接至節點NB，電晶體3024的閘極耦接至節點N。電晶體3026的源極耦接至第二參考電壓V2，電晶體3026的汲極耦接至節點N，電晶體3026的閘極耦接至節點NB。電晶體3028的源極耦接至第二參考電壓V2，電晶體3028的汲極耦接至節點NB，電晶體3028的閘極耦接至節點N。The volatile memory cell 302 includes a transistor 3022 , a transistor 3024 , a transistor 3026 and a transistor 3028 . In this embodiment, the transistor 3022 and the transistor 3024 are P-type transistors; the transistor 3026 and the transistor 3028 are N-type transistors. The source of the transistor 3022 is coupled to the first reference voltage V1 , the drain of the transistor 3022 is coupled to the node N, and the gate of the transistor 3022 is coupled to the node NB. The source of the transistor 3024 is coupled to the first reference voltage V1 , the drain of the transistor 3024 is coupled to the node NB, and the gate of the transistor 3024 is coupled to the node N. The source of the transistor 3026 is coupled to the second reference voltage V2 , the drain of the transistor 3026 is coupled to the node N, and the gate of the transistor 3026 is coupled to the node NB. The source of the transistor 3028 is coupled to the second reference voltage V2 , the drain of the transistor 3028 is coupled to the node NB, and the gate of the transistor 3028 is coupled to the node N.

非揮發性記憶體胞元包含N型浮閘電晶體（Floating-gate MOSFET）3042以及N型浮閘電晶體3044。N型浮閘電晶體3042耦接於節點N和位線（bitline）BL之間，且N型浮閘電晶體3042的閘極耦接字線（wordline）WL；N型浮閘電晶體3044耦接於節點NB和互補位線（complementary bitline）BLB之間，且N型浮閘電晶體3044的閘極耦接字線WL。在本實施例中，第一參考電壓V1高於第二參考電壓V2，例如第二參考電壓V2可以是接地電壓。此外應注意的是，依據本實施例的操作原理，亦可針對本實施例中各電晶體的配置及/或極性做進一步調整。The non-volatile memory cell includes an N-type floating-gate MOSFET (Floating-gate MOSFET) 3042 and an N-type floating-gate MOSFET 3044 . The N-type floating gate transistor 3042 is coupled between the node N and the bit line (bitline) BL, and the gate of the N-type floating gate transistor 3042 is coupled to the word line (wordline) WL; the N-type floating gate transistor 3044 is coupled It is connected between the node NB and a complementary bitline BLB, and the gate of the N-type floating gate transistor 3044 is coupled to the wordline WL. In this embodiment, the first reference voltage V1 is higher than the second reference voltage V2, for example, the second reference voltage V2 may be a ground voltage. In addition, it should be noted that according to the operating principle of the present embodiment, the configuration and/or polarity of each transistor in the present embodiment can also be further adjusted.

以物理不可複製函數電路300來說，初始階段又包含初始值設定階段以及程式化階段。如圖4所示，在初始值設定階段，字線WL的電壓被設定成低電壓電平（例如可以是第二參考電壓V2），以及位線BL和互補位線BLB的電壓被設定成高電壓電平（例如可以是第一參考電壓V1）。在此假設因為製程不匹配造成節點N的電壓高於節點NB，即節點N的電壓為第一參考電壓V1，節點NB的電壓為第二參考電壓V2，以便後續說明。For the physically non-clonable function circuit 300, the initial stage includes an initial value setting stage and a programming stage. As shown in FIG. 4, in the initial value setting stage, the voltage of the word line WL is set to a low voltage level (for example, it may be the second reference voltage V2), and the voltages of the bit line BL and the complementary bit line BLB are set to high A voltage level (for example, it may be the first reference voltage V1). It is assumed here that the voltage of the node N is higher than the node NB due to process mismatch, that is, the voltage of the node N is the first reference voltage V1, and the voltage of the node NB is the second reference voltage V2, for the sake of subsequent description.

接着進入程式化階段時，如圖5所示，位線BL和互補位線BLB的電壓被設定成低電壓電平（例如可以是第二參考電壓V2），以及字線WL的電壓被設定成高電壓電平（例如可以是第一參考電壓V1）。由於節點N的電壓（第一參考電壓V1）高於位線BL的電壓（第二參考電壓V2），N型浮閘電晶體3042會產生通道熱載子注入到浮動匣極造成臨界電壓的上昇。而節點NB的電壓（第二參考電壓V2）等於互補位線BLB的電壓（第二參考電壓V2），N型浮閘電晶體3044不會產生熱載子注入浮動閘極而保持原有的臨界電壓。因此在程式化階段完成後，N型浮閘電晶體3042的臨界電壓會高於N型浮閘電晶體3044的臨界電壓。When entering the programming stage, as shown in FIG. 5, the voltages of the bit line BL and the complementary bit line BLB are set to a low voltage level (such as the second reference voltage V2), and the voltage of the word line WL is set to A high voltage level (eg, may be the first reference voltage V1 ). Since the voltage of the node N (the first reference voltage V1) is higher than the voltage of the bit line BL (the second reference voltage V2), the N-type floating gate transistor 3042 will generate channel hot carriers and inject them into the floating gate, resulting in an increase in the critical voltage . And the voltage of the node NB (the second reference voltage V2) is equal to the voltage of the complementary bit line BLB (the second reference voltage V2), and the N-type floating gate transistor 3044 will not generate hot carriers into the floating gate and maintain the original critical Voltage. Therefore, after the programming phase is completed, the threshold voltage of the N-type floating gate transistor 3042 is higher than the threshold voltage of the N-type floating gate transistor 3044 .

當物理不可複製函數電路300下電之後再重新上電時，由於位線BL和互補位線BLB的電壓一般會先經過電源開關，因此充電的時間會相對落後。加上N型浮閘電晶體3042的臨界電壓被程式化為高於N型浮閘電晶體3044的臨界電壓，因此使得節點NB會比節點N點更容易偏向低電壓電平（例如可以是第二參考電壓）。也就是說，利用N型浮閘電晶體3042和N型浮閘電晶體3044，可以加強揮發性記憶體胞元中節點N和節點NB原本的電壓偏好，使物理不可複製函數電路300的穩定性大幅提升。When the physical non-clonable function circuit 300 is powered off and then powered on again, since the voltages of the bit line BL and the complementary bit line BLB generally pass through the power switch first, the charging time will be relatively late. In addition, the threshold voltage of the N-type floating gate transistor 3042 is programmed to be higher than the threshold voltage of the N-type floating gate transistor 3044, so that the node NB is more likely to be biased towards a low voltage level than the node N point (for example, it can be the first Two reference voltages). That is to say, by using the N-type floating gate transistor 3042 and the N-type floating gate transistor 3044, the original voltage preference of the node N and the node NB in the volatile memory cell can be strengthened, so that the stability of the physically irreproducible function circuit 300 can be enhanced. Substantially improved.

本申請的物理不可複製函數電路100/200/300可大幅提高傳統的物理不可複製函數電路的穩定性，因而可省去錯誤更正電路。換句話說，本申請的物理不可複製函數電路100/200/300可以在實現基於物理不可複製函數的認證機制時，提高穩定性及降低成本。The physical non-reproducible function circuit 100/200/300 of the present application can greatly improve the stability of the traditional physical non-reproducible function circuit, so that the error correction circuit can be omitted. In other words, the physically non-clonable function circuit 100/200/300 of the present application can improve stability and reduce costs when implementing an authentication mechanism based on a physically non-clonable function.

本申請還提出一種晶片，包含物理不可複製函數電路100/200/300設置於其中。本申請還提出一種包含該晶片的電子裝置。具體來說，該電子裝置可包含但不限於行動通信設備、超級行動電腦、可擕式娛樂設備和其他的電子設備。行動通信設備的特點是具備行動通信功能，並且以提供語音、資料通信為主要目標。這類設備包括：智慧型手機（例如iPhone）、多媒體手機、功能性手機，以及低端手機等。超級行動電腦屬於個人電腦的範疇，有計算和處理功能，一般也具備行動上網特性。這類設備包括：PDA、MID和UMPC設備等，例如iPad。可擕式娛樂設備可以顯示和播放多媒體內容。該類設備包括：音訊、影片播放機（例如iPod），掌上遊戲機，電子書，以及智慧玩具和可擕式車載導航設備。The present application also proposes a chip including a physically non-replicable function circuit 100/200/300 disposed therein. The application also proposes an electronic device including the chip. Specifically, the electronic device may include but not limited to mobile communication equipment, super mobile computer, portable entertainment equipment and other electronic equipment. The characteristic of mobile communication equipment is that it has mobile communication functions, and its main goal is to provide voice and data communication. Such devices include: smart phones (such as iPhone), multimedia phones, feature phones, and low-end phones. Super mobile computers belong to the category of personal computers, which have computing and processing functions, and generally have mobile Internet features. Such devices include: PDA, MID and UMPC devices, such as iPad. Portable entertainment devices can display and play multimedia content. Such devices include: audio and video players (such as iPod), handheld game consoles, e-books, as well as smart toys and portable car navigation devices.

上文的敘述簡要地提出了本發明某些實施例之特徵，而使得本發明所屬技術領域具有通常知識者能夠更全面地理解本發明內容的多種態樣。本發明所屬技術領域具有通常知識者當可明瞭，其可輕易地利用本發明內容作為基礎，來設計或更動其他製程與結構，以實現與此處之實施方式相同的目的和/或達到相同的優點。本發明所屬技術領域具有通常知識者應當明白，這些均等的實施方式仍屬於本發明內容之精神與範圍，且其可進行各種變更、替代與更動，而不會悖離本發明內容之精神與範圍。The foregoing description briefly presents features of some embodiments of the present invention, so that those skilled in the art to which the present invention pertains can more fully understand various aspects of the present invention. Those with ordinary knowledge in the technical field of the present invention should understand that they can easily use the content of the present invention as a basis to design or modify other processes and structures to achieve the same purpose and/or achieve the same purpose as the embodiment here advantage. Those with ordinary knowledge in the technical field of the present invention should understand that these equivalent embodiments still belong to the spirit and scope of the present invention, and various changes, substitutions and changes can be made without departing from the spirit and scope of the present invention. .

100,200,300:物理不可複製函數電路100,200,300: physically non-reproducible functional circuits

102:圖案產生器102:Pattern Generator

104:可程式化電路104: Programmable circuit

202,302:揮發性記憶體202,302: Volatile memory

204,304:非揮發性記憶體204,304: Non-volatile memory

3022,3024:P型電晶體3022,3024: P-type transistor

3026,3028:N型電晶體3026,3028: N-type transistor

3042,3044:N型浮閘電晶體3042,3044: N-type floating gate transistor

BL:位線BL: bit line

BLB:互補位線BLB: complementary bit line

Dp:偏好的電壓值Dp: preferred voltage value

N,NB:節點N, NB: node

Sc:質詢訊號Sc: challenge signal

V1:第一參考電壓V1: the first reference voltage

V2:第二參考電壓V2: Second reference voltage

WL:字線WL: word line

結合附圖閱讀以下詳細描述會最佳地理解本發明之態樣。應注意，各種特徵可能未按比例繪製。事實上，可出於論述清楚起見，而任意地增大或減小各種特徵之尺寸。Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

圖1為本發明的物理不可複製函數電路的示意圖。FIG. 1 is a schematic diagram of a physically non-clonable function circuit of the present invention.

圖2為本發明的物理不可複製函數電路的第一實施例的示意圖。FIG. 2 is a schematic diagram of the first embodiment of the physically non-clonable function circuit of the present invention.

圖3為本發明的物理不可複製函數電路的第二實施例的示意圖。FIG. 3 is a schematic diagram of a second embodiment of the physically non-clonable function circuit of the present invention.

圖4為本發明的物理不可複製函數電路的第二實施例操作在初始值設定階段的示意圖。FIG. 4 is a schematic diagram of the operation of the second embodiment of the physically non-clonable function circuit in the initial value setting stage of the present invention.

圖5為本發明的物理不可複製函數電路的第二實施例操作在程式化階段的示意圖。FIG. 5 is a schematic diagram of the operation of the second embodiment of the physical non-clonable function circuit of the present invention in the programming stage.

100:物理不可複製函數電路 100: Physically non-reproducible function circuits

102:圖案產生器 102:Pattern Generator

104:可程式化電路 104: Programmable circuit

Dp:偏好的電壓值 Dp: preferred voltage value

Sc:質詢訊號 Sc: challenge signal

Claims (12)

一種物理不可複製函數電路，包括：圖案產生器，其中該物理不可複製函數電路上電時，該圖案產生器依據本身的製程不匹配特性及當下的環境因子形成偏好的電壓值，該偏好的電壓值具有隨機性，且該偏好的電壓值在該物理不可複製函數電路下電時揮發佚失；以及可程式化電路，耦接該圖案產生器，用來依據該圖案產生器形成之該偏好的電壓值來被程式化，該可程式化電路被程式化的結果在該物理不可複製函數電路下電時不揮發佚失；其中在初始階段，該圖案產生器形成之該偏好的電壓值被利用來程式化該可程式化電路，其中該物理不可複製函數電路僅在第一次上電時進入該初始階段；以及其中該圖案產生器包含揮發性記憶體胞元，以及該可程式化電路包含非揮發性記憶體胞元，並且於該初始階段，該揮發性記憶體胞元形成之該偏好的電壓值被儲存至該非揮發性記憶體胞元。 A physical non-reproducible function circuit, including: a pattern generator, wherein when the physical non-reproducible function circuit is powered on, the pattern generator forms a preferred voltage value according to its own process mismatch characteristics and current environmental factors, and the preferred voltage The value is random, and the preferred voltage value is volatile and lost when the physical non-replicable function circuit is powered off; and a programmable circuit, coupled to the pattern generator, is used to form the preference according to the pattern generator The programmable voltage value is programmed, and the programmed result of the programmable circuit is not volatile and lost when the physical non-reproducible function circuit is powered off; wherein in the initial stage, the preferred voltage value formed by the pattern generator is used to program the programmable circuit, wherein the physically non-reproducible function circuit enters the initial stage only when powered on for the first time; and wherein the pattern generator comprises volatile memory cells, and the programmable circuit comprises non-volatile memory cells, and in the initial stage, the preferred voltage value formed by the volatile memory cells is stored in the non-volatile memory cells. 如請求項1的物理不可複製函數電路，其中該偏好的電壓值通過該可程式化電路被輸出，以回應來自該物理不可複製函數電路之外的質詢訊號。 The physical non-reproducible function circuit as claimed in claim 1, wherein the preferred voltage value is output through the programmable circuit in response to an inquiry signal from outside the physically non-reproducible function circuit. 如請求項1的物理不可複製函數電路，其中該非揮發性記憶體胞元所儲存之該偏好的電壓值被輸出，以回應來自該物理不可複製函數電路之外 的質詢訊號。 The physical non-reproducible function circuit as claimed in claim 1, wherein the preferred voltage value stored in the non-volatile memory cell is output in response to a signal from outside the physically non-reproducible function circuit query signal. 如請求項1的物理不可複製函數電路，其中該揮發性記憶體胞元包含：第一P型電晶體，包含汲極、源極和閘極，該第一P型電晶體的源極耦接至第一參考電壓，該第一P型電晶體的汲極耦接至第一節點，該第一P型電晶體的閘極耦接至第二節點；第二P型電晶體，包含汲極、源極和閘極，該第二P型電晶體的源極耦接至該第一參考電壓，該第一P型電晶體的汲極耦接至該第二節點，該第二P型電晶體的閘極耦接至該第一節點；第一N型電晶體，包含汲極、源極和閘極，該第一N型電晶體的源極耦接至第二參考電壓，該第一N型電晶體的汲極耦接至該第一節點，該第一N型電晶體的閘極耦接至該第二節點；以及第二N型電晶體，包含汲極、源極和閘極，該第二N型電晶體的源極耦接至該第二參考電壓，該第二N型電晶體的汲極耦接至該第二節點，該第二N型電晶體的閘極耦接至該第一節點。 The physical non-replicable function circuit as claimed in item 1, wherein the volatile memory cell includes: a first P-type transistor, including a drain, a source and a gate, and the source of the first P-type transistor is coupled to To the first reference voltage, the drain of the first P-type transistor is coupled to the first node, and the gate of the first P-type transistor is coupled to the second node; the second P-type transistor includes the drain , source and gate, the source of the second P-type transistor is coupled to the first reference voltage, the drain of the first P-type transistor is coupled to the second node, and the second P-type transistor The gate of the crystal is coupled to the first node; the first N-type transistor includes a drain, a source and a gate, the source of the first N-type transistor is coupled to a second reference voltage, and the first The drain of the N-type transistor is coupled to the first node, the gate of the first N-type transistor is coupled to the second node; and the second N-type transistor includes a drain, a source and a gate. , the source of the second N-type transistor is coupled to the second reference voltage, the drain of the second N-type transistor is coupled to the second node, and the gate of the second N-type transistor is coupled to to the first node. 如請求項4的物理不可複製函數電路，其中該可程式化電路包含非揮發性記憶體胞元，包含：第一N型浮閘電晶體，耦接於該第一節點和位線之間，且該第一N型浮閘電晶體的閘極耦接字線；以及第二N型浮閘電晶體，耦接於該第二節點和該位線的互補位線之間，且該第二N型浮閘電晶體的閘極耦接該字線。 The physical non-replicable function circuit according to claim 4, wherein the programmable circuit includes a non-volatile memory cell, including: a first N-type floating gate transistor coupled between the first node and a bit line, And the gate of the first N-type floating gate transistor is coupled to the word line; and the second N-type floating gate transistor is coupled between the second node and the complementary bit line of the bit line, and the second The gate of the N-type floating gate transistor is coupled to the word line. 如請求項5的物理不可複製函數電路，其中在該初始階段中的初始值設定階段，該字線的電壓被設定成該第二參考電壓，以及該位線和該互補位線的電壓被設定成該第一參考電壓。 The physically non-clonable function circuit as claimed in claim 5, wherein in the initial value setting stage in the initial stage, the voltage of the word line is set to the second reference voltage, and the voltages of the bit line and the complementary bit line are set into the first reference voltage. 如請求項6的物理不可複製函數電路，其中在該初始階段中的程式化階段，該位線和該互補位線的電壓被設定成該第二參考電壓，以及該字線的電壓被設定成該第一參考電壓，使該非揮發性記憶胞元依據該揮發性記憶體胞元之該偏好的電壓值被程式化。 The physically non-clonable function circuit as claimed in claim 6, wherein in the programming stage in the initial stage, the voltages of the bit line and the complementary bit line are set to the second reference voltage, and the voltage of the word line is set to The first reference voltage enables the non-volatile memory cell to be programmed according to the preferred voltage value of the volatile memory cell. 如請求項7的物理不可複製函數電路，其中在該初始值設定階段，該第一節點的電壓高於該第二節點的電壓，以及經過該程式化階段後，該第一N型浮閘電晶體的臨界電壓高於該第二N型浮閘電晶體的臨界電壓。 The physical non-reproducible function circuit according to claim 7, wherein in the initial value setting stage, the voltage of the first node is higher than the voltage of the second node, and after the programming stage, the first N-type floating gate The critical voltage of the crystal is higher than the critical voltage of the second N-type floating gate transistor. 如請求項4的物理不可複製函數電路，其中該第一參考電壓高於該第二參考電壓。 The physically non-clonable function circuit according to claim 4, wherein the first reference voltage is higher than the second reference voltage. 如請求項1的物理不可複製函數電路，其中該環境因子包含環境溫度或供應給該圖案產生器的電壓中的至少一者。 The physically non-clonable function circuit of claim 1, wherein the environmental factor includes at least one of ambient temperature or a voltage supplied to the pattern generator. 一種晶片，包括：如請求項1所述的物理不可複製函數電路。 A chip, comprising: the physically non-reproducible functional circuit as described in Claim 1. 一種電子裝置，包括：如請求項11所述的晶片。 An electronic device, comprising: the wafer as claimed in claim 11.
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