TWI780521B - Electronic device and multiplexing method of spatial - Google Patents

Electronic device and multiplexing method of spatial Download PDF

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TWI780521B
TWI780521B TW109141207A TW109141207A TWI780521B TW I780521 B TWI780521 B TW I780521B TW 109141207 A TW109141207 A TW 109141207A TW 109141207 A TW109141207 A TW 109141207A TW I780521 B TWI780521 B TW I780521B
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target area
completion message
message
writing
processing instruction
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TW109141207A
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TW202221496A (en
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林帥
胡昭耀
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大陸商合肥沛睿微電子股份有限公司
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Abstract

An electronic device includes a memory, a processor and function hardware. The memory includes a queue. The processor is configured to write at least one processing command into at least one target area of the queue. The function hardware is configured to read the at least one processing command from the at least one target area. The function hardware generates at least one completion message after executing the at least one processing command, and write the at least one completion message into the at least one target area. The at least one completion message correspond to the at least one processing command.

Description

電子裝置及空間複用方法Electronic device and space multiplexing method

本案是關於儲存空間的使用技術，特別是一種可提高儲存利用率的電子裝置及空間複用方法。 This case is about the utilization technology of storage space, especially an electronic device and space multiplexing method that can improve storage utilization.

在系統運作中，處理器可透過匯流排來調度各個功能硬體進行相關運算與數據處理，以完成整個系統功能。一般而言，處理器會透過處理指令來下達執行任務給功能硬體，且功能硬體於執行完任務後會透過完成訊息來反饋給處理器。 During system operation, the processor can dispatch various functional hardware through the bus to perform relevant calculations and data processing, so as to complete the entire system function. Generally speaking, the processor will issue execution tasks to the functional hardware by processing instructions, and the functional hardware will feed back to the processor through a completion message after executing the task.

傳統上，需於系統中配置兩個獨立的儲存空間以分別儲存處理指令與完成訊息，因而佔用了不少儲存空間。 Traditionally, two independent storage spaces need to be configured in the system to store processing instructions and completion messages respectively, thus occupying a lot of storage space.

本案提供一種電子裝置。在一實施例中，電子裝置包含記憶體、處理器與功能硬體。記憶體包含佇列。處理器用以儲存至少一處理指令至佇列的至少一目標區。功能硬體用以自目標區讀取至少一處理指令。功能硬體於執行完至少一處理指令後產生至少一完成訊息，並將至少一完成訊息寫入至至少一目標區中，其中，該至少一完成訊息係相對應於該至少一處理指令。 This case provides an electronic device. In one embodiment, the electronic device includes a memory, a processor and functional hardware. Memory contains queues. The processor is used for storing at least one processing instruction in at least one target area of the queue. The functional hardware is used for reading at least one processing instruction from the target area. The functional hardware generates at least one completion message after executing at least one processing instruction, and writes at least one completion message into at least one target area, wherein the at least one completion message corresponds to the at least one processing instruction.

本案提供一種空間複用方法。在一實施例中，空間複用方 法包含：依據至少一處理指令以決定出至少一目標區的大小，其中該至少一目標區係位於一記憶體之一佇列；寫入該至少一處理指令至記憶體之佇列中的該至少一目標區；自該至少一目標區讀取該至少一處理指令；執行該至少一處理指令後產生至少一完成訊息；寫入該至少一完成訊息至該至少一目標區中；及自該至少一目標區中讀取該至少一完成訊息。 This case provides a space multiplexing method. In one embodiment, the spatial multiplexer The method includes: determining the size of at least one target area according to at least one processing instruction, wherein the at least one target area is located in a memory queue; writing the at least one processing instruction to the memory queue At least one target area; read the at least one processing command from the at least one target area; generate at least one completion message after executing the at least one processing command; write the at least one completion message into the at least one target area; and from the at least one target area The at least one completion message is read from at least one target area.

以下在實施方式中詳細敘述本案之詳細特徵以及優點，其內容足以使任何熟習相關技藝者瞭解本案之技術內容並據以實施，且根據本說明書所揭露之內容、申請專利範圍及圖式，任何熟習相關技藝者可輕易地理解本案相關之目的及優點。 The detailed features and advantages of this case are described in detail below in the implementation mode. The content is enough to make any person familiar with the related art understand the technical content of this case and implement it according to the content disclosed in this specification. Those who are familiar with the related art can easily understand the purpose and advantages related to this case.

100:電子裝置 100: Electronic device

110:記憶體 110: memory

120:處理器 120: Processor

130:功能硬體 130: Functional hardware

140:匯流排 140: busbar

150:暫存器檔案 150:Scratch file

A1:狀態欄 A1: status bar

A2:儲存欄 A2: storage column

C1-C4:處理指令 C1-C4: Processing instructions

C41-C42:子處理指令 C41-C42: Subprocessing instructions

D31-D32:假指令 D31-D32: false instruction

D41:假訊息 D41: Fake news

M1-M4:完成訊息 M1-M4: Completion message

M31-M33:子完成訊息 M31-M33: Sub completion message

PC1:指令寫入指標 PC1: Instruction write indicator

PC2:指令讀取指標 PC2: Instruction read indicator

PM1:訊息寫入指標 PM1: message writing indicator

PM2:訊息讀取指標 PM2: Message reading indicator

Q1:佇列 Q1: Queue

Q11-Q1n:儲存塊 Q11-Q1n: storage block

T1-T4:目標區 T1-T4: target area

S01-S06:步驟 S01-S06: Steps

圖1為本案電子裝置之一實施例的方塊示意圖。 FIG. 1 is a schematic block diagram of an embodiment of the electronic device of the present invention.

圖2為本案空間複用方法之一實施例的流程示意圖。 Fig. 2 is a schematic flow chart of an embodiment of the spatial multiplexing method in this case.

圖3為處理指令與完成訊息在佇列中複用空間之一實施例的示意圖。 FIG. 3 is a schematic diagram of an embodiment of multiplexing spaces in queues for processing instructions and completion messages.

圖4為佇列於初始狀態下之一實施例的概要示意圖。 FIG. 4 is a schematic diagram of an embodiment of the queue in an initial state.

圖5為寫入至少一處理指令至佇列之至少一目標區後的概要示意圖。 FIG. 5 is a schematic diagram after writing at least one processing instruction into at least one target area of the queue.

圖6為自圖5之佇列中讀取至少一處理指令後的概要示意圖。 FIG. 6 is a schematic diagram of reading at least one processing instruction from the queue in FIG. 5 .

圖7為寫入至少一完成訊息至圖5之佇列中後的概要示意圖。 FIG. 7 is a schematic diagram after writing at least one completion message into the queue of FIG. 5 .

圖8為自圖7之佇列中讀取至少一完成訊息後的概要示意圖。 FIG. 8 is a schematic diagram of reading at least one completion message from the queue in FIG. 7 .

圖9為寫入至少一處理指令至圖8之佇列中後的概要示意圖。 FIG. 9 is a schematic diagram of writing at least one processing instruction into the queue of FIG. 8 .

圖10為寫入至少一完成訊息至圖9之佇列中後的概要示意圖。 FIG. 10 is a schematic diagram after writing at least one completion message into the queue of FIG. 9 .

圖11為自圖10之佇列中讀取至少一完成訊息後的概要示意圖。 FIG. 11 is a schematic diagram of reading at least one completion message from the queue in FIG. 10 .

為使本案之實施例之上述目的、特徵和優點能更明顯易懂，下文配合所附圖式，作詳細說明如下。 In order to make the above-mentioned purpose, features and advantages of the embodiments of the present case more comprehensible, a detailed description is given below in conjunction with the accompanying drawings.

請參閱圖1，電子裝置100包含記憶體110、處理器120與功能硬體130，且記憶體110耦接於處理器120與功能硬體130。其中，各個數量並非以此為限，且是為了說明方便而皆以一個作為例示。在一些實施例中，處理器120與功能硬體130可分別透過匯流排(BUS)140耦接於記憶體110。 Referring to FIG. 1 , the electronic device 100 includes a memory 110 , a processor 120 and functional hardware 130 , and the memory 110 is coupled to the processor 120 and the functional hardware 130 . Wherein, each number is not limited thereto, and one is used as an example for the convenience of description. In some embodiments, the processor 120 and the functional hardware 130 are respectively coupled to the memory 110 through a bus (BUS) 140 .

記憶體110包含佇列Q1，且佇列Q1可包含串列的複數儲存塊Q11-Q1n。在一些實施例中，n為大於1之正整數，且n的大小(即佇列Q1之大小)可由處理器120事先設定。但是佇列Q1之大小並非自此固定，處理器120於設定後可更根據其對此佇列Q1的訪問度來動態地調整，以有效利用記憶體110之空間。在一些實施態樣中，記憶體110可例如但不限於為靜態隨機存取記憶體(SRAM)、動態隨機存取記憶體(DRAM)或快閃記憶體。 The memory 110 includes a queue Q1, and the queue Q1 may include a plurality of storage blocks Q11-Q1n in series. In some embodiments, n is a positive integer greater than 1, and the size of n (that is, the size of the queue Q1 ) can be preset by the processor 120 . However, the size of the queue Q1 is not fixed from then on. After setting, the processor 120 can dynamically adjust it according to its access to the queue Q1, so as to effectively use the space of the memory 110 . In some implementation aspects, the memory 110 may be, for example but not limited to, static random access memory (SRAM), dynamic random access memory (DRAM) or flash memory.

處理器120可用以產生處理指令C1，並將處理指令C1透過匯流排140寫入至記憶體110之佇列Q1中。功能硬體130可透過匯流排140自佇列Q1取得並執行處理指令C1。於執行完處理指令C1後，功能硬體130可根據執行結果產生完成訊息M1，並且將完成訊息M1寫入至記憶體110之佇列Q1中。其中，完成訊息M1系對應於處理指令C1。特別的是，本案任一實施例之電子裝置100可執行任一實施例之空間複用 方法，以提高記憶體110的儲存利用率。 The processor 120 can be used to generate the processing instruction C1 and write the processing instruction C1 into the queue Q1 of the memory 110 through the bus 140 . The functional hardware 130 can obtain and execute the processing instruction C1 from the queue Q1 through the bus 140 . After executing the processing command C1 , the functional hardware 130 can generate a completion message M1 according to the execution result, and write the completion message M1 into the queue Q1 of the memory 110 . Wherein, the completion message M1 corresponds to the processing instruction C1. In particular, the electronic device 100 of any embodiment of the present application can implement the spatial multiplexing of any embodiment method to improve the storage utilization of the memory 110 .

在一些實施態樣中，處理器120可利用系統單晶片(SoC)、中央處理器(CPU)、微控制器(MCU)、嵌入式控制器(Embedded Controller)、特殊應用積體電路(ASIC)、應用處理器(AP)或其他任何適用的電子組件來實現。此外，功能硬體130可為各式硬體組件，例如但不限於顯示卡、網路卡、音效卡等。 In some implementations, the processor 120 can utilize a system-on-chip (SoC), a central processing unit (CPU), a microcontroller (MCU), an embedded controller (Embedded Controller), an application-specific integrated circuit (ASIC) , application processor (AP) or any other suitable electronic components. In addition, the functional hardware 130 can be various hardware components, such as but not limited to a display card, a network card, a sound card, and the like.

請參閱圖1至圖3，在空間複用方法之一實施例中，電子裝置100之處理器120於產生處理指令C1後，可將處理指令C1寫入至佇列Q1的目標區T1中(步驟S01)。其中，目標區T1包含複數儲存塊Q11-Q1n中的至少一個，且目標區T1所涵蓋的儲存塊數量可由處理器120決定。電子裝置100之功能硬體130可自目標區T1讀取處理指令C1(步驟S02)，以執行處理指令C1，並且於執行完處理指令C1後產生完成訊息M1(步驟S03)。之後，功能硬體130再將完成訊息M1寫入回佇列Q1的目標區T1中(步驟S04)。如此，處理指令C1與完成訊息M1可複用同一個儲存空間(即，目標區T1)，從而提升儲存利用率。此外，處理器120可更從目標區T1中讀取完成訊息M1(步驟S05)，以根據完成訊息M1得知處理指令C1的執行狀況，例如執行成功、失敗、發生錯誤等。 1 to 3, in one embodiment of the spatial multiplexing method, after the processor 120 of the electronic device 100 generates the processing command C1, it can write the processing command C1 into the target area T1 of the queue Q1 ( Step S01). Wherein, the target area T1 includes at least one of the plurality of storage blocks Q11 - Q1n, and the number of storage blocks covered by the target area T1 can be determined by the processor 120 . The functional hardware 130 of the electronic device 100 can read the processing command C1 from the target area T1 (step S02 ) to execute the processing command C1 , and generate a completion message M1 after executing the processing command C1 (step S03 ). Afterwards, the functional hardware 130 writes the completion message M1 back into the target area T1 of the queue Q1 (step S04 ). In this way, the processing instruction C1 and the completion message M1 can reuse the same storage space (ie, the target area T1 ), thereby improving storage utilization. In addition, the processor 120 may further read the completion message M1 from the target area T1 (step S05 ), so as to know the execution status of the processing instruction C1 according to the completion message M1 , such as execution success, failure, error, etc.

處理器120可更用以產生複數處理指令C1-C4。因此，在步驟S01之一實施例中，處理器120可將複數處理指令C1-C4寫入至佇列Q1的複數目標區T1-T4中。其中，各處理指令C1-C4可對應於複數目標區T1-T4中之一者。舉例而言，處理器120可分別根據各處理指令C1-C4於佇列Q1中規劃出相應的目標區T1-T4，並將處理指令C1-C4分別寫入 至目標區T1-T4中。例如，處理器120可將處理指令C1-C4分別依序寫入至目標區T1-T4中。於此，目標區T1-T4可依序串接，例如目標區T1涵蓋了儲存塊Q11，目標區T2涵蓋了儲存塊Q12而串接於目標區T1之後，目標區T3涵蓋了儲存塊Q13-Q15而串接於目標區T2之後，且目標區T4涵蓋了儲存塊Q16-Q17而串接於目標區T3之後。其中，各目標區T1-T4所涵蓋的儲存塊數量可不相同，且各目標區T1-T4所涵蓋的儲存塊數量之決策將留待後方做詳細解說。 The processor 120 can be further used to generate complex processing instructions C1-C4. Therefore, in an embodiment of step S01 , the processor 120 may write the plurality of processing instructions C1 - C4 into the plurality of target areas T1 - T4 of the queue Q1 . Wherein, each processing instruction C1-C4 may correspond to one of the plurality of target areas T1-T4. For example, the processor 120 can plan the corresponding target areas T1-T4 in the queue Q1 according to the processing instructions C1-C4 respectively, and write the processing instructions C1-C4 into to target zone T1-T4. For example, the processor 120 may sequentially write the processing instructions C1-C4 into the target areas T1-T4 respectively. Here, the target areas T1-T4 can be connected sequentially. For example, the target area T1 covers the storage block Q11, the target area T2 covers the storage block Q12 and is connected in series after the target area T1, and the target area T3 covers the storage blocks Q13- Q15 is serially connected after the target area T2, and the target area T4 covers the storage blocks Q16-Q17 and is serially connected after the target area T3. Wherein, the number of storage blocks covered by each target area T1-T4 may be different, and the decision on the number of storage blocks covered by each target area T1-T4 will be explained in detail later.

相應地，在步驟S02至步驟S04之一實施例中，功能硬體130可自目標區T1-T4中讀取處理指令C1-C4，以分別執行處理指令C1-C4。於分別執行完處理指令C1-C4後，功能硬體130可分別產生相應的完成訊息M1-M4，並將完成訊息M1-M4分別回存至相應的目標區T1-T4中。舉例而言，功能硬體130於執行完處理指令C1後產生完成訊息M1，並將完成訊息M1回存至目標區T1，以複用處理指令C1所使用過的儲存空間(即目標區T1)。依此順序類推至處理指令C4，功能硬體130於執行完處理指令C4後產生完成訊息M4，並將完成訊息M4回存至目標區T4，以複用處理指令C4所使用過的儲存空間(即目標區T4)。相應地，在步驟S05之一實施例中，處理器120可從目標區T1-T4中讀取完成訊息M1-M4，以根據各完成訊息M1-M4得知各處理指令C1-C4的執行狀況。 Correspondingly, in one embodiment of step S02 to step S04 , the functional hardware 130 can read the processing instructions C1 - C4 from the target areas T1 - T4 to execute the processing instructions C1 - C4 respectively. After executing the processing instructions C1-C4 respectively, the functional hardware 130 can generate corresponding completion messages M1-M4 respectively, and store the completion messages M1-M4 back into corresponding target areas T1-T4 respectively. For example, the functional hardware 130 generates a completion message M1 after executing the processing instruction C1, and stores the completion message M1 back into the target area T1, so as to reuse the storage space used by the processing instruction C1 (ie, the target area T1) . By analogy to the processing instruction C4 in this order, the functional hardware 130 generates a completion message M4 after executing the processing instruction C4, and stores the completion message M4 back into the target area T4 to reuse the storage space used by the processing instruction C4 ( Namely the target zone T4). Correspondingly, in one embodiment of step S05, the processor 120 can read the completion messages M1-M4 from the target area T1-T4, so as to know the execution status of each processing instruction C1-C4 according to each completion message M1-M4 .

需注意的是，本案並未限定步驟S02至步驟S04需於步驟S01整個執行完後才執行。即便處理器120仍在將另一筆處理指令存至佇列Q1之目標區中(即步驟S01仍在執行中)，只要佇列Q1中尚存有未被 執行的處理指令，功能硬體130便可執行步驟S02至步驟S04。例如，佇列Q1之目標區T1中已存有處理指令C1，且處理器120接續在將處理指令C2寫入至目標區T2，此時功能硬體130便可開始執行步驟S02至步驟S04，即功能硬體130可將處理指令C1自目標區T1中取出且執行，並將執行完後所產生的完成訊息M1回存至目標區T1中。同樣地，在步驟S05中，只要佇列Q1中存有完成訊息，處理器120便可自佇列Q1中取出完成訊息。甚至，處理器120更可待佇列Q1中所存之完成訊息的數量累積到一定數量後再開始執行步驟S05。 It should be noted that this application does not limit that the steps S02 to S04 need to be executed after the entire execution of the step S01 is completed. Even if the processor 120 is still storing another processing instruction in the target area of the queue Q1 (that is, step S01 is still being executed), as long as there are still unused commands in the queue Q1 With the executed processing instructions, the functional hardware 130 can execute steps S02 to S04. For example, the processing instruction C1 is already stored in the target area T1 of the queue Q1, and the processor 120 continues to write the processing instruction C2 into the target area T2. At this time, the functional hardware 130 can start to execute steps S02 to S04, That is, the functional hardware 130 can fetch and execute the processing instruction C1 from the target area T1 , and store the completion message M1 generated after the execution into the target area T1 . Similarly, in step S05, as long as there is a completion message in the queue Q1, the processor 120 can retrieve the completion message from the queue Q1. Furthermore, the processor 120 may wait until the number of completion messages stored in the queue Q1 has accumulated to a certain amount before starting to execute step S05.

此外，本案亦未限定功能硬體130要在步驟S02中一次取完佇列Q1中當前所存的所有處理指令。例如，佇列Q1之目標區T1-T4中分別已存有處理指令C1-C4，功能硬體130可只先取出並執行目標區T1-T2中的處理指令C1-C2，以分別產生完成訊息M1-M2。並在將完成訊息M1-M2分別回存至目標區T1-T2後，功能硬體130再取出目標區T3-T4中的處理指令C3-C4來執行。其中，功能硬體130一次可執行的指令數量端視其處理能力而定。 In addition, this case does not limit the functional hardware 130 to fetch all processing instructions currently stored in the queue Q1 in step S02 . For example, the processing instructions C1-C4 are already stored in the target areas T1-T4 of the queue Q1, and the functional hardware 130 can only fetch and execute the processing instructions C1-C2 in the target areas T1-T2 to generate completion messages respectively M1-M2. And after storing the completed messages M1-M2 back into the target areas T1-T2 respectively, the functional hardware 130 fetches the processing instructions C3-C4 in the target areas T3-T4 for execution. Wherein, the number of instructions that the functional hardware 130 can execute at one time depends on its processing capability.

在一些實施例中，其中該處理器120根據該處理指令C1-C4以預先決定出該完成訊息M1-M4的大小。具體而言，處理器120於產生各處理指令C1-C4時便可知道各處理指令C1-C4之大小。並且，處理器120可根據各處理指令C1-C4預先得知屆時對應之各完成訊息M1-M4之大小。例如，處理器120可根據各處理指令C1-C4的指令類型來得知對應之各完成訊息M1-M4之大小。此外，各指令類型之處理指令與所對應之完成訊息之間的大小比例可事先約定，例如透過程式宣告 等。 In some embodiments, the processor 120 predetermines the size of the completion messages M1-M4 according to the processing instructions C1-C4. Specifically, the processor 120 can know the size of each processing instruction C1-C4 when generating each processing instruction C1-C4. Moreover, the processor 120 can know in advance the sizes of the corresponding completion messages M1-M4 at that time according to the processing instructions C1-C4. For example, the processor 120 can know the sizes of the corresponding completion messages M1-M4 according to the instruction types of the processing instructions C1-C4. In addition, the size ratio between the processing instructions of each instruction type and the corresponding completion message can be agreed in advance, for example, through program declaration Wait.

為了使各完成訊息M1-M4可回存在對應之處理指令C1-C4於佇列Q1中存過的地方，且不覆蓋到其他處理指令，因此在步驟S01前，依據至少一處理指令以(預先)決定出至少一目標區的大小，其中該至少一目標區係位於一記憶體之一佇列。具體而言，處理器120更可以各處理指令C1-C4之大小與相應之各完成訊息M1-M4之大小(預先決定出的該完成訊息M1-M4的大小)中較大者作為各目標區T1-T4之大小，或於各處理指令C1-C4之大小與相等於相應之各完成訊息M1-M4之大小時以各處理指令C1-C4之大小作為各目標區T1-T4之大小(步驟S06)。 In order to make each completion message M1-M4 return to the place where the corresponding processing instructions C1-C4 have been stored in the queue Q1, and not overwrite other processing instructions, therefore, before step S01, according to at least one processing instruction (in advance ) determines the size of at least one target area, wherein the at least one target area is located in a queue of a memory. Specifically, the processor 120 can further use the larger of the size of each processing instruction C1-C4 and the size of each corresponding completion message M1-M4 (the size of the completion message M1-M4 determined in advance) as each target area The size of T1-T4, or when the size of each processing instruction C1-C4 is equal to the size of each corresponding completion message M1-M4, use the size of each processing instruction C1-C4 as the size of each target area T1-T4 (step S06).

舉例而言，假設處理器120已知處理指令C1儲存於佇列Q1時需佔用一個儲存塊且對應之完成訊息M1亦需佔用一個儲存塊，此時由於處理指令C1的大小大致相等於與完成訊息M1之大小，處理器120便可以處理指令C1之大小作為目標區T1之大小，而規劃目標區T1包含一個儲存塊Q11。再例如，假設處理器120已知處理指令C3儲存於佇列Q1時需佔用一個儲存塊且對應之完成訊息M3需佔用三個儲存塊，此時由於完成訊息M3為較大者，處理器120可以完成訊息M3之大小作為目標區T3之大小，而規劃目標區T3包含三個儲存塊Q13-Q15。其中，如圖3所示，完成訊息M3可分成三個子完成訊息M31-M33，而處理器120在寫入時分別寫入在儲存塊Q13-Q15中。又例如，假設處理器120已知處理指令C4儲存於佇列Q1時需佔用二個儲存塊且對應之完成訊息M4需佔用一個儲存塊，此時由於處理指令C4為較大者，處理器120可以處 理指令C4之大小作為目標區T4之大小，而規劃目標區T4包含二個儲存塊Q16-Q17。其中，如圖3所示，處理指令C4可分成二個子處理指令C41-C42，而在寫入時分別寫入在儲存塊Q16-Q17中。 For example, assuming that the processor 120 knows that when the processing instruction C1 is stored in the queue Q1, it needs to occupy a storage block and the corresponding completion message M1 also needs to occupy a storage block. The size of the message M1, the processor 120 can process the size of the instruction C1 as the size of the target area T1, and the planned target area T1 includes a storage block Q11. For another example, assume that the processor 120 needs to occupy one storage block when the processing instruction C3 is stored in the queue Q1 and the corresponding completion message M3 needs to occupy three storage blocks. At this time, since the completion message M3 is the larger one, the processor 120 The size of the message M3 can be completed as the size of the target area T3, and the planned target area T3 includes three storage blocks Q13-Q15. Wherein, as shown in FIG. 3 , the completion message M3 can be divided into three sub-completion messages M31 - M33 , and the processor 120 respectively writes them into the storage blocks Q13 - Q15 when writing. For another example, assume that the processor 120 needs to occupy two storage blocks when the processing instruction C4 is stored in the queue Q1 and the corresponding completion message M4 needs to occupy one storage block. At this time, since the processing instruction C4 is the larger one, the processor 120 Can be dealt with The size of the processing instruction C4 is used as the size of the target area T4, and the planned target area T4 includes two storage blocks Q16-Q17. Wherein, as shown in FIG. 3 , the processing instruction C4 can be divided into two sub-processing instructions C41-C42, which are respectively written into the storage blocks Q16-Q17 when writing.

在步驟S01之一些實施例中，當完成訊息之大小大於處理指令之大小時，目標區之大小亦會大於處理指令之大小，此時該處理器120寫入該至少一處理指令以及至少一假(dummy)指令於該目標區T3。在一些實施例中，處理器120除了寫入處理指令於目標區外，更以假指令寫入於目標區中除了處理指令之外的空間。例如，如圖3所示，處理器120可寫入處理指令C3於目標區T3的儲存塊Q13，並以假指令D31-D32寫入於目標區T3的儲存塊Q14-Q15。 In some embodiments of step S01, when the size of the completion message is larger than the size of the processing instruction, the size of the target area will also be larger than the size of the processing instruction. At this time, the processor 120 writes the at least one processing instruction and at least one dummy (dummy) instruction in the target area T3. In some embodiments, in addition to writing the processing instructions in the target area, the processor 120 writes dummy instructions in the target area except for the processing instructions. For example, as shown in FIG. 3 , the processor 120 may write the processing instruction C3 into the storage block Q13 of the target area T3, and write the dummy instructions D31-D32 into the storage blocks Q14-Q15 of the target area T3.

在步驟S03與步驟S04之一些實施例中，當處理指令之大小大於完成訊息之大小時，目標區之大小亦會大於完成訊息之大小，此時功能硬體130除了產生完成訊息之外，更可產生假訊息，且該功能硬體130寫入該至少一完成訊息以及至少一假(dummy)訊息於該目標區T4中。在一些實施例中，功能硬體130除了寫入完成訊息於目標區外，更以假訊息寫入於目標區中除了完成訊息之外的空間。例如，功能硬體130可產生完成訊息M4與假訊息D41，且如圖3所示，功能硬體130寫入完成訊息M4於目標區T4的儲存塊Q16並寫入假訊息D41於目標區T4的儲存塊Q17。 In some embodiments of step S03 and step S04, when the size of the processing instruction is greater than the size of the completion message, the size of the target area will also be greater than the size of the completion message. At this time, the functional hardware 130 will not only generate the completion message, but also A dummy message can be generated, and the functional hardware 130 writes the at least one completion message and at least one dummy message in the target area T4. In some embodiments, in addition to writing the completion message in the target area, the functional hardware 130 writes a dummy message in a space other than the completion message in the target area. For example, the functional hardware 130 can generate a completion message M4 and a false message D41, and as shown in FIG. storage block Q17.

前述的寫入假(dummy)指令或/及假訊息的一實施例可以是寫入固定的數值(例如：皆為0、或皆為1)，也可以僅是保留寫入空間，而無寫入任何數值。 An embodiment of the aforementioned dummy (dummy) command or/and dummy message can be written into a fixed value (for example: all 0, or all 1), also can only reserve the write space, without writing Enter any value.

在一些實施例中，電子裝置100中可更包含暫存器檔案(register file)150，且暫存器檔案150可透過匯流排140耦接於處理器120與功能硬體130。在一些實施態樣中，暫存器檔案150可利用多個暫存器所組成之陣列來實現，例如但不限於利用靜態隨機記憶體來實現。 In some embodiments, the electronic device 100 may further include a register file 150 , and the register file 150 may be coupled to the processor 120 and the functional hardware 130 through the bus 140 . In some implementation aspects, the register file 150 can be implemented by using an array of multiple registers, such as but not limited to using SRAM.

請參閱圖1至圖11，暫存器檔案150中可包含指令寫入指標PC1、指令讀取指標PC2、訊息寫入指標PM1與訊息讀取指標PM2。指令寫入指標PC1用以指示最新一筆之處理指令在佇列Q1中的儲存位置。指令讀取指標PC2用以指示自佇列Q1中讀取之最近一筆的處理指令的讀取位置。訊息寫入指標PM1用以指示最新一筆之完成訊息在佇列Q1中的儲存位置。並且，訊息讀取指標PM2用以指示自佇列Q1中讀取之最近一筆的完成訊息的讀取位置。於此，指令寫入指標PC1、指令讀取指標PC2、訊息寫入指標PM1與訊息讀取指標PM2於初始狀態時可皆指示於佇列Q1之起始位置，如圖4所示。 Referring to FIG. 1 to FIG. 11 , the register file 150 may include a command write pointer PC1 , a command read pointer PC2 , a message write pointer PM1 and a message read pointer PM2 . The command writing pointer PC1 is used to indicate the storage position of the latest processing command in the queue Q1. The command read pointer PC2 is used to indicate the read position of the latest processing command read from the queue Q1. The message writing indicator PM1 is used to indicate the storage position of the latest completed message in the queue Q1. Moreover, the message reading indicator PM2 is used to indicate the reading position of the latest complete message read from the queue Q1. Here, the command writing pointer PC1 , the command reading pointer PC2 , the message writing pointer PM1 and the message reading pointer PM2 can all indicate the initial position of the queue Q1 in the initial state, as shown in FIG. 4 .

在一些實施例中，處理器120於步驟S01中寫入複數處理指令C1-C4中至少一者至複數目標區T1-T4中至少一者後，可透過匯流排140訪問暫存器檔案150，以更新指令寫入指標PC1。例如，如圖5所示，處理器120可於寫入處理指令C1-C3至目標區T1-T3後訪問暫存器檔案150，並將指令寫入指標PC1自起始位置更新至目標區T3之儲存塊Q15的位置。 In some embodiments, after the processor 120 writes at least one of the plurality of processing instructions C1-C4 to at least one of the plurality of target areas T1-T4 in step S01, it can access the register file 150 through the bus 140, Write to pointer PC1 with an update command. For example, as shown in FIG. 5, the processor 120 can access the register file 150 after writing the processing instructions C1-C3 to the target area T1-T3, and update the command write pointer PC1 from the initial position to the target area T3 The location of the storage block Q15.

功能硬體130於步驟S02中自複數目標區T1-T4中至少一者讀取複數處理指令C1-C4中至少一者後，可透過匯流排140訪問暫存 器檔案150以更新指令讀取指標PC2。例如，如圖6所示，功能硬體130可於自目標區T1-T2中讀取處理指令C1-C2後訪問暫存器檔案150，並將指令讀取指標PC2自起始位置更新至目標區T2之儲存塊Q12的位置。功能硬體130於步驟S04中寫入複數完成訊息M1-M4中至少一者至複數目標區T1-T4中至少一者後，可透過匯流排140訪問暫存器檔案150，以更新訊息寫入指標PM1。例如，如圖7所示，功能硬體130可於寫入完成訊息M1-M2至目標區T1-T2後訪問暫存器檔案150，並將訊息寫入指標PM1自起始位置更新至目標區T2之儲存塊Q12的位置。處理器120於步驟S05中自複數目標區T1-T4中至少一者讀取複數完成訊息M1-M4中至少一者後，可透過匯流排140訪問暫存器檔案150，以更新訊息讀取指標PM2。例如，如圖8所示，處理器120可於自目標區T1-T2讀取完成訊息M1-M2後訪問暫存器檔案150，並將訊息讀取指標PM2自起始位置更新至目標區T2之儲存塊Q12的位置。 After the functional hardware 130 reads at least one of the plurality of processing instructions C1-C4 from at least one of the plurality of target areas T1-T4 in step S02, the temporary storage can be accessed through the bus 140 The device file 150 reads the pointer PC2 with an update command. For example, as shown in FIG. 6, the functional hardware 130 can access the register file 150 after reading the processing instructions C1-C2 from the target area T1-T2, and update the instruction read pointer PC2 from the initial position to the target The location of storage block Q12 in region T2. After the functional hardware 130 writes at least one of the plurality of completion messages M1-M4 to at least one of the plurality of target areas T1-T4 in step S04, it can access the register file 150 through the bus 140 to update the information written Indicator PM1. For example, as shown in FIG. 7 , the functional hardware 130 can access the register file 150 after writing the completion message M1-M2 to the target area T1-T2, and update the message writing pointer PM1 from the initial position to the target area The location of storage block Q12 of T2. After the processor 120 reads at least one of the plurality of completion messages M1-M4 from at least one of the plurality of target areas T1-T4 in step S05, it can access the register file 150 through the bus 140 to update the message read pointer PM2. For example, as shown in FIG. 8 , the processor 120 can access the register file 150 after reading the completed messages M1-M2 from the target area T1-T2, and update the message read pointer PM2 from the initial position to the target area T2 The location of the storage block Q12.

在步驟S01之一些實施例中，處理器120可先訪問暫存器檔案150以得到新的指令寫入指標PC1，並根據指令寫入指標PC1寫入複數處理指令C1-C4中至少一者於指令寫入指標PC1所指之順序後方的至少一目標區。例如，在得到指令寫入指標PC1指向目標區T3之儲存塊Q15的位置(如圖8所示之一實施態樣)時，處理器120可將處理指令C4寫入至位於指令寫入指標PC1所指之順序後方的目標區T4，並於寫入完後將指令寫入指標PC1更新至目標區T4之儲存塊Q17的位置，如圖9所示。 In some embodiments of step S01, the processor 120 may first access the register file 150 to obtain a new command write pointer PC1, and write at least one of the plurality of processing instructions C1-C4 according to the command write pointer PC1 The instruction is written into at least one target area behind the sequence pointed by the pointer PC1. For example, when it is obtained that the instruction writing pointer PC1 points to the location of the storage block Q15 of the target area T3 (as shown in FIG. 8 ), the processor 120 can write the processing instruction C4 into the location of the instruction writing pointer PC1. Point to the target area T4 behind the sequence, and update the command write pointer PC1 to the location of the storage block Q17 of the target area T4 after writing, as shown in FIG. 9 .

在步驟S02之一些實施例中，功能硬體130可先訪問暫存器檔案150以得到新的指令寫入指標PC1與新的指令讀取指標PC2，並根據 指令寫入指標PC1與指令讀取指標PC2讀取指令讀取指標PC2所指之下一順位的目標區至指令寫入指標PC1所指之目標區中的至少一處理指令。例如，在指令寫入指標PC1指向目標區T4之儲存塊Q17的位置且指令讀取指標PC2指向目標區T2之儲存塊Q12的位置(如圖9所示之一實施態樣)時，功能硬體130可自指令讀取指標PC2所指之下一順位的目標區，即目標區T3至指令寫入指標PC1所指之目標區T4中讀取位於目標區T3的處理指令C3，並更新指令讀取指標PC2至目標區T3之儲存塊Q15的位置。此外，在一些實施例中，功能硬體130更可根據指令寫入指標PC1與指令讀取指標PC2計算出尚有多少筆待執行的處理指令。 In some embodiments of step S02, the functional hardware 130 can first access the register file 150 to obtain the new command write pointer PC1 and the new command read pointer PC2, and according to The command write pointer PC1 and the command read pointer PC2 read at least one processing instruction from the next sequential target area pointed by the command read pointer PC2 to the target area pointed by the command write pointer PC1. For example, when the instruction write pointer PC1 points to the location of the storage block Q17 of the target area T4 and the instruction read pointer PC2 points to the location of the storage block Q12 of the target area T2 (an implementation as shown in FIG. 9 ), the function hard The bank 130 can read the processing instruction C3 located in the target area T3 from the next target area pointed by the instruction read pointer PC2, that is, the target area T3, to the target area T4 pointed by the instruction write pointer PC1, and update the instruction Read the pointer PC2 to the location of the storage block Q15 of the target area T3. In addition, in some embodiments, the functional hardware 130 can further calculate how many processing instructions are still to be executed according to the instruction writing index PC1 and the instruction reading index PC2.

在一些實施態樣中，功能硬體130於讀取處理指令C3後可對處理指令C3進行解析，例如但不限於透過處理指令C3中的標頭(header)得知處理指令C3的長度大小，進而判斷出後方之假指令D31-D32是假的而不需處理，例如但不限於不讀取假指令D31-D32並直接更新指令讀取指標PC2至目標區T3之儲存塊Q15的位置。 In some implementations, the functional hardware 130 can analyze the processing instruction C3 after reading the processing instruction C3, such as but not limited to knowing the length of the processing instruction C3 through the header in the processing instruction C3, Then it is determined that the following dummy instructions D31-D32 are false and no processing is required, for example but not limited to not reading the dummy instructions D31-D32 and directly updating the instruction read pointer PC2 to the location of the storage block Q15 of the target area T3.

在步驟S03之一些實施例中，功能硬體130可於解析處理指令C3後，例如但不限於透過處理指令C3中的標頭得知處理指令C3與完成訊息M3之間的比例關係，而於執行完處理指令C3後產生出具有相應比例之完成訊息M3。例如，處理指令C3與完成訊息M3之間為1：3，則功能硬體130會產生可分成三個子完成訊息M31-M33的完成訊息M3。 In some embodiments of step S03, after analyzing the processing instruction C3, the functional hardware 130 can know the proportional relationship between the processing instruction C3 and the completion message M3 through, for example but not limited to, the header in the processing instruction C3, and then After the processing command C3 is executed, a completion message M3 with a corresponding proportion is generated. For example, if the relationship between the processing command C3 and the completion message M3 is 1:3, the functional hardware 130 will generate the completion message M3 which can be divided into three sub-completion messages M31-M33.

在步驟S04之一些實施例中，功能硬體130可先訪問暫存器檔案150以得到新的訊息寫入指標PM1，並根據訊息寫入指標PM1寫入複數完成訊息M1-M4中至少一者於訊息寫入指標PM1所指之順序後方 的至少一目標區。例如，在訊息寫入指標PM1指向目標區T2之儲存塊Q12的位置時，功能硬體130可將完成訊息M3寫入至位於訊息寫入指標PM1所指之順序後方的目標區T3，並將訊息寫入指標PM1更新至目標區T3之儲存塊Q15的位置，如圖10所示。 In some embodiments of step S04, the functional hardware 130 can first access the register file 150 to obtain a new message writing indicator PM1, and write at least one of the plurality of completion messages M1-M4 according to the message writing indicator PM1 After the sequence indicated by the message writing indicator PM1 at least one target area of . For example, when the message writing pointer PM1 points to the location of the storage block Q12 of the target area T2, the functional hardware 130 can write the completion message M3 into the target area T3 located behind the sequence indicated by the message writing pointer PM1, and The message writing pointer PM1 is updated to the location of the storage block Q15 in the target area T3, as shown in FIG. 10 .

在步驟S05之一些實施例中，處理器120可先訪問暫存器檔案150以得到新的訊息寫入指標PM1與新的訊息讀取指標PM2，並根據訊息寫入指標PM1與訊息讀取指標PM2讀取訊息讀取指標PM2所指之下一順位的目標區至訊息寫入指標PM1所指之目標區中的至少一完成訊息。例如，在訊息寫入指標PM1指向目標區T3之儲存塊Q15的位置且訊息讀取指標PM2指向目標區T2之儲存塊Q12的位置(如圖10所示之一實施態樣)時，訊息讀取指標PM2所指之下一順位的目標區即為目標區T3而相同於訊息寫入指標PM1所指之目標區，故處理器120此時可自目標區T3中讀取完成訊息M3，並將訊息讀取指標PM2更新至目標區T3之儲存塊Q15的位置，如圖11所示。此外，在一些實施例中，處理器120更可根據訊息寫入指標PM1與訊息讀取指標PM2計算出尚有多少筆待處理的完成訊息。 In some embodiments of step S05, the processor 120 may first access the register file 150 to obtain the new message write pointer PM1 and the new message read pointer PM2, and then write the message according to the message write pointer PM1 and the message read pointer PM2 reads at least one completed message from the next target area pointed by the message read pointer PM2 to the target area pointed by the message write pointer PM1. For example, when the message write pointer PM1 points to the position of the storage block Q15 of the target area T3 and the message read pointer PM2 points to the position of the storage block Q12 of the target area T2 (an implementation as shown in FIG. 10 ), the message read The target area next to the point of the index PM2 is the target area T3, which is the same as the target area pointed to by the message writing index PM1, so the processor 120 can read the completion message M3 from the target area T3 at this time, and Update the message reading pointer PM2 to the location of the storage block Q15 in the target area T3, as shown in FIG. 11 . In addition, in some embodiments, the processor 120 can further calculate how many completed messages to be processed according to the message writing indicator PM1 and the message reading indicator PM2.

在一些實施態樣中，處理器120於讀取完成訊息M4後可讀取完成訊息M4，進而得知後方之假訊息D41是假的而不需處理，例如但不限於不讀取假訊息D41或讀取假訊息D41但不執行，並且直接更新訊息讀取指標PM2至目標區T4之儲存塊Q17的位置。 In some implementations, the processor 120 can read the completion message M4 after reading the completion message M4, and then know that the subsequent false message D41 is false without processing, for example but not limited to not reading the false message D41 Or read the dummy message D41 but not execute it, and directly update the message read pointer PM2 to the location of the storage block Q17 of the target area T4.

在一些實施例中，功能硬體130可訪問暫存器檔案150以得到新的訊息寫入指標PM1與新的訊息讀取指標PM2，並根據訊息寫入指 標PM1與訊息讀取指標PM2計算出尚有多少筆待處理的完成訊息，進而據此判斷是否需要中斷通知處理器120去處理此些完成訊息。 In some embodiments, the functional hardware 130 can access the register file 150 to obtain the new message write pointer PM1 and the new message read pointer PM2, and write the message according to the message The index PM1 and the message reading index PM2 calculate how many completion messages are still waiting to be processed, and then judge whether to interrupt the notification processor 120 to process these completion messages based on this.

在一些實施例中，各目標區T1-T4可包含狀態欄A1與儲存欄A2。其中，狀態欄A1可用以指示儲存欄A2中所存的是一種指令或訊息。處理器120於步驟S01中寫入處理指令C1-C4至目標區T1-T4時，可將各處理指令C1-C4寫入於各目標區T1-T4之儲存欄A2中，並寫入一第一值於各目標區T1-T4之狀態欄A1。功能硬體130於步驟S04寫入完成訊息M1-M4至目標區T1-T4時，可將各完成訊息M1-M4寫入於各目標區T1-T4之儲存欄A2中，並寫入一第二值於各目標區T1-T4之狀態欄A1。其中，第二值不同於第一值。在一些實施態樣中，第一值可為但不限於1，且第二值可為但不限於0。 In some embodiments, each target area T1-T4 may include a status column A1 and a storage column A2. Wherein, the status column A1 can be used to indicate that what is stored in the storage column A2 is an instruction or a message. When the processor 120 writes the processing instructions C1-C4 to the target areas T1-T4 in step S01, each processing instruction C1-C4 can be written into the storage column A2 of each target area T1-T4, and written into a first A value in the status column A1 of each target zone T1-T4. When the functional hardware 130 writes the completion messages M1-M4 to the target areas T1-T4 in step S04, each completion message M1-M4 can be written in the storage column A2 of each target area T1-T4, and write a first The binary value is in the status column A1 of each target area T1-T4. Wherein, the second value is different from the first value. In some implementation aspects, the first value may be but not limited to 1, and the second value may be but not limited to 0.

在一些實施例中，各儲存塊Q11-Q1n可分成前述的狀態欄A1與儲存欄A2。處理器120可將處理指令寫入至儲存塊的儲存欄A2，並寫入第一值於儲存塊的狀態欄A1。功能硬體130可將完成訊息寫入至儲存塊的儲存欄A2，並寫入第二值於儲存塊的狀態欄A1。特別的是，即便是寫入假指令，例如寫入假指令D31-D32至儲存塊Q14-Q15的儲存欄A2，處理器120亦會寫入第一值於儲存塊Q14-Q15的狀態欄A1。而即便是寫入假訊息，例如寫入假訊息D41至儲存塊Q17的儲存欄A2，功能硬體130亦會寫入第二值於儲存塊Q17的狀態欄A1。 In some embodiments, each storage block Q11-Q1n can be divided into the aforementioned status column A1 and storage column A2. The processor 120 can write the processing instruction into the storage column A2 of the storage block, and write the first value into the status column A1 of the storage block. The functional hardware 130 can write the completion message into the storage column A2 of the storage block, and write the second value into the status column A1 of the storage block. In particular, even if a dummy command is written, for example, a dummy command D31-D32 is written to the storage column A2 of the storage block Q14-Q15, the processor 120 will also write the first value into the status column A1 of the storage block Q14-Q15 . Even if a false message is written, for example, a false message D41 is written into the storage column A2 of the storage block Q17, the functional hardware 130 will also write the second value into the status column A1 of the storage block Q17.

在一些實施例中，功能硬體130可透過解析電路來解析自佇列Q1中取得的各處理指令C1-C4。此外，電子裝置100中之功能硬體130的數量可為多個，且同一佇列Q1中所存的處理指令C1-C4可能是用 以給多個功能硬體130執行。此時，功能硬體130可先透過解析電路解析自佇列Q1中取得的處理指令，再將此處理指令分發給相應的功能硬體130去執行。在一些實施態樣中，所述之解析電路可包含於功能硬體130中，抑或獨立設置並耦接於功能硬體130與記憶體110。 In some embodiments, the functional hardware 130 can parse the processing instructions C1-C4 obtained from the queue Q1 through the parsing circuit. In addition, the number of functional hardware 130 in the electronic device 100 may be multiple, and the processing instructions C1-C4 stored in the same queue Q1 may be used To be executed by multiple functional hardware 130 . At this time, the functional hardware 130 can first analyze the processing instruction obtained from the queue Q1 through the analysis circuit, and then distribute the processing instruction to the corresponding functional hardware 130 for execution. In some implementations, the analysis circuit may be included in the functional hardware 130 , or independently configured and coupled to the functional hardware 130 and the memory 110 .

綜上所述，本案實施例之電子裝置及空間複用方法，其將處理指令寫入於記憶體之佇列的目標區中，並將對應於前述之處理指令的完成訊息回存於同一目標區中，使得處理指令與相應之完成訊息可複用同一佇列中的儲存空間，進而提高記憶體的儲存利用率。 To sum up, the electronic device and the space multiplexing method of the embodiment of the present case write the processing instruction into the target area of the queue of the memory, and return the completion message corresponding to the aforementioned processing instruction to the same target In the area, the processing instruction and the corresponding completion message can reuse the storage space in the same queue, thereby improving the storage utilization rate of the memory.

雖然本案的技術內容已經以較佳實施例揭露如上，然其並非用以限定本案，任何熟習此技藝者，在不脫離本案之精神所作些許之更動與潤飾，皆應涵蓋於本案的範疇內，因此本案之保護範圍當視後附之申請專利範圍所界定者為準。 Although the technical content of this case has been disclosed above with the preferred embodiment, it is not used to limit this case. Anyone who is familiar with this technology and makes some changes and modifications without departing from the spirit of this case should be included in the scope of this case. Therefore, the protection scope of this case should be defined by the scope of the attached patent application.

100:電子裝置 100: Electronic device

110:記憶體 110: memory

120:處理器 120: Processor

130:功能硬體 130: Functional hardware

140:匯流排 140: busbar

150:暫存器檔案 150:Scratch file

C1:處理指令 C1: Processing instructions

M1:完成訊息 M1: Completion message

Q1:佇列 Q1: Queue

Q11-Q1n:儲存塊 Q11-Q1n: storage block

Claims (12)

一種電子裝置，包含： 一記憶體，包含一佇列； 一處理器，用以寫入至少一處理指令至該佇列的至少一目標區；及 一功能硬體，用以自該目標區讀取該至少一處理指令，該功能硬體於執行完該至少一處理指令後產生至少一完成訊息並將該至少一完成訊息寫入至該至少一目標區，其中，該至少一完成訊息係相對應於該至少一處理指令。 An electronic device comprising: a memory including a queue; a processor for writing at least one processing instruction to at least one target area of the queue; and A functional hardware for reading the at least one processing command from the target area, the functional hardware generates at least one completion message after executing the at least one processing command and writes the at least one completion message into the at least one The target area, wherein the at least one completion message corresponds to the at least one processing instruction. 如請求項1所述的電子裝置，其中該處理器更自該至少一目標區讀取該至少一完成訊息。The electronic device as claimed in claim 1, wherein the processor further reads the at least one completion message from the at least one target area. 如請求項2所述的電子裝置，更包含一暫存器檔案，該暫存器檔案包含一指令寫入指標、一指令讀取指標、一訊息寫入指標與一訊息讀取指標； 其中，該處理器於儲存該至少一處理指令至該至少一目標區後更新該指令寫入指標； 其中，該功能硬體自該至少一目標區讀取該至少一處理指令後更新該指令讀取指標； 其中，該功能硬體寫入該至少一完成訊息至該至少一目標區後更新該訊息寫入指標；以及 其中，該處理器自該至少一目標區讀取該至少一完成訊息後更新該訊息讀取指標。 The electronic device as described in claim 2 further includes a register file, the register file includes a command write pointer, a command read pointer, a message write pointer and a message read pointer; Wherein, the processor updates the instruction write pointer after storing the at least one processing instruction in the at least one target area; Wherein, the functional hardware updates the command read indicator after reading the at least one processing command from the at least one target area; Wherein, the functional hardware updates the message writing indicator after writing the at least one completion message to the at least one target area; and Wherein, the processor updates the message reading indicator after reading the at least one completion message from the at least one target area. 如請求項1至3中任一項所述的電子裝置，其中該處理器根據該至少一處理指令以預先決定出該完成訊息的大小，該處理器根據該至少一處理指令大小及預先決定出的該完成訊息的大小以決定出該目標區的大小。The electronic device according to any one of claims 1 to 3, wherein the processor predetermines the size of the completion message according to the at least one processing instruction, and the processor predetermines the size of the completion message according to the at least one processing instruction size and The size of the completion message determines the size of the target area. 如請求項4所述的電子裝置，其中在該至少一目標區的大小大於該至少一處理指令的大小時，該處理器寫入該至少一處理指令以及至少一假(dummy)指令於該目標區。The electronic device as described in claim 4, wherein when the size of the at least one target area is larger than the size of the at least one processing instruction, the processor writes the at least one processing instruction and at least one dummy instruction in the target Area. 如請求項4所述的電子裝置，其中在該至少一目標區的大小大於該至少一完成訊息的大小時，該功能硬體寫入該至少一完成訊息以及至少一假(dummy)訊息於該目標區中。The electronic device as described in claim 4, wherein when the size of the at least one target area is greater than the size of the at least one completion message, the functional hardware writes the at least one completion message and at least one dummy message in the at least one completion message in the target area. 如請求項4所述的電子裝置，其中該至少一目標區包含一狀態欄與一儲存欄，其中該處理器寫入該至少一處理指令於該儲存欄，並寫入一第一值於該狀態欄，該功能硬體寫入該至少一完成訊息於該儲存欄，並寫入一第二值於該狀態欄。The electronic device as described in claim 4, wherein the at least one target area includes a status column and a storage column, wherein the processor writes the at least one processing instruction in the storage column, and writes a first value in the storage column In the status column, the functional hardware writes the at least one completion message in the storage column, and writes a second value in the status column. 一種空間複用方法，包含： 依據至少一處理指令以決定出至少一目標區的大小，其中該至少一目標區係位於一記憶體之一佇列； 寫入該至少一處理指令至該至少一目標區； 自該至少一目標區讀取該至少一處理指令； 執行該至少一處理指令後產生至少一完成訊息； 寫入該至少一完成訊息至該至少一目標區中；及 自該至少一目標區中讀取該至少一完成訊息。 A method for spatial multiplexing, comprising: Determine the size of at least one target area according to at least one processing instruction, wherein the at least one target area is located in a queue of a memory; writing the at least one processing instruction to the at least one target area; reading the at least one processing instruction from the at least one target area; generating at least one completion message after executing the at least one processing instruction; writing the at least one completion message into the at least one target area; and The at least one completion message is read from the at least one target area. 如請求項8所述的空間複用方法，包含： 於寫入該至少一處理指令至該至少一目標區後，更新一暫存器檔案中的一指令寫入指標； 自該至少一目標區讀取該至少一處理指令後，更新該暫存器檔案中的一指令讀取指標； 於寫入該至少一完成訊息至該至少一目標區後，更新該暫存器檔案中的一訊息寫入指標；及 自該至少一目標區中讀取該至少一完成訊息後，更新該暫存器檔案中的一訊息讀取指標。 The spatial multiplexing method as described in claim item 8, comprising: After writing the at least one processing command into the at least one target area, updating a command write pointer in a register file; after reading the at least one processing command from the at least one target area, updating a command read pointer in the register file; updating a message write pointer in the register file after writing the at least one completion message to the at least one target area; and After reading the at least one completion message from the at least one target area, updating a message read indicator in the register file. 如請求項8所述的空間複用方法，其中在該完成訊息之該大小大於該處理指令之該大小時，寫入該至少一處理指令至該記憶體之該佇列中的該至少一目標區之步驟係寫入該至少一處理指令以及一假(dummy)指令至該至少一目標區中。The space multiplexing method as described in claim 8, wherein when the size of the completion message is larger than the size of the processing instruction, writing the at least one processing instruction to the at least one object in the queue of the memory The step of area is writing the at least one processing instruction and a dummy instruction into the at least one target area. 如請求項8所述的空間複用方法，其中在該處理指令的大小大於該完成訊息的大小時，寫入該至少一完成訊息至該至少一目標區中之步驟係寫入該至少一完成訊息以及一假(dummy)訊息至該至少一目標區中。The space multiplexing method as described in claim 8, wherein when the size of the processing instruction is larger than the size of the completion message, the step of writing the at least one completion message into the at least one target area is writing the at least one completion message A message and a dummy message are sent to the at least one target area. 如請求項8所述的空間複用方法，其中該目標區包含一狀態欄與一儲存欄，寫入該至少一處理指令至該記憶體之該佇列中的該至少一目標區之步驟係寫入該至少一處理指令於該儲存欄並寫入一第一值於該狀態欄，寫入該至少一完成訊息至該目標區中之步驟係寫入該至少一完成訊息於該儲存欄，並寫入一第二值於該狀態欄。The space multiplexing method as described in claim 8, wherein the target area includes a status column and a storage column, and the step of writing the at least one processing command to the at least one target area in the queue of the memory is writing the at least one processing instruction in the storage column and writing a first value in the status column, the step of writing the at least one completion message in the target area is writing the at least one completion message in the storage column, And write a second value in the status column.
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