TWI779617B - Method for manufacturing semiconductor stack structure with ultra thin die - Google Patents
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本發明是有關一種半導體結構的製造方法，尤其是一種半導體超薄堆疊結構的製造方法。The invention relates to a method for manufacturing a semiconductor structure, in particular to a method for manufacturing an ultra-thin semiconductor stack structure.
隨著電子產業的蓬勃發展，電子產品逐漸進入多功能、高性能的研發方向，其中半導體科技已廣泛地應用於製造記憶體、中央處理單元等晶片組。為了達成高積集度(Integration)與高速度等目的，半導體積體電路之尺寸持續地縮減，目前已發展出多種不同之材料與技術以達成上述之積集度與速度要求，亦已研發出了包括多層基板(multiple substrates)之堆疊結構，藉以改善電路之操作速度。當半導體平面封裝相關技術到達極限，可藉由積體化滿足微小化的需求，堆疊晶圓之技術對未來科技有很大的助力，亦成為當前相關領域極需改進的目標。With the vigorous development of the electronic industry, electronic products have gradually entered the direction of multi-functional and high-performance research and development. Among them, semiconductor technology has been widely used in the manufacture of chipsets such as memories and central processing units. In order to achieve high integration and high speed, the size of semiconductor integrated circuits continues to shrink. At present, a variety of different materials and technologies have been developed to meet the above integration and speed requirements, and have also been developed. A stacked structure including multiple substrates is provided to improve the operation speed of the circuit. When the technology related to semiconductor planar packaging has reached its limit, the need for miniaturization can be met through integration. The technology of stacking wafers will greatly help future technology, and it has also become a goal that needs to be improved in current related fields.
本發明提供一種半導體超薄堆疊結構的製造方法，使半導體超薄堆疊結構可滿足高積集度與速度要求，而具有更佳的電氣特性及效率。The invention provides a method for manufacturing a semiconductor ultra-thin stack structure, which enables the semiconductor ultra-thin stack structure to meet the requirements of high accumulation degree and speed, and has better electrical characteristics and efficiency.
本發明所提供的半導體超薄堆疊結構的製造方法，包含：製造多個半導體晶圓，選擇其中一半導體晶圓作為底層之第一半導體晶圓，部分的半導體晶圓則作為待堆疊的第二半導體晶圓及第三半導體晶圓，每一半導體晶圓的製造步驟包含：提供半導體基板，具有相對的主動面及背面；形成停止層結構於半導體基板內，將半導體基板分為基板第一部分及基板第二部分，其中基板第一部分位於停止層結構及主動面之間，基板第二部分位於停止層結構及背面之間，停止層結構至少包含氮化矽層，氮化矽層的製造包含先於半導體基板的第一深度進行氮離子佈植製程，接著進行高溫處理製程，使氮離子佈植的區域形成氮化矽層；以及於主動面設置多個電氣元件及內連層，內連層包含多個互連接點，並於基板第一部分設置多個導電結構連接內連層及停止層結構。將第二半導體晶圓相對於第一半導體晶圓倒裝，使第一半導體晶圓的內連層及第二半導體晶圓的內連層相對且以混合鍵合技術接合在一起；進行第一背面研磨製程，自第二半導體晶圓的背面進行研磨，以移除第二半導體晶圓之基板第二部分的一部分；進行第一薄化製程，以形成薄化第二半導體晶圓；進行第二背面研磨製程，自第一半導體晶圓的背面進行研磨，以移除第一半導體晶圓之基板第二部分的一部分；以及進行第二薄化製程，以形成薄化第一半導體晶圓，其中，第一薄化製程及第二薄化製程包含基板去除步驟及停止層去除步驟，其中基板去除步驟移除剩餘的基板第二部分，以顯露停止層結構；停止層去除步驟移除停止層結構，以顯露基板第一部分及導電結構。The method for manufacturing a semiconductor ultra-thin stack structure provided by the present invention includes: manufacturing a plurality of semiconductor wafers, selecting one of the semiconductor wafers as the first semiconductor wafer at the bottom, and part of the semiconductor wafers as the second semiconductor wafer to be stacked. A semiconductor wafer and a third semiconductor wafer, the manufacturing steps of each semiconductor wafer include: providing a semiconductor substrate having an opposite active surface and a back surface; forming a stop layer structure in the semiconductor substrate, dividing the semiconductor substrate into a first part of the substrate and The second part of the substrate, wherein the first part of the substrate is located between the stop layer structure and the active surface, the second part of the substrate is located between the stop layer structure and the back surface, the stop layer structure includes at least a silicon nitride layer, and the manufacture of the silicon nitride layer includes a prior Nitrogen ion implantation process is performed on the first depth of the semiconductor substrate, followed by high temperature treatment process, so that the nitrogen ion implanted area forms a silicon nitride layer; and multiple electrical components and interconnection layers are arranged on the active surface, and the interconnection layer It includes a plurality of interconnection points, and a plurality of conductive structures are arranged on the first part of the substrate to connect the interconnection layer and the stop layer structure. Flip-chip the second semiconductor wafer relative to the first semiconductor wafer, make the interconnection layer of the first semiconductor wafer and the interconnection layer of the second semiconductor wafer face each other and bond them together by hybrid bonding technology; perform the first backside grinding process, grinding from the backside of the second semiconductor wafer to remove a part of the second portion of the substrate of the second semiconductor wafer; performing a first thinning process to form a thinned second semiconductor wafer; performing a second Two backside grinding processes, grinding from the backside of the first semiconductor wafer to remove a portion of the second portion of the substrate of the first semiconductor wafer; and performing a second thinning process to form a thinned first semiconductor wafer, Wherein, the first thinning process and the second thinning process include a substrate removal step and a stop layer removal step, wherein the substrate removal step removes the remaining second part of the substrate to reveal the stop layer structure; the stop layer removal step removes the stop layer structure to expose the first portion of the substrate and the conductive structure.
在本發明的一實施例中，在進行上述第二背面研磨製程之前，更可於薄化第二半導體晶圓上依序進行多個薄化第三半導體晶圓的堆疊，其中每一薄化第三半導體晶圓的堆疊步驟包含：將第三半導體晶圓相對於第一半導體晶圓倒裝，使第三半導體晶圓的內連層及薄化第二半導體晶圓的基板第一部分相對且接合在一起；進行第三背面研磨製程，自第三半導體晶圓的背面進行研磨，以移除第三半導體晶圓之基板第二部分的一部分；以及進行第三薄化製程，包含基板去除步驟及停止層去除步驟。In an embodiment of the present invention, before performing the above-mentioned second back grinding process, a plurality of thinned third semiconductor wafers can be stacked sequentially on the thinned second semiconductor wafer, wherein each thinned The stacking step of the third semiconductor wafer includes: flipping the third semiconductor wafer relative to the first semiconductor wafer, so that the interconnection layer of the third semiconductor wafer and the first part of the substrate of the thinned second semiconductor wafer are opposite and bonding together; performing a third backside grinding process, grinding from the backside of the third semiconductor wafer to remove a portion of the second portion of the substrate of the third semiconductor wafer; and performing a third thinning process, including a substrate removal step and stop layer removal steps.
在本發明的一實施例中，上述之停止層結構更包含二氧化矽層，二氧化矽層設置氮化矽層上，以介於氮化矽層及主動面之間。In an embodiment of the present invention, the above stop layer structure further includes a silicon dioxide layer, and the silicon dioxide layer is disposed on the silicon nitride layer so as to be between the silicon nitride layer and the active surface.
在本發明的一實施例中，形成上述之二氧化矽層的步驟包含：於氮離子佈植製程後，先在半導體基板的第二深度進行氧離子佈植製程，且第二深度小於第一深度，之後再進行高溫處理製程，使氧離子佈植的區域形成二氧化矽層。In one embodiment of the present invention, the step of forming the above-mentioned silicon dioxide layer includes: after the nitrogen ion implantation process, performing an oxygen ion implantation process at a second depth of the semiconductor substrate, and the second depth is smaller than the first Depth, followed by a high temperature treatment process to form a silicon dioxide layer in the region implanted with oxygen ions.
在本發明的一實施例中，上述之停止層去除步驟包含：先移除氮化矽層，再移除二氧化矽層。In an embodiment of the present invention, the above step of removing the stopper layer includes: removing the silicon nitride layer first, and then removing the silicon dioxide layer.
在本發明的一實施例中，上述之基板去除步驟選自化學機械研磨、溼式蝕刻及電漿乾式蝕刻其中之一，其中矽及氮化矽的選擇比介於20至80之間。In an embodiment of the present invention, the substrate removal step is selected from one of chemical mechanical polishing, wet etching and plasma dry etching, wherein the selectivity ratio of silicon and silicon nitride is between 20 and 80.
在本發明的一實施例中，上述之氮化矽層及二氧化矽層的移除方法選自化學機械研磨及電漿乾式蝕刻其中之一，其中氮化矽及二氧化矽的選擇比介於10至20之間，二氧化矽及矽的選擇比約為5。In an embodiment of the present invention, the removal method of the silicon nitride layer and the silicon dioxide layer is selected from one of chemical mechanical polishing and plasma dry etching, wherein the selectivity of silicon nitride and silicon dioxide is relatively low. Between 10 and 20, the selectivity ratio of silicon dioxide and silicon is about 5.
在本發明的一實施例中，上述之停止層結構與主動面的距離介於1微米至5微米之間，薄化第二半導體晶圓的厚度不大於12微米。In an embodiment of the present invention, the distance between the stop layer structure and the active surface is between 1 micron and 5 microns, and the thickness of the thinned second semiconductor wafer is not greater than 12 microns.
在本發明的一實施例中，於形成上述之薄化第一半導體晶圓之後，更包含以下步驟：於薄化第一半導體晶圓之遠離薄化第二半導體晶圓的一側設置多個銲球，以分別電性連接導電結構；以及進行電性測試與切單。In one embodiment of the present invention, after forming the above-mentioned thinned first semiconductor wafer, the following steps are further included: arranging a plurality of Solder balls are used to electrically connect the conductive structures respectively; and electrical testing and singulation are performed.
本發明所提供的半導體超薄堆疊結構的製造方法，包含製造多個半導體晶圓，每一半導體晶圓的製造步驟包含：提供半導體基板，具有相對的主動面及背面；形成停止層結構於半導體基板內，將半導體基板分為基板第一部分及基板第二部分，其中基板第一部分位於停止層結構及主動面之間，基板第二部分位於停止層結構及背面之間，停止層結構至少包含氮化矽層，氮化矽層的製造包含先於半導體基板的第一深度進行氮離子佈植製程，接著進行高溫處理製程，使氮離子佈植的區域形成氮化矽層；以及於主動面設置多個電氣元件及內連層，內連層包含多個互連接點，並於基板第一部分設置多個導電結構連接內連層及停止層結構。選擇其中一半導體晶圓作為底層之第一半導體晶圓，部分的半導體晶圓則進行切單而作為待堆疊的第一批半導體晶片及至少一第二批半導體晶片；將第一批半導體晶片相對於第一半導體晶圓倒裝，使第一批半導體晶片的內連層及第一半導體晶圓的內連層相對且以混合鍵合技術接合在一起；進行第一模製製程，以在第一半導體晶圓上形成第一封裝膠體包覆第一批半導體晶片；進行第一背面研磨製程，自第一封裝膠體遠離第一半導體晶圓的一側除去部分第一封裝膠體以及移除第一批半導體晶片之基板第二部分的一部分；進行第一薄化製程，以形成第一半導體晶片層；進行第二背面研磨製程，自第一半導體晶圓的背面進行研磨，以移除第一半導體晶圓之基板第二部分的一部分；以及進行第二薄化製程，以形成薄化第一半導體晶圓，其中，第一薄化製程及第二薄化製程包含基板去除步驟及停止層去除步驟，其中基板去除步驟移除剩餘的基板第二部分，以顯露停止層結構，停止層去除步驟移除停止層結構，以顯露基板第一部分及導電結構。The method for manufacturing a semiconductor ultra-thin stack structure provided by the present invention includes manufacturing a plurality of semiconductor wafers, and the manufacturing steps of each semiconductor wafer include: providing a semiconductor substrate with a relative active surface and a back surface; forming a stop layer structure on the semiconductor In the substrate, the semiconductor substrate is divided into a first part of the substrate and a second part of the substrate, wherein the first part of the substrate is located between the stop layer structure and the active surface, and the second part of the substrate is located between the stop layer structure and the back surface, and the stop layer structure contains at least nitrogen The manufacture of the silicon nitride layer and the silicon nitride layer includes a nitrogen ion implantation process at the first depth of the semiconductor substrate, followed by a high temperature treatment process to form a silicon nitride layer in the area implanted with nitrogen ions; A plurality of electrical components and an interconnection layer, the interconnection layer includes a plurality of interconnection points, and a plurality of conductive structures are arranged on the first part of the substrate to connect the interconnection layer and the stop layer structure. One of the semiconductor wafers is selected as the first semiconductor wafer of the bottom layer, and part of the semiconductor wafers are then singulated as the first batch of semiconductor wafers to be stacked and at least one second batch of semiconductor wafers; Flip-chip on the first semiconductor wafer, make the interconnection layer of the first batch of semiconductor wafers and the interconnection layer of the first semiconductor wafer face each other and bond them together by hybrid bonding technology; perform the first molding process, in order to A first encapsulant is formed on a semiconductor wafer to cover the first batch of semiconductor wafers; a first back grinding process is performed to remove part of the first encapsulant and remove the first encapsulant from the side of the first encapsulant away from the first semiconductor wafer. Part of the second portion of the substrate of the batch of semiconductor wafers; a first thinning process is performed to form a first semiconductor wafer layer; a second back grinding process is performed to grind from the back of the first semiconductor wafer to remove the first semiconductor a portion of the second portion of the substrate of the wafer; and performing a second thinning process to form a thinned first semiconductor wafer, wherein the first thinning process and the second thinning process include a substrate removal step and a stop layer removal step , wherein the substrate removing step removes the remaining second portion of the substrate to expose the stop layer structure, and the stop layer removing step removes the stop layer structure to expose the first portion of the substrate and the conductive structure.
在本發明的一實施例中，在進行上述之第二背面研磨製程之前，更可於第一半導體晶片層上依序進行至少一第二半導體晶片層的堆疊，其中每一第二半導體晶片層的堆疊步驟包含：將第二批半導體晶片相對於第一半導體晶圓倒裝，使第二批半導體晶片的內連層及第一半導體晶片層的基板第一部分相對且接合在一起；進行第二模製製程，以在第一半導體晶片層上形成第二封裝膠體包覆第二批半導體晶片；進行第三背面研磨製程，自第二封裝膠體遠離第一半導體晶片層的一側除去部分第二封裝膠體以及移除第二批半導體晶片之基板第二部分的一部分；以及進行第三薄化製程，包含基板去除步驟及停止層去除步驟。In an embodiment of the present invention, before performing the second back grinding process, at least one second semiconductor wafer layer can be stacked sequentially on the first semiconductor wafer layer, wherein each second semiconductor wafer layer The stacking step includes: flipping the second batch of semiconductor wafers relative to the first semiconductor wafer, so that the interconnection layer of the second batch of semiconductor wafers and the first part of the substrate of the first semiconductor wafer layer are opposite and bonded together; A molding process to form a second encapsulant on the first semiconductor wafer layer to cover the second batch of semiconductor wafers; perform a third back grinding process to remove part of the second encapsulant from the side of the second encapsulant away from the first semiconductor wafer layer. encapsulating colloid and removing a part of the second portion of the substrate of the second batch of semiconductor chips; and performing a third thinning process, including a substrate removal step and a stopper layer removal step.
本發明所提供的半導體超薄堆疊結構的製造方法，包含：提供承載板，並於承載板上形成多個第一導電柱。提供多個半導體晶片，每一半導體晶片的製造步驟包含：提供半導體基板，具有相對的主動面及背面；形成停止層結構於半導體基板內，將半導體基板分為基板第一部分及基板第二部分，其中基板第一部分位於停止層結構及主動面之間，基板第二部分位於停止層結構及背面之間，停止層結構至少包含氮化矽層，氮化矽層的製造包含先於半導體基板的第一深度進行氮離子佈植製程，接著進行高溫處理製程，使氮離子佈植的區域形成氮化矽層；於主動面設置多個電氣元件及內連層，內連層包含多個互連接點，並於基板第一部分設置多個導電結構連接內連層及停止層結構；以及進行切單。從半導體晶片揀選出第一批半導體晶片及至少一第二批半導體晶片，第一批半導體晶片包含多個第一半導體晶片，第二批半導體晶片包含多個第二半導體晶片。倒裝設置第一批半導體晶片於承載板上，且第一導電柱介於相鄰的第一半導體晶片之間，其中第一批半導體晶片的內連層鄰近承載板且半導體基板遠離承載板。進行第一模製製程，以在承載板上形成第一封裝膠體包覆第一批半導體晶片及第一導電柱。進行第一背面研磨製程，自第一封裝膠體遠離承載板的一側除去部分第一封裝膠體以及移除第一批半導體晶片之基板第二部分的一部分。進行第一薄化製程以形成第一半導體晶片層，第一薄化製程包含依序移除第一批半導體晶片之剩餘的基板第二部分以及停止層結構，以顯露基板第一部分、導電結構以及第一導電柱。設置多個第二導電柱，以電性連接第一半導體晶片層的部分導電結構。倒裝設置第二批半導體晶片於第一半導體晶片層上，其中第二半導體晶片分別跨接在相鄰的第一半導體晶片之間，使第二半導體晶片的內連層電性連接顯露的第一導電柱及第一半導體晶片層的部分導電結構，且部分第二導電柱介於相鄰的第二半導體晶片之間。進行第二模製製程，以在第一半導體晶片層上形成第二封裝膠體包覆第二批半導體晶片及第二導電柱。進行第二背面研磨製程，自第二封裝膠體遠離第一半導體晶片層的一側除去部分第二封裝膠體以及移除第二批半導體晶片之基板第二部分的一部分。進行第二薄化製程以形成第二半導體晶片層，第二薄化製程包含依序移除第二批半導體晶片之剩餘的基板第二部分以及停止層結構，以顯露基板第一部分、導電結構以及第二導電柱。移除承載板，以顯露第一半導體晶片層的內連層及第一導電柱。The manufacturing method of the semiconductor ultra-thin stack structure provided by the present invention includes: providing a carrier board, and forming a plurality of first conductive pillars on the carrier board. A plurality of semiconductor wafers are provided, and the manufacturing steps of each semiconductor wafer include: providing a semiconductor substrate having an opposite active surface and a back surface; forming a stop layer structure in the semiconductor substrate, dividing the semiconductor substrate into a first part of the substrate and a second part of the substrate, The first part of the substrate is located between the stop layer structure and the active surface, the second part of the substrate is located between the stop layer structure and the back surface, the stop layer structure includes at least a silicon nitride layer, and the manufacture of the silicon nitride layer includes the first step prior to the semiconductor substrate. A nitrogen ion implantation process is carried out in depth, and then a high temperature treatment process is performed to form a silicon nitride layer in the area implanted with nitrogen ions; multiple electrical components and interconnection layers are arranged on the active surface, and the interconnection layer includes multiple interconnection points , and disposing a plurality of conductive structures on the first part of the substrate to connect the interconnection layer and the stop layer structure; and performing singulation. A first batch of semiconductor chips and at least one second batch of semiconductor chips are sorted out from the semiconductor chips. The first batch of semiconductor chips includes a plurality of first semiconductor chips, and the second batch of semiconductor chips includes a plurality of second semiconductor chips. The first batch of semiconductor chips is flip-chip disposed on the carrier board, and the first conductive pillars are interposed between adjacent first semiconductor chips, wherein the interconnection layer of the first batch of semiconductor chips is adjacent to the carrier board and the semiconductor substrate is away from the carrier board. A first molding process is performed to form a first encapsulant encapsulating the first batch of semiconductor chips and the first conductive pillars on the carrier board. A first back grinding process is performed to remove part of the first encapsulant from the side of the first encapsulant away from the carrier plate and remove a part of the second portion of the substrate of the first batch of semiconductor chips. performing a first thinning process to form a first semiconductor wafer layer, the first thinning process includes sequentially removing the remaining second portion of the substrate and the stop layer structure of the first batch of semiconductor wafers to expose the first portion of the substrate, the conductive structure and the first conductive column. A plurality of second conductive pillars are provided to electrically connect part of the conductive structures of the first semiconductor wafer layer. The second batch of semiconductor chips is flip-chip arranged on the first semiconductor chip layer, wherein the second semiconductor chips are respectively bridged between the adjacent first semiconductor chips, so that the interconnection layers of the second semiconductor chips are electrically connected to the exposed first semiconductor chips. A conductive column and a part of the conductive structure of the first semiconductor chip layer, and a part of the second conductive column is interposed between adjacent second semiconductor chips. A second molding process is performed to form a second encapsulant on the first semiconductor chip layer to cover the second batch of semiconductor chips and the second conductive pillars. A second back grinding process is performed to remove part of the second encapsulant from the side of the second encapsulant away from the layer of the first semiconductor chip and remove a part of the second part of the substrate of the second batch of semiconductor chips. performing a second thinning process to form a second semiconductor wafer layer, the second thinning process includes sequentially removing the remaining second portion of the substrate and the stop layer structure of the second batch of semiconductor wafers to expose the first portion of the substrate, the conductive structure and the second conductive column. The carrier board is removed to expose the interconnection layer and the first conductive column of the first semiconductor chip layer.
在本發明的一實施例中，於移除上述之承載板之後，更包含以下步驟：於第一半導體晶片層之遠離第二半導體晶片層的一側設置多個銲球，以分別電性連接內連層及第一導電柱；以及進行切單。In one embodiment of the present invention, after removing the above-mentioned carrier plate, the following steps are further included: setting a plurality of solder balls on the side of the first semiconductor chip layer far away from the second semiconductor chip layer to electrically connect them respectively the interconnection layer and the first conductive column; and performing singulation.
在本發明的一實施例中，上述之第一批半導體晶片之多個第一半導體晶片具有不同的電性功能。In an embodiment of the present invention, the plurality of first semiconductor chips in the above-mentioned first batch of semiconductor chips have different electrical functions.
在本發明的一實施例中，上述之第二批半導體晶片之第二半導體晶片具有不同的電性功能。In an embodiment of the present invention, the second semiconductor chips of the above-mentioned second batch of semiconductor chips have different electrical functions.
本發明在製造半導體晶圓時，先以離子佈植製程形成停止層結構於半導體基板內，再於半導體基板的主動面設置電氣元件及內連層；之後將兩半導體晶圓進行上下接合，亦或將半導體晶圓進行切單以形成多個半導體晶片後，使批次的半導體晶片與最底層之半導體晶圓進行結合。每進行一次半導體晶圓/晶片的接合(及模製封裝膠體)後，以背面研磨及薄化製程自上方半導體晶圓/晶片的背面去除上方半導體晶圓/晶片的部分半導體基板及停止層結構，使上方半導體晶圓/晶片形成薄化半導體晶圓/半導體晶片層，之後逐一在薄化半導體晶圓/晶片進行另一半導體晶圓/晶片的接合(及模製封裝膠體)、背面研磨及薄化製程，而往上堆疊另一薄化半導體晶圓/半導體晶片層，最後對最下方半導體晶圓進行背面研磨及薄化製程。由於每一薄化半導體晶圓/半導體晶片層厚度不大於12微米，在晶片總厚度限制為700微米的限制下，可堆疊至57層晶片層，進而滿足高積集度與速度要求。When the present invention manufactures semiconductor wafers, the ion implantation process is used to form a stop layer structure in the semiconductor substrate first, and then electrical components and interconnection layers are arranged on the active surface of the semiconductor substrate; after that, the two semiconductor wafers are bonded up and down, also Or after the semiconductor wafer is diced to form a plurality of semiconductor wafers, the batch of semiconductor wafers is combined with the bottom semiconductor wafer. After each semiconductor wafer/chip is bonded (and molded encapsulant), the backside grinding and thinning process is used to remove part of the semiconductor substrate and stop layer structure of the upper semiconductor wafer/chip from the back of the upper semiconductor wafer/chip Make the upper semiconductor wafer/chip form a thinned semiconductor wafer/semiconductor chip layer, and then carry out bonding (and molding encapsulant) of another semiconductor wafer/chip on the thinned semiconductor wafer/chip one by one, back grinding and Thinning process, and another thinned semiconductor wafer/semiconductor wafer layer is stacked on top, and finally the bottom semiconductor wafer is subjected to back grinding and thinning process. Since the thickness of each thinned semiconductor wafer/semiconductor wafer layer is not greater than 12 microns, it can be stacked to 57 wafer layers under the limit of the total wafer thickness of 700 microns, thereby meeting the requirements of high integration and speed.
為讓本發明之上述和其他目的、特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式，作詳細說明如下。In order to make the above and other objects, features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.
圖1A至圖1S所示是本發明一第一實施例半導體超薄堆疊結構的製造方法的剖面示意圖。首先，製造多個半導體晶圓10(標示於圖1E)，選擇其中一個半導體晶圓10作為堆疊底層的第一半導體晶圓10a(標示於圖1F)，其他的半導體晶圓10則作為待堆疊的第二半導體晶圓10b(標示於圖1F)及第三半導體晶圓10c(標示於圖1L)，多個半導體晶圓10的製造過程相同或相近，圖1A至圖1E所示即為製造半導體晶圓10的剖面示意圖。如圖1A所示，提供半導體基板12，半導體基板12例如矽基板(silicon substrate)、 磊晶矽基板(epitaxial silicon substrate)、矽鍺基板(silicon germanium substrate)、碳化矽基板(silicon carbide substrate)或矽覆絕緣(silicon on insulation，SOI)基板，於一實施例中，半導體基板的厚度例如為700至800微米(um)，較佳者為775微米，半導體基板12具有相對的主動面121及背面122。1A to 1S are schematic cross-sectional views of a method for manufacturing an ultra-thin semiconductor stack structure according to a first embodiment of the present invention. First, manufacture a plurality of semiconductor wafers 10 (marked in FIG. 1E ), select one of the semiconductor wafers 10 as the
接著，形成停止層結構於半導體基板12內。於一實施例中，停止層結構的製造包含進行至少一離子佈植製程及高溫處理製程。於一實施例中，離子佈植製程包含先進行氮離子佈植，再進行氧離子佈植。如圖1B及圖1C所示，先在半導體基板12的第一深度D1進行氮離子佈植製程14，再於半導體基板12的第二深度D2進行氧離子佈植製程16，於一實施例中，氮離子佈植區14’的第一深度D1為距離主動面121例如約1至5微米的深度，氧離子佈植區16’的第二深度D2則較氮離子佈植區14的第一深度D1小，亦即氧離子佈植區16’較為靠近主動面121。Next, a stop layer structure is formed in the
之後進行高溫處理，如圖1D所示，在氮離子佈植區14’形成氮化矽(Si3N4)層14a，在氧離子佈植區16’形成二氧化矽(SiO2)層16a，其中，二氧化矽層16a較為鄰近主動面121，氮化矽層14a較為鄰近背面122，於此實施例中，氮化矽層14a及二氧化矽層16a即構成上述之停止層結構18，其中，二氧化矽層16a位於氮化矽層14上且介於氮化矽層14a及主動面121之間。於一實施例中，氮化矽層14a及二氧化矽層16a的厚度例如為500奈米(nm)。又便於說明，將停止層結構18之二氧化矽層16a至主動面121之間的半導體基板12稱為基板第一部分123，停止層結構18之氮化矽層14a至背面122之間的半導體基板12稱為基板第二部分124。於一實施例中，當半導體晶圓10後續是應用在金屬氧化物半導體場效電晶體(MOSFET)的製作時，則為配合一般N型井(N well)的深度約為2微米，因此基板第一部分123的厚度應保留在不低於2微米的前提下，亦即在進行上述氮離子佈植製程14及氧離子佈植製程16時，氮離子佈植區14’的第一深度D1及氧離子佈植區16’的第二深度皆應略大於2微米。Afterwards, a high-temperature treatment is performed, as shown in FIG. 1D, a silicon nitride (Si3N4)
接續上述說明，如圖1E所示，於主動面121設置有多個電氣元件20及具有互連接點221的內連層22，電氣元件20例如包含金屬氧化物半導體(MOS)，並於基板第一部分123設置多個導電結構，於一實施例中，導電結構例如包含矽穿孔（Through Silicon Via，TSV）24，矽穿孔24垂直連接內連層22及停止層結構18之二氧化矽層16a。其中電氣元件20、內連層22及矽穿孔24的製造流程包含一般半導體製程的前段製程(front-end-of-line，FEOL)及後段製程(back-end-of-line，BEOL)，前段製程例如在半導體基板12上作出電阻、電容、二極體、電晶體等元件，後段製程例如在各個元件之間做出連接用金屬佈線及互連接點221；於一實施例中互連接點221例如為銅接點。圖1E所示即為本發明一實施例之半導體晶圓10示意圖，以下說明之第一半導體晶圓10a、第二半導體晶圓10b及第三半導體晶圓10c沿用半導體晶圓10描述所用的元件符號。其中第一半導體晶圓10a之矽穿孔24的位置例如對應於後續製程中銲球的安裝位置，第二半導體晶圓10b之矽穿孔24的位置例如與第三半導體晶圓10c之內連層22的互連接點221對應。Continuing the above description, as shown in FIG. 1E , a plurality of
如圖1F所示，將第二半導體晶圓10b相對於第一半導體晶圓10a倒裝，使第一半導體晶圓10a及第二半導體晶圓10b的內連層22相對且互連接點221各自對應；接著以混合鍵合技術(Hybrid bonding)，如圖1G所示，使第一半導體晶圓10a及第二半導體晶圓10b上下堆疊在一起，其中混合鍵合技術包含銅對銅接合及回火等製程。As shown in FIG. 1F, the
接著，利用第一背面研磨(Grind)製程自第二半導體晶圓10b的背面122進行研磨，以除去第二半導體晶圓10b之基板第二部分124的一部分，如圖1H所示，殘留厚度極薄的基板第二部分124，於一實施例中，殘留之基板第二部分124得厚度約為20。Then, use a first backside grinding (Grind) process to grind from the
之後，進行第一薄化製程，以形成一薄化第二半導體晶圓，第一薄化製程包含基板去除步驟以及停止層去除步驟，圖1I至圖1K所示即為第一薄化製程的示意圖。基板去除步驟用以移除殘留的基板第二部分124，如圖1I所示，以顯露出停止層結構18，例如為顯露氮化矽層14a，於一實施例中，基板去除步驟為第一化學機械研磨(CMP)製程，其中，矽及氮化矽的選擇比例如為20，亦即Si/Si3N4為20；停止層去除步驟為用以移除停止層結構18，亦即依序移除氮化矽層14a以及二氧化矽層16a，以顯露基板第一部分123及矽穿孔24；於一實施例中，先以第二化學機械研磨製程移除氮化矽層14a，如圖1J所示，以顯露二氧化矽層16a，其中氮化矽及二氧化矽的選擇比例如為10，亦即Si3N4/SiO2為10；再以第三化學機械研磨製程移除二氧化矽層16a，如圖1K所示，以顯露基板第一部分123及矽穿孔24，其中二氧化矽及矽的選擇比例如為5，亦即SiO2/Si為5。藉由基板第一部分123及矽穿孔24的顯露，而形成薄化之第二半導體晶圓10b’。Afterwards, a first thinning process is performed to form a thinned second semiconductor wafer. The first thinning process includes a substrate removal step and a stopper layer removal step, as shown in FIGS. 1I to 1K. schematic diagram. The substrate removal step is used to remove the remaining
接續上述說明，上述已完成第一半導體晶圓10a及薄化第二半導體晶圓10b’的堆疊；接著，如圖1L所示，將第三半導體晶圓10c相對於第一半導體晶圓10a倒裝，使第三半導體晶圓10c的內連層22面對薄化第二半導體晶圓10b’的基板第一部分123，於一實施例中，第三半導體晶圓10c之內連層22的互連接點221分別對應於薄化第二半導體晶圓10b’的矽穿孔24。之後，重覆上述第一背面研磨製程及第一薄化製程，以完成薄化第三半導體晶圓10c’及薄化第二半導體晶圓10b’的堆疊，於一實施例中，薄化第二半導體晶圓10b’或薄化第三半導體晶圓10c’的厚度例如為12微米。如此，在具有多個半導體晶圓10的前提下，逐個重覆進行上述半導體晶圓10的接合製程、第一背面研磨製程及第一薄化製程，即可完成多層薄化半導體晶圓10’與第一半導體晶圓10a的堆疊，如圖1M所示，於一實施例中，作為堆疊在最上方的薄化半導體晶圓10’，其基板第一部分123可不需形成有矽穿孔24。Continuing the above description, the stacking of the
在完成預定數目的多個薄化半導體晶圓10’的堆疊之後，利用第二背面研磨製程自第一半導體晶圓10a的背面122進行研磨，如圖1N所示，以除去第一半導體晶圓10a之基板第二部分124的一部分，而殘留厚度極薄的基板第二部分124；接著，進行第二薄化製程，如圖1O至圖1Q所示，利用上述基板去除步驟及停止層去除步驟，以依序移除第一半導體晶圓10a殘留的基板第二部分124、氮化矽層14a及二氧化矽層16a，進而顯露薄化第一半導體晶圓10a’的基板第一部分123及矽穿孔24，如此完成薄化第一半導體晶圓10a’、薄化第二半導體晶圓10b’、薄化第三半導體晶圓10c’….等多個薄化半導體晶圓10’的堆疊。After completing the stacking of a predetermined number of thinned semiconductor wafers 10', a second backside grinding process is used to grind from the
之後，如圖1R所示，於薄化第一半導體晶圓10a’之遠離薄化第二半導體晶圓10b’的一側設置多個銲球26，以分別電性連接顯露的矽穿孔24；並於進行晶圓針測（Chip Probing，CP），以進行電性功能上的測試（Test）後，進行切單(die saw)，以完成如圖1S所示之半導體超薄堆疊結構28，其中每一層薄化半導體晶圓10’切單後作為一半導體晶片層10”，由於每一薄化半導體晶圓10’的厚度可例如為12微米，在晶片總厚度限制為700微米的限制下，本發明實施例半導體超薄堆疊結構28中可堆疊至57層薄化半導體晶片層10”，可滿足高積集度與速度要求，而具有更佳的電氣特性及效率。Afterwards, as shown in FIG. 1R , a plurality of
又在上述第一薄化製程及第二薄化製程中，是以基板去除步驟及停止層去除步驟共包含三道化學機械研磨製程為例進行說明，惟不限於此，於又一實施例中，第一/第二薄化製程包含一溼式蝕刻製程及二化學機械研磨製程，亦即在基板去除步驟中，以溼式蝕刻製程取代上述第一化學機械研磨製程，薄化製程的剖面示意圖仍可參閱圖1H至圖1K或者圖1N至圖1Q所示，先以溼式蝕刻製程移除殘留的基板第二部分124，以顯露出氮化矽層14a，溼式蝕刻製程中矽及氮化矽的選擇比例如為40，亦即Si/Si3N4為40；再依序進行第二化學機械研磨製程及第三化學機械研磨製程，以依序將氮化矽層14a及二氧化矽層16a移除。In the first thinning process and the second thinning process above, the substrate removal step and the stop layer removal step include three chemical mechanical polishing processes as an example for illustration, but it is not limited thereto. In another embodiment , the first/second thinning process includes a wet etching process and two chemical mechanical polishing processes, that is, in the substrate removal step, the wet etching process is used to replace the first chemical mechanical polishing process, and the cross-sectional schematic diagram of the thinning process Still refer to FIG. 1H to FIG. 1K or FIG. 1N to FIG. 1Q, the remaining
又於另一實施例中，第一/第二薄化製程亦可以三道電漿乾式蝕刻(plasma dry etching)製程取代上述三道化學機械研磨製程，薄化製程的剖面示意圖仍可參閱圖1H至圖1K或者圖1N至圖1Q所示，先以第一電漿乾式蝕刻製程移除殘留的基板第二部分124，以顯露出氮化矽層14a，於一實施例中，第一電漿乾式蝕刻中矽及氮化矽的選擇比例如為80，亦即Si/Si3N4為80；接著，以第二電漿乾式蝕刻製程移除氮化矽層14a，以顯露二氧化矽層16a，於一實施例中，第二電漿乾式蝕刻製程中氮化矽及二氧化矽的選擇比例如為20，亦即Si3N4/SiO2為20；接著，以第三電漿乾式蝕刻製程移除二氧化矽層16a，以顯露基板第一部分123及矽穿孔24，於一實施例中，第三電漿乾式蝕刻製程中二氧化矽及矽的選擇比例如為5，亦即SiO2/Si為5。In yet another embodiment, the first/second thinning process can also be replaced by three plasma dry etching (plasma dry etching) processes. The schematic cross-sectional view of the thinning process can still refer to FIG. 1H As shown in FIG. 1K or FIG. 1N to FIG. 1Q, the remaining
在上述第一實施例中，是以晶圓堆疊晶圓（Wafer on Wafer，WoW）的方式進行，惟不限於此，圖2A至圖2K所示是本發明一第二實施例半導體超薄堆疊結構的製造方法的剖面示意圖。於此第二實施例中，先提供多個半導體晶圓10，其製造步驟已揭示於上述圖1A至圖1E所示，於此不再贅述；接著，選擇其中一部分半導體晶圓10作為底層之第一半導體晶圓10a(標示於圖2B)，另一部分半導體晶圓10則進行電性功能測試，揀選電性功能良好的晶粒進行切單，如圖2A所示，以獲得多個半導體晶片30，每一半導體晶片30仍包含電氣元件20、內連層22及半導體基板12，半導體基板12中形成有停止層結構18，停止層結構18將半導體基板12分為基板第一部分123及基板第二部分124，基板第一部分123並形成有矽穿孔24，以連接停止層結構18及內連層22。底下為便於說明，將多個半導體晶片30依後續製程的先後順序區分為第一批半導體晶片30a及及第二批半導體晶片30b，每一批中包含多個半導體晶片30。In the above-mentioned first embodiment, it is carried out in the way of stacking wafers on wafers (Wafer on Wafer, WoW), but it is not limited to this. Figure 2A to Figure 2K show a second embodiment of semiconductor ultra-thin stacking of the present invention. Schematic cross-sectional illustration of the fabrication method of the structure. In this second embodiment, a plurality of
如圖2B所示，將第一批半導體晶片30a相對於第一半導體晶圓10a倒裝，使第一批半導體晶片30a的內連層22及第一半導體晶圓10a的內連層22相對且互連接點221各自對應；接著以混合鍵合技術，如圖2C所示，使第一半導體晶圓10a及第一批半導體晶片30a上下接合在一起。As shown in FIG. 2B, the first batch of
接著，進行第一模製(molding)製程，如圖2D所示，在第一半導體晶圓10a上形成第一封裝膠體(molding compound)32a包覆第一批半導體晶片30a；之後，利用第一背面研磨製程自第一封裝膠體32a遠離第一半導體晶圓10a的一側除去部分第一封裝膠體32a以及第一批半導體晶片30a之基板第二部分124的一部分，如圖2E所示，第一批半導體晶片30a殘留厚度極薄的基板第二部分124以及與基板第二部分124平齊的第一封裝膠體32a。Next, a first molding (molding) process is carried out, as shown in FIG. 2D, a first packaging compound (molding compound) 32a is formed on the
之後，進行第一薄化製程，包含第一實施例所述之基板去除步驟以及停止層去除步驟，藉以移除第一批半導體晶片30a之殘留的基板第二部分124、停止層結構18及部分的封裝膠體32，如圖2F所示，顯露第一批半導體晶片30a的基板第一部分123及矽穿孔24，如此即形成薄化之第一半導體晶片層30a’，第一半導體晶片層30a’堆疊於第一半導體晶圓10a上。Afterwards, the first thinning process is carried out, including the substrate removal step and the stop layer removal step described in the first embodiment, so as to remove the remaining
接著，將第二批半導體晶片30b仍然相對於第一半導體晶圓10a倒裝，使第二批半導體晶片30b的內連層22分別對應於第一半導體晶片層30a’的基板第一部分123，並進行第二批半導體晶片30b與第一半導體晶片層30a’的接合；進行第二模製製程，以在第一半導體晶片層30a’上形成第二封裝膠體32b包覆第二批半導體晶片30b；進行背面研磨製程及薄化製程，藉以自第二封裝膠體32b遠離第一半導體晶片層30a’的一側除去部分第二封裝膠體32b、第二批半導體晶片30b之基板第二部分(未繪示)及停止層結構(未繪示)，如圖2G所示，顯露第二批半導體晶片30b的基板第一部分123及矽穿孔24，以形成薄化之第二半導體晶片層30b’。如此，逐批重覆進行上述批次半導體晶片30的接合製程、模製製程、背面研磨製程及第一薄化製程，即可完成第一半導體晶片層30a’及多層第二半導體晶片層30b’與第一半導體晶圓10a的堆疊，如圖2H所示，於一實施例中，作為堆疊在最上方的第二半導體晶片層30b’，其基板第一部分123可不需形成有矽穿孔24。Next, the second batch of
接著，與第一實施例相同地，在完成預定數目的第二半導體晶片層30b’的堆疊之後，利用第二背面研磨製程及第二薄化製程自第一半導體晶圓10a的背面122依序除去第一半導體晶圓10a的基板第二部分124及停止層結構18，如圖2I所示，以顯露基板第一部分123及矽穿孔24，如此完成薄化之第一半導體晶圓10a’及多個半導體晶片30的堆疊。Next, similar to the first embodiment, after completing the stacking of a predetermined number of second semiconductor wafer layers 30b', a second back grinding process and a second thinning process are sequentially applied from the
上述第一及第二薄化製程包含第一實施例所述之基板去除步驟以及停止層去除步驟，其中對於基板去除步驟以及停止層去除步驟的製程選擇，例如是三道化學機械研磨製程、或是溼式蝕刻製程搭配化學機械研磨製程、或者皆為電漿乾式蝕刻製程，以及對於矽、氮化矽及二氧化矽等材料之間選擇比的採用已敘述於第一實施例中，於此不再贅述。The above-mentioned first and second thinning processes include the substrate removal step and the stop layer removal step described in the first embodiment, wherein the process selection for the substrate removal step and the stop layer removal step is, for example, three chemical mechanical polishing processes, or Whether it is a wet etching process combined with a chemical mechanical polishing process, or both are plasma dry etching processes, and the selection ratio between materials such as silicon, silicon nitride, and silicon dioxide has been described in the first embodiment, here No longer.
之後，如圖2J所示，於薄化第一半導體晶圓10a’之顯露的矽穿孔24上設置銲球，並於進行電性功能上的測試後，沿著第一封裝膠體32a及第二封裝膠體32b的切割道321進行切單，以完成如圖2K所示之半導體超薄堆疊結構34。在此實施例半導體超薄堆疊結構34中，由於進行堆疊的半導體晶片30已先進行電性功能的測試及揀選，因此半導體超薄堆疊結構34的良率較高。Afterwards, as shown in FIG. 2J , solder balls are placed on the exposed through-
圖3A至圖3L所示是本發明一第三實施例半導體超薄堆疊結構的製造方法的剖面示意圖。於第三實施例中，首先，提供一承載板40，並於承載板40上形成多個第一導電柱42，如圖3A所示，承載板40例如為厚度500微米且長度301毫米(mm)的玻璃，第一導電柱42例如為銅柱。3A to 3L are schematic cross-sectional views of a method for manufacturing an ultra-thin semiconductor stack structure according to a third embodiment of the present invention. In the third embodiment, firstly, a
接著，揀選多個經電性功能測試的半導體晶片44(標示於圖3B)，半導體晶片44可具有相同或不同的電性功能，多種半導體晶片44為經由分別對多種半導體晶圓10進行切單而來，而每一種半導體晶圓10的製造步驟已揭示於上述圖1A至圖1E所示，於此不再贅述。每一半導體晶片44仍包含電氣元件20、內連層22及半導體基板12，半導體基板12中形成有停止層結構18，停止層結構18將半導體基板12分為基板第一部分123及基板第二部分124，基板第一部分123並形成有矽穿孔24，以連接停止層結構18及內連層22。於一實施例中，半導體基板12的厚度例如為775微米，內連層22的厚度例如為10微米。Then, pick a plurality of semiconductor wafers 44 (marked in FIG. 3B ) through the electrical function test. The
將揀選的第一批半導體晶片倒裝接合於承載板40上，如圖3B所示，以第一批的半導體晶片44包含三個第一半導體晶片44a為例，三個第一半導體晶片44a可具有相同或不同的電性功能，且第一導電柱42介於相鄰第一半導體晶片44a之間，於一實施例中，在進行第一半導體晶片44a的倒裝接合時，是以內連層22鄰近承載板40且半導體基板12遠離承載板10的倒裝方式進行接合。The first batch of semiconductor chips picked are flip-chip bonded on the
之後，進行第一模製製程，如圖3C所示，在承載板40上形成第一封裝膠體46a包覆三個第一半導體晶片44a及第一導電柱42。接著，利用上述第一背面研磨製程及第一薄化製程自第一封裝膠體46a遠離承載板40的一側除去部分第一封裝膠體46a以及第一半導體晶片44a的基板第二部分124及停止層結構18，如圖3D所示，顯露基板第一部分123與矽穿孔24、以及第一導電柱44，如此即形成薄化之第一半導體晶片層44a’。Afterwards, a first molding process is performed. As shown in FIG. 3C , a
之後，進行第二導電柱48的設置，第二導電柱48例如為垂直設置在部分矽穿孔24上，如圖3E所示，每一薄化之第一半導體晶片44a的至少一矽穿孔24上設置有第二導電柱48，第二導電柱48例如為銅柱。之後將揀選的第二批半導體晶片倒裝跨接在相鄰兩薄化的第一半導體晶片44a之間，如圖3F所示，以第二批半導體晶片包含兩個第二半導體晶片44b為例，兩個半導體晶片44b可具有相同或不同的電性功能，於一實施例中，第二半導體晶片44b的內連層22與第一半導體晶片層44a’的基板第一部分123相對，第二半導體晶片44b的互連接點221與部分矽穿孔24及第一導電柱42形成電性連接，且部分第二導電柱48介於相鄰的第二半導體晶片44b之間。Afterwards, the setting of the second
接著，依序進行第二模製製程、第二背面研磨製程及第二薄化製程，以在第一半導體晶片層44a’上形成第二封裝膠體46b包覆第二半導體晶片44b及第二導電柱48後，再以第二背面研磨製程及第二薄化製程移除第二半導體晶片44b的基板第二部分124、停止結構層18、以及部分的第二封裝膠體46b，如圖3G所示，顯露基板第一部分123與矽穿孔124、以及第二導電柱48，如此即形成薄化之第二半導體晶片層44b’。Then, the second molding process, the second back grinding process and the second thinning process are performed in order to form a
如此，重複地進行第三導電柱50的設置、第三半導體晶片44c倒裝設置於第二半導體晶片層44b’上、封膠模製製程、背面研磨製程及薄化製程，以完成第三半導體晶片層44c’的堆疊，如圖3H所示，以及陸續更多層半導體晶片層的堆疊，如圖3I所示。In this way, the arrangement of the third
之後，移除承載板40，如圖3J所示，以顯露第一半導體晶片層的內連層22以及第一導電柱42，且在內連層22所預設的電路接點(未繪示)及第一導電柱上設置銲球26，如圖3K所示，並進行切單，以完成如圖3L所示的半導體超薄堆疊結構52。Afterwards, remove the
在上述第一/第二/第三實施例半導體超薄堆疊結構的製造方法中，停止層結構的製造是以先後進行氮離子及氧離子佈植，並進行高溫處理以形成氮化矽層及二氧化矽層為例進行說明，惟不限於此，於一實施例中，停止層結構可僅包含氮化矽層，亦即在半導體基板內進行氮離子佈植製程後即進行高溫處理製程，以便在距離主動面1至5微米的深度形成氮化矽層；則對應地，後續第一/第二薄化製程的停止層去除步驟僅需對氮化矽層進行移除，其他後續製程則相同，於此不再贅述。In the manufacturing method of the semiconductor ultra-thin stacked structure of the first/second/third embodiment above, the manufacture of the stop layer structure is to implant nitrogen ions and oxygen ions successively, and perform high temperature treatment to form a silicon nitride layer and The silicon dioxide layer is described as an example, but it is not limited thereto. In one embodiment, the stop layer structure may only include a silicon nitride layer, that is, a high-temperature treatment process is performed after the nitrogen ion implantation process is performed in the semiconductor substrate, In order to form a silicon nitride layer at a depth of 1 to 5 microns from the active surface; correspondingly, only the silicon nitride layer needs to be removed in the stop layer removal step of the subsequent first/second thinning process, and the other subsequent processes The same, and will not be repeated here.
在本發明實施例中，藉由停止層結構的形成於半導體基板的一深度，以及後續薄化製程中基板移除步驟及停止層結構的逐步進行，使得半導體基板可確實被研磨或蝕刻至僅保留基板第一部分，亦即僅保留1至5微米的基板厚度，而使得每一半導體晶片層的整體厚度不大於12微米，在晶片總厚度限制為700微米的限制下，本發明實施例半導體超薄堆疊結構28中可堆疊至50多層薄化半導體晶片層，可滿足高積集度與速度要求，而具有更佳的電氣特性及效率。In the embodiment of the present invention, the semiconductor substrate can be polished or etched to only Retain the first part of the substrate, that is, only retain the thickness of the substrate from 1 to 5 microns, so that the overall thickness of each semiconductor wafer layer is not greater than 12 microns. Under the limitation of the total thickness of the wafer to 700 microns, the semiconductor superconductor of the embodiment of the present invention Up to 50 layers of thinned semiconductor wafers can be stacked in the
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field of the present invention can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.
10、10’:半導體晶圓 10a、10a’:第一半導體晶圓 10b、10b’:第二半導體晶圓 10c:第三半導體晶圓 10”:半導體晶片層 12:半導體基板 121:主動面 122:背面 123:基板第一部分 124:基板第二部分 D1:第一深度 D2:第二深度 14:氮離子佈植製程 14’:氮離子佈植區 14a:氮化矽層 16:氧離子佈植製程 16’:氧離子佈植區 16a:二氧化矽層 18:停止層結構 20:電氣元件 22:內連層 221:互連接點 24:矽穿孔 26:銲球 28、34、52:半導體超薄堆疊結構 30:半導體晶片 30a:第一批半導體晶片 30a’:第一半導體晶片層 30b:第二批半導體晶片 30b’:第二半導體晶片層 32a:第一封裝膠體 32b:第二封裝膠體 321:切割道 40:承載板 42:第一導電柱 44:半導體晶片 44a:第一半導體晶片 44a’:第一半導體晶片層 44b:第二半導體晶片 44b’:第二半導體晶片層 44c:第三半導體晶片 44c’:第三半導體晶片層 46a:第一封裝膠體 46b:第二封裝膠體 48:第二導電柱 50:第三導電柱 10, 10': semiconductor wafer 10a, 10a': the first semiconductor wafer 10b, 10b': the second semiconductor wafer 10c: the third semiconductor wafer 10": semiconductor wafer layer 12: Semiconductor substrate 121: active side 122: back 123: Substrate Part 1 124: Substrate Part II D1: first depth D2: second depth 14: Nitrogen ion implantation process 14': Nitrogen ion implantation area 14a: silicon nitride layer 16: Oxygen ion implantation process 16': Oxygen ion implantation area 16a: Silicon dioxide layer 18: Stop layer structure 20: Electrical components 22: Inner layer 221: interconnection point 24: TSV 26: solder ball 28, 34, 52: Semiconductor ultra-thin stack structure 30: Semiconductor wafer 30a: First batch of semiconductor wafers 30a': first semiconductor wafer layer 30b: Second batch of semiconductor wafers 30b': second semiconductor wafer layer 32a: the first packaging colloid 32b: the second packaging colloid 321: cutting road 40: Loading board 42: The first conductive column 44: Semiconductor wafer 44a: first semiconductor wafer 44a': first semiconductor wafer layer 44b: second semiconductor wafer 44b': second semiconductor wafer layer 44c: the third semiconductor wafer 44c': the third semiconductor wafer layer 46a: the first packaging colloid 46b: Second encapsulation colloid 48: The second conductive column 50: The third conductive column
圖1A至圖1S所示是本發明一第一實施例半導體超薄堆疊結構的製造方法的剖面示意圖。 圖2A至圖2K所示是本發明一第二實施例半導體超薄堆疊結構的製造方法的剖面示意圖。 圖3A至圖3L所示是本發明一第三實施例半導體超薄堆疊結構的製造方法的剖面示意圖。 1A to 1S are schematic cross-sectional views of a method for manufacturing an ultra-thin semiconductor stack structure according to a first embodiment of the present invention. 2A to 2K are schematic cross-sectional views of a method for manufacturing an ultra-thin semiconductor stack structure according to a second embodiment of the present invention. 3A to 3L are schematic cross-sectional views of a method for manufacturing an ultra-thin semiconductor stack structure according to a third embodiment of the present invention.
10:半導體晶圓 10: Semiconductor wafer
123:基板第一部分 123: Substrate Part 1
124:基板第二部分 124: Substrate Part II
14a:氮化矽層 14a: silicon nitride layer
16a:二氧化矽層 16a: Silicon dioxide layer
18:停止層結構 18: Stop layer structure
20:電氣元件 20: Electrical components
22:內連層 22: Inner layer
221:互連接點 221: interconnection point
24:矽穿孔 24: TSV
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| US17/740,461 US20220375918A1 (en) | 2021-05-19 | 2022-05-10 | Method of manufacturing three-dimensional system-on-chip and three-dimensional system-on-chip |
| CN202210509287.5A CN115376994A (en) | 2021-05-19 | 2022-05-11 | Semiconductor structure with power supply connection structure under transistor and manufacturing method thereof |
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| US20130147032A1 (en) * | 2011-12-07 | 2013-06-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Passivation layer for packaged chip |
| TW201834162A (en) * | 2017-02-28 | 2018-09-16 | 艾馬克科技公司 | Semiconductor device and method of manufacturing thereof |
| US20190206864A1 (en) * | 2015-11-09 | 2019-07-04 | International Business Machines Corporation | Stoplayer |
| TW202101728A (en) * | 2019-06-20 | 2021-01-01 | 台灣積體電路製造股份有限公司 | Semiconductor structure and method manufacturing the same |
| TW202119587A (en) * | 2019-07-25 | 2021-05-16 | 南韓商三星電子股份有限公司 | Semiconductor package and method for manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20130147032A1 (en) * | 2011-12-07 | 2013-06-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Passivation layer for packaged chip |
| US20190206864A1 (en) * | 2015-11-09 | 2019-07-04 | International Business Machines Corporation | Stoplayer |
| TW201834162A (en) * | 2017-02-28 | 2018-09-16 | 艾馬克科技公司 | Semiconductor device and method of manufacturing thereof |
| TW202101728A (en) * | 2019-06-20 | 2021-01-01 | 台灣積體電路製造股份有限公司 | Semiconductor structure and method manufacturing the same |
| TW202119587A (en) * | 2019-07-25 | 2021-05-16 | 南韓商三星電子股份有限公司 | Semiconductor package and method for manufacturing the same |
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