TWI778788B - Driving circuit - Google Patents
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Abstract
Description
本案係關於一種驅動電路，特別係關於一種驅動發光元件的驅動電路。This case relates to a driving circuit, especially a driving circuit for driving light-emitting elements.
在現今的顯示器技術當中，隨著發光元件尺寸越來越小，如何提供維持較大的驅動電流以增強顯示器的亮度為本領域中重要的議題。In today's display technology, as the size of light-emitting elements is getting smaller and smaller, how to provide and maintain a large driving current to enhance the brightness of the display is an important issue in the field.
本揭示文件提供一種驅動電路。驅動電路包含發光元件、第一電晶體、第二電晶體、第一控制電路以及第二控制電路。驅動電流自系統高電壓端經由第一電晶體以及發光元件流至系統低電壓端。第二電晶體電性耦接第一電晶體的閘極端。第一控制電路用以控制第一電晶體以調整驅動電流的脈衝幅度。第一控制電路包含第一重置電路。第一重置電路電性耦接第一電晶體的閘極端，第一重置電路用以接收第一控制訊號，並且第一重置電路依據第一控制訊號重置第一電晶體。第二控制電路用以控制第二電晶體以調整驅動電流的脈衝寬度。第二控制電路包含第二重置電路。第二重置電路電性耦接第二電晶體的閘極端，用以接收第二控制訊號，並且第二重置電路依據第二控制訊號重置第二電晶體。The present disclosure provides a driving circuit. The driving circuit includes a light-emitting element, a first transistor, a second transistor, a first control circuit, and a second control circuit. The driving current flows from the high voltage terminal of the system to the low voltage terminal of the system through the first transistor and the light-emitting element. The second transistor is electrically coupled to the gate terminal of the first transistor. The first control circuit is used for controlling the first transistor to adjust the pulse amplitude of the driving current. The first control circuit includes a first reset circuit. The first reset circuit is electrically coupled to the gate terminal of the first transistor, the first reset circuit is used for receiving the first control signal, and the first reset circuit resets the first transistor according to the first control signal. The second control circuit is used for controlling the second transistor to adjust the pulse width of the driving current. The second control circuit includes a second reset circuit. The second reset circuit is electrically coupled to the gate terminal of the second transistor for receiving the second control signal, and the second reset circuit resets the second transistor according to the second control signal.
綜上所述，本揭示文件的驅動電路利用第一重置電路依據第一控制訊號重置第一電晶體的閘極端的電位，並且利用第二重置電路依據第二控制訊號重置第二電晶體的閘極端的電位，從而加強畫面的均勻度。To sum up, the driving circuit of the present disclosure uses the first reset circuit to reset the potential of the gate terminal of the first transistor according to the first control signal, and uses the second reset circuit to reset the second voltage according to the second control signal The potential of the gate terminal of the transistor enhances the uniformity of the picture.
下列係舉實施例配合所附圖示做詳細說明，但所提供之實施例並非用以限制本揭露所涵蓋的範圍，而結構運作之描述非用以限制其執行順序，任何由元件重新組合之結構，所產生具有均等功效的裝置，皆為本揭露所涵蓋的範圍。另外，圖示僅以說明為目的，並未依照原尺寸作圖。為使便於理解，下述說明中相同元件或相似元件將以相同之符號標示來說明。The following examples are described in detail in conjunction with the accompanying drawings, but the provided examples are not intended to limit the scope of the present disclosure, and the description of the structure and operation is not intended to limit its execution order. The structure and the resulting device with equal efficacy are all within the scope of the present disclosure. In addition, the drawings are for illustrative purposes only, and are not drawn according to the original size. For ease of understanding, the same or similar elements in the following description will be described with the same symbols.
在全篇說明書與申請專利範圍所使用之用詞(terms)，除有特別註明除外，通常具有每個用詞使用在此領域中、在此揭露之內容中與特殊內容中的平常意義。The terms used throughout the specification and the scope of the patent application, unless otherwise specified, generally have the ordinary meaning of each term used in the field, in the content disclosed herein and in the specific content.
此外，在本文中所使用的用詞『包含』、『包括』、『具有』、『含有』等等，均為開放性的用語，即意指『包含但不限於』。此外，本文中所使用之『及／或』，包含相關列舉項目中一或多個項目的任意一個以及其所有組合。In addition, the terms "comprising", "including", "having", "containing" and the like used in this document are all open-ended terms, ie, meaning "including but not limited to". In addition, the term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
於本文中，當一元件被稱為『耦接』或『連接』時，可指『電性耦接』或『電性連接』。『耦接』或『連接』亦可用以表示二或多個元件間相互搭配操作或互動。此外，雖然本文中使用『第一』、『第二』、…等用語描述不同元件，該用語僅是用以區別以相同技術用語描述的元件或操作。In this document, when an element is referred to as being "coupled" or "connected", it may be referred to as "electrically coupled" or "electrically connected". "Coupled" or "connected" may also be used to indicate the cooperative operation or interaction between two or more elements. In addition, although terms such as "first", "second", . . . are used herein to describe different elements, the terms are only used to distinguish elements or operations described by the same technical terms.
請參閱第1圖，第1圖為依據本揭露一些實施例之驅動電路100的功能方塊示意圖。如第1圖所示，驅動電路100包含第一電晶體T1、第二電晶體T2、第一控制電路110、第二控制電路120以及發光元件L1。發光元件L1可以由微型發光二極體、次毫米發光二極體、發光二極體或其他發光元件實施。Please refer to FIG. 1. FIG. 1 is a functional block diagram of a
在架構上，第一電晶體T1以及發光元件L1電性耦接在系統高電壓端OVDD以及系統低電壓端之間OVSS。第一控制電路110電性耦接第一電晶體T1的閘極端。第二電晶體T2電性耦接第一電晶體T1的閘極端。第二控制電路120電性耦接第二電晶體T2的閘極端。Structurally, the first transistor T1 and the light-emitting element L1 are electrically coupled between the system high voltage terminal OVDD and the system low voltage terminal OVSS. The
在功能上，第一控制電路110用以控制第一電晶體T1以調整自系統高電壓端OVDD經由第一電晶體T1以及發光元件L1至系統低電壓端OVSS的驅動電流的脈衝幅度。第二控制電路120用以控制第二電晶體T2以調整前述驅動電流的脈衝寬度。Functionally, the
第一控制電路110包含第一重置電路112、第一寫入電路114、第一補償電路116、第二電容C2以及第三電容C3。詳細而言，第一重置電路112電性耦接第一電晶體T1的閘極端，並且用以接收第一控制訊號RG1以及第一參考電壓Data_H。第一重置電路112用以依據第一控制訊號RG1將第一參考電壓Data_H傳送至第一電晶體T1的閘極端，藉此重置第一電晶體T1的閘極端的電位。第一寫入電路114電性耦接第一電晶體T1的第二端，並且用以接收第一資料訊號DATA1以及第三控制訊號Spam。第一寫入電路114用以依據第三控制訊號Spam將第一資料訊號DATA1傳送至第一電晶體T1的第二端。The
第一補償電路116電性耦接在第一電晶體T1的第一端以及第二端之間，並且用以接收第三控制訊號Spam。第一補償電路116用以依據第三控制訊號Spam導通第一電晶體T1的第一端及閘極端之間的電路路徑。The
第二重置電路122電性耦接第一電晶體T2的閘極端，並且用以接收第二控制訊號RG2以及第一參考電壓Data_H。第二重置電路122用以依據第二控制訊號RG2將第一參考電壓Data_H傳送至第二電晶體T2的閘極端，藉此重置第二電晶體T2的閘極端的電位。第二寫入電路124電性耦接第二電晶體T2的第二端，並且用以接收第二資料訊號DATA2以及第四控制訊號Spwm(n)。第二寫入電路124用以依據第四控制訊號Spwm(n)將第二資料訊號DATA2傳送至第二電晶體T2的第二端。
The
第二補償電路126電性耦接在第二電晶體T2的第一端以及第二端之間，並且用以接收第四控制訊號Spwm(n)。第二補償電路126用以依據第四控制訊號Spwm(n)導通第二電晶體T2的第一端及閘極端之間的電路路徑。
The
在本揭示的一些實施例中，驅動電路100更包含第一電容C1、第二電容C2、第三電容C3、第九電晶體T9、第十電晶體T10以及第十一電晶體T11。詳細而言，第一電容C1電性耦接第二電晶體T2的閘極端，並且用以接收掃頻訊號TCS，第一電容C1用以透過電容耦合作用將掃頻訊號TCS傳送至第二電晶體T2的閘極端。第二電容C2電性耦接在系統高電壓端OVDD第一電晶體T1的閘極端之間，藉以穩定第一電晶體T1的閘極端的電位。第三電容C3電性耦接在第一電晶體的閘極端以
及第二端之間，藉以穩定第一電晶體T1的閘極端的電位。
In some embodiments of the present disclosure, the
第九電晶體T9電性耦接第二控制電路120，並且用以接收第二參考電壓Data_L以及第五控制訊號EM。第九電晶體T9用以依據第五控制訊號EM將第二參考電壓Data_L傳送至第二控制電路120。第十電晶體T10以及第十一電晶體T11電性耦接在提供予發光元件L1的驅動電流的電流路徑上，並且用以接收第五控制訊號EM。第十電晶體T10以及第十一電晶體T11用以依據第五控制訊號EM導通驅動電流的電流路徑。
The ninth transistor T9 is electrically coupled to the
前述該些電晶體分別具有第一端、第二端以及閘極端(Gate)。當其中一電晶體的第一端為汲極端(源極端)時，該電晶體的第二端則為源極端(汲極端)。另外，前述電容亦分別具有第一端以及第二端。 The aforementioned transistors respectively have a first terminal, a second terminal and a gate terminal (Gate). When the first terminal of one of the transistors is the drain terminal (source terminal), the second terminal of the transistor is the source terminal (drain terminal). In addition, the aforementioned capacitors also have a first end and a second end, respectively.
請參閱第2圖，第2圖為依據本揭露一些實施例之驅動電路100的電路架構圖。如第2圖所示，第一重置電路112包含第三電晶體T3。第三電晶體T3的第一端電性耦接第一電晶體T1的閘極端，第三電晶體T3的第二端用以接收第一參考電壓Data_H，第三電晶體T3的閘極端用以接收第一控制訊號RG1。
Please refer to FIG. 2 , which is a circuit structure diagram of a
第一寫入電路114包含第五電晶體T5。第五電晶體T5的第一端電性耦接第一電晶體T1的第二端，第五電晶體T5的第二端用以接收第一資料訊號DATA1，第五電晶體T5的閘極端用以接收第三控制訊號Spam。
The
第一補償電路116包含第六電晶體T6。第六電晶體T6的第一端電性耦接第一電晶體T1的第一端，第六電晶體T6的第二端電性耦接第一電晶體T1的閘極端，第六電晶體T6的閘極端用以接收第三控制訊號Spam。
The
第二重置電路122包含第四電晶體T4。第四電晶體T4的第一端用以接收第一參考電壓Data_H，第四電晶體T4的第二端電性耦接第二電晶體T2的閘極端，第四電晶體T4的閘極端用以接收第二控制訊號RG2(n)。
The
第二寫入電路124包含第七電晶體T7。第七電晶體T7的第一端用以接收第二資料訊號DATA2，第七電晶體T7的第二端電性耦接第二電晶體T2的第二端，第七電晶體T7的閘極端用以接收第四控制訊號Spwm(n)。
The
第二補償電路126包含第八電晶體T8。第八電晶體T8的第一端電性耦接第二電晶體T2的閘極端，第八電晶體T8的第二端電性耦接第二電晶體T2的第一端，第八電晶體T8的閘極端用以接收第四控制訊號Spwm(n)。
The
進一步而言，第九電晶體T9的第一端電性耦接第二電晶體T2的第二端，第九電晶體T9的第二端用以接收第二參考電壓Data_L，第九電晶體T9的閘極端用以接收第五控制訊號EM。 Further, the first end of the ninth transistor T9 is electrically coupled to the second end of the second transistor T2, the second end of the ninth transistor T9 is used for receiving the second reference voltage Data_L, and the ninth transistor T9 The gate terminal of the is used for receiving the fifth control signal EM.
第十電晶體T10的第一端電性耦接系統高電壓端OVDD，第十電晶體T10的第二端電性耦接第一電晶體T1的第一端，第十電晶體T10的閘極端用以接收第五控制訊號EM。 The first terminal of the tenth transistor T10 is electrically coupled to the system high voltage terminal OVDD, the second terminal of the tenth transistor T10 is electrically coupled to the first terminal of the first transistor T1, and the gate terminal of the tenth transistor T10 for receiving the fifth control signal EM.
第十一電晶體T11的第一端電性耦接第一電晶體T1的第二端，第十一電晶體T11的第二端電性耦接發光元件L1的第一端，第十一電晶體T11的閘極端用以接收第五控制訊號EM。 The first terminal of the eleventh transistor T11 is electrically coupled to the second terminal of the first transistor T1, the second terminal of the eleventh transistor T11 is electrically coupled to the first terminal of the light-emitting element L1, and the eleventh transistor T11 is electrically coupled to the first terminal of the light-emitting element L1. The gate terminal of the crystal T11 is used for receiving the fifth control signal EM.
發光元件L1的第二端電性耦接系統低電壓端OVSS。可將電容C4視為發光元件L1的內部電容。 The second terminal of the light emitting element L1 is electrically coupled to the system low voltage terminal OVSS. The capacitance C4 can be regarded as the internal capacitance of the light emitting element L1.
第一電容C1的第一端電性耦接第二電晶體T2的閘極端，第一電容C1的第二端用以接收掃頻訊號TCS。第二電容C2的第一端電性耦接系統高電壓端OVDD，第二電容C2的第二端電性耦接第一電晶體T1的閘極端。第三電容C3的第一端電性耦接第一電晶體的閘極端，第三電容C3的第二端電性耦接第一電晶體的第二端。 The first terminal of the first capacitor C1 is electrically coupled to the gate terminal of the second transistor T2, and the second terminal of the first capacitor C1 is used for receiving the frequency sweep signal TCS. The first terminal of the second capacitor C2 is electrically coupled to the system high voltage terminal OVDD, and the second terminal of the second capacitor C2 is electrically coupled to the gate terminal of the first transistor T1. The first terminal of the third capacitor C3 is electrically coupled to the gate terminal of the first transistor, and the second terminal of the third capacitor C3 is electrically coupled to the second terminal of the first transistor.
為了更佳的理解驅動電路100的操作方式，請參閱第3圖。第3圖為第2圖的驅動電路100在逐行掃描期間TP1以及全域掃描期間TP2的控制訊號的時序圖。如第3圖所示，逐行掃描期間TP1包含重置期間P1以及寫入及補償期間P2。全域掃描期間TP2包含重置期間P3、寫入及補償期間P4以及發光期間P5。需特別說明的是，第3圖中的該些期間的時間長度僅用以示例，並非用以限制本揭露文件。
For a better understanding of the operation of the driving
詳細而言，第二控制訊號RG2(n)在重置期間P1具有第一邏輯位準(例如，高邏輯位準)，並且第二控制訊號RG2(n)在寫入及補償期間P2至發光期間P5具有第二邏輯位準(例如，低邏輯位準)。第四控制訊號Spwm(n)在寫入及補償期間P2具有高邏輯位準，並且第四控制訊號Spwm(n)在重置期間P1及P3、寫入及補償期間P4以及發光期間P5具有低邏輯位準。第一控制訊號RG1在重置期間P3具有高邏輯位準，並且第一控制訊號RG1在重置期間P1、寫入及補償期間P2及P4以及發光期間P5具有低邏輯位準。 In detail, the second control signal RG2(n) has a first logic level (eg, a high logic level) during the reset period P1, and the second control signal RG2(n) emits light during the writing and compensation period P2 Period P5 has a second logic level (eg, a low logic level). The fourth control signal Spwm(n) has a high logic level during the writing and compensation period P2, and the fourth control signal Spwm(n) has a low logic level during the reset periods P1 and P3, the writing and compensation period P4, and the light-emitting period P5 logical level. The first control signal RG1 has a high logic level during the reset period P3, and the first control signal RG1 has a low logic level during the reset period P1, the writing and compensation periods P2 and P4, and the light-emitting period P5.
第三控制訊號Spam在寫入及補償期間P4具有高邏輯位準，並且第三控制訊號Spam在重置期間P1及P3、寫入及補償期間P2以及發光期間P5具有低邏輯位準。第五控制訊號EM在發光期間P5具有高邏輯位準，並且第五控制訊號EM在重置期間P1、P3以及寫入及補償期間P2、P4具有低邏輯位準。需要注意的是，在本揭示文件中，第一參考電壓Data_H的電位可以在高邏輯位準，第二參考電壓Data_L可以的電位可以在低邏輯位準。 The third control signal Spam has a high logic level during the writing and compensation period P4, and the third control signal Spam has a low logic level during the reset periods P1 and P3, the writing and compensation period P2, and the light-emitting period P5. The fifth control signal EM has a high logic level during the light-emitting period P5, and the fifth control signal EM has a low logic level during the reset periods P1, P3 and the writing and compensation periods P2, P4. It should be noted that, in this disclosure, the potential of the first reference voltage Data_H may be at a high logic level, and the potential of the second reference voltage Data_L may be at a low logic level.
為使畫素驅動電路100的整體操作更加清楚易懂，以下請一併參考第1~4F圖。第4A圖為依據本揭露一些實施例之驅動電路100在逐行掃描期間TP1中的重置期間P1的示意圖。第4B圖為依據本揭露一些實施例之驅動電路100在逐行掃描期間TP1中的寫入及補償期
間P2的示意圖。第4C圖為依據本揭露一些實施例之驅動電路100在全域掃描期間TP2中的重置期間P3的示意圖。第4D圖為依據本揭露一些實施例之驅動電路100在全域掃描期間TP2中的寫入及補償期間P4的示意圖。第4E圖為依據本揭露一些實施例之驅動電路100在全域掃描期間TP2中的發光期間P5的示意圖。第4F圖為依據本揭露一些實施例之驅動電路100在全域掃描期間TP2中的發光期間P5的示意圖。
In order to make the overall operation of the
於逐行掃描期間TP1的重置期間P1中，由於第二控制訊號RG2(n)具有高邏輯位準，因此第四電晶體T4會導通。另一方面，由於第一控制訊號RG1、第三控制訊號Spam、第四控制訊號Spwm(n)以及第五控制訊號EM具有低邏輯位準，因此第三電晶體T3、第五電晶體T5、第六電晶體T6、第七電晶體T7、第八電晶體T8、第九電晶體T9、第十電晶體T10以及第十一電晶體T11會關斷。 In the reset period P1 of the progressive scan period TP1, since the second control signal RG2(n) has a high logic level, the fourth transistor T4 is turned on. On the other hand, since the first control signal RG1, the third control signal Spam, the fourth control signal Spwm(n) and the fifth control signal EM have low logic levels, the third transistor T3, the fifth transistor T5, The sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10 and the eleventh transistor T11 are turned off.
詳細而言，於重置期間P1，第一參考電壓Data_H經由第四電晶體T4傳送至第二電晶體T2的閘極端以及第一電容C1的第二端，使第二電晶體T2的閘極端的電位被上拉至高邏輯位準，藉此重置第二電晶體T2的閘極端的電位。並且，此時第一電容C1的第二端的電位實質上等於第一參考電壓Data_H。 Specifically, in the reset period P1, the first reference voltage Data_H is transmitted to the gate terminal of the second transistor T2 and the second terminal of the first capacitor C1 through the fourth transistor T4, so that the gate terminal of the second transistor T2 The potential of t is pulled up to a high logic level, thereby resetting the potential of the gate terminal of the second transistor T2. Moreover, at this time, the potential of the second end of the first capacitor C1 is substantially equal to the first reference voltage Data_H.
於逐行掃描期間TP1的寫入及補償期間P2中，由於第四控制訊號Spwm(n)具有高邏輯位準，因此第七 電晶體T7以及第八第晶體T8會導通。另一方面，由於第一控制訊號RG1、第二控制訊號RG2(n)、第三控制訊號Spam以及第五控制訊號EM具有低邏輯位準，因此第三電晶體T3、第四電晶體T4、第五電晶體T5、第六電晶體T6、第九電晶體T9、第十電晶體T10以及第十一電晶體T11會關斷。 In the writing and compensation period P2 of the progressive scan period TP1, since the fourth control signal Spwm(n) has a high logic level, the seventh The transistor T7 and the eighth transistor T8 are turned on. On the other hand, since the first control signal RG1, the second control signal RG2(n), the third control signal Spam and the fifth control signal EM have low logic levels, the third transistor T3, the fourth transistor T4, The fifth transistor T5, the sixth transistor T6, the ninth transistor T9, the tenth transistor T10 and the eleventh transistor T11 are turned off.
詳細而言，於寫入及補償期間P2，第二資料訊號DATA2的資料電壓會經由第七電晶體T7傳送至第二電晶體T2的第二端，使第二電晶體T2的第二端的電位實質上等於第二資料訊號DATA2的資料電壓。並且，第一電容C1的第二端的電位經由第八電晶體T8以及第二電晶體T2傳送至第二電晶體T2的第二端直到第二電晶體T2截止。換言之，當第二電晶體T2的源極端的電位比第二電晶體T2的閘極端的電位小一個第二電晶體T2的臨界電壓(例如，臨界電壓Vth2)時，第二電晶體T2截止。此時第二電晶體T2的閘極端的電位實質上等於第二資料訊號DATA2的電壓加上第二電晶體T2的臨界電壓Vth2。第二電晶體T2的第二端的電位實質上等於第二資料訊號DATA2的資料電壓。如此，於寫入及補償期間P2中，即可將第二資料訊號DATA2的資料電壓寫入並第二控制電路120並對將第二電晶體T2的臨界電壓進行補償操作。
Specifically, during the writing and compensation period P2, the data voltage of the second data signal DATA2 is transmitted to the second end of the second transistor T2 through the seventh transistor T7, so that the potential of the second end of the second transistor T2 is substantially equal to the data voltage of the second data signal DATA2. In addition, the potential of the second end of the first capacitor C1 is transmitted to the second end of the second transistor T2 through the eighth transistor T8 and the second transistor T2 until the second transistor T2 is turned off. In other words, when the potential of the source terminal of the second transistor T2 is smaller than the potential of the gate terminal of the second transistor T2 by a threshold voltage (eg, the threshold voltage Vth2) of the second transistor T2, the second transistor T2 is turned off. At this time, the potential of the gate terminal of the second transistor T2 is substantially equal to the voltage of the second data signal DATA2 plus the threshold voltage Vth2 of the second transistor T2. The potential of the second terminal of the second transistor T2 is substantially equal to the data voltage of the second data signal DATA2. In this way, in the writing and compensation period P2, the data voltage of the second data signal DATA2 can be written into the
於全域掃描期間TP2的重置期間P3中，由於第一控制訊號RG1具有高邏輯位準，因此第三電晶體T3 會導通。另一方面，由於第二控制訊號RG2(n)、第三控制訊號Spam、第四控制訊號Spwm(n)以及第五控制訊號EM具有低邏輯位準，因此第四電晶體T4、第五電晶體T5、第六電晶體T6、第七第晶體T7、第八第晶體T8、第九電晶體T9、第十電晶體T10以及第十一電晶體T11會關斷。 In the reset period P3 of the global scanning period TP2, since the first control signal RG1 has a high logic level, the third transistor T3 will turn on. On the other hand, since the second control signal RG2(n), the third control signal Spam, the fourth control signal Spwm(n) and the fifth control signal EM have low logic levels, the fourth transistor T4, the fifth transistor The transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10 and the eleventh transistor T11 are turned off.
詳細而言，於重置期間P3，第一參考電壓Data_H經由第三電晶體T3傳送至第一電晶體T1的閘極端、第二電容C2的第二端以及第三電容C3的第一端，藉此重置第二電晶體T2的閘極端的電位。並且，此時第二電容C2的第二端以及第三電容C3的第一端的電位實質上等於第一參考電壓Data_H。 In detail, during the reset period P3, the first reference voltage Data_H is transmitted to the gate terminal of the first transistor T1, the second terminal of the second capacitor C2 and the first terminal of the third capacitor C3 through the third transistor T3, Thereby, the potential of the gate terminal of the second transistor T2 is reset. Moreover, at this time, the potentials of the second end of the second capacitor C2 and the first end of the third capacitor C3 are substantially equal to the first reference voltage Data_H.
於全域掃描期間TP2的寫入及補償期間P4中，由於第三控制訊號Spam具有高邏輯位準，因此第五電晶體T5以及第六電晶體T6會導通。另一方面，由於第一控制訊號RG1、第二控制訊號RG2(n)、第四控制訊號Spwm(n)以及第五控制訊號EM具有低邏輯位準，因此第三電晶體T3、第四電晶體T4、第七第晶體T7、第八第晶體T8、第九電晶體T9、第十電晶體T10以及第十一電晶體T11會關斷。 During the writing and compensation period P4 of the global scanning period TP2, since the third control signal Spam has a high logic level, the fifth transistor T5 and the sixth transistor T6 are turned on. On the other hand, since the first control signal RG1, the second control signal RG2(n), the fourth control signal Spwm(n) and the fifth control signal EM have low logic levels, the third transistor T3, the fourth transistor The crystal T4, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10 and the eleventh transistor T11 are turned off.
詳細而言，於寫入及補償期間P4，第一資料訊號DATA1的資料電壓會經由第五電晶體T5傳送至第一電晶體T1的第二端，使第一電晶體T1的第二端的電位實質上等於第一資料訊號DATA1的資料電壓。並且，第
二電容C2的第二端的電位經由第六電晶體T6以及第一電晶體T1傳送至第一電晶體T1的第二端直到第一電晶體T1截止。換言之，當第一電晶體T1的源極端的電位比第一電晶體T1的閘極端的電位小一個第一電晶體T1的臨界電壓(例如，臨界電壓Vth1)時，第一電晶體T1截止。此時第一電晶體T1的閘極端的電位實質上等於第一資料訊號DATA1的電壓加上第一電晶體T1的臨界電壓Vth1。第一電晶體T1的第二端的電位實質上等於第一資料訊號DATA1的資料電壓。如此，於寫入及補償期間P4中，即可將第一資料訊號DATA1的資料電壓寫入並第一控制電路110並對將第一電晶體T1的臨界電壓進行補償操作。
Specifically, during the writing and compensation period P4, the data voltage of the first data signal DATA1 is transmitted to the second end of the first transistor T1 through the fifth transistor T5, so that the potential of the second end of the first transistor T1 is It is substantially equal to the data voltage of the first data signal DATA1. And, the first
The potential of the second end of the two capacitors C2 is transmitted to the second end of the first transistor T1 through the sixth transistor T6 and the first transistor T1 until the first transistor T1 is turned off. In other words, when the potential of the source terminal of the first transistor T1 is smaller than the potential of the gate terminal of the first transistor T1 by a threshold voltage (eg, the threshold voltage Vth1 ) of the first transistor T1 , the first transistor T1 is turned off. At this time, the potential of the gate terminal of the first transistor T1 is substantially equal to the voltage of the first data signal DATA1 plus the threshold voltage Vth1 of the first transistor T1. The potential of the second terminal of the first transistor T1 is substantially equal to the data voltage of the first data signal DATA1. In this way, in the writing and compensation period P4, the data voltage of the first data signal DATA1 can be written into the
於全域掃描期間TP2的寫入及發光期間P5中，由於第五控制訊號EM具有高邏輯位準，因此第九電晶體T9、第十電晶體T10以及第十一電晶體T11會導通。另一方面，由於第一控制訊號RG1、第二控制訊號RG2(n)、第三控制訊號Spam以及第四控制訊號Spwm(n)具有低邏輯位準，因此第三電晶體T3、第四電晶體T4、第五電晶體T5、第六電晶體T6、第七第晶體T7、第八第晶體T8會關斷。 In the writing and light-emitting period P5 of the global scanning period TP2, since the fifth control signal EM has a high logic level, the ninth transistor T9, the tenth transistor T10 and the eleventh transistor T11 are turned on. On the other hand, since the first control signal RG1, the second control signal RG2(n), the third control signal Spam and the fourth control signal Spwm(n) have low logic levels, the third transistor T3, the fourth transistor The crystal T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.
詳細而言，於發光期間P5，驅動電流自系統高電壓端OVDD經由第十電晶體T10、第一電晶體T1、第十一電晶體T11、發光元件L1流至系統低電壓端OVSS，使發光元件L1發光。 In detail, in the light-emitting period P5, the driving current flows from the system high voltage terminal OVDD to the system low voltage terminal OVSS through the tenth transistor T10, the first transistor T1, the eleventh transistor T11, and the light-emitting element L1, so as to emit light Element L1 emits light.
此時，掃頻訊號TCS的斜波電壓經由第一電容C1透過電容耦合作用逐漸上拉第二電晶體T2的閘極端的電位，使第二電晶體T2導通。當第二電晶體T2導通時，第二參考電壓Data_L會經由第九電晶體T9、第二電晶體T2傳送至第一電晶體T1的閘極端，使第一電晶體T1關斷。換言之，於寫入及補償期間P2中第二資料訊號的資料電壓的大小會影響第二電晶體T2的閘極端的電位，從而決定於發光期間EM5中第二電晶體T2依據掃頻訊號TCS而導通的時間點，進而控制驅動電流的脈衝寬度，藉以控制發光元件L1的灰階。 At this time, the ramp voltage of the frequency sweep signal TCS gradually pulls up the potential of the gate terminal of the second transistor T2 through the first capacitor C1 through capacitive coupling, so that the second transistor T2 is turned on. When the second transistor T2 is turned on, the second reference voltage Data_L is transmitted to the gate terminal of the first transistor T1 via the ninth transistor T9 and the second transistor T2, so that the first transistor T1 is turned off. In other words, the data voltage of the second data signal in the writing and compensation period P2 will affect the potential of the gate terminal of the second transistor T2, so that the second transistor T2 is determined according to the frequency sweep signal TCS in the light-emitting period EM5. The turn-on time point further controls the pulse width of the driving current, thereby controlling the gray scale of the light-emitting element L1.
需要注意的是，於顯示面板的一幀中，不同列的畫素在逐行掃描期間TP1依據不同的控制訊號依序進行重置操作並接收第二資料訊號DATA2。舉例而言，第n列的驅動電路依據第二控制訊號RG2(n)進行重置操作，並依據第四控制訊號Spwm(n)收第二資料訊號DATA2中相應的資料電壓。第n+1列的驅動電路依據第二控制訊號RG2(n+1)進行重置操作，並且依據第四控制訊號Spwm(n+1)接收第二資料訊號DATA2中相應的資料電壓。 It should be noted that, in one frame of the display panel, the pixels of different columns are sequentially reset according to different control signals during the progressive scan period TP1 and receive the second data signal DATA2. For example, the driving circuit in the nth row performs the reset operation according to the second control signal RG2(n), and receives the corresponding data voltage in the second data signal DATA2 according to the fourth control signal Spwm(n). The driving circuit of the n+1th row performs the reset operation according to the second control signal RG2(n+1), and receives the corresponding data voltage in the second data signal DATA2 according to the fourth control signal Spwm(n+1).
並且，於顯示面板的一幀中，不同列的畫素在全域掃描期間TP2依據相同的控制訊號接近形重置操作並收第一資料訊號DATA1。舉例而言，第n列的驅動電路依據第一控制訊號RG1進行重置操作，並且依據第四控制訊號Spam接收第二資料訊號DATA2中相應的資料 電壓。第n+1列的驅動電路依據第一控制訊號RG1進行重置操作，並且依據第四控制訊號Spam收第二資料訊號DATA2中相應的資料電壓。 In addition, in one frame of the display panel, the pixels of different rows are in the global scanning period TP2 according to the same control signal to approximate the reset operation and receive the first data signal DATA1. For example, the driving circuit in the nth row performs the reset operation according to the first control signal RG1, and receives the corresponding data in the second data signal DATA2 according to the fourth control signal Spam Voltage. The driving circuit of the n+1th row performs the reset operation according to the first control signal RG1, and receives the corresponding data voltage in the second data signal DATA2 according to the fourth control signal Spam.
請參閱第5圖，第5圖為依據本揭露一些實施例之驅動電路200的電路架構圖。如第5圖所示，驅動電路200包含第一電晶體T1、第二電晶體T2、第一控制電路110、第二控制電路120、發光元件L1、第一電容C1、第二電容C2、第九電晶體T9、第十電晶體T10以及第十一電晶體T11。與第2圖之實施例中的驅動電路100相較，第5圖之實施例中的驅動電路200不同之處在於，不具有第三電容C3。於驅動電路200的其他細部連接關係與作動方式，大致相同於先前第2圖之實施例中畫素驅動電路100，在此不另贅述。
Please refer to FIG. 5 , which is a circuit structure diagram of a
請參閱第6圖，第6圖為依據本揭露一些實施例之驅動電路300的電路架構圖。如第6圖所示，驅動電路200包含第一電晶體T1、第二電晶體T2、第一控制電路110、第二控制電路120、發光元件L1、第一電容C1、第二電容C2、第三電容C3、第九電晶體T9、第十電晶體T10、第十一電晶體T11以及第十二電晶體T2。與第5圖之實施例中的驅動電路200相較，第6圖之實施例中的驅動電路300不同之處在於，增加第十二電晶體。詳細而言，第十二電晶體T12的第一端電性耦接第發光元件L1的第一端，第十二電晶體T12的第二端用以接收第三參考電壓Vsus，第十二電晶體T12的閘極端
用以接收第六控制訊號R_anode。第十二電晶體T12用以依據第六控制訊號R_anode將第三參考電壓Vsus傳送至發光元件L1的第一端，藉以重置發光元件L1的第一端的電位。在一些實施例中，第六控制訊號R_anode的波形可以類似於第一控制訊號RG1，並且第三參考電壓Vsus的電位在低邏輯位準，故在此不再贅述。於驅動電路200的其他細部連接關係與作動方式，大致相同於先前第2圖之實施例中畫素驅動電路100，在此不另贅述。
Please refer to FIG. 6 , which is a circuit structure diagram of a
請參考第7圖，第7圖為依據本揭露一些實施例之驅動電路400的電路架構圖。如第7圖所示，驅動電路400包含第一電晶體T1、第二電晶體T2、第一控制電路110、第二控制電路120、發光元件L1、第一電容C1、第二電容C2、第九電晶體T9、第十電晶體T10。與第5圖之實施例中的驅動電路200相較，第7圖之實施例中的驅動電路400不同之處在於，不具有第十一電晶體T11。於驅動電路400的其他細部連接關係與作動方式，大致相同於先前第5圖之實施例中畫素驅動電路200，在此不另贅述。
Please refer to FIG. 7 , which is a circuit structure diagram of a
請參閱第8圖，第8圖為依據本揭露一些實施例之驅動電路500的電路架構圖。如第8圖所示，驅動電路500包含第一電晶體T1、第二電晶體T2、第一控制電路110、第二控制電路120、發光元件L1、第一電容C1、第二電容C2、第九電晶體T9、第十電晶體T10。
與第5圖之實施例中的驅動電路200相較，第8圖之實施例中的驅動電路500不同之處在於，發光元件L1的連接位置。詳細而言，發光元件L1的第一端電性耦接系統高電壓端OVDD，發光元件L1的第二端電性耦接第十電晶體T10的第一端。於驅動電路500的其他細部連接關係與作動方式，大致相同於先前第5圖之實施例中畫素驅動電路200，在此不另贅述。
Please refer to FIG. 8 , which is a circuit structure diagram of a
請參閱第9圖，第9圖為依據本揭露一些實施例之驅動電路600的電路架構圖。如第9圖所示，驅動電路500包含第一電晶體T1、第二電晶體T2、第一控制電路110、第二控制電路120、發光元件L1、第一電容C1、第二電容C2、第九電晶體T9、第十電晶體T10以及第十三電晶體T13。與第8圖之實施例中的驅動電路500相較，第9圖之實施例中的驅動電路600不同之處在於，新增第十三電晶體T13。詳細而言，第十三電晶體T13的第一端電性耦接系統高電壓端OVDD，第十三電晶體T13的第二端電性耦接第十電晶體T10的第一端，第十三電晶體T13的閘極端用以接收第七控制訊號Reset。在一些實施例中，第七控制訊號Reset的波形可以類似於第一控制訊號RG1，在此不再贅述。於驅動電路600的其他細部連接關係與作動方式，大致相同於先前第8圖之實施例中畫素驅動電路500，在此不另贅述。
Please refer to FIG. 9 , which is a circuit structure diagram of a
前述該些電晶體是以N型金屬氧化物半導體場效電晶體(N-type MOSFET,NMOS)開關作為舉例說明，但本揭示文件並不以此為限。於另一實施例中，本領域習知技藝人士可將上述該些電晶體替換為P型金屬氧化物半導體場效電晶體(P-type MOSFET,PMOS)開關、C型金屬氧化物半導體場效電晶體(C-type MOSFET,CMOS)開關或其他相似的開關元件，並對系統電壓(例如，系統高電壓端OVDD、系統低電壓端OVSS、第一參考電壓Data_H以及第二參考電壓Data_L)、控制訊號(例如，第一控制訊號RG1、第二控制訊號RG2(n)、第三控制訊號Spam、第四控制訊號Spwm(n)及第五控制訊號EM)、資料訊號(例如，第一資料訊號DATA1以及第二資料訊號DATA2)相對應地調整，也可以達到與本實施例相同的功能。 The aforementioned transistors are exemplified by N-type metal oxide semiconductor field effect transistor (N-type MOSFET, NMOS) switches, but the present disclosure is not limited thereto. In another embodiment, those skilled in the art can replace the above transistors with P-type metal oxide semiconductor field effect transistors (P-type MOSFET, PMOS) switches, C-type metal oxide semiconductor field effect transistors A transistor (C-type MOSFET, CMOS) switch or other similar switching elements, and control system voltages (eg, the system high voltage terminal OVDD, the system low voltage terminal OVSS, the first reference voltage Data_H and the second reference voltage Data_L), Control signals (for example, the first control signal RG1, the second control signal RG2(n), the third control signal Spam, the fourth control signal Spwm(n), and the fifth control signal EM), the data signals (for example, the first data The signal DATA1 and the second data signal DATA2) are adjusted correspondingly to achieve the same function as this embodiment.
綜上所述，本案之驅動電路100、200、300、400以及500利用第一控制電路110控制第一電晶體T1以調整提供予發光元件L1的驅動電流的脈衝幅度，並利用第二控制電路120控制第二電晶體T2以調整提供予發光元件L1的驅動電流的脈衝寬度，從而調整發光元件L1的灰階，進而增進發光元件可顯示的亮度。再者，藉由第一重置電路112依據第一控制訊號RG1重置第一電晶體T1的閘極端的電位，並且利用第二重置電路122依據第二控制訊號RG2重置第二電晶體T1的閘極端的電位，從而加強畫面的均勻度。
To sum up, the driving
雖然本揭露已以實施方式揭露如上，然其並非用以限定本揭露，任何本領域通具通常知識者，在不脫離本揭露之精神和範圍內，當可作各種之更動與潤飾，因此本揭露之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present disclosure has been disclosed as above in embodiments, it is not intended to limit the present disclosure. Anyone with ordinary knowledge in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. The scope of protection disclosed shall be determined by the scope of the appended patent application.
為使本揭露之上述和其他目的、特徵、優點與實施例能更明顯易懂，所附符號之說明如下： In order to make the above and other objects, features, advantages and embodiments of the present disclosure more clearly understood, the descriptions of the appended symbols are as follows:
100,200,300,400,500:驅動電路 100,200,300,400,500: Driver circuit
110:第一控制電路 110: The first control circuit
112:第一重置電路 112: First reset circuit
114:第一寫入電路 114: The first write circuit
116:第一補償電路 116: The first compensation circuit
120:第二控制電路 120: The second control circuit
122:第二重置電路 122: Second reset circuit
124:第二寫入電路 124: Second write circuit
126:第二補償電路 126: Second compensation circuit
L1:發光元件 L1: Light-emitting element
T1:第一電晶體 T1: first transistor
T2:第二電晶體 T2: Second transistor
T3:第三電晶體 T3: The third transistor
T4:第四電晶體 T4: Fourth transistor
T5:第五電晶體 T5: Fifth transistor
T6:第六電晶體 T6: sixth transistor
T7:第七電晶體 T7: seventh transistor
T8:第八電晶體 T8: Eighth transistor
T9:第九電晶體 T9: ninth transistor
T10:第十電晶體 T10: Tenth transistor
T11:第十一電晶體 T11: Eleventh transistor
T12:第十二電晶體 T12: The twelfth transistor
T13:第十三電晶體 T13: Thirteenth transistor
C1:第一電容 C1: first capacitor
C2:第二電容 C2: second capacitor
C3:第三電容 C3: the third capacitor
C4:第四電容 C4: Fourth capacitor
DATA1:第一資料訊號 DATA1: The first data signal
DATA2:第二資料訊號 DATA2: The second data signal
RG1:第一控制訊號 RG1: The first control signal
RG2(n),RG2(n+1):第二控制訊號 RG2(n), RG2(n+1): The second control signal
Spam:第三控制訊號 Spam: the third control signal
Spwm(n),Spwm(n+1):第四控制訊號 Spwm(n), Spwm(n+1): the fourth control signal
EM:第五控制訊號 EM: Fifth control signal
R_anode:第六控制訊號 R_anode: sixth control signal
Reset:第七控制訊號 Reset: the seventh control signal
TCS:掃頻訊號 TCS: frequency sweep signal
OVDD:系統高電壓端 OVDD: system high voltage terminal
OVSS:系統低電壓端 OVSS: System Low Voltage Side
Data_H:第一參考電壓 Data_H: The first reference voltage
Data_L:第二參考電壓 Data_L: Second reference voltage
TP1:逐行掃描期間 TP1: During progressive scan
TP2:全域掃描期間 TP2: During global scan
P1,P3:重置期間 P1, P3: reset period
P2,P4:寫入及補償期間 P2, P4: During writing and compensation
P5:發光期間 P5: During light emission
為使本揭露之上述和其他目的、特徵、優點與實施例能更明顯易懂，所附圖式之說明如下： 第1圖為依據本揭露一些實施例之驅動電路的功能方塊示意圖。 第2圖為依據本揭露一些實施例之驅動電路的電路架構圖。 第3圖為第2圖的驅動電路在逐行掃描期間以及全域掃描期間的控制訊號的時序圖。 第4A圖為依據本揭露一些實施例之驅動電路在逐行掃描期間中的重置期間的示意圖。 第4B圖為依據本揭露一些實施例之驅動電路在逐行掃描期間中的寫入及補償期間的示意圖。 第4C圖為依據本揭露一些實施例之驅動電路在全域掃描期間中的重置期間的示意圖。 第4D圖為依據本揭露一些實施例之驅動電路在全域掃描期間中的寫入及補償期間的示意圖。 第4E圖為依據本揭露一些實施例之驅動電路在全域掃描期間中的發光期間的示意圖。 第4F圖為依據本揭露一些實施例之驅動電路在全域掃描期間中的發光期間的示意圖。 第5圖為依據本揭露一些實施例之驅動電路的電路架構圖。 第6圖為依據本揭露一些實施例之驅動電路的電路架構圖。 第7圖為依據本揭露一些實施例之驅動電路的電路架構圖。 第8圖為依據本揭露一些實施例之驅動電路的電路架構圖。 第9圖為依據本揭露一些實施例之驅動電路的電路架構圖。 In order to make the above and other objects, features, advantages and embodiments of the present disclosure more clearly understood, the accompanying drawings are described as follows: FIG. 1 is a functional block diagram of a driving circuit according to some embodiments of the present disclosure. FIG. 2 is a circuit structure diagram of a driving circuit according to some embodiments of the present disclosure. FIG. 3 is a timing diagram of the control signals of the driving circuit of FIG. 2 during the progressive scanning period and the global scanning period. FIG. 4A is a schematic diagram of a reset period of a driving circuit in a progressive scan period according to some embodiments of the present disclosure. FIG. 4B is a schematic diagram of a writing and compensation period in a progressive scan period of a driving circuit according to some embodiments of the present disclosure. FIG. 4C is a schematic diagram of the reset period of the driving circuit in the global scanning period according to some embodiments of the present disclosure. FIG. 4D is a schematic diagram of the writing and compensation periods in the global scanning period of the driving circuit according to some embodiments of the present disclosure. FIG. 4E is a schematic diagram of a light-emitting period of a driving circuit in a global scanning period according to some embodiments of the present disclosure. FIG. 4F is a schematic diagram of a light-emitting period in a global scanning period of a driving circuit according to some embodiments of the present disclosure. FIG. 5 is a circuit structure diagram of a driving circuit according to some embodiments of the present disclosure. FIG. 6 is a circuit structure diagram of a driving circuit according to some embodiments of the present disclosure. FIG. 7 is a circuit structure diagram of a driving circuit according to some embodiments of the present disclosure. FIG. 8 is a circuit structure diagram of a driving circuit according to some embodiments of the present disclosure. FIG. 9 is a circuit structure diagram of a driving circuit according to some embodiments of the present disclosure.
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無 Domestic storage information (please note in the order of storage institution, date and number) none Foreign deposit information (please note in the order of deposit country, institution, date and number) none
100:驅動電路 100: Drive circuit
112:第一重置電路 112: First reset circuit
114:第一寫入電路 114: The first write circuit
116:第一補償電路 116: The first compensation circuit
122:第二重置電路 122: Second reset circuit
124:第二寫入電路 124: Second write circuit
126:第二補償電路 126: Second compensation circuit
L1:發光元件 L1: Light-emitting element
T1:第一電晶體 T1: first transistor
T2:第二電晶體 T2: Second transistor
T3:第三電晶體 T3: The third transistor
T4:第四電晶體 T4: Fourth transistor
T5:第五電晶體 T5: Fifth transistor
T6:第六電晶體 T6: sixth transistor
T7:第七電晶體 T7: seventh transistor
T8:第八電晶體 T8: Eighth transistor
T9:第九電晶體 T9: ninth transistor
T10:第十電晶體 T10: Tenth transistor
T11:第十一電晶體 T11: Eleventh transistor
C1:第一電容 C1: first capacitor
C2:第二電容 C2: second capacitor
C3:第三電容 C3: the third capacitor
C4:第四電容 C4: Fourth capacitor
DATA1:第一資料訊號 DATA1: The first data signal
DATA2:第二資料訊號 DATA2: The second data signal
RG1:第一控制訊號 RG1: The first control signal
RG2(n):第二控制訊號 RG2(n): The second control signal
Spam:第三控制訊號 Spam: the third control signal
Spwm(n):第四控制訊號 Spwm(n): Fourth control signal
EM:第五控制訊號 EM: Fifth control signal
TCS:掃頻訊號 TCS: frequency sweep signal
OVDD:系統高電壓端 OVDD: system high voltage terminal
OVSS:系統低電壓端 OVSS: System Low Voltage Side
Data_H:第一參考電壓 Data_H: The first reference voltage
Data_L:第二參考電壓 Data_L: Second reference voltage
Claims (13)
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| TW110134223A TWI778788B (en) | 2021-09-14 | 2021-09-14 | Driving circuit |
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| TW110134223A TWI778788B (en) | 2021-09-14 | 2021-09-14 | Driving circuit |
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| TWI778788B true TWI778788B (en) | 2022-09-21 |
| TW202312123A TW202312123A (en) | 2023-03-16 |
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| TWI818761B (en) * | 2022-10-07 | 2023-10-11 | 友達光電股份有限公司 | Sweep voltage generator |
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