TWI776587B - Display data access method and control circuit, display and information processing device using the same - Google Patents

Display data access method and control circuit, display and information processing device using the same Download PDF

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TWI776587B
TWI776587B TW110125381A TW110125381A TWI776587B TW I776587 B TWI776587 B TW I776587B TW 110125381 A TW110125381 A TW 110125381A TW 110125381 A TW110125381 A TW 110125381A TW I776587 B TWI776587 B TW I776587B
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TW202242844A (en
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張海川
雍尚剛
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大陸商北京集創北方科技股份有限公司
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

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  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Communication Control (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

一種顯示資料存取方法，其包括：對接收到的N位元顯示資料進行一高位保留程序以產生一旗標位元值及保留N-m個高位位元的資料以產生共N-m+1個位元的位元縮減資料，並將其寫入以N-m+1個位元為儲存單位之一記憶體單元中，其中，m小於N， m、N均為大於1的整數；以及自該記憶體單元讀取所述位元縮減資料並依所述旗標位元值對所述位元縮減資料進行一位元擴充程序以產生N位元的輸出資料。A display data access method, comprising: performing a high-order reservation procedure on received N-bit display data to generate a flag bit value and reserving N-m high-order bits of data to generate a total of N-m+1 data bit-bit bit-reduced data, and writing it into a memory unit with N-m+1 bits as a storage unit, where m is less than N, and both m and N are integers greater than 1; and The memory unit reads the bit-reduced data and performs a one-bit expansion process on the bit-reduced data according to the flag bit value to generate N-bit output data.

Description

顯示資料存取方法及利用其之控制電路、顯示器和資訊處理裝置Display data access method and control circuit, display and information processing device using the same

本發明係有關顯示資料的存取技術，尤指一種可降低顯示資料儲存量的存取技術。The present invention relates to an access technology for display data, in particular to an access technology that can reduce the storage capacity of display data.

顯示記憶體是用來儲存顯示晶片處理過或者即將讀取的顯示資料以供一顯示器顯示一畫面。The display memory is used for storing the display data processed or about to be read by the display chip for a display to display a picture.

隨著顯示器的解析度的增加，顯示記憶體的使用量也跟著大幅增加而抬高了資訊產品，例如智慧型手機或攜帶型電腦的成本，從而為製造商的競爭力帶來新的挑戰。因此，如何在畫面品質與顯示記憶體使用量之間求取一個平衡點已是一迫切需要解決的問題。As the resolution of displays has increased, the use of display memory has also increased significantly, driving up the cost of information products such as smartphones or portable computers, creating new challenges for manufacturers' competitiveness. Therefore, how to obtain a balance point between the picture quality and the usage of the display memory is an urgent problem to be solved.

為解決上述的問題，本領域亟需一種新穎的顯示資料的存取技術。In order to solve the above problems, there is an urgent need in the art for a novel access technology for display data.

本發明之一目的在於提供一種顯示資料存取方法，其可藉由產生一旗標及保留主要的高位位元資料而減少記憶體的需求空間並降低顯示資料的恢復失真率，從而在畫面品質與顯示記憶體使用量之間獲得一個平衡點以提升顯示器的性價比。An object of the present invention is to provide a display data access method, which can reduce the required space of memory and reduce the recovery distortion rate of display data by generating a flag and retaining the main high-order bit data, thereby improving the picture quality. There is a balance between the amount of display memory and the display memory usage to improve the cost performance of the display.

本發明之另一目的在於提供一種控制電路，其可藉由產生一旗標及保留主要的高位位元資料而減少記憶體的需求空間並降低顯示資料的恢復失真率，從而在畫面品質與顯示記憶體使用量之間獲得一個平衡點以提升顯示器的性價比。Another object of the present invention is to provide a control circuit, which can reduce the required space of memory and reduce the recovery distortion rate of display data by generating a flag and retaining the main high-order bit data, thereby improving the picture quality and display. There is a balance between memory usage to improve the monitor's price/performance ratio.

本發明之另一目的在於提供一種顯示器，其可藉由在存取顯示資料時產生一旗標及保留主要的高位位元資料，而減少記憶體的需求空間並降低顯示資料的恢復失真率，從而在畫面品質與顯示記憶體使用量之間獲得一個平衡點以提升該顯示器的性價比。Another object of the present invention is to provide a display, which can reduce the required space of memory and reduce the recovery distortion rate of display data by generating a flag and retaining the main high-order bit data when accessing the display data, Thereby, a balance point is obtained between the picture quality and the amount of display memory used to improve the cost-effectiveness of the display.

本發明之又一目的在於提供一種資訊處理裝置，其可藉由在存取顯示資料時產生一旗標及保留主要的高位位元資料，而減少記憶體的需求空間並降低顯示資料的恢復失真率，從而在畫面品質與顯示記憶體使用量之間獲得一個平衡點以提升該資訊處理裝置的性價比。Another object of the present invention is to provide an information processing device, which can reduce the required space of memory and reduce the restoration distortion of display data by generating a flag when accessing display data and retaining the main high-order bit data rate, so as to obtain a balance point between the picture quality and the usage of the display memory, so as to improve the cost performance of the information processing device.

為達到前述之目的，一種顯示資料存取方法乃被提出，其包括：In order to achieve the aforementioned purpose, a display data access method is proposed, which includes:

對接收到的N位元顯示資料進行一高位保留程序以產生一旗標位元值及保留N-m個高位位元的資料以產生共N-m+1個位元的位元縮減資料，並將其寫入以N-m+1個位元為儲存單位之一記憶體單元中，其中，m小於N， m、N均為大於1的整數；以及Perform a high-order reservation process on the received N-bit display data to generate a flag bit value and reserve N-m high-order bits of data to generate a total of N-m+1 bits of bit-reduced data, and put It is written into a memory unit with N-m+1 bits as a storage unit, wherein m is less than N, and both m and N are integers greater than 1; and

自該記憶體單元讀取所述位元縮減資料並依所述旗標位元值對所述位元縮減資料進行一位元擴充程序以產生N位元的輸出資料。The bit-reduced data is read from the memory unit and a bit-expanding process is performed on the bit-reduced data according to the flag bit value to generate N-bit output data.

在一實施例中，該高位保留程序包括：判斷該顯示資料的最高的m個位元的數值是否為0，若是，則使該旗標位元值為0，並將該旗標位元值與該顯示資料的剩餘的N-m個位元值併接以寫入該記憶體單元中；以及若否，則使該旗標位元值為1，並將該旗標位元值與該顯示資料的最高的N-m個位元值併接以寫入該記憶體單元中。In one embodiment, the high bit reservation procedure includes: judging whether the value of the highest m bits of the display data is 0, if so, setting the flag bit value to 0, and setting the flag bit value to 0 write into the memory cell in parallel with the remaining N-m bit values of the display data; and if not, set the flag bit value to 1 and associate the flag bit value with the display data The highest N-m bit values of are concatenated to write into the memory cell.

在一實施例中，該位元擴充程序包括：判斷所述位元縮減資料的所述旗標位元值是否為0，若是，則使該輸出資料的較高的m個位元為0，並使該輸出資料的剩餘的N-m個位元等於所述位元縮減資料的剩餘的N-m個位元；以及若否，則使該輸出資料的較高的N-m個位元等於所述位元縮減資料的剩餘的N-m個位元，並使該輸出資料的最低的m個位元等於0。In one embodiment, the bit-expansion procedure includes: determining whether the flag bit value of the bit-reduced data is 0, and if so, setting the upper m bits of the output data to be 0, and make the remaining N-m bits of the output data equal to the remaining N-m bits of the bit-reduced data; and if not, make the upper N-m bits of the output data equal to the bit-reduced data the remaining N-m bits of data and make the lowest m bits of the output data equal to zero.

為達到前述之目的，本發明進一步提出一種控制電路，其具有一高位保留處理模組、一記憶體單元及一位元擴充模組以執行一顯示資料存取方法，該方法包括：In order to achieve the aforementioned object, the present invention further provides a control circuit, which has a high-order reserved processing module, a memory unit and a one-bit expansion module to execute a display data access method, the method comprising:

該高位保留處理模對接收到的N位元顯示資料進行一高位保留程序以產生一旗標位元值及保留N-m個高位位元的資料以產生共N-m+1個位元的位元縮減資料，並將其寫入以N-m+1個位元為儲存單位之該記憶體單元中，其中，m小於N， m、N均為大於1的整數；以及The high-order reservation processing module performs a high-order reservation process on the received N-bit display data to generate a flag bit value and reserves N-m high-order bits of data to generate a total of N-m+1 bits of bits. Reduce the data and write it into the memory unit with N-m+1 bits as the storage unit, where m is less than N, and both m and N are integers greater than 1; and

該位元擴充模組自該記憶體單元讀取所述位元縮減資料並依所述旗標位元值對所述位元縮減資料進行一位元擴充程序以產生N位元的輸出資料。The bit-expansion module reads the bit-reduced data from the memory unit and performs a one-bit expansion process on the bit-reduced data according to the flag bit value to generate N-bit output data.

在一實施例中，該高位保留程序包括：判斷該顯示資料的最高的m個位元的數值是否為0，若是，則使該旗標位元值為0，並將該旗標位元值與該顯示資料的剩餘的N-m個位元值併接以寫入該記憶體單元中；以及若否，則使該旗標位元值為1，並將該旗標位元值與該顯示資料的最高的N-m個位元值併接以寫入該記憶體單元中。In one embodiment, the high bit reservation procedure includes: judging whether the value of the highest m bits of the display data is 0, if so, setting the flag bit value to 0, and setting the flag bit value to 0 write into the memory cell in parallel with the remaining N-m bit values of the display data; and if not, set the flag bit value to 1 and associate the flag bit value with the display data The highest N-m bit values of are concatenated to write into the memory cell.

在一實施例中，該位元擴充程序包括：判斷所述位元縮減資料的所述旗標位元值是否為0，若是，則使該輸出資料的較高的m個位元為0，並使該輸出資料的剩餘的N-m個位元等於所述位元縮減資料的剩餘的N-m個位元；以及若否，則使該輸出資料的較高的N-m個位元等於所述位元縮減資料的剩餘的N-m個位元，並使該輸出資料的最低的m個位元等於0。In one embodiment, the bit-expansion procedure includes: determining whether the flag bit value of the bit-reduced data is 0, and if so, setting the upper m bits of the output data to be 0, and make the remaining N-m bits of the output data equal to the remaining N-m bits of the bit-reduced data; and if not, make the upper N-m bits of the output data equal to the bit-reduced data the remaining N-m bits of data and make the lowest m bits of the output data equal to zero.

為達到前述之目的，本發明進一步提出一種顯示器，其具有一畫素陣列及用以驅動該畫素陣列之一控制單元，其中，該控制單元包含一控制電路以執行一顯示資料存取方法，該方法包括：In order to achieve the aforementioned object, the present invention further provides a display having a pixel array and a control unit for driving the pixel array, wherein the control unit includes a control circuit for executing a display data access method, The method includes:

對接收到的N位元顯示資料進行一高位保留程序以產生一旗標位元值及保留N-m個高位位元的資料以產生共N-m+1個位元的位元縮減資料，並將其寫入以N-m+1個位元為儲存單位之一記憶體單元中，其中，m小於N， m、N均為大於1的整數；以及Perform a high-order reservation process on the received N-bit display data to generate a flag bit value and reserve N-m high-order bits of data to generate a total of N-m+1 bits of bit-reduced data, and put It is written into a memory unit with N-m+1 bits as a storage unit, wherein m is less than N, and both m and N are integers greater than 1; and

自該記憶體單元讀取所述位元縮減資料並依所述旗標位元值對所述位元縮減資料進行一位元擴充程序以產生N位元的輸出資料。在可能的實施例中，所述灰階調降處理可為一明、暗交替程序或一PWM 調光程序。The bit-reduced data is read from the memory unit and a bit-expanding process is performed on the bit-reduced data according to the flag bit value to generate N-bit output data. In a possible embodiment, the gray-scale downscaling process may be a bright/dark alternation procedure or a PWM dimming procedure.

在一實施例中，該高位保留程序包括：判斷該顯示資料的最高的m個位元的數值是否為0，若是，則使該旗標位元值為0，並將該旗標位元值與該顯示資料的剩餘的N-m個位元值併接以寫入該記憶體單元中；以及若否，則使該旗標位元值為1，並將該旗標位元值與該顯示資料的最高的N-m個位元值併接以寫入該記憶體單元中。In one embodiment, the high bit reservation procedure includes: judging whether the value of the highest m bits of the display data is 0, if so, setting the flag bit value to 0, and setting the flag bit value to 0 write into the memory cell in parallel with the remaining N-m bit values of the display data; and if not, set the flag bit value to 1 and associate the flag bit value with the display data The highest N-m bit values of are concatenated to write into the memory cell.

在一實施例中，該位元擴充程序包括：判斷所述位元縮減資料的所述旗標位元值是否為0，若是，則使該輸出資料的較高的m個位元為0，並使該輸出資料的剩餘的N-m個位元等於所述位元縮減資料的剩餘的N-m個位元；以及若否，則使該輸出資料的較高的N-m個位元等於所述位元縮減資料的剩餘的N-m個位元，並使該輸出資料的最低的m個位元等於0。In one embodiment, the bit-expansion procedure includes: determining whether the flag bit value of the bit-reduced data is 0, and if so, setting the upper m bits of the output data to be 0, and make the remaining N-m bits of the output data equal to the remaining N-m bits of the bit-reduced data; and if not, make the upper N-m bits of the output data equal to the bit-reduced data the remaining N-m bits of data and make the lowest m bits of the output data equal to zero.

在可能的實施例中，所述之顯示器可為一LED顯示器或一OLED顯示器。In a possible embodiment, the display can be an LED display or an OLED display.

為達到前述之目的，本發明進一步提出一種資訊處理裝置，其具有一中央處理單元及如前述之顯示器，其中，該中央處理單元係用以與該顯示器通信。In order to achieve the aforementioned object, the present invention further provides an information processing device, which has a central processing unit and the aforementioned display, wherein the central processing unit is used for communication with the display.

在可能的實施例中，該資訊處理裝置可為一攜帶型電腦或一智慧型手持裝置。In a possible embodiment, the information processing device may be a portable computer or a smart handheld device.

本發明之原理在於：The principle of the present invention is:

(一)在圖像顯示中， MSB(most significant bit；最高位元)的數值(0或1)佔有主要作用的地位，在一LED像素的顯示資料或一OLED像素的顯示資料達到一定灰階後，若只保留其中的高位，並不會特別影響圖像的顯示品質；(1) In the image display, the value (0 or 1) of MSB (most significant bit) plays a major role, and the display data of an LED pixel or the display data of an OLED pixel reaches a certain gray scale After that, if only the high bits are kept, it will not affect the display quality of the image;

(二)因此，本發明乃對接收到的N位元資料DATA[N-1:0]進行一高位保留程序以產生一旗標位元值及保留N-m個高位位元的資料，並利用一RAM_DATA[FL, N-m-1:0]共N-m+1個位元的記憶體予以儲存，其中，FL係用以儲存該旗標位元值，m小於N，且m、N均為大於1的整數。詳細而言，本發明係對接收到的N位資料DATA[N-1:0]的一高位組合DATA[N-1:N-m]進行判斷，若其值為0則將旗標位元FL設為0，並將DATA[N-m-1:0]寫入RAM_DATA[N-m-1:0] 中；以及若其值不為0則將旗標位元FL設為1，並將DATA[N-1: m]寫入RAM_DATA[N-m-1:0] 中；(2) Therefore, the present invention performs a high-order reservation procedure on the received N-bit data DATA[N-1:0] to generate a flag bit value and reserve N-m high-order bits of data, and utilizes a RAM_DATA[FL, N-m-1:0] is stored in a memory of N-m+1 bits in total, where FL is used to store the flag bit value, m is less than N, and both m and N are greater than An integer of 1. Specifically, the present invention judges a high-order combination DATA[N-1:N-m] of the received N-bit data DATA[N-1:0], and sets the flag bit FL if its value is 0 is 0, and DATA[N-m-1:0] is written into RAM_DATA[N-m-1:0]; and if its value is not 0, the flag bit FL is set to 1, and DATA[N-1 : m] is written into RAM_DATA[N-m-1:0];

(三)在以RD_DATA[N-1:0]共N位元的格式讀取該記憶體所儲存的資料時，若FL=0，則使RD_DATA[N-1:N-m] 為0，亦即使較高的m個位元為0，並使RD_DATA[N-m-1:0]，亦即較低的N-m個位元，等於RAM_DATA[N-m-1:0]；以及若FL=1，則使RD_DATA[N-1:m]，亦即較高的N-m個位元，等於RAM_DATA[N-m-1:0]，並使RD_DATA[m-1:0]，亦即較低的m個位元，等於0。(3) When reading the data stored in the memory in the format of RD_DATA[N-1:0] totaling N bits, if FL=0, set RD_DATA[N-1:N-m] to 0, that is, even if FL=0 The upper m bits are 0 and make RD_DATA[N-m-1:0], the lower N-m bits, equal to RAM_DATA[N-m-1:0]; and if FL=1, make RD_DATA [N-1:m], the upper N-m bits, equals RAM_DATA[N-m-1:0], and makes RD_DATA[m-1:0], the lower m bits, equal to 0.

依此，本發明即可節省存儲空間而有效降低製造成本。Accordingly, the present invention can save storage space and effectively reduce manufacturing cost.

請參照圖1，其繪示用以實現本發明之顯示資料存取方法之一控制電路之一實施例之方塊圖。如圖1所示，一控制電路100包括一高位保留處理模組110、一記憶體單元120及一位元擴充模組130。Please refer to FIG. 1 , which shows a block diagram of an embodiment of a control circuit for implementing the display data access method of the present invention. As shown in FIG. 1 , a control circuit 100 includes a high bit reservation processing module 110 , a memory unit 120 and a one-bit expansion module 130 .

高位保留處理模組110係用以對接收到的N位元顯示資料D DISP[N-1:0]進行一高位保留程序以產生一旗標位元值及保留N-m個高位位元的資料以產生位元縮減資料D REDUCED[N-m:0]，並藉由一寫入命令WR將該位元縮減資料D REDUCED[N-m:0]寫入以N-m+1個位元為儲存單位的記憶體單元120中，其中，m小於N， m、N均為大於1的整數，且該高位保留程序包括：判斷顯示資料D DISP[N-1:0]的最高的m個位元的數值是否為0，若是，則使該旗標位元值為0，並將該旗標位元值與顯示資料D DISP[N-1:0]的剩餘的N-m個位元值併接以寫入記憶體單元120中；若否，則使該旗標位元值為1，並將該旗標位元值與顯示資料D DISP[N-1:0]的最高的N-m個位元值併接以寫入記憶體單元120中。 The high-order reservation processing module 110 is used for performing a high-order reservation procedure on the received N-bit display data D DISP [N-1:0] to generate a flag bit value and reserve Nm high-order bits of data for Generate the bit-reduced data D REDUCED [Nm:0], and write the bit-reduced data D REDUCED [Nm:0] into the memory with N-m+1 bits as the storage unit by a write command WR In the body unit 120, where m is less than N, and both m and N are integers greater than 1, and the high-order reservation procedure includes: judging whether the value of the highest m bits of the display data D DISP [N-1:0] is If it is 0, if it is, set the flag bit value to 0, and write the flag bit value and the remaining Nm bit values of the display data D DISP [N-1:0] into memory. In the body unit 120; if not, the flag bit value is set to 1, and the flag bit value and the highest Nm bit value of the display data D DISP [N-1:0] are concatenated with written into the memory unit 120 .

位元擴充模組130係藉由一讀取命令RD自記憶體單元120讀取N-m+1位元的儲存資料D OUT1[N-m:0]並對其進行一位元擴充程序以產生N位元的輸出資料D OUT[N-1:0]，其中，該位元擴充程序包括：判斷儲存資料D OUT1[N-m:0]的所述旗標位元值是否為0，若是，則使輸出資料D OUT[N-1:0]的較高的m個位元為0，並使輸出資料D OUT[N-1:0]的剩餘的N-m個位元等於儲存資料D OUT1[N-m:0] 的剩餘的N-m個位元；以及若否，則使輸出資料D OUT[N-1:0]的較高的N-m個位元等於儲存資料D OUT1[N-m:0] 的剩餘的N-m個位元，並使輸出資料D OUT[N-1:0]的最低的m個位元等於0。 The bit expansion module 130 reads N-m+1 bits of storage data D OUT1 [Nm: 0] from the memory unit 120 through a read command RD and performs a bit expansion procedure on it to generate N Bit output data D OUT [N-1:0], wherein the bit expansion procedure includes: judging whether the flag bit value of the stored data D OUT1 [Nm:0] is 0, if so, use The upper m bits of the output data D OUT [N-1:0] are 0, and make the remaining Nm bits of the output data D OUT [N-1:0] equal to the stored data D OUT1 [Nm: 0] the remaining Nm bits of; and if not, make the upper Nm bits of the output data D OUT [N-1:0] equal to the remaining Nm bits of the storage data D OUT1 [Nm:0] bits and make the lowest m bits of the output data D OUT [N-1:0] equal to 0.

以N=16，m=3為例。在進行該高位保留程序時，高位保留處理模組110係先判斷顯示資料D DISP[15:0]的最高的3個位元的數值是否為0，若是，則使該旗標位元值為0，並將該旗標位元值與顯示資料D DISP[15:0]的剩餘的13個位元值併接以寫入記憶體單元120中；若否，則使該旗標位元值為1，並將該旗標位元值與顯示資料D DISP[15:0]的最高的13個位元值併接以寫入記憶體單元120中；以及在進行該位元擴充程序時，位元擴充模組130係先判斷儲存資料D OUT1[13:0]的所述旗標位元值是否為0，若是，則使輸出資料D OUT[15:0]的較高的3個位元為0，並使輸出資料D OUT[15:0]的剩餘的13個位元等於儲存資料D OUT1[13:0] 的剩餘的13個位元；以及若否，則使輸出資料D OUT[15:0]的較高的13個位元等於儲存資料D OUT1[13:0] 的剩餘的13個位元，並使輸出資料D OUT[15:0]的最低的3個位元等於0。 Take N=16, m=3 as an example. When performing the high-order reservation process, the high-order reservation processing module 110 first determines whether the value of the highest 3 bits of the display data D DISP [15:0] is 0, and if so, sets the value of the flag bit to be 0 0, and the flag bit value and the remaining 13 bit values of the display data D DISP [15:0] are connected to the memory unit 120 in parallel; if not, the flag bit value is set to is 1, and the flag bit value and the highest 13-bit value of the display data D DISP [15:0] are concatenated and written into the memory unit 120; and when the bit expansion process is performed, The bit expansion module 130 first determines whether the flag bit value of the stored data D OUT1 [13:0] is 0, and if so, outputs the upper 3 bits of the data D OUT1 [15:0] 0 and make the remaining 13 bits of the output data D OUT [15:0] equal to the remaining 13 bits of the stored data D OUT1 [13:0]; and if not, make the output data D OUT The upper 13 bits of [15:0] are equal to the remaining 13 bits of the storage data D OUT1 [13:0], and make the lowest 3 bits of the output data D OUT [15:0] equal to 0.

依上述的說明，本發明提出一種顯示資料存取方法。請參照圖2，其繪示本發明之顯示資料存取方法之一實施例之流程圖。如圖2所示，該方法包含：對接收到的N位元顯示資料進行一高位保留程序以產生一旗標位元值及保留N-m個高位位元的資料以產生共N-m+1個位元的位元縮減資料，並將其寫入以N-m+1個位元為儲存單位之一記憶體單元中，其中，m小於N， m、N均為大於1的整數，且該高位保留程序包括：判斷該顯示資料的最高的m個位元的數值是否為0，若是，則使該旗標位元值為0，並將該旗標位元值與該顯示資料的剩餘的N-m個位元值併接以寫入該記憶體單元中；若否，則使該旗標位元值為1，並將該旗標位元值與該顯示資料的最高的N-m個位元值併接以寫入該記憶體單元中(步驟a)；以及自該記憶體單元讀取所述位元縮減資料並對其進行一位元擴充程序以產生N位元的輸出資料，其中，該位元擴充程序包括：判斷所述位元縮減資料的所述旗標位元值是否為0，若是，則使該輸出資料的較高的m個位元為0，並使該輸出資料的剩餘的N-m個位元等於所述位元縮減資料的剩餘的N-m個位元；以及若否，則使該輸出資料的較高的N-m個位元等於所述位元縮減資料的剩餘的N-m個位元，並使該輸出資料的最低的m個位元等於0 (步驟b)。According to the above description, the present invention provides a display data access method. Please refer to FIG. 2 , which shows a flow chart of an embodiment of the display data access method of the present invention. As shown in FIG. 2, the method includes: performing a high-order reservation procedure on the received N-bit display data to generate a flag bit value and reserving N-m high-order bits of data to generate a total of N-m+1 data The bit-reduced data of the bits is written into a memory unit with N-m+1 bits as the storage unit, where m is less than N, m and N are both integers greater than 1, and the The high-order reservation procedure includes: judging whether the value of the highest m bits of the display data is 0; N-m bit values are written into the memory cell in parallel; if not, set the flag bit value to 1, and compare the flag bit value with the highest N-m bit value of the display data write into the memory unit in parallel (step a); and read the bit-reduced data from the memory unit and perform a one-bit expansion process on it to generate N-bit output data, wherein the The bit-expanding procedure includes: judging whether the flag bit value of the bit-reduced data is 0, and if so, making the upper m bits of the output data 0, and making the rest of the output data The N-m bits of the output data are equal to the remaining N-m bits of the bit-reduced data; and if not, make the upper N-m bits of the output data equal to the remaining N-m bits of the bit-reduced data and make the lowest m bits of the output data equal to 0 (step b).

依上述的位元縮減儲存方式，恢復出來的輸出資料的誤差率最大僅為0.0854%，對顯示器的顯示效果而言是完全可以接受的。According to the above-mentioned bit reduction storage method, the maximum error rate of the recovered output data is only 0.0854%, which is completely acceptable for the display effect of the monitor.

依上述的說明，本發明進一步提出一顯示器。請參照圖3，其繪示本發明之顯示器之一實施例之方塊圖。如圖3所示， 一顯示器200，可為一LED顯示器或一OLED顯示器，具有一控制單元210及一畫素陣列220，其中，控制單元210包含控制電路100以驅動畫素陣列220。According to the above description, the present invention further provides a display. Please refer to FIG. 3, which shows a block diagram of an embodiment of the display of the present invention. As shown in FIG. 3 , a display 200 , which can be an LED display or an OLED display, has a control unit 210 and a pixel array 220 , wherein the control unit 210 includes the control circuit 100 to drive the pixel array 220 .

另外，依上述的說明，本發明進一步提出一資訊處理裝置。請參照圖4，其繪示本發明之資訊處理裝置之一實施例的方塊圖。如圖4所示，一資訊處理裝置300具有一中央處理單元310及一顯示器320，其中，中央處理單元310係用以與顯示器320通信且顯示器320係由顯示器200實現。另外，資訊處理裝置300可為一攜帶型電腦或一智慧型手持裝置。In addition, according to the above description, the present invention further provides an information processing device. Please refer to FIG. 4 , which shows a block diagram of an embodiment of the information processing apparatus of the present invention. As shown in FIG. 4 , an information processing apparatus 300 has a central processing unit 310 and a display 320 , wherein the central processing unit 310 is used for communicating with the display 320 and the display 320 is realized by the display 200 . In addition, the information processing device 300 can be a portable computer or a smart handheld device.

依上述的說明可知，本發明可提供以下的優點：According to the above description, the present invention can provide the following advantages:

1. 本發明的顯示資料存取方法可藉由產生一旗標及保留主要的高位位元資料而減少記憶體的需求空間並降低顯示資料的恢復失真率，從而在畫面品質與顯示記憶體使用量之間獲得一個平衡點以提升顯示器的性價比。1. The display data access method of the present invention can reduce the required space of the memory and reduce the recovery distortion rate of the display data by generating a flag and retaining the main high-bit data, so as to be used in the image quality and display memory. A balance point is obtained between the amount to improve the cost performance of the display.

2.本發明的控制電路可藉由產生一旗標及保留主要的高位位元資料而減少記憶體的需求空間並降低顯示資料的恢復失真率，從而在畫面品質與顯示記憶體使用量之間獲得一個平衡點以提升顯示器的性價比。2. The control circuit of the present invention can reduce the required space of the memory and reduce the recovery distortion rate of the display data by generating a flag and retaining the main high-bit data, so as to be between the picture quality and the usage of the display memory. Get a balance to improve the monitor's price/performance ratio.

3.本發明的顯示器可藉由在存取顯示資料時產生一旗標及保留主要的高位位元資料，而減少記憶體的需求空間並降低顯示資料的恢復失真率，從而在畫面品質與顯示記憶體使用量之間獲得一個平衡點以提升該顯示器的性價比。3. The display of the present invention can reduce the required space of the memory and reduce the recovery distortion rate of the display data by generating a flag and retaining the main high-order bit data when accessing the display data, thereby improving the picture quality and display. There is a balance between memory usage to improve the price/performance ratio of this monitor.

4.本發明的資訊處理裝置可藉由在存取顯示資料時產生一旗標及保留主要的高位位元資料，而減少記憶體的需求空間並降低顯示資料的恢復失真率，從而在畫面品質與顯示記憶體使用量之間獲得一個平衡點以提升該資訊處理裝置的性價比。4. The information processing device of the present invention can reduce the required space of the memory and reduce the recovery distortion rate of the display data by generating a flag and retaining the main high-bit data when accessing the display data, thereby improving the picture quality. A balance is obtained between the usage of the display memory and the cost performance of the information processing device.

本發明所揭示者，乃較佳實施例之一種，舉凡局部之變更或修飾而源於本發明之技術思想而為熟習該項技藝知人所易於推知者，俱不脫本發明之專利權範疇。What is disclosed in the present invention is one of the preferred embodiments, and any partial changes or modifications originating from the technical idea of the present invention and easily inferred by those skilled in the art are within the scope of the patent right of the present invention.

綜上所陳，本案無論目的、手段與功效，皆顯示其迥異於習知技術，且其首先發明合於實用，確實符合發明之專利要件，懇請　貴審查委員明察，並早日賜予專利俾嘉惠社會，是為至禱。To sum up, regardless of the purpose, means and effect of this case, it shows that it is completely different from the conventional technology, and its first invention is suitable for practical use, and indeed meets the patent requirements of the invention. Society is to pray for the best.

100:控制電路 110:高位保留處理模組 120:記憶體單元 130:位元擴充模組 200:顯示器 210:控制單元 220:畫素陣列 300:資訊處理裝置 310:中央處理單元 320:顯示器 步驟a:對接收到的N位元顯示資料進行一高位保留程序以產生一旗標位元值及保留N-m個高位位元的資料以產生共N-m+1個位元的位元縮減資料，並將其寫入以N-m+1個位元為儲存單位之一記憶體單元中，其中，m小於N， m、N均為大於1的整數，且該高位保留程序包括：判斷該顯示資料的最高的m個位元的數值是否為0，若是，則使該旗標位元值為0，並將該旗標位元值與該顯示資料的剩餘的N-m個位元值併接以寫入該記憶體單元中；若否，則使該旗標位元值為1，並將該旗標位元值與該顯示資料的最高的N-m個位元值併接以寫入該記憶體單元中 步驟b:自該記憶體單元讀取所述位元縮減資料並對其進行一位元擴充程序以產生N位元的輸出資料，其中，該位元擴充程序包括：判斷所述位元縮減資料的所述旗標位元值是否為0，若是，則使該輸出資料的較高的m個位元為0，並使該輸出資料的剩餘的N-m個位元等於所述位元縮減資料的剩餘的N-m個位元；以及若否，則使該輸出資料的較高的N-m個位元等於所述位元縮減資料的剩餘的N-m個位元，並使該輸出資料的最低的m個位元等於0 100: Control circuit 110: High bit reservation processing module 120: memory unit 130:Bit expansion module 200: Monitor 210: Control Unit 220: pixel array 300: Information processing device 310: Central Processing Unit 320: Display Step a: perform a high-order reservation procedure on the received N-bit display data to generate a flag bit value and reserve N-m high-order bits of data to generate a total of N-m+1 bits of bit-reduced data , and write it into a memory unit with N-m+1 bits as the storage unit, wherein m is less than N, m and N are both integers greater than 1, and the high-order reservation procedure includes: judging the Whether the value of the highest m bits of the display data is 0, if so, set the flag bit value to 0, and concatenate the flag bit value with the remaining N-m bit values of the display data to write into the memory unit; if not, set the flag bit value to 1, and connect the flag bit value and the highest N-m bit values of the display data to write into the memory body unit Step b: Read the bit-reduced data from the memory unit and perform a one-bit expansion procedure on it to generate N-bit output data, wherein the bit-scale expansion procedure includes: judging the bit-reduced data Whether the value of the flag bit is 0, if so, make the upper m bits of the output data 0, and make the remaining N-m bits of the output data equal to the bit reduction data the remaining N-m bits; and if not, make the upper N-m bits of the output data equal to the remaining N-m bits of the bit-reduced data, and make the lowest m bits of the output data yuan equals 0

為進一步揭示本發明之具體技術內容，首先請參閱圖式，其中： 圖1繪示用以實現本發明之顯示資料存取方法之一控制電路之一實施例之方塊圖。 圖2繪示本發明之顯示資料存取方法之一實施例之流程圖。 圖3繪示本發明之顯示器之一實施例之方塊圖。 圖4繪示本發明之資訊處理裝置之一實施例之方塊圖。 In order to further disclose the specific technical content of the present invention, please refer to the drawings first, wherein: FIG. 1 is a block diagram illustrating an embodiment of a control circuit for implementing the display data access method of the present invention. FIG. 2 is a flow chart illustrating an embodiment of the display data access method of the present invention. FIG. 3 shows a block diagram of one embodiment of the display of the present invention. FIG. 4 is a block diagram illustrating an embodiment of the information processing apparatus of the present invention.

步驟a:對接收到的N位元顯示資料進行一高位保留程序以產生一旗標位元值及保留N-m個高位位元的資料以產生共N-m+1個位元的位元縮減資料，並將其寫入以N-m+1個位元為儲存單位之一記憶體單元中，其中，m小於N，m、N均為大於1的整數，且該高位保留程序包括：判斷該顯示資料的最高的m個位元的數值是否為0，若是，則使該旗標位元值為0，並將該旗標位元值與該顯示資料的剩餘的N-m個位元值併接以寫入該記憶體單元中；若否，則使該旗標位元值為1，並將該旗標位元值與該顯示資料的最高的N-m個位元值併接以寫入該記憶體單元中 Step a: perform a high-order reservation procedure on the received N-bit display data to generate a flag bit value and reserve N-m high-order bits of data to generate a total of N-m+1 bits of bit-reduced data , and write it into a memory unit with N-m+1 bits as the storage unit, wherein m is less than N, m and N are both integers greater than 1, and the high-order reservation procedure includes: judging the Whether the value of the highest m bits of the display data is 0, if so, set the flag bit value to 0, and concatenate the flag bit value with the remaining N-m bit values of the display data to write into the memory unit; if not, set the flag bit value to 1, and connect the flag bit value and the highest N-m bit values of the display data to write into the memory body unit

步驟b:自該記憶體單元讀取所述位元縮減資料並對其進行一位元擴充程序以產生N位元的輸出資料，其中，該位元擴充程序包括：判斷所述位元縮減資料的所述旗標位元值是否為0，若是，則使該輸出資料的較高的m個位元為0，並使該輸出資料的剩餘的N-m個位元等於所述位元縮減資料的剩餘的N-m個位元；以及若否，則使該輸出資料的較高的N-m個位元等於所述位元縮減資料的剩餘的N-m個位元，並使該輸出資料的最低的m個位元等於0 Step b: Read the bit-reduced data from the memory unit and perform a one-bit expansion procedure on it to generate N-bit output data, wherein the bit-scale expansion procedure includes: judging the bit-reduced data Whether the value of the flag bit is 0, if so, make the upper m bits of the output data 0, and make the remaining N-m bits of the output data equal to the bit reduction data the remaining N-m bits; and if not, make the upper N-m bits of the output data equal to the remaining N-m bits of the bit-reduced data, and make the lowest m bits of the output data yuan equals 0

Claims (12)

一種顯示資料存取方法，其包括：對接收到的N位元顯示資料進行一高位保留程序以產生一旗標位元值及保留N-m個高位位元的資料以產生共N-m+1個位元的位元縮減資料，並將其寫入以N-m+1個位元為儲存單位之一記憶體單元中，其中，m小於N，m、N均為大於1的整數；以及自該記憶體單元讀取所述位元縮減資料並依所述旗標位元值對所述位元縮減資料進行一位元擴充程序以產生N位元的輸出資料。 A display data access method, comprising: performing a high-order reservation procedure on received N-bit display data to generate a flag bit value and reserving N-m high-order bits of data to generate a total of N-m+1 data bit-bit bit-reduced data and writing it into a memory unit with N-m+1 bits as a storage unit, where m is less than N, and both m and N are integers greater than 1; and The memory unit reads the bit-reduced data and performs a one-bit expansion process on the bit-reduced data according to the flag bit value to generate N-bit output data. 如申請專利範圍第1項所述之顯示資料存取方法，其中，該高位保留程序包括：判斷該顯示資料的最高的m個位元的數值是否為0，若是，則使該旗標位元值為0，並將該旗標位元值與該顯示資料的剩餘的N-m個位元值併接以寫入該記憶體單元中；以及若否，則使該旗標位元值為1，並將該旗標位元值與該顯示資料的最高的N-m個位元值併接以寫入該記憶體單元中。 The display data access method described in claim 1, wherein the high-order reservation procedure includes: judging whether the value of the highest m bits of the display data is 0, and if so, setting the flag bit value 0, and write the flag bit value in parallel with the remaining N-m bit values of the display data into the memory cell; and if not, set the flag bit value to 1, and write the flag bit value and the highest N-m bit value of the display data into the memory unit in parallel. 如申請專利範圍第1項所述之顯示資料存取方法，其中，該位元擴充程序包括：判斷所述位元縮減資料的所述旗標位元值是否為0，若是，則使該輸出資料的較高的m個位元為0，並使該輸出資料的剩餘的N-m個位元等於所述位元縮減資料的剩餘的N-m個位元；以及若否，則使該輸出資料的較高的N-m個位元等於所述位元縮減資料的剩餘的N-m個位元，並使該輸出資料的最低的m個位元等於0。 The display data access method described in claim 1, wherein the bit expansion procedure comprises: judging whether the flag bit value of the bit reduction data is 0, and if so, enabling the output The upper m bits of the data are 0, and make the remaining N-m bits of the output data equal to the remaining N-m bits of the bit-reduced data; and if not, make the upper m bits of the output data equal. The upper N-m bits are equal to the remaining N-m bits of the bit-reduced data, and make the lowest m bits of the output data equal to zero. 一種控制電路，其具有一高位保留處理模組、一記憶體單元及一位元擴充模組以執行一顯示資料存取方法，該方法包括：該高位保留處理模組對接收到的N位元顯示資料進行一高位保留程序以產生一旗標位元值及保留N-m個高位位元的資料以產生共N-m+1個位元的位元縮減資料，並將其寫入以N-m+1個位元為儲存單位之該記憶體單元中，其中，m小於N，m、N均為大於1的整數；以及該位元擴充模組自該記憶體單元讀取所述位元縮減資料並依所述旗標位元值對所述位元縮減資料進行一位元擴充程序以產生N位元的輸出資料。 A control circuit, which has a high-order reservation processing module, a memory unit and a one-bit expansion module to execute a display data access method, the method comprises: the high-order reservation processing module responds to the received N bits The display data is subjected to a high-order reservation procedure to generate a flag bit value and the data of N-m high-order bits are reserved to generate a total of N-m+1 bits of bit-reduced data, and written to N-m +1 bits are the storage unit in the memory unit, wherein m is less than N, and both m and N are integers greater than 1; and the bit expansion module reads the bit reduction from the memory unit and performing a one-bit expansion process on the bit-reduced data according to the flag bit value to generate N-bit output data. 如申請專利範圍第4項所述之控制電路，其中，該高位保留程序包括：判斷該顯示資料的最高的m個位元的數值是否為0，若是，則使該旗標位元值為0，並將該旗標位元值與該顯示資料的剩餘的N-m個位元值併接以寫入該記憶體單元中；以及若否，則使該旗標位元值為1，並將該旗標位元值與該顯示資料的最高的N-m個位元值併接以寫入該記憶體單元中。The control circuit as described in item 4 of the claimed scope, wherein the high-order reservation procedure includes: judging whether the value of the highest m bits of the display data is 0, and if so, setting the flag bit to 0 , and write the flag bit value in parallel with the remaining N-m bit values of the display data into the memory cell; and if not, set the flag bit value to 1, and set the The flag bit value and the uppermost N-m bit values of the display data are written into the memory cell in parallel. 如申請專利範圍第4項所述之控制電路，其中，該位元擴充程序包括：判斷所述位元縮減資料的所述旗標位元值是否為0，若是，則使該輸出資料的較高的m個位元為0，並使該輸出資料的剩餘的N-m個位元等於所述位元縮減資料的剩餘的N-m個位元；以及若否，則使該輸出資料的較高的N-m個位元等於所述位元縮減資料的剩餘的N-m個位元，並使該輸出資料的最低的m個位元等於0。The control circuit according to claim 4, wherein the bit expansion procedure comprises: judging whether the value of the flag bit of the bit-reduced data is 0, and if so, making a comparison of the output data the upper m bits are 0, and make the remaining N-m bits of the output data equal to the remaining N-m bits of the bit-reduced data; and if not, make the upper N-m bits of the output data bits equals the remaining N-m bits of the bit-reduced data, and makes the lowest m bits of the output data equal to zero. 一種顯示器，其具有一畫素陣列及用以驅動該畫素陣列之一控制單元，其中，該控制單元包含一控制電路以執行一顯示資料存取方法，該方法包括： 對接收到的N位元顯示資料進行一高位保留程序以產生一旗標位元值及保留N-m個高位位元的資料以產生共N-m+1個位元的位元縮減資料，並將其寫入以N-m+1個位元為儲存單位之一記憶體單元中，其中，m小於N， m、N均為大於1的整數；以及 自該記憶體單元讀取所述位元縮減資料並依所述旗標位元值對所述位元縮減資料進行一位元擴充程序以產生N位元的輸出資料。 A display has a pixel array and a control unit for driving the pixel array, wherein the control unit includes a control circuit to execute a display data access method, the method comprising: Perform a high-order reservation process on the received N-bit display data to generate a flag bit value and reserve N-m high-order bits of data to generate a total of N-m+1 bits of bit-reduced data, and put It is written into a memory unit with N-m+1 bits as a storage unit, wherein m is less than N, and both m and N are integers greater than 1; and The bit-reduced data is read from the memory unit and a bit-expanding process is performed on the bit-reduced data according to the flag bit value to generate N-bit output data. 如申請專利範圍第7項所述之顯示器，其中，該高位保留程序包括：判斷該顯示資料的最高的m個位元的數值是否為0，若是，則使該旗標位元值為0，並將該旗標位元值與該顯示資料的剩餘的N-m個位元值併接以寫入該記憶體單元中；以及若否，則使該旗標位元值為1，並將該旗標位元值與該顯示資料的最高的N-m個位元值併接以寫入該記憶體單元中。The display according to item 7 of the claimed scope, wherein the high-order reservation procedure includes: judging whether the value of the highest m bits of the display data is 0, and if so, setting the flag bit to 0, and write the flag bit value in parallel with the remaining N-m bit values of the display data into the memory cell; and if not, set the flag bit value to 1 and set the flag bit value to 1 The scalar bit value and the uppermost N-m bit values of the display data are written into the memory cell in parallel. 如申請專利範圍第7項所述之顯示器，其中，該位元擴充程序包括：判斷所述位元縮減資料的所述旗標位元值是否為0，若是，則使該輸出資料的較高的m個位元為0，並使該輸出資料的剩餘的N-m個位元等於所述位元縮減資料的剩餘的N-m個位元；以及若否，則使該輸出資料的較高的N-m個位元等於所述位元縮減資料的剩餘的N-m個位元，並使該輸出資料的最低的m個位元等於0。The display according to claim 7, wherein the bit expansion procedure comprises: judging whether the flag bit value of the bit-reduced data is 0, and if so, setting a higher value of the output data The m bits of the output data are 0, and make the remaining N-m bits of the output data equal to the remaining N-m bits of the bit-reduced data; and if not, make the higher N-m bits of the output data Bits are equal to the remaining N-m bits of the bit-reduced data, and make the lowest m bits of the output data equal to zero. 如申請專利範圍第7項所述之顯示器，其係一LED顯示器或一OLED顯示器。The display according to item 7 of the patent application scope is an LED display or an OLED display. 一種資訊處理裝置，其具有一中央處理單元及如申請專利範圍第7至10項中任一項所述之顯示器，其中，該中央處理單元係用以與該顯示器通信。An information processing device has a central processing unit and the display according to any one of the claims 7 to 10, wherein the central processing unit is used for communication with the display. 如申請專利範圍第11項所述之資訊處理裝置，其係一攜帶型電腦或一智慧型手持裝置。The information processing device described in item 11 of the scope of the application is a portable computer or a smart handheld device.
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