TWI776456B - Method for processing rf signal and rf receiver - Google Patents
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Abstract
Description
本發明總體涉及delta-sigma(Δ-Σ) 類比數位轉換器(analog-to-digital converter,ADC)。The present invention generally relates to delta-sigma (delta-sigma) analog-to-digital converters (ADCs).
Delta-sigma(Δ-Σ)類比數位轉換器(analog-to-digital converter,ADC)使用積分器(integrator),諧振器(resonator)和反饋回路(feedback loop)來濾除低頻中的雜訊,以便增強訊號雜訊比(signal-to-noise ratio)。一些Δ-Σ ADC包括反饋回路中的數位類比轉換器(digital-to-analog converter,DAC)。Delta-sigma (delta-sigma) analog-to-digital converter (ADC) uses integrator (integrator), resonator (resonator) and feedback loop (feedback loop) to filter out low frequency noise, In order to enhance the signal-to-noise ratio (signal-to-noise ratio). Some delta-sigma ADCs include a digital-to-analog converter (DAC) in a feedback loop.
一些實施例涉及一種用於處理射頻(radio-frequency,RF)信號的方法。該方法包括:放大RF信號; 在RF域中利用Δ-Σ ADC對RF信號數位化,其中對所述RF信號數位化包括:用n階諧振帶通濾波器(resonant bandpass filter)對所述RF信號濾波,其中n> 1;在第i個奈奎斯特區域(ith Nyquist zone)對濾波後的RF信號進行採樣,其中i> 1;根據採樣後的信號,產生數位的同相(I)信號和正交(Q)信號。其中,n階諧振帶通濾波器對所述RF信號濾波可以是對放大後的RF信號進行濾波。Some embodiments relate to a method for processing radio-frequency (RF) signals. The method includes: amplifying an RF signal; digitizing the RF signal using a delta-sigma ADC in the RF domain, wherein digitizing the RF signal includes: digitizing the RF signal with an nth order resonant bandpass filter Signal filtering, where n >1; sample the filtered RF signal at the i th Nyquist zone, where i >1; generate a digital in-phase (I) from the sampled signal signal and quadrature (Q) signal. Wherein, filtering the RF signal by the n-order resonant bandpass filter may be filtering the amplified RF signal.
一些實施例涉及一種RF接收器,其包括低雜訊放大器(low noise amplifier,LNA),RF域的Δ-Σ ADC和電路。ADC包括:n階諧振帶通濾波器(其中n> 1),量化器,用於在第i個奈奎斯特區域對所述n階諧振帶通濾波器輸出的RF信號採樣,其中i> 1。該電路,與所述量化器的輸出端耦接,用於產生數位的同相(I)信號和正交(Q)信號,其中,所述電路集成在所述Δ-Σ類比數位轉換器中或者位於所述Δ-Σ類比數位轉換器之外;其中,所述電路可以是數位信號處理器(digital signal processor,DSP)。Some embodiments relate to an RF receiver including a low noise amplifier (LNA), a delta-sigma ADC and circuitry in the RF domain. The ADC includes: an n-order resonant band-pass filter (where n>1), a quantizer for sampling the RF signal output by the n-order resonant band-pass filter in the ith Nyquist region, where i> 1. the circuit, coupled to the output of the quantizer, for generating a digital in-phase (I) signal and a quadrature (Q) signal, wherein the circuit is integrated in the delta-sigma analog-to-digital converter or outside the delta-sigma analog-to-digital converter; wherein the circuit may be a digital signal processor (DSP).
一些實施例涉及一種RF接收器,其包括ADC,該ADC被配置為至少部分地通過以下方式在RF域中對RF信號數位化:利用n階諧振帶通濾波器對RF信號進行濾波,其中n> 1; 在第i個奈奎斯特區域對濾波後的RF信號進行採樣,其中i> 1; 根據採樣後的信號,產生數位的同相(I)信號和正交(Q)信號。Some embodiments relate to an RF receiver including an ADC configured to digitize an RF signal in the RF domain, at least in part, by filtering the RF signal with an n-order resonant bandpass filter, where n > 1; the filtered RF signal is sampled at the ith Nyquist zone, where i > 1; digital in-phase (I) and quadrature (Q) signals are generated from the sampled signal.
本發明實施例通過在RF域中對RF信號數位化,在數位域中產生同相信號和正交信號,可以使得RF接收器具有較好的抗噪性且具有較低的功耗。In the embodiment of the present invention, by digitizing the RF signal in the RF domain, and generating the in-phase signal and the quadrature signal in the digital domain, the RF receiver can have better noise immunity and lower power consumption.
前述發明內容是以說明的方式提供的,而不旨在限制本發明。The foregoing summary is provided by way of illustration, and is not intended to limit the invention.
發明人已經認識並理解,需要基於帶通ADC的緊湊,低功率,低雜訊的射頻RF接收器。與設計成首先將接收的RF信號轉換為基帶信號然後對基帶信號數位化的接收器相比,以帶通方式(直接在RF域中)對接收的RF信號數位化的接收器具有若干優點。例如,由於RF域數位化通常不涉及使用本地振盪器和混頻器,這些接收器明顯較小且功率效率較高。The inventors have recognized and understood that there is a need for a compact, low power, low noise radio frequency RF receiver based on a bandpass ADC. A receiver that digitizes the received RF signal in a bandpass fashion (directly in the RF domain) has several advantages over receivers that are designed to first convert the received RF signal to a baseband signal and then digitize the baseband signal. For example, these receivers are significantly smaller and more power efficient since RF domain digitization typically does not involve the use of local oscillators and mixers.
存在基於帶通ADC的RF接收器。然而,這些實施方式中的一些的雜訊太大和/或太耗電。由發明人開發的基於帶通ADC的RF接收器相比其他實施方式更能抵抗雜訊,實現例如超過95dB的圖像抑制比(image rejection ratio,IRR),並且表現出較低的功耗。這種基於帶通ADC的RF接收器利用以下技術中的一種或多種來增強抗噪性和降低功耗:(1)在數字域中生成同相(I)和正交(Q)路徑,(2)n階諧振帶通濾波,其中 n> 1,以及(3)在第i個奈奎斯特區域中的信號子採樣,其中 i>1。Bandpass ADC based RF receivers exist. However, some of these implementations are too noisy and/or too power-hungry. The bandpass ADC-based RF receiver developed by the inventors is more resistant to noise than other implementations, achieves image rejection ratios (IRRs) such as over 95dB, and exhibits lower power consumption. This bandpass ADC-based RF receiver utilizes one or more of the following techniques to enhance noise immunity and reduce power consumption: (1) generate in-phase (I) and quadrature (Q) paths in the digital domain, (2) ) resonant bandpass filtering of order n, where n > 1, and (3) subsampling of the signal in the ith Nyquist region, where i > 1.
在一些實施例中,在數位域中生成I路徑和Q路徑,例如使用數位信號處理器。與在類比域中生成I路徑和Q路徑的RF接收器相比,這些RF接收器表現出較高的IRR。這是因為由於製造公差(tolerance)和工藝-電壓-溫度(process-voltage-temperature,PVT)變化的影響,類比的同相I路徑和正交Q路徑容易同相/正交(IQ)失配(mismatch),因此,類比I路徑的一個或多個屬性(例如,增益,頻率,時間延遲,時鐘相位和時鐘幅度)與類比Q路徑的一個或多個屬性(例如,增益,頻率,時間延遲,時鐘相位和時鐘幅度)不同。In some embodiments, the I-path and Q-path are generated in the digital domain, eg, using a digital signal processor. These RF receivers exhibit higher IRR compared to RF receivers that generate I-path and Q-path in the analog domain. This is because the analog in-phase I path and quadrature Q path are prone to in-phase/quadrature (IQ) mismatches due to the effects of manufacturing tolerances (tolerance) and process-voltage-temperature (PVT) variations ), therefore, one or more properties of an analog I path (e.g., gain, frequency, time delay, clock phase, and clock amplitude) are compared to one or more properties of an analog Q path (e.g., gain, frequency, time delay, clock phase and clock amplitude) are different.
在一些實施例中,可以通過使用n> 1的n階諧振帶通濾波器來進一步增強IRR。這些類型的濾波器顯著的衰減了在RF接收器中不可避免產生的且不需要的圖像音調(tone)。In some embodiments, the IRR can be further enhanced by using an n-order resonant bandpass filter with n>1. These types of filters significantly attenuate unwanted image tones that are unavoidable in RF receivers.
在一些實施例中,在第i個奈奎斯特區(ith Nyquist zone)中對所接收的RF信號進行子採樣(sub-sample),其中i> 1。以這種方式對RF信號進行子採樣導致功耗的顯著降低和片上使用空間的顯著降低,因為它放寬了對信號進行採樣的頻率。In some embodiments, the received RF signal is sub-sampled in the i th Nyquist zone, where i>1. Subsampling the RF signal in this way results in a significant reduction in power consumption and a significant reduction in the space used on-chip because it relaxes the frequency at which the signal is sampled.
本文描述的RF接收器的類型被設計為在RF域中對接收的RF信號進行採樣,而不是首先將RF信號轉換為基帶信號。這樣,在一些實施例中,這些RF接收器可能沒有本地振盪器和/或可能沒有混頻器。為了比較,第1圖示出了基於基帶ADC的RF接收器,該RF接收器包括本地振盪器和一對混頻器。RF接收器100包括天線102,低雜訊放大器(low noise amplifier,LNA)103,本地振盪器(local oscillator,LO)104,混頻器106和108,基帶ADC 110和112以及數位信號處理器(digital signal processor,DSP)114。如圖所示,使用混頻器106和108將接收的信號與LO 104提供的音調混頻,以產生基帶類比I信號和基帶類比Q信號。使用基帶ADC 110對基帶類比I信號數位化,並且使用基帶ADC 112對基帶類比Q信號數位化。使用DSP 114進一步處理ADC的輸出。The type of RF receiver described herein is designed to sample the received RF signal in the RF domain, rather than first converting the RF signal to a baseband signal. As such, in some embodiments, these RF receivers may not have local oscillators and/or may not have mixers. For comparison, Figure 1 shows a baseband ADC based RF receiver that includes a local oscillator and a pair of mixers. The
由於製造公差(tolerance)和工藝-電壓-溫度(process-voltage-temperature,PVT)變化,基帶類比I信號傳播的路徑的一個或者多個特性可以與基帶類比Q信號傳播的路徑的相應特性不同。這個行為導致IRR的惡化。Due to manufacturing tolerances (tolerance) and process-voltage-temperature (PVT) variations, one or more characteristics of the path through which the baseband analog I signal propagates may differ from corresponding characteristics of the path through which the baseband analog Q signal propagates. This behavior leads to worsening of the IRR.
相比之下,第2圖的RF接收器被設計為在RF域中對接收的RF信號採樣,並且數位化(digitally)生成I信號和Q信號。RF接收器200包括接收節點202,LNA 204,ADC 206和DSP 208。例如,如果通信鏈路是無線的,接收節點202可以包括天線,或者,例如,如果通信鏈路是有線的,接收節點202可以包括其他類型的導電終端(terminal)。被設計為在RF域中數位化,在一些實施例中,RF接收器200可以沒有本地振盪器和/或混頻器,在其他實施例中RF接收器200可以包括本地振盪器和/或混頻器。In contrast, the RF receiver of Figure 2 is designed to sample the received RF signal in the RF domain and digitally generate the I and Q signals.
如下面將進一步詳細描述的,在一些實施例中,ADC206可以以Δ-ΣADC實施。這樣,ADC206可以被配置為對雜訊傳遞函數(noise transfer function)進行整形,使得低頻處的雜訊功率密度(noise power density)低於較高頻率處的雜訊功率密度。ADC206可以被設計以使得接收的信號落入雜訊功率密度較低的頻帶中。ADC206可以包括一個或多個低通濾波器或一個或多個帶通濾波器,用於根據需要對雜訊傳遞函數進行整形。As will be described in further detail below, in some embodiments ADC 206 may be implemented as a delta-sigma ADC. In this way, the ADC 206 can be configured to shape the noise transfer function such that the noise power density at low frequencies is lower than the noise power density at higher frequencies. The ADC 206 can be designed such that the received signal falls into a frequency band with lower noise power density. ADC 206 may include one or more low pass filters or one or more band pass filters for shaping the noise transfer function as desired.
在一些實施例中,LNA 204可以直接連接到ADC 206(除了導電路徑之外沒有其他元件在LNA 204和ADC 206之間)。具有直接連接可以增強正在被數位化的RF信號的訊號雜訊比(signal-to-noise ratio)。然而,並非所有實施例都需要在LNA 204和ADC 206之間具有直接連接,也就是說,LNA 204和ADC 206之間可以存在其他組件。In some embodiments, the LNA 204 may be directly connected to the ADC 206 (with no other elements between the
如第2圖所示,在ADC 206的下游,在數位域中生成I和Q信號。以這種方式,防止了當在模擬域中生成I和Q信號時(如第1圖中)可能出現的IQ失配。在一些實施例中,ADC 206可以被配置為提供n階諧振帶通濾波(具有n> 1)並且在具有i> 1的第i個奈奎斯特區域中對接收的信號進行子採樣。As shown in Figure 2, downstream of
第3圖示出根據一些實施例的ADC 206的一個非限制性實施方式。在該實施方式中,ADC206包括運算放大器(operational amplifier,OA)302和304,電阻器R1和R2,電容器C1和C2,諧振帶通濾波器(bandpass resonant filter)3101
和3102
,量化器312和DAC 314。應當理解的是,LNA 204可以配置為電壓放大器和/或電流放大器。在第3圖的示例中,LNA 204可以被配置為輸出放大的電流IRF
,其表示在接收節點202處接收的信號。例如,如圖所示,在一種實施方式中,電容器C1的一端耦接OA302的輸入,另一端耦接OA302的輸出,電阻器R1的一端耦接OA302的輸入,另一端耦接OA304的輸出,電容器C2的一端耦接OA304的輸入,另一端耦接OA304的輸出,電阻器R2的一端與電容器C1的另一端以及OA302的輸出耦接,電阻器R2的另一端與電容器C2的一端以及OA304的輸入耦接。諧振帶通濾波器3101
的輸入端與OA304的輸出耦接,諧振帶通濾波器3102
的輸入端與諧振帶通濾波器3101
的輸出端耦接,量化器312的輸入端與諧振帶通濾波器3102
的輸出端耦接,量化器312的輸出端與DSP208的輸入端耦接。Figure 3 illustrates one non-limiting implementation of ADC 206 in accordance with some embodiments. In this embodiment, ADC 206 includes operational amplifiers (OA) 302 and 304, resistors R1 and R2, capacitors C1 and C2, resonant bandpass filters 310 1 and 310 2 ,
在一些實施例中,運算放大器,電阻器和電容器可以共同配置作為跨阻放大器(transimpedance amplifier),從而將電流IRF
轉換為OA304的輸出處的電壓VRF
。在第3圖的例子中,通過連接在OA 302的輸入和OA 304的輸出之間的電阻器R1提供跨阻抗放大。此外,在一些實施例中,運算放大器,電阻器和電容器可以共同配置作為低通濾波器或者帶通濾波器(例如,諧振帶通濾波器)。在一個例子中,OA 302與電容器C1和電阻器R1形成積分器(integrator),並且OA 304與電容器C2和電阻器R2形成積分器。由於積分器串聯連接,因此電阻器R1提供的回饋是負反饋。第一個積分器在增益等於1的頻率處提供90度相移。使用兩個積分器串聯,增益在這樣的頻率下保持等於1,並且總相移為180度,導致積分器表現為諧振器。應注意的是,該電路僅在增益為單位(unitary)的頻率處呈現諧振。In some embodiments, the operational amplifier, resistor and capacitor may be configured together as a transimpedance amplifier, converting the current I RF to the voltage VRF at the output of the OA 304 . In the example of Figure 3, transimpedance amplification is provided by resistor R1 connected between the input of
在包括諧振帶通濾波器的一些實施例中,濾波器的品質因數(quality factor)可以是可調節的,例如通過使用一個或多個可控電阻器調節。In some embodiments including a resonant bandpass filter, the quality factor of the filter may be adjustable, eg, by using one or more controllable resistors.
應該理解的是,在其他實施例中可以使用除了第3圖的佈置之外的佈置。其他實施例,例如,可以包括一個運算放大器或兩個以上的運算放大器,和/或可以包括以不同方式佈置的電阻器和電容器。It should be understood that arrangements other than that of Figure 3 may be used in other embodiments. Other embodiments, for example, may include one operational amplifier or more than two operational amplifiers, and/or may include resistors and capacitors arranged in different ways.
在一些實施例中,ADC 206可以包括n階諧振帶通濾波器(其中n> 1)。發明人已經意識到,實施具有大於1的階數的諧振濾波器可以顯著增強ADC的IRR。N階諧振帶通濾波器可以以任何合適的方式實現,包括使用彼此串聯的多個諧振帶通濾波器。在第3圖中,例如,ADC206包括與諧振帶通濾波器3102
串聯的諧振帶通濾波器3101
。應當理解的是,ADC206不限於包括兩個諧振帶通濾波器310,因為也可以使用一個或兩個以上的諧振帶通濾波器。下面進一步詳細描述這種濾波器的示例性實施方式。In some embodiments,
在一些實施例中,ADC的第一濾波器(在從LNA到DSP的資料路徑中與LNA最近的濾波器)可以具有比後續濾波器大的動態範圍。因為ADC的回路增益降低了後續級的雜訊和其他損傷(impairment),所以相對於第一濾波器,可以放寬後續濾波器的動態範圍。本質上,第一諧振器的增益衰減了後續級的雜訊。這反過來簡化了濾波器3101 和3102 的設計。其中,在一些實施例中,ADC的第一濾波器可以是ADC中的第一個濾波器。In some embodiments, the first filter of the ADC (the filter closest to the LNA in the data path from the LNA to the DSP) may have a larger dynamic range than subsequent filters. Because the loop gain of the ADC reduces noise and other impairments in subsequent stages, the dynamic range of subsequent filters can be relaxed relative to the first filter. Essentially, the gain of the first resonator attenuates the noise of subsequent stages. This in turn simplifies the design of filters 310 1 and 310 2 . Wherein, in some embodiments, the first filter of the ADC may be the first filter in the ADC.
量化器312將接收的RF信號映射到一組預定義的離散值。量化器312對接收的RF信號進行採樣的頻率可以由時鐘clk的頻率決定(dicatate)。在一些實施例中,可以選擇時鐘clk的頻率fs,以便在第i個奈奎斯特區中對所接收的類比信號進行採樣,其中i> 1。這樣,ADC 206可以被配置為對RF信號進行子採樣。例如,採樣頻率fs可以小於fRF
,其中fRF
是在接收節點202處接收的RF信號的頻率。對接收的RF信號進行子採樣減少了ADC 206的總功耗。The
DSP 208接收ADC 206的輸出,並且作為回應,它產生I輸出(Iout)和Q輸出(Qout)。Iout和Qout可以相對於彼此異相π/2,或者更概括的說,異相±nπ/2,其中n是奇數。因為I輸出和Q輸出是數字化生成的,所以在一些實施例中,ADC 206可以包括單個資料路徑,而不是彼此正交的一對資料路徑。在一可選實施例中,DSP 208可以集成在ADC 206中。The
第4圖示出了根據一些實施例的ADC 206的示例性頻率相關的雜訊衰減回應。 在該例子中,假設接收的RF信號具有等於大約2GHz的載波頻率,然而其他值也是可能的,包括例如等於或大於1GHz的任何值。Figure 4 illustrates an exemplary frequency-dependent noise attenuation response of
在第4圖中,回應表現出量化雜訊阻帶(和輸入信號阻帶)401和量化雜訊阻帶(和輸入信號通帶)402。應當注意,由於使用了n階諧振帶通濾波器,量化雜訊阻帶401表現出尖銳的回應,該尖銳的回應具有大的滾降(roll-off),如上所述。量化雜訊阻帶401表現出具有-95dB雜訊衰減的下降(dip)。在一些實施例中,ADC 206被設計以使得圖像音調(tone)落入量化雜訊阻帶401內。在這樣的實施例中,ADC 206可以表現出95dB的IRR。In Figure 4, the response exhibits a quantization noise stopband (and input signal stopband) 401 and a quantization noise stopband (and input signal passband) 402. It should be noted that due to the use of an nth order resonant bandpass filter, the
DAC 314可以配置作為混頻器DAC。 這樣,DAC314可以接收具有特定頻率的信號,並且可以輸出具有較高頻率的信號。可以通過將提供給DAC的信號與參考信號混頻來執行上變換(up-conversion)。例如,在一些實施例中,DAC 314可以將量化器312的頻率輸出從2GHz到4GHz之間的值上變換到6GHz到12GHz之間的值。
第5圖示出根據一些實施例的諧振濾波器310的一個非限制性實施方式。在這種情況下,示出了三個諧振濾波器3101
,3102
和3103
。每個濾波器包括一對運算放大器,500Ω電阻器和160fF電容器,然而也可以使用其他電阻器和電容器。濾波器通過具有增長的電阻的成對的電阻器彼此耦接。 例如,濾波器3101
通過一對4000Ω電阻器耦接到濾波器3102
,而濾波器3102
通過一對6000Ω電阻器耦接到濾波器3103
。Figure 5 illustrates one non-limiting implementation of a resonant filter 310 in accordance with some embodiments. In this case, three resonant filters 310 1 , 310 2 and 310 3 are shown. Each filter consists of a pair of op amps, 500Ω resistors and 160fF capacitors, however other resistors and capacitors can be used. The filters are coupled to each other through pairs of resistors with increasing resistance. For example,
每個濾波器包括內反饋回路和外反饋回路。每個反饋回路包括耦接到量化器312的輸出的DAC。DAC1
,DAC3
和DAC5
分別是濾波器3101
,3102
和3103
的外反饋回路的一部分,並且連接到這些濾波器的輸入。 DAC2
,DAC4
和DAC6
分別是濾波器3101
,3102
和3103
的內反饋回路的一部分,並且連接到這些濾波器的相應的第二運算放大器。Each filter includes an inner feedback loop and an outer feedback loop. Each feedback loop includes a DAC coupled to the output of
在一些實施例中,DAC1 和DAC2 可以被設計為三電平(tri-level)的DAC,DAC3 ,DAC4 ,DAC5 和DAC6 可以被設計為雙電平(dual-level)的DAC。當接收的數位信號被解碼為雙電平格式時,DAC可以被配置為被時鐘信號的邊沿觸發,將電流從正輸出節點引導到負輸出節點或從負輸出節點引導到正輸出節點。相比之下,當接收的數位信號被解碼成三電平格式時,DAC可以被配置為被時鐘信號的邊沿觸發,將電流引導到正輸出節點或負輸出節點,或者傾瀉(dump)電流到浮動節點。當接收的數位信號被解碼為三電平格式時,可以配置附加的輸出開關將電流傾瀉(dump)到浮動節點,這降低了雜訊。In some embodiments, DAC 1 and DAC 2 may be designed as tri-level DACs, and DAC 3 , DAC 4 , DAC 5 and DAC 6 may be designed as dual-level DACs DAC. When the received digital signal is decoded into bi-level format, the DAC can be configured to be edge-triggered by the clock signal to direct current from the positive output node to the negative output node or vice versa. In contrast, when the received digital signal is decoded into a tri-level format, the DAC can be configured to be edge-triggered by the clock signal, direct current to the positive or negative output node, or dump current to floating node. When the received digital signal is decoded into tri-level format, additional output switches can be configured to dump current to the floating node, which reduces noise.
在一些實施例中,上述描述的運算放大器的任何一個,包括OA 302, OA 304和第5圖中的運算放大器,可以使用多路徑的運算放大器實現。在一些實施例中,多路徑運算放大器提供的高增益導致高諧振器品質因數。此外,或者可替換的,多路徑運算放大器提供的高增益為高採樣速率DAC提供良好的虛擬地(virtual ground)。In some embodiments, any of the operational amplifiers described above, including
第6圖中示出多路徑運算放大器的例子。多路徑運算放大器600形成具有差分運算放大器602,604和606的第一路徑和具有差分運算放大器602,608和610的第二路徑。多路徑運算放大器600包括具有電晶體T1,T2,T3和T4的輸出級。每對電晶體(包括T1和T3的第一對和包括T2和T4的第二對)可以被佈置作為反相器(inverter)。電容器C3, C4, C5, C6 和 C7可以具有任何適當的電容。Figure 6 shows an example of a multipath operational amplifier. Multipath
現有的RF接收器中I路徑和Q路徑是在類比域中產生的,所以現有的RF接收器易受IQ失配的影響,因此現有的RF接收器表現較高的IRR。本申請中,使用了具有n> 1的n階諧振帶通濾波器衰減了不想要的圖像音調。所以本申請的基於ADC的RF接收器展示出增強的抗噪性,實現例如超過95dB的IRR。The I path and the Q path in the existing RF receiver are generated in the analog domain, so the existing RF receiver is susceptible to IQ mismatch, so the existing RF receiver exhibits a higher IRR. In this application, an n-order resonant bandpass filter with n>1 is used to attenuate unwanted image tones. So the ADC-based RF receiver of the present application exhibits enhanced noise immunity, achieving, for example, an IRR in excess of 95 dB.
在請求項中使用諸如“第一”,“第二”,“第三”等的序數術語來修飾請求項元素本身並不意味著一個請求項元素相對另一個請求項元素的優先順序,或順序,或者執行方法的動作的時間順序,但僅用作標記以將具有特定名稱的一個請求項元素與具有相同名稱的另一個請求項元素區分,以區分請求項元素。The use of ordinal terms such as "first", "second", "third", etc. in a request item to modify a request item element does not by itself imply the priority, or order, of one request item element relative to another request item element , or the chronological order in which the actions of a method are performed, but only used as a marker to distinguish one request item element with a specific name from another request item element with the same name to distinguish request item elements.
此外,這裡使用的措辭和術語是出於描述的目的,而不應被視為限制。本文中“包括”,“包含”,“具有”,“含有”或“涉及”及其變化形式的使用旨在涵蓋其後列出的項目及其等同物以及其他項目。Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of "including," "including," "having," "containing," or "involving," and variations thereof herein, is intended to encompass the items listed thereafter and equivalents thereof, as well as other items.
“耦接”或“連接”的使用意味著指電路元件或信號彼此直接連接或通過中間元件間接連接。The use of "coupled" or "connected" means that circuit elements or signals are directly connected to each other or indirectly connected through intervening elements.
術語“大約”,“基本上”和“大致”可以用於表示在一些實施例中在目標值的±20%內,在一些實施例中在目標值的±10%內,在一些實施例中在目標值的±5%內,在一些實施例中在目標值的±2%內。術語“大約”,“基本上”和“大致”可以包括目標值。The terms "about", "substantially" and "approximately" may be used to mean within ±20% of the target value in some embodiments, within ±10% of the target value in some embodiments, in some embodiments Within ±5% of the target value, in some embodiments within ±2% of the target value. The terms "about", "substantially" and "approximately" can include target values.
100:RF接收器
102:天線
103:低雜訊放大器
104:本地振盪器
106,108:混頻器
110,112:基帶ADC
114:數位信號處理器
200:RF接收器
202:接收節點
204:低雜訊放大器
206:ADC
208:數位信號處理器
R1,R2:電阻器
C1,C2:電容器
304:運算放大器
3101
,3102
,3103
:諧振濾波器
312:量化器
314:DAC
600:多路徑運算放大器
602,604,606,608,610:差分運算放大器
T1,T2,T3,T4:電晶體
C3,C4,C5,C6,C7:電容器100: RF Receiver 102: Antenna 103: Low Noise Amplifier 104:
附圖不旨在按比例繪製。在附圖中,在各個圖中示出的每個相同或幾乎相同的部件由相同的數字表示。為清楚起見,並非每個部件都在每個圖中標記出。 第1圖是示出包括基帶ADC的RF接收器的框圖。 第2圖是根據一些實施例示出的包括帶通ADC的RF接收器的框圖。 第3圖是根據一些實施例示出的包括帶通Δ-Σ ADC的RF接收器的框圖。 第4圖是根據一些實施例示出的第3圖中接收器的頻率相關雜訊響應的示例的示意圖。 第5圖是根據一些實施例示出的與第3圖中接收器結合使用的諧振濾波器的框圖。 第6圖是根據一些實施例示出的與第3圖中接收器結合使用的運算放大器的電路圖。The drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component that is illustrated in various figures is represented by a like numeral. For clarity, not every component is labeled in every drawing. Figure 1 is a block diagram illustrating an RF receiver including a baseband ADC. Figure 2 is a block diagram of an RF receiver including a bandpass ADC shown in accordance with some embodiments. Figure 3 is a block diagram illustrating an RF receiver including a bandpass delta-sigma ADC, according to some embodiments. FIG. 4 is a schematic diagram illustrating an example of the frequency-dependent noise response of the receiver in FIG. 3, according to some embodiments. Figure 5 is a block diagram of a resonant filter for use with the receiver of Figure 3, shown in accordance with some embodiments. FIG. 6 is a circuit diagram of an operational amplifier used in conjunction with the receiver of FIG. 3, shown in accordance with some embodiments.
200:RF接收器 200: RF Receiver
202:接收節點 202: Receiving node
204:低雜訊放大器 204: Low Noise Amplifier
206:ADC 206: ADC
208:數位信號處理器 208: Digital Signal Processors
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Also Published As
Publication number | Publication date |
---|---|
US11196442B2 (en) | 2021-12-07 |
CN110875741A (en) | 2020-03-10 |
EP3618286A1 (en) | 2020-03-04 |
TWI727409B (en) | 2021-05-11 |
CN110875741B (en) | 2023-07-28 |
US10862504B2 (en) | 2020-12-08 |
US20200076448A1 (en) | 2020-03-05 |
US20210050863A1 (en) | 2021-02-18 |
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TW202010266A (en) | 2020-03-01 |
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