TWI772950B

TWI772950B - Meta-structure for semiconductor substrate and method for manufacturing thereof

Info

Publication number: TWI772950B
Application number: TW109138374A
Authority: TW
Inventors: 蘇文生
Original assignee: 長河企業有限公司
Priority date: 2020-11-04
Filing date: 2020-11-04
Publication date: 2022-08-01
Also published as: TW202220231A

Abstract

The invention related to a meta-structure for a semiconductor substrate and a method for manufacturing thereof. The substrate meta-structure comprises a substrate with a plurality of first micro structures and second micro structures formed on there. The substrate with the first micro structures and second micro structures is formed from a base material by the etched process. The epitaxy layer on the substrate will be flat by the area difference and symmetry arrangement of the first micro structures and second micro structures.

Description

半導體基板超穎結構及其製造方法Semiconductor substrate metastructure and manufacturing method thereof

本發明係有關一種半導體結構及其製造方法，尤其是一種半導體基板超穎結構及其製造方法。 The present invention relates to a semiconductor structure and a manufacturing method thereof, in particular to a semiconductor substrate metastructure and a manufacturing method thereof.

由於發光二極體(LED)具有體積小、使用壽命長以及反應快等優點，漸漸取代了以往的燈泡、日光燈管等傳統光源。然而，當應用於照明領域時，與螢光燈管相比，LED在發光效率上仍有改善空間，也因此各家廠商無不致力於發光效率的提升，以期能提供人們更好的發光元件。 Light-emitting diodes (LEDs) have gradually replaced traditional light sources such as light bulbs and fluorescent tubes due to their small size, long service life, and fast response. However, when used in the field of lighting, compared with fluorescent tubes, LEDs still have room for improvement in luminous efficiency. Therefore, various manufacturers are committed to improving the luminous efficiency in order to provide people with better light-emitting components. .

一般來說，市售白光LED均以藍光LED晶粒作為激發源，而藍光LED晶粒大都是以氮化鎵系列(如GaN、GaInN等)作為主要的發光材料，並將氮化鎵沉積於具有相同晶體結構的藍寶石基板(氮化鎵與藍寶石基板皆為六方晶型的晶體結構)上，以形成藍光LED晶粒。而為了能有效提高LED的發光效率，在現有的技術中，更在藍寶石基板上進行圖案化，藉由規則排列的圖案來增加內部量子效率(Internal Quantum Efficiency)與提高光萃取效率(Extraction Efficiency)，有效的增加LED的亮度。 In general, commercially available white LEDs use blue LED chips as the excitation source, while blue LED chips mostly use gallium nitride series (such as GaN, GaInN, etc.) as the main luminescent material, and gallium nitride is deposited on the On a sapphire substrate with the same crystal structure (both gallium nitride and sapphire substrate have a hexagonal crystal structure), blue LED chips are formed. In order to effectively improve the luminous efficiency of LEDs, in the prior art, patterning is performed on a sapphire substrate, and regular patterns are used to increase the internal quantum efficiency (Internal Quantum Efficiency) and improve the extraction efficiency (Extraction Efficiency) , effectively increase the brightness of the LED.

一般而言，關於磊晶之應力問體，針對發光二極體之磊晶結構在N型半導體層與發光層之間，會設置一層超晶格層(Super-lattice layer)，藉由超晶格層用以降低因晶格不匹配所產生之殘餘應力，可使得磊晶結構之界面差排缺陷的密度降低。由於超晶格層由多對(pairs)交互堆疊之兩種半導體材料層所構成。較常使用的材質例如是由氮化鋁鎵/氮化鎵(AlGaN/GaN)或者是由不同摻雜銦金屬比例的氮化銦鎵/氮化銦鎵(Inx1Ga1-x1N/Inx2Ga1-x2N)所組成。雖然超晶格層可降低應力累積以提升磊晶品質。 Generally speaking, regarding the epitaxial stress, for the epitaxial structure of the light-emitting diode, a super-lattice layer is provided between the N-type semiconductor layer and the light-emitting layer. The lattice layer is used to reduce the residual stress caused by lattice mismatch, which can make the interface of the epitaxial structure The density of dislocation defects is reduced. Since the superlattice layer is composed of two layers of semiconductor materials stacked alternately in pairs. The more commonly used materials are, for example, aluminum gallium nitride/gallium nitride (AlGaN/GaN) or indium gallium nitride/indium gallium nitride (Inx1Ga1-x1N/Inx2Ga1-x2N) with different indium metal ratios. composition. Although the superlattice layer can reduce the stress accumulation to improve the epitaxial quality.

然而，磊晶製程中所發生之缺陷問題，並非僅發生於N型半導體層與發光層之間，而是從緩衝層形成於基板上的製程開始，即開始需要注意差排缺陷，通常容易長成貫穿差排缺陷(threading dislocation densities,TDDs)，例如：刃差排、螺旋差排或混合差排。 However, the defect problem occurred in the epitaxial process is not only between the N-type semiconductor layer and the light-emitting layer, but starts from the process of forming the buffer layer on the substrate, that is, it is necessary to pay attention to the misalignment defects, which are usually easy to grow. Threading dislocation densities (TDDs), such as flute, helical, or mixed dislocations.

現今對於藍寶石基板的技術手段為另設置一層半導體層於藍寶石基板上，而形成一層超穎結構，但是為了形成此一層超穎結構需另外利用回火製程，使其固化於藍寶石基板上，因而導致另外藍寶石基板殘餘熱應力，縱使解決了磊晶所造成之缺陷問題卻另外衍生了熱應力問題，為此需拉長製程時間，或輔以其他技術手段消除熱應力。如此讓基板之生產製程甚為複雜。 The current technical means for the sapphire substrate is to provide another layer of semiconductor layer on the sapphire substrate to form a layer of metastructure, but in order to form this layer of metastructure, an additional tempering process is required to cure it on the sapphire substrate, resulting in In addition, the residual thermal stress of the sapphire substrate, even if the defect problem caused by epitaxial deposition is solved, the thermal stress problem is also derived. Therefore, it is necessary to lengthen the process time, or supplemented by other technical means to eliminate the thermal stress. This makes the production process of the substrate very complicated.

基於上述之問題，本發明提供一種半導體結構及其基板製造方法，其依據不同蝕刻圖案進行蝕刻，以讓基板上形成不同單位面積之超穎結構，並讓不同單位面積之超穎結構對稱排列，藉此不僅可消除應力問題，更可讓基板上之磊晶層平坦。 Based on the above-mentioned problems, the present invention provides a semiconductor structure and a method for manufacturing a substrate thereof, wherein etching is performed according to different etching patterns, so that metastructures with different unit areas are formed on the substrate, and the metastructures with different unit areas are symmetrically arranged, In this way, not only the stress problem can be eliminated, but also the epitaxial layer on the substrate can be made flat.

本發明之主要目的，提供一種半導體基板結構及其製造方法，其藉由不同蝕刻圖案之參照形成不同單位面積之超穎結構於基板上，以減少差排情況。 The main purpose of the present invention is to provide a semiconductor substrate structure and a manufacturing method thereof, which can form metastructures of different unit areas on the substrate by referring to different etching patterns, so as to reduce the misalignment.

本發明揭示了一種半導體基板結構之製造方法，其先提供一基材；爾後，在基材之上形成一光阻層，之後將複數個第一蝕刻圖案與複數個第二蝕刻圖案定義於光阻層上，其中，該些個第二蝕刻圖案位於該些個第一蝕刻圖案之周圍並對稱，且該些個第一蝕刻圖案之單位面積不同於該些個第二蝕刻圖案之單位面積；然後，依據該光阻層與該第一遮罩層以及該些個第一蝕刻圖案與該些個第二蝕刻圖案之排列進行蝕刻製程，以透過乾式蝕刻去除該光阻層並透過乾式蝕刻或濕式蝕刻而蝕刻該第一遮罩層而形成一基板，並使該基板之一表面上於一第一磊晶區域形成複數個第一超穎結構，同時使該基板之表面上於之一第二磊晶區域形成複數個第二超穎結構，該些個第一超穎結構之單位面積大於該些個第二超穎結構之單位面積，該些個第一超穎結構與該些個第二超穎結構對應於該些個第一蝕刻圖案與該些個第二蝕刻圖案之面積改變而形成漸變式結構。因此當磊晶層形成於本發明之基板上時，磊晶層即會順著該些個第一超穎結構與該些個第二超穎結構之排列向外推送磊晶缺陷。 The invention discloses a manufacturing method of a semiconductor substrate structure, which firstly provides a base material; then, a photoresist layer is formed on the base material, and then a plurality of first etching patterns and a plurality of second etching patterns are defined on the photoresist layer. on the resist layer, wherein the second etching patterns are located around the first etching patterns and are symmetrical, and the unit area of the first etching patterns is different from the unit area of the second etching patterns; Then, an etching process is performed according to the arrangement of the photoresist layer, the first mask layer and the first etching patterns and the second etching patterns to remove the photoresist layer by dry etching and dry etching or The first mask layer is etched by wet etching to form a substrate, and a plurality of first metastructures are formed on a surface of the substrate in a first epitaxial region, and at the same time, a surface of the substrate is formed on a The second epitaxial region forms a plurality of second metastructures, the unit areas of the first metastructures are larger than the unit areas of the second metastructures, the first metastructures and the first metastructures The second metastructure forms a graded structure corresponding to the area change of the first etching patterns and the second etching patterns. Therefore, when the epitaxial layer is formed on the substrate of the present invention, the epitaxial layer will push out epitaxial defects along the arrangement of the first metastructures and the second metastructures.

本發明提供一實施例，其在於依據該光阻層與該第一遮罩層進行蝕刻製程之步驟中，其先依據該光阻層及其該些個第一蝕刻圖案與該些個第二蝕刻圖案進行蝕刻，使該第一遮罩層形成複數個第一微結構與該些個第二微結構並對應於該基板之表面；然後，依據該些個第一微結構與該些個第二微結構進行蝕刻，以形成該基板並使該基板之表面依據該些個第一蝕刻圖案與該些個第二蝕刻圖案形成該些個第一超穎結構與該些個第二超穎結構。 The present invention provides an embodiment, which is in the step of performing the etching process according to the photoresist layer and the first mask layer, firstly according to the photoresist layer and the first etching patterns and the second etching patterns The etching pattern is etched, so that the first mask layer forms a plurality of first microstructures and the second microstructures corresponding to the surface of the substrate; then, according to the first microstructures and the first microstructures Two microstructures are etched to form the substrate and to form the first metastructures and the second metastructures on the surface of the substrate according to the first etching patterns and the second etching patterns .

本發明提供一實施例，其在於依據該光阻層及其該些個第一蝕刻圖案與該些個第二蝕刻圖案進行蝕刻之步驟前，進一步先形成一第二遮罩層於該光阻層上；然後依據該些個第一蝕刻圖案與該些個第二蝕刻圖案形成對應之複數個第三圖案與複數個第四圖案於該第二遮罩層上。 The present invention provides an embodiment of further forming a second mask layer on the photoresist before performing the etching according to the photoresist layer and the first etching patterns and the second etching patterns. layer; and then form a plurality of third patterns and a plurality of fourth patterns corresponding to the second mask layer on the second mask layer according to the first etching patterns and the second etching patterns.

本發明提供一實施例，其在於該乾式蝕刻為採用電漿對該些個第一微結構、該些個第二微結構與該基板之表面進行蝕刻。 An embodiment of the present invention is that the dry etching uses plasma to etch the first microstructures, the second microstructures and the surface of the substrate.

本發明提供一實施例，其在於進一步接續執行形成一氮化鎵磊晶層之一第一磊晶部於該第一磊晶區域上並形成該氮化鎵磊晶層之一第二磊晶部位於該第二磊晶區域上，該第一磊晶部之高度不同或相同於該第二磊晶部之高度。 The present invention provides an embodiment of further performing forming a first epitaxial portion of a gallium nitride epitaxial layer on the first epitaxial region and forming a second epitaxial portion of the gallium nitride epitaxial layer The portion is located on the second epitaxial region, and the height of the first epitaxial portion is different or the same as the height of the second epitaxial portion.

本發明另揭示了一種半導體基板結構，其包含一基板，其一表面具有一第一磊晶區域與一第二磊晶區域，該二第二磊晶區域接壤於該第一磊晶區域之周圍並對稱，該第一磊晶區域形成複數個第一超穎結構，該第二磊晶區域形成複數個第二超穎結構，該些個第一超穎結構之單位面積相同或不同於該些個第二超穎結構之單位面積，該些個第一超穎結構與該些個第二超穎結構形成漸變式結構。因此當磊晶層形成於本發明之基板上時，磊晶層即會順著該些個第一超穎結構與該些個第二超穎結構之排列向外推送磊晶缺陷。 The present invention further discloses a semiconductor substrate structure, which includes a substrate, a surface of which has a first epitaxial region and a second epitaxial region, and the two second epitaxial regions border around the first epitaxial region and symmetrical, the first epitaxial region forms a plurality of first metastructures, the second epitaxial region forms a plurality of second metastructures, and the unit areas of the first metastructures are the same or different from those of the first metastructures The unit area of the second metastructures, the first metastructures and the second metastructures form a gradient structure. Therefore, when the epitaxial layer is formed on the substrate of the present invention, the epitaxial layer will push out epitaxial defects along the arrangement of the first metastructures and the second metastructures.

本發明提供另一實施例，其在於該些個第一超穎結構與該些個第二超穎結構之高度差距為0.05至10微米。 The present invention provides another embodiment, wherein the height difference between the first metastructures and the second metastructures is 0.05 to 10 microns.

本發明提供另一實施例，其在於該基板上進一步設有一氮化鎵磊晶層，其形成於該基板與該些個第一超穎結構及該些個第二超穎結構之上，該氮化鎵磊晶層具有一第一磊晶部與一第二磊晶部，該第一磊晶部高於該第二磊晶部，該第一磊晶部之一上表面呈一平坦面，該些個第二超穎結構之頂端穿透該第二磊晶部之一上表面。 The present invention provides another embodiment, which is that a gallium nitride epitaxial layer is further provided on the substrate, which is formed on the substrate, the first metastructures and the second metastructures, the The gallium nitride epitaxial layer has a first epitaxial portion and a second epitaxial portion, the first epitaxial portion is higher than the second epitaxial portion, and an upper surface of the first epitaxial portion is a flat surface , the tops of the second metastructures penetrate an upper surface of the second epitaxial portion.

10:基材 10: Substrate

10S:上表面 10S: Top surface

102:第一超穎結構 102: The first metastructure

104:第二超穎結構 104: Second metastructure

10A:基板 10A: Substrate

12:第一遮罩層 12: The first mask layer

122:第一微結構 122: First Microstructure

124:第二微結構 124: Second Microstructure

14:光阻層 14: photoresist layer

142:第一蝕刻圖案 142: First etching pattern

142A:第一蝕刻柱 142A: First etch pillar

144:第二蝕刻圖案 144: Second etching pattern

144A:第二蝕刻柱 144A: Second etch pillar

16:第二遮罩層 16: Second mask layer

162:第三蝕刻圖案 162: Third etching pattern

162A:第三蝕刻柱 162A: Third etched pillar

164:第四蝕刻圖案 164: Fourth etching pattern

164A:第四蝕刻柱 164A: Fourth etched pillar

20:氮化鎵磊晶層 20: GaN epitaxial layer

202:第一磊晶部 202: The first epitaxy department

204:第二磊晶部 204: The second epitaxy department

30:基材 30: Substrate

30A:基板 30A: Substrate

302:第一超穎結構 302: The first metastructure

304:第二超穎結構 304: Second metastructure

40:氮化鎵磊晶層 40: GaN epitaxial layer

402:第一磊晶部 402: The first epitaxy department

404:第二磊晶部 404: Second Epitaxy Department

D1:第一間隔 D1: first interval

A1:第一單位面積 A1: The first unit area

A2:第二單位面積 A2: The second unit area

A3:第三單位面積 A3: The third unit area

D2:第二間隔 D2: Second interval

D3:第三間隔 D3: Third interval

E1:第一磊晶區域 E1: The first epitaxial region

E2:第二磊晶區域 E2: The second epitaxial region

S10-S60:步驟 S10-S60: Steps

S52:步驟 S52: Step

S54:步驟 S54: Step

S110-S155:步驟 S110-S155: Steps

S210-S253:步驟 S210-S253: Steps

S310-S350:步驟 S310-S350: Steps

第一A圖：其為本發明之一實施例之製造基板之流程圖。 Figure 1 A: It is a flow chart of manufacturing a substrate according to an embodiment of the present invention.

第一B圖：其為本發明之一實施例之蝕刻製程之流程圖。 Figure 1 B: It is a flow chart of an etching process according to an embodiment of the present invention.

第二A圖至第二F圖：其為本發明之一實施例之部分流程示意圖。 Second Figure A to Second Figure F: These are schematic diagrams of part of the flow of an embodiment of the present invention.

第三圖：其為本發明之一實施例之半導體結構形成之流程圖。 Figure 3: It is a flow chart of forming a semiconductor structure according to an embodiment of the present invention.

第四圖：其為本發明之一實施例之半導體結構形成之示意圖。 Figure 4: It is a schematic diagram of the formation of a semiconductor structure according to an embodiment of the present invention.

第五圖：其為本發明之一實施例之半導體結構形成之示意圖。 Figure 5: It is a schematic diagram of the formation of a semiconductor structure according to an embodiment of the present invention.

第六A圖：其為本發明之另一實施例之製造基板之流程圖。 Sixth Figure A: It is a flow chart of manufacturing a substrate according to another embodiment of the present invention.

第六B圖：其為本發明之另一實施例之蝕刻製程之流程圖。 Sixth Figure B: It is a flow chart of an etching process according to another embodiment of the present invention.

第七A圖至第七I圖：其為本發明之另一實施例之部分流程示意圖。 Fig. 7A to Fig. 7I: they are partial flow diagrams of another embodiment of the present invention.

第八A圖至第八B圖：其為本發明之蝕刻圖案之示意圖。 Eighth Figure A to Eighth Figure B: These are schematic diagrams of the etching pattern of the present invention.

第九A圖：其為本發明之另一實施例之製造基板之流程圖。 Figure 9A: It is a flow chart of manufacturing a substrate according to another embodiment of the present invention.

第九B圖：其為本發明之另一實施例之蝕刻製程之流程圖。 Figure 9 B: It is a flow chart of an etching process according to another embodiment of the present invention.

第十A圖至第十G圖：其為本發明之另一實施例之部分流程示意圖。 Figures 10A to 10G: they are partial flow diagrams of another embodiment of the present invention.

第十一圖：其為本發明之另一實施例之製造基板之流程圖。 Figure 11: It is a flow chart of manufacturing a substrate according to another embodiment of the present invention.

第十二A圖至第十二D圖：其為本發明之另一實施例之部分流程示意圖。 The twelfth A to the twelfth D: they are partial flow diagrams of another embodiment of the present invention.

第十三A圖至第十三B圖：其為本發明之基板之俯視圖一與俯視圖二。 Figures 13A to 13B: These are the top views 1 and 2 of the substrate of the present invention.

為使貴審查委員對本發明之特徵及所達成之功效有更進一步之瞭解與認識，謹佐以實施例及配合說明，說明如後： In order to make your examiners have a further understanding and understanding of the features of the present invention and the effects achieved, I would like to add examples and explanations, and the explanations are as follows:

有鑑於半導體結構缺陷呈現於主要磊晶區域，據此，本發明遂提出一種半導體基板結構及其製造方法，以解決習知磊晶技術所造成之缺陷呈現在主要磊晶區域之問題。 Considering that the defects of the semiconductor structure appear in the main epitaxial region, the present invention proposes a semiconductor substrate structure and a manufacturing method thereof to solve the problem of defects in the main epitaxial region caused by the conventional epitaxial technology.

以下，將進一步說明本發明揭示一種半導體基板結構所包含之特性、所搭配之結構：首先，請參閱第一A圖，其為本發明之一實施例之製造基板之流程圖。如圖所示，本發明之半導體基板結構之製造方法的步驟包含：步驟S10：提供基材；步驟S20：形成第一遮罩層於基材上；步驟S30：形成光阻層於第一遮罩層上；步驟S40：定義第一蝕刻圖案與第二蝕刻圖案於光阻層上；以及步驟S50：依據光阻層與第一遮罩層以及第一蝕刻圖案與第二蝕刻圖案之排列進行蝕刻製程，以蝕刻光阻層與第一遮罩層而形成基板。 Hereinafter, the characteristics and matching structures of a semiconductor substrate structure disclosed by the present invention will be further described. First, please refer to FIG. 1 A, which is a flowchart of manufacturing a substrate according to an embodiment of the present invention. As shown in the figure, the steps of the manufacturing method of the semiconductor substrate structure of the present invention include: step S10: providing a substrate; step S20: forming a first mask layer on the substrate; step S30: forming a photoresist layer on the first mask on the mask layer; step S40: defining the first etching pattern and the second etching pattern on the photoresist layer; and step S50: performing according to the arrangement of the photoresist layer and the first mask layer and the first etching pattern and the second etching pattern In the etching process, the photoresist layer and the first mask layer are etched to form a substrate.

於步驟S10中，如第二A圖所示，提供一欲作為基板10A之一基材10，例如：藍寶石基材、矽基材、碳化矽；於步驟S20中，如第二B圖所示，形成一第一遮罩層12於該基材10上，例如：氧化矽、氧化鈦；於步驟S30中，如第二C圖所示，一般為採用樹脂材料作為光阻材料，而形成一光阻層14於該第一遮罩層12上，並可透過紫外光固化或熱固化或電子束固化；於步驟S40中，如第二D圖所示，在該光阻層14上定義了一第一蝕刻圖案142與一第二蝕刻圖案144，且該第一蝕刻圖案142與該第二蝕刻圖案144所構成之間隔自中央向外縮減，也就是一第一間隔D1、一第二間隔D2至一第三間隔D3持續縮減。 In step S10, as shown in Figure 2 A, a substrate 10 to be used as a substrate 10A is provided, such as a sapphire substrate, a silicon substrate, and silicon carbide; in step S20, as shown in Figure 2 B , forming a first mask layer 12 on the substrate 10, such as silicon oxide, titanium oxide; in step S30, as shown in the second figure C, generally a resin material is used as a photoresist material to form a The photoresist layer 14 is on the first mask layer 12, and can be cured by ultraviolet light, thermal curing, or electron beam curing; in step S40, as shown in the second diagram D, the photoresist layer 14 is defined A first etching pattern 142 and a second etching pattern 144, and the interval formed by the first etching pattern 142 and the second etching pattern 144 decreases from the center to the outside, that is, a first interval D1, a second interval D2 to a third interval D3 continues to decrease.

於步驟S50中，利用蝕刻製程蝕刻掉該光阻層14與該第一遮罩層12，以形成一基板10A，並請進一步參閱第一B圖，其為本發明之一實施例之蝕刻製程之流程圖，其中步驟S50中進一步包含步驟如下：步驟S52：依據光阻層及其第一蝕刻圖案與第二蝕刻圖案進行乾式蝕刻，使第一遮罩層形成第一微結構與第二微結構並對應於基板之表面；以及步驟S54：依據第一微結構與第二微結構進行蝕刻，以形成基板並使基板之表面依據第一微結構與第二微結構形成第一超穎結構與第二超穎結構。 In step S50, the photoresist layer 14 and the first mask layer 12 are etched away by an etching process to form a substrate 10A, and please refer to the first figure B, which is an etching process of an embodiment of the present invention The flow chart of the flow chart, wherein step S50 further includes the following steps: step S52: dry etching is performed according to the photoresist layer and its first etching pattern and second etching pattern, so that the first mask layer is formed into a first microstructure and a second microstructure structure and corresponds to the surface of the substrate; and Step S54: Etching is performed according to the first microstructure and the second microstructure to form a substrate, and the surface of the substrate forms a first metastructure and a second metastructure according to the first microstructure and the second microstructure.

於步驟S52中，如第二E圖所示，依據前步驟S40所定義該第一蝕刻圖案142與該第二蝕刻圖案144以及該光阻層14而一併蝕刻該光阻層14與該第一遮罩層12，因而讓該第一遮罩層12形成複數個第一微結構122與複數個第二微結構124。於步驟S54中，如第二F圖所示，藉由乾式蝕刻或是濕式蝕刻，依據步驟S52所形成之該第一微結構122與該第二微結構124，將該基材10蝕刻成該基板10A，且該基板10A之上表面10S對應形成一第一超穎結構102與一第二超穎結構104，由於該第一蝕刻圖案142與該第二蝕刻圖案144構成不同單位面積以及不同間隔，且該第一微結構122與該第二微結構124之排列對應於該第一蝕刻圖案142與該第二蝕刻圖案144之排列與單位面積，因此該第一超穎結構102與該第二超穎結構104對應於該第一微結構122與該第二微結構124之排列而自中央向外呈現排列間隔改變或單位面積改變，本實施例為舉例排列間隔由大到小構成第一間隔D1、第二間隔D2、第三間隔D3，且，該些個第一超穎結構102之單位面積不同於該些個第二超穎結構104之單位面積，以及該些個第一超穎結構102之尺寸不同於該些個第二超穎結構104之尺寸，例如：該些個第一超穎結構102與該些個第二超穎結構104之高度差距為0.05至10微米。 In step S52, as shown in the second figure E, the photoresist layer 14 and the photoresist layer 14 are etched together according to the first etching pattern 142, the second etching pattern 144 and the photoresist layer 14 defined in the previous step S40. A mask layer 12 , so that the first mask layer 12 forms a plurality of first microstructures 122 and a plurality of second microstructures 124 . In step S54, as shown in FIG. 2 F, by dry etching or wet etching, the substrate 10 is etched according to the first microstructure 122 and the second microstructure 124 formed in step S52. The substrate 10A, and the upper surface 10S of the substrate 10A respectively form a first metastructure 102 and a second metastructure 104, because the first etching pattern 142 and the second etching pattern 144 form different unit areas and different interval, and the arrangement of the first microstructure 122 and the second microstructure 124 corresponds to the arrangement and unit area of the first etching pattern 142 and the second etching pattern 144, so the first metastructure 102 and the second The two metastructures 104 correspond to the arrangement of the first microstructures 122 and the second microstructures 124 and exhibit a change in arrangement interval or a change in unit area from the center to the outside. In this embodiment, the arrangement interval from large to small constitutes the first The interval D1, the second interval D2, the third interval D3, and the unit areas of the first metastructures 102 are different from the unit areas of the second metastructures 104, and the first metastructures The dimensions of the structures 102 are different from those of the second metastructures 104 , for example, the height difference between the first metastructures 102 and the second metastructures 104 is 0.05 to 10 μm.

請一併參閱第三圖與第四圖，其為本發明之一實施例之半導體結構形成之流程圖及示意圖。如第三圖所示，其為第一圖之步驟S10至步驟S50進一步包含形成磊晶層之步驟S60，因此步驟S10至步驟S50不再贅述。本發明之半導體基板結構之製造方法於完成後，更進一步包含：步驟S60：形成氮化鎵磊晶層之第一磊晶部於第一磊晶區域上並形成氮化鎵磊晶層之第二磊晶部位於第二磊晶區域上。 Please refer to FIG. 3 and FIG. 4 together, which are flowcharts and schematic diagrams of forming a semiconductor structure according to an embodiment of the present invention. As shown in the third figure, the steps S10 to S50 in the first figure further include the step S60 of forming an epitaxial layer, so the steps S10 to S50 will not be repeated. After the manufacturing method of the semiconductor substrate structure of the present invention is completed, it further comprises: Step S60 : forming a first epitaxial portion of the gallium nitride epitaxial layer on the first epitaxial region and forming a second epitaxial portion of the gallium nitride epitaxial layer on the second epitaxial region.

於步驟S60中，如第四圖所示，基板10A之上表面上定義成一第一磊晶區域E1與一第二磊晶區域E2，該第一磊晶區域E1即該第一超穎結構102之設置區域，該第二磊晶區域E2即該第二超穎結構104之設置區域，而一氮化鎵磊晶層20之一第一磊晶部202形成於該第一磊晶區域E1，該氮化鎵磊晶層20之一第二磊晶部204形成於該第二磊晶區域E2，其中該第一磊晶部202之上表面為平坦面，該第二超穎結構104之頂端為穿過該第二磊晶部204之上表面。 In step S60 , as shown in FIG. 4 , a first epitaxial region E1 and a second epitaxial region E2 are defined on the upper surface of the substrate 10A, and the first epitaxial region E1 is the first superstructure 102 The second epitaxial region E2 is the setting region of the second superstructure 104, and a first epitaxial portion 202 of a gallium nitride epitaxial layer 20 is formed in the first epitaxial region E1, A second epitaxial portion 204 of the GaN epitaxial layer 20 is formed in the second epitaxial region E2, wherein the upper surface of the first epitaxial portion 202 is a flat surface, and the top of the second metastructure 104 to pass through the upper surface of the second epitaxial portion 204 .

如第五圖所示，其揭示本發明之另一實施例之基材30及其一第一超穎結構302與一第二超穎結構304，且一氮化鎵磊晶層40之一第一磊晶部402形成於第一磊晶區域E1，該氮化鎵磊晶層40之一第二磊晶部404形成於第二磊晶區域E2，其中該第一磊晶部402之上表面為平坦面，該第二超穎結構304之頂端為穿過該第二磊晶部404之上表面，該第一超穎結構302與該第二超穎結構304進一步呈現錐狀。 As shown in FIG. 5 , it discloses a substrate 30 , a first metastructure 302 and a second metastructure 304 of another embodiment of the present invention, and a first metastructure 304 of a gallium nitride epitaxial layer 40 . An epitaxial portion 402 is formed in the first epitaxial region E1, and a second epitaxial portion 404 of the gallium nitride epitaxial layer 40 is formed in the second epitaxial region E2, wherein the upper surface of the first epitaxial portion 402 Being a flat surface, the top of the second metastructure 304 passes through the upper surface of the second epitaxial portion 404 , and the first metastructure 302 and the second metastructure 304 are further tapered.

請參閱第六A圖，其為本發明之一實施例之製造基板之流程圖。如圖所示，本發明之半導體基板結構之製造方法的步驟包含：步驟S110：提供基材；步驟S120：形成第一遮罩層於基材上；步驟S130：形成光阻層於第一遮罩層上；步驟S140：定義第一蝕刻圖案與第二蝕刻圖案於光阻層；以及步驟S150：依據光阻層與第一遮罩層以及第一蝕刻圖案與第二蝕刻圖案之排列進行蝕刻製程，以去除光阻層與第一遮罩層而形成一基板。 Please refer to FIG. 6A, which is a flowchart of manufacturing a substrate according to an embodiment of the present invention. As shown in the figure, the steps of the manufacturing method of the semiconductor substrate structure of the present invention include: step S110: providing a substrate; step S120: forming a first mask layer on the substrate; step S130: forming a photoresist layer on the first mask on the mask layer; step S140 : defining the first etching pattern and the second etching pattern on the photoresist layer; and step S150 : etching according to the arrangement of the photoresist layer and the first mask layer and the first etching pattern and the second etching pattern The process is used to remove the photoresist layer and the first mask layer to form a substrate.

步驟S110至步驟S140同於前一實施例之步驟S10至步驟S40，因此不再贅述，對應之第七A圖至第七D圖所示之部分步驟示意圖，亦是不再贅述。 Steps S110 to S140 are the same as steps S10 to S40 in the previous embodiment, and therefore will not be repeated, and the corresponding schematic diagrams of some steps shown in Figures 7A to 7D are also omitted.

於步驟S150中，如第六B圖所示，其為本發明之一實施例之蝕刻製程之流程圖，其中步驟S150中進一步包含：步驟S151：形成第二遮罩層於光阻層上；步驟S152：依據第一蝕刻圖案與第二蝕刻圖案定義對應之第三蝕刻圖案與第四蝕刻圖案於第二遮罩層上；步驟S153：依據第二遮罩層、光阻層及其第一蝕刻圖案與第二蝕刻圖案及對應之第三蝕刻圖案與第四蝕刻圖案進行乾式蝕刻，使第一遮罩層形成第一微結構與第二微結構及第二遮罩層形成對應之第三微結構與第四微結構並對應於基板之表面；步驟S154：去除第三微結構與第四微結構；以及步驟S155：依據第一微結構與第二微結構進行蝕刻，以形成基板並使基板之表面依據第一微結構與第二微結構及對應之第三微結構與第四微結構形成第一超穎結構與第二超穎結構。 In step S150, as shown in FIG. 6B, which is a flowchart of an etching process according to an embodiment of the present invention, the step S150 further includes: step S151: forming a second mask layer on the photoresist layer; Step S152: Define the third etching pattern and the fourth etching pattern corresponding to the first etching pattern and the second etching pattern on the second mask layer; Step S153: According to the second mask layer, the photoresist layer and the first etching pattern The etching pattern, the second etching pattern and the corresponding third etching pattern and the fourth etching pattern are dry-etched, so that the first mask layer forms the first microstructure and the second microstructure and the second mask layer forms the corresponding third The microstructure and the fourth microstructure correspond to the surface of the substrate; step S154: remove the third microstructure and the fourth microstructure; and step S155: perform etching according to the first microstructure and the second microstructure to form the substrate and make the The surface of the substrate forms a first metastructure and a second metastructure according to the first microstructure, the second microstructure and the corresponding third microstructure and the fourth microstructure.

於步驟S151中，如第七E圖所示，透過氣相沉積法，例如：化學氣象沉積法(CVD)，將金屬鉻沉積於該光阻層14，而形成一第二遮罩層16，接續於步驟S152中，如第七F圖所示，在該第二遮罩層16上對應該光阻層14上的該第一蝕刻圖案142與該第二蝕刻圖案144，而對應形成一第三蝕刻圖案162與一第四蝕刻圖案164。之後，於步驟S153中，如第七G圖所示，進行乾式蝕刻，而將該第一遮罩層12上的該光阻層14與該第二遮罩層16去除，同時依據該光阻層14上的該第一蝕刻圖案142與該第二蝕刻圖案144而形成微結構，即該光阻層 14去除後，形成複數個第一蝕刻柱142A、第二蝕刻柱144A甚至是對應於該第三蝕刻圖案162與該第四蝕刻圖案164之第三蝕刻柱162A與第四蝕刻柱164A。於步驟S154中，如第七H圖所示，進一步將該第一蝕刻柱142A、該第二蝕刻柱144A、該第三蝕刻柱162A與該第四蝕刻柱164A，藉由蝕刻製程中的乾式蝕刻或是濕式蝕刻去除掉，以露出該基板30並對應將第一遮罩層12蝕刻出該第一微結構122以及該第二微結構124。於步驟S155中，如第七I圖所示，依據該第一微結構122以及該第二微結構124進行蝕刻，因而產生對應於第一磊晶區域E1之第一超穎結構102，同時產生對應於第二磊晶區域E2之第二超穎結構104。 In step S151, as shown in FIG. 7E, metal chromium is deposited on the photoresist layer 14 by vapor deposition, such as chemical vapor deposition (CVD), to form a second mask layer 16. Continuing in step S152, as shown in FIG. 7F, corresponding to the first etching pattern 142 and the second etching pattern 144 on the photoresist layer 14, a first etching pattern is formed on the second mask layer 16. Three etching patterns 162 and a fourth etching pattern 164 . After that, in step S153, as shown in FIG. 7 G, dry etching is performed to remove the photoresist layer 14 and the second mask layer 16 on the first mask layer 12. Meanwhile, according to the photoresist The first etching pattern 142 and the second etching pattern 144 on the layer 14 form a microstructure, that is, the photoresist layer After 14 is removed, a plurality of first etching pillars 142A, second etching pillars 144A and even third etching pillars 162A and fourth etching pillars 164A corresponding to the third etching pattern 162 and the fourth etching pattern 164 are formed. In step S154, as shown in FIG. 7 H, the first etching column 142A, the second etching column 144A, the third etching column 162A and the fourth etching column 164A are further processed by dry etching in the etching process. It is removed by etching or wet etching to expose the substrate 30 and correspondingly etch the first microstructure 122 and the second microstructure 124 from the first mask layer 12 . In step S155, as shown in FIG. 7 I, etching is performed according to the first microstructure 122 and the second microstructure 124, thereby generating the first metastructure 102 corresponding to the first epitaxial region E1, and simultaneously generating The second metastructure 104 corresponds to the second epitaxial region E2.

如第八A圖所示，以上實施例為該光阻層14屬於正光阻，或該光阻層14上設置該第二遮罩層16作為舉例，以增加抗蝕刻能力。除此之外，本發明之另一實施例更可為去除該第二遮罩層16，使該光阻層14轉為負光阻之揭示，即步驟S152中，去除該第二遮罩層16，而讓該光阻層14轉換成負光阻，如第八B圖所示。 As shown in FIG. 8A, in the above embodiment, the photoresist layer 14 is a positive photoresist, or the second mask layer 16 is provided on the photoresist layer 14 as an example to increase the etching resistance. In addition to this, another embodiment of the present invention may further be the disclosure of removing the second mask layer 16 to turn the photoresist layer 14 into a negative photoresist, that is, in step S152, removing the second mask layer 16, and the photoresist layer 14 is converted into a negative photoresist, as shown in Figure B of the eighth.

請參閱第九A圖，其為本發明之另一實施例之製造基板之流程圖。其中第六A圖與第九A圖之差異在於第九A圖省略形成該第一遮罩層12之步驟，因此，本發明之半導體基板結構之製造方法，其步驟包含：步驟S210：提供基材；步驟S230：形成光阻層於氧化層上；步驟S240：定義第一蝕刻圖案與第二蝕刻圖案於光阻層；以及步驟S250：依據光阻層以及第一蝕刻圖案與第二蝕刻圖案之排列進行蝕刻製程，以形成基板。 Please refer to FIG. 9A, which is a flowchart of manufacturing a substrate according to another embodiment of the present invention. The difference between the sixth A and the ninth A is that the ninth A omits the step of forming the first mask layer 12. Therefore, the manufacturing method of the semiconductor substrate structure of the present invention includes the following steps: Step S210: providing a base material; step S230: forming a photoresist layer on the oxide layer; step S240: defining a first etching pattern and a second etching pattern on the photoresist layer; and step S250: according to the photoresist layer and the first etching pattern and the second etching pattern The arrangement is subjected to an etching process to form a substrate.

步驟S210、步驟S230與步驟S240相當於上述步驟S110、步驟S130與步驟S140，因此不再贅述，其對應之圖式第十A圖至第十C圖之圖式不再贅述。於步驟S250中，請進一步參閱第九B圖以及對應第十D圖至第十G圖，其步驟如下：步驟S251：形成第二遮罩層於光阻層上；步驟S252：依據第一蝕刻圖案與第二蝕刻圖案定義對應之第三蝕刻圖案與第四蝕刻圖案於第二遮罩層上；步驟S253：依據第二遮罩層、光阻層及其第一蝕刻圖案與第二蝕刻圖案及對應之第三蝕刻圖案與第四蝕刻圖案進行乾式蝕刻，以形成基板並使基板之表面形成第一超穎結構與第二超穎結構。由於步驟S251至步驟S253相當於上述步驟S151至步驟S155，因此不再贅述。此外，本實施例中，由於該第二遮罩層16形成於該光阻層14之上，因而讓該光阻層14最後的該第一蝕刻柱142A與該第二蝕刻柱144A的所在位置與該第一遮罩層12之該第一微結構122與該第二微結構124所在位置錯位，或反轉，因而形成為負光阻。 Step S210 , step S230 and step S240 are equivalent to the above-mentioned steps S110 , step S130 and step S140 , so they will not be described again, and the corresponding diagrams in the tenth A to the tenth C diagram are not the same. Repeat. In step S250, please further refer to the ninth B and the corresponding tenth D to ten G, the steps are as follows: step S251: forming a second mask layer on the photoresist layer; step S252: according to the first etching The pattern and the second etching pattern define the third etching pattern and the fourth etching pattern on the second mask layer; Step S253 : according to the second mask layer, the photoresist layer and the first etching pattern and the second etching pattern and the corresponding third etching pattern and the fourth etching pattern are dry-etched to form a substrate and form the first meta-structure and the second meta-structure on the surface of the substrate. Since steps S251 to S253 are equivalent to the above-mentioned steps S151 to S155, they will not be repeated here. In addition, in this embodiment, since the second mask layer 16 is formed on the photoresist layer 14 , the last positions of the first etching column 142A and the second etching column 144A of the photoresist layer 14 are The positions of the first microstructures 122 and the second microstructures 124 of the first mask layer 12 are displaced or reversed, thereby forming a negative photoresist.

請參閱第十一圖，其為本發明之另一實施例之製造基板之流程圖。其中第九A圖至第九B圖與第十一圖之差異在於第十一圖簡化步驟S250，也就是第十一圖省略了第二遮罩層之步驟。對應如圖第十二A圖至第十二D圖所示，其步驟如下：步驟S310：提供基材；步驟S330：形成光阻層於基材上；步驟S340：定義第一蝕刻圖案與第二蝕刻圖案於光阻層；以及步驟S350：依據光阻層及其第一蝕刻圖案與第二蝕刻圖案進行蝕刻，使基板之表面依據第一蝕刻圖案與第二蝕刻圖案形成第一超穎結構與第二超穎結構。 Please refer to FIG. 11, which is a flow chart of manufacturing a substrate according to another embodiment of the present invention. The difference between the ninth diagrams A to ninth B and the eleventh diagram is that the eleventh diagram simplifies the step S250, that is, the eleventh diagram omits the step of the second mask layer. Corresponding to the twelfth A to the twelfth D, the steps are as follows: step S310: providing a substrate; step S330: forming a photoresist layer on the substrate; step S340: defining the first etching pattern and the first etching pattern Two etching patterns are formed on the photoresist layer; and step S350 : performing etching according to the photoresist layer and its first etching pattern and second etching pattern, so that the surface of the substrate forms a first metastructure according to the first etching pattern and the second etching pattern with the second metastructure.

步驟S310、步驟S330與步驟S340相當於上述步驟S210、步驟S230與步驟S240，因此不再贅述。於步驟S350中，直接以該光阻層14直接蝕刻，因此蝕刻前如第十二C圖所示，蝕刻後即如第十二D圖所示，形成該基板10A、該第一超穎結構102與該第二超穎結構104。 Step S310 , step S330 and step S340 are equivalent to the above-mentioned step S210 , step S230 and step S240 , and thus will not be described again. In step S350, the photoresist layer 14 is directly etched Therefore, the substrate 10A, the first metastructure 102 and the second metastructure 104 are formed as shown in FIG. 12 C before etching and as shown in FIG. 12 D after etching.

如此，如本發明提供較佳之基板結構，用於氮化鎵磊晶層，並藉由基板10A上之該第一超穎結構102以及該第二超穎結構104形成一漸變式結構，例如：自中央向外縮減間隔，即第一間隔D1至第三間隔D3遞減，或者遞增，藉此氮化鎵磊晶層於第一磊晶區域E1所產生之缺陷會因磊晶應力而逐漸向外擠壓至第二磊晶區域E2，使第一磊晶區域E1之磊晶層平坦化。該漸變式結構更可為該第一超穎結構102以及該第二超穎結構104之面積大小自第一超穎結構102向第二超穎結構104而向外不斷改變面積或排列間隔。如第十三A圖所示，基板10A如以上所述之實施例，該第一超穎結構102向外至該第二超穎結構104之排列間隔自第一間隔D1遞減至第三間隔D3，另外，如第十三B圖所示，本發明亦可針對該第一超穎結構102向外至該第二超穎結構104之單位面積自一第一單位面積A1遞減至一第二單位面積A2以及後再遞減至一第三單位面積A3，除了排列間隔遞減或面積遞減之外，更可為排列間隔遞增或面積遞增。 In this way, the present invention provides a better substrate structure for a GaN epitaxial layer, and a graded structure is formed by the first metastructure 102 and the second metastructure 104 on the substrate 10A, such as: The interval is reduced from the center to the outside, that is, the first interval D1 to the third interval D3 decreases or increases gradually, so that the defects generated by the gallium nitride epitaxial layer in the first epitaxial region E1 will gradually outward due to epitaxial stress Pressing to the second epitaxial region E2 to flatten the epitaxial layer of the first epitaxial region E1. The gradient structure may further be that the area or the arrangement interval of the first metastructure 102 and the second metastructure 104 continuously changes outward from the first metastructure 102 to the second metastructure 104 . As shown in FIG. 13A, the substrate 10A is the same as the above-mentioned embodiment, and the arrangement interval from the first metastructure 102 outward to the second metastructure 104 decreases from the first interval D1 to the third interval D3 , In addition, as shown in FIG. 13B, the present invention can also decrease the unit area from a first unit area A1 to a second unit from a first unit area A1 outward from the first metastructure 102 to the second metastructure 104 The area A2 and then decrease to a third unit area A3, in addition to the decreasing arrangement interval or the decreasing area, the arrangement interval may be increased or the area may be increased.

綜上所述，本發明之半導體基板結構及其製造方法，其提供蝕刻圖案呈現對稱且漸變式結構之排列，因而讓基材經蝕刻製程後，在其上表面形成對應之第一超穎結構與第二超穎結構，並基於第二超穎結構在第一磊晶區域外，及第一超穎結構在第一磊晶區域內，因而讓磊晶層可在磊晶完成後，向外推擠缺陷至邊緣，因而讓第一磊晶區域內的磊晶層為平坦化，並在第一磊晶區域外清楚表示切割圖案。 To sum up, the semiconductor substrate structure and the manufacturing method thereof of the present invention provide a symmetrical and gradient structure arrangement of the etching pattern, so that the corresponding first metastructure is formed on the upper surface of the substrate after the etching process. and the second metastructure, and based on the fact that the second metastructure is outside the first epitaxial region, and the first metastructure is in the first epitaxial region, so that the epitaxial layer can be moved outward after the epitaxial is completed. Defects are pushed to the edge, thereby flattening the epitaxial layer in the first epitaxial region and clearly showing the cutting pattern outside the first epitaxial region.

故本發明實為一具有新穎性、進步性及可供產業上利用者，應符合我國專利法專利申請要件無疑，爰依法提出發明專利申請，祈鈞局早日賜准專利，至感為禱。 Therefore, the present invention is indeed novel, progressive and available for industrial use, and it should meet the requirements for patent application in my country's patent law.

惟以上所述者，僅為本發明之較佳實施例而已，並非用來限定本發明實施之範圍，舉凡依本發明申請專利範圍所述之形狀、構造、特徵及精神所為之均等變化與修飾，均應包括於本發明之申請專利範圍內。 However, the above descriptions are only preferred embodiments of the present invention, and are not intended to limit the scope of implementation of the present invention. All changes and modifications made in accordance with the shape, structure, features and spirit described in the scope of the patent application of the present invention are equivalent. , shall be included in the scope of the patent application of the present invention.

10S:上表面 10S: Top surface

10A:基板 10A: Substrate

102:第一超穎結構 102: The first metastructure

104:第二超穎結構 104: Second metastructure

D1:第一間隔 D1: first interval

D2:第二間隔 D2: Second interval

D3:第三間隔 D3: Third interval

Claims

一種半導體基板超穎結構之製造方法，其步驟包含: 提供一基材；形成一光阻層於該基材之上；定義複數個第一蝕刻圖案與複數個第二蝕刻圖案於該光阻層，該些個第二蝕刻圖案位於該些個第一蝕刻圖案之周圍並對稱，且該些個第一蝕刻圖案之單位面積不同於該些個第二蝕刻圖案之單位面積；以及依據該光阻層以及該些個第一蝕刻圖案與該些個第二蝕刻圖案之排列進行一蝕刻製程，以去除該光阻層並透過該蝕刻製程形成一基板，並使該基板之一表面上之一第一磊晶區域形成複數個第一超穎結構，同時使該表面上之一第二磊晶區域形成複數個第二超穎結構，該些個第一蝕刻圖案與該些個第二蝕刻圖案之排列使該些個第一超穎結構與該些個第二超穎結構對應形成一漸變式結構，且該些個第一蝕刻圖案與該些個第二蝕刻圖案之單位面積差異讓該些個第一超穎結構之單位面積對應地不同於該些個第二超穎結構之單位面積。 A method for manufacturing a semiconductor substrate metastructure, the steps comprising: provide a substrate; forming a photoresist layer on the substrate; Define a plurality of first etching patterns and a plurality of second etching patterns on the photoresist layer, the second etching patterns are located around the first etching patterns and are symmetrical, and the units of the first etching patterns the area is different from the unit area of the second etching patterns; and An etching process is performed according to the photoresist layer and the arrangement of the first etching patterns and the second etching patterns to remove the photoresist layer and form a substrate through the etching process, and make a surface of the substrate A first epitaxial region on the surface forms a plurality of first metastructures, while a second epitaxial region on the surface forms a plurality of second metastructures, the first etching patterns and the first The arrangement of the two etching patterns makes the first metastructures and the second metastructures correspond to form a graded structure, and the unit area difference between the first etching patterns and the second etching patterns Let the unit areas of the first metastructures be correspondingly different from the unit areas of the second metastructures.

如請求項1所述之半導體基板超穎結構之製造方法，其中於形成一光阻層於該基材之上之步驟前，進一步包含: 形成一第一遮罩層於該基板上。 The method for manufacturing a semiconductor substrate metastructure as claimed in claim 1, before the step of forming a photoresist layer on the substrate, further comprising: A first mask layer is formed on the substrate.

如請求項2所述之半導體基板超穎結構之製造方法，其中於依據該光阻層以及該些個第一蝕刻圖案與該些個第二蝕刻圖案之排列進行蝕刻製程之步驟中，其包含: 依據該光阻層及其該些個第一蝕刻圖案與該些個第二蝕刻圖案進行乾式蝕刻，使該第一遮罩層形成複數個第一微結構與該些個第二微結構並對應於該表面；以及依據該些個第一微結構與該些個第二微結構進行乾式蝕刻或濕式蝕刻，以形成該基板並使該表面依據該些個第一微結構與該些個第二微結構形成該些個第一超穎結構與該些個第二超穎結構。 The method for manufacturing a semiconductor substrate metastructure as claimed in claim 2, wherein in the step of performing the etching process according to the photoresist layer and the arrangement of the first etching patterns and the second etching patterns, the method comprises: : Dry etching is performed according to the photoresist layer and the first etching patterns and the second etching patterns, so that the first mask layer forms a plurality of first microstructures and the second microstructures corresponding to each other on the surface; and Dry etching or wet etching is performed according to the first microstructures and the second microstructures to form the substrate and to form the surface according to the first microstructures and the second microstructures some first metastructures and some second metastructures.

如請求項1所述之半導體基板超穎結構之製造方法，其中於依據該光阻層以及該些個第一蝕刻圖案與該些個第二蝕刻圖案之排列進行蝕刻製程之步驟前，進一步包含: 形成一第二遮罩層於該光阻層上。 The method for manufacturing a semiconductor substrate metastructure as claimed in claim 1, further comprising, before the steps of performing the etching process according to the photoresist layer and the arrangement of the first etching patterns and the second etching patterns, further comprising: : A second mask layer is formed on the photoresist layer.

如請求項4所述之半導體基板超穎結構之製造方法，其中於依據該光阻層以及該些個第一蝕刻圖案與該些個第二蝕刻圖案之排列進行蝕刻製程之步驟前，進一步包含: 依據該些個第一蝕刻圖案與該些個第二蝕刻圖案定義對應之複數個第三蝕刻圖案與複數個第四蝕刻圖案於該第二遮罩層上。 The method for manufacturing a semiconductor substrate metastructure as claimed in claim 4, further comprising, before the steps of performing the etching process according to the photoresist layer and the arrangement of the first etching patterns and the second etching patterns, further comprising: : A plurality of third etching patterns and a plurality of fourth etching patterns corresponding to the first etching patterns and the second etching patterns are defined on the second mask layer.

如請求項5所述之半導體基板超穎結構之製造方法，其中於依據該光阻層及其該些個第一蝕刻圖案與該些個第二蝕刻圖案進行乾式蝕刻之步驟中，進一步依據該些個第三蝕刻圖案與該些個第四蝕刻圖案進行乾式蝕刻，以讓該些個第一微結構之上分別具有一第三微結構，並讓該些個第二微結構之上分別具有一第四微結構。The method for manufacturing a semiconductor substrate metastructure as claimed in claim 5, wherein in the step of dry etching the photoresist layer and the first etching patterns and the second etching patterns, further according to the Dry etching is performed on the third etching patterns and the fourth etching patterns, so that the first microstructures are respectively provided with a third microstructure, and the second microstructures are respectively provided with a fourth microstructure.

如請求項3所述之半導體基板超穎結構之製造方法，其中該乾式蝕刻為採用電漿對該些個第一微結構、該些個第二微結構與該表面進行蝕刻。The method for manufacturing a semiconductor substrate metastructure as claimed in claim 3, wherein the dry etching is to use plasma to etch the first microstructures, the second microstructures and the surface.

如請求項1所述之半導體基板超穎結構之製造方法，更包含: 形成一氮化鎵磊晶層之一第一磊晶部於該第一磊晶區域上並形成該氮化鎵磊晶層之一第二磊晶部位於該第二磊晶區域上，該第一磊晶部之高度不同或相同於該第二磊晶部之高度。 The method for manufacturing a semiconductor substrate metastructure as claimed in claim 1, further comprising: forming a first epitaxial portion of a gallium nitride epitaxial layer on the first epitaxial region and forming a second epitaxial portion of the gallium nitride epitaxial layer on the second epitaxial region, the first epitaxial region The height of an epitaxial portion is different from or the same as the height of the second epitaxial portion.

如請求項1所述之半導體基板超穎結構之製造方法，其中該漸變式結構為自該些個第一超穎結構往該些個第二超穎結構逐漸改變面積或排列間隔。The method for manufacturing a semiconductor substrate metastructure as claimed in claim 1, wherein the graded structure gradually changes the area or the arrangement interval from the first metastructures to the second metastructures.

一種半導體基板超穎結構，其包含: 一基板，其一表面具有一第一磊晶區域與一第二磊晶區域，該二第二磊晶區域接壤於該第一磊晶區域之周圍並對稱，該第一磊晶區域形成複數個第一超穎結構，該第二磊晶區域形成複數個第二超穎結構，該些個第一超穎結構之單位面積大於該些個第二超穎結構之單位面積，該些個第一超穎結構與該些個第二超穎結構形成一漸變式結構(graded structure)。 A semiconductor substrate metastructure, comprising: A substrate, a surface of which has a first epitaxial region and a second epitaxial region, the two second epitaxial regions border the periphery of the first epitaxial region and are symmetrical, and the first epitaxial region forms a plurality of a first metastructure, the second epitaxial region forms a plurality of second metastructures, the unit areas of the first metastructures are larger than the unit areas of the second metastructures, the first metastructures The metastructure and the second metastructures form a graded structure.

如請求項10所述之半導體基板超穎結構，其中該些個第一超穎結構之單位面積與該些個第二超穎結構之高度差距為0.05至10微米。The semiconductor substrate metastructure of claim 10, wherein the difference between the unit area of the first metastructures and the height of the second metastructures is 0.05 to 10 microns.

如請求項10所述之半導體基板超穎結構，其中該基板上進一步設有一氮化鎵磊晶層，其形成於該基板與該些個第一超穎結構及該些個第二超穎結構之上，該氮化鎵磊晶層具有一第一磊晶部與一第二磊晶部，該第一磊晶部之高度不同或相同於該第二磊晶部之高度，該第一磊晶部之一上表面呈一平坦面，該些個第二超穎結構之頂端穿透該第二磊晶部之一上表面。The semiconductor substrate metastructure of claim 10, wherein a gallium nitride epitaxial layer is further provided on the substrate, which is formed on the substrate and the first metastructures and the second metastructures Above, the gallium nitride epitaxial layer has a first epitaxial portion and a second epitaxial portion, the height of the first epitaxial portion is different or the same as the height of the second epitaxial portion, the first epitaxial portion An upper surface of the crystal portion is a flat surface, and tops of the second superstructures penetrate an upper surface of the second epitaxial portion.

如請求項10所述之半導體基板超穎結構，其中該漸變式結構為自該些個第一超穎結構往該些個第二超穎結構逐漸改變面積或排列間隔。The semiconductor substrate metastructure of claim 10, wherein the graded structure gradually changes the area or the arrangement interval from the first metastructures to the second metastructures.