TWI771977B - Method for cleaning deposition chamber - Google Patents
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本揭露是一種關於沉積室的清潔方法。The present disclosure is related to a method of cleaning a deposition chamber.
物理氣相沉積(Physical vapor deposition; PVD)或濺射為用於製造電子元件之製程。PVD為在真空腔室中執行之電漿製程,其中負偏壓之靶材暴露於具有相對重原子之惰性氣體(例如,氬氣(Ar))或包含此種惰性氣體之氣體混合物的電漿。惰性氣體之離子對靶之轟擊導致靶材之原子的噴射。所噴射之原子作為沉積膜累積在基板上,此基板係放置在設置於腔室內之基板支撐底座上。Physical vapor deposition (PVD) or sputtering is a process used to manufacture electronic components. PVD is a plasma process performed in a vacuum chamber in which a negatively biased target is exposed to a plasma of an inert gas having relatively heavy atoms (eg, argon (Ar)) or a gas mixture comprising such an inert gas . The bombardment of the target by ions of the noble gas results in the ejection of atoms of the target material. The ejected atoms are accumulated as a deposited film on a substrate, which is placed on a substrate support base provided in the chamber.
本揭露的一實施例為一種沉積室的清潔方法,包含將基板移動至半導體處理腔室的基板支撐件上;執行沉積製程,以在基板上沉積材料層;將基板移出半導體處理腔室;執行第一清潔製程,其中執行第一清潔製程包括經由基板支撐件內的第一導管提供第一氣體至半導體處理腔室內,以及開啟射頻源以產生第一氣體的電漿以清潔基板支撐件的表面;以及執行第二清潔製程,其中執行第二清潔製程包括經由配置於半導體處理腔室的側壁的第二導管提供第二氣體至半導體處理腔室內,以及開啟射頻源以產生第二氣體的電漿以清潔基板支撐件的表面。An embodiment of the present disclosure is a method of cleaning a deposition chamber, including moving a substrate onto a substrate support of a semiconductor processing chamber; performing a deposition process to deposit a material layer on the substrate; moving the substrate out of the semiconductor processing chamber; performing a first cleaning process, wherein performing the first cleaning process includes providing a first gas into the semiconductor processing chamber through a first conduit in the substrate support, and turning on a radio frequency source to generate a plasma of the first gas to clean the surface of the substrate support and performing a second cleaning process, wherein performing the second cleaning process includes providing a second gas into the semiconductor processing chamber through a second conduit disposed on a sidewall of the semiconductor processing chamber, and turning on a radio frequency source to generate a plasma of the second gas to clean the surface of the substrate support.
本揭露的一實施例為一種沉積室的清潔方法,包含將一基板移動至一半導體處理腔室的基板支撐件上;執行一沉積製程,以在基板上沉積材料層;將基板移出半導體處理腔室;執行第一清潔製程,其中執行第一清潔製程包括在半導體處理腔室內產生第一電漿以清潔基板支撐件的表面,第一電漿在基板支撐件的表面的中心部分的清潔速率大於在表面的周邊部分的清潔速率;以及執行第二清潔製程,其中執行第二清潔製程包括在半導體處理腔室內產生第二電漿以清潔基板支撐件的表面,第二電漿在基板支撐件的表面的周邊部分的清潔速率大於在表面的中心部分的清潔速率。An embodiment of the present disclosure is a method for cleaning a deposition chamber, including moving a substrate onto a substrate support of a semiconductor processing chamber; performing a deposition process to deposit a material layer on the substrate; and moving the substrate out of the semiconductor processing chamber a chamber; performing a first cleaning process, wherein performing the first cleaning process includes generating a first plasma within the semiconductor processing chamber to clean the surface of the substrate support, the first plasma cleaning at a central portion of the surface of the substrate support at a rate greater than a cleaning rate at a peripheral portion of the surface; and performing a second cleaning process, wherein performing the second cleaning process includes generating a second plasma within the semiconductor processing chamber to clean the surface of the substrate support, the second plasma at the surface of the substrate support The cleaning rate of the peripheral portion of the surface is greater than the cleaning rate of the central portion of the surface.
本揭露的一實施例為一種沉積室的清潔方法,包含在一半導體處理腔室內執行沉積製程,以在基板支撐件上方的基板上沉積材料層;確認基板與基板支撐件之間的一偏壓是否正常;若偏壓不正常,則執行第一清潔製程,其中執行第一清潔製程包括在半導體處理腔室內產生第一電漿以清潔基板支撐件的表面,第一電漿在基板支撐件的表面的一中心部分的濃度大於在表面的一周邊部分的濃度;以及執行第二清潔製程,其中執行第二清潔製程包括在半導體處理腔室內產生第二電漿以清潔基板支撐件的表面,第二電漿在基板支撐件的表面的周邊部分的濃度大於在表面的中心部分的濃度。An embodiment of the present disclosure is a method of cleaning a deposition chamber, including performing a deposition process in a semiconductor processing chamber to deposit a material layer on a substrate above a substrate support; confirming a bias voltage between the substrate and the substrate support Whether it is normal; if the bias voltage is abnormal, perform a first cleaning process, wherein performing the first cleaning process includes generating a first plasma in the semiconductor processing chamber to clean the surface of the substrate support, and the first plasma is in the substrate support. a central portion of the surface has a greater concentration than a peripheral portion of the surface; and performing a second cleaning process, wherein performing the second cleaning process includes generating a second plasma within the semiconductor processing chamber to clean the surface of the substrate support, the first The concentration of the second plasma is greater in the peripheral portion of the surface of the substrate support than in the central portion of the surface.
以下揭露內容提供許多不同實施例或實例,用於實施提供的標的的不同特徵。以下描述組件及配置的具體實例以簡化本揭露內容。當然,此等僅為實例,且並不意欲為限制性。舉例而言,在接下來的描述中,第一特徵在第二特徵上方或上的形成可包括第一與第二特徵直接接觸地形成的實施例,且亦可包括額外特徵可形成於第一與第二特徵之間使得第一與第二特徵可不直接接觸的實施例。此外,在各種實例中,本揭露內容可重複參考數字及/或字母。此重複係為了簡單且清晰的目的,且自身並不規定論述的各種實施例及/或組態之間的關係。The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the description that follows, the formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include additional features that may be formed on the first feature. Embodiments in which the first and second features may not be in direct contact with the second feature. Furthermore, in various instances, the present disclosure may repeat reference numbers and/or letters. This repetition is for the purpose of simplicity and clarity, and does not in itself prescribe the relationship between the various embodiments and/or configurations discussed.
另外,為了易於描述,諸如「在……之下(beneath)」、「在……下方(below)」、「下部(lower)」、「在……上方(above)」及「上部(upper)」及類似者的空間相對術語可在本文中用以描述如在圖中圖示的一個元件或特徵與另一元件或特徵的關係。除了圖中描繪的定向之外,該些空間相對術語意欲亦涵蓋在使用或操作中的元件的不同定向。可將設備以其他方式定向(旋轉90度或以其他定向),且同樣地可將本文中使用的空間相對描述詞相應地作出解釋。In addition, for ease of description, such as "beneath", "below", "lower", "above" and "upper" ” and similar spatially relative terms may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. In addition to the orientation depicted in the figures, these spatially relative terms are intended to encompass different orientations of the elements in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and likewise the spatially relative descriptors used herein interpreted accordingly.
本揭露之實施方式大致提供一種處理腔室。在部分實施例中,本揭露的實施例為一種用於執行物理氣相沉積(PVD)製程之基板處理方法。處理腔室為真空腔室,其包含靜電吸盤(electrostatic chuck, E-chuck)以支撐並保持基板,藉由靶材之轟擊而噴射之原子在PVD處理期間沉積在此些基板上。靜電吸盤包含陶瓷球,此陶瓷球在其中具有一或更多個電極。向電極施加夾持電壓以便以靜電方式將基板保持至靜電吸盤。Embodiments of the present disclosure generally provide a processing chamber. In some embodiments, an embodiment of the present disclosure is a substrate processing method for performing a physical vapor deposition (PVD) process. The processing chamber is a vacuum chamber that includes an electrostatic chuck (E-chuck) to support and hold the substrates on which atoms ejected by bombardment of the target are deposited during PVD processing. The electrostatic chuck includes a ceramic ball having one or more electrodes therein. A clamping voltage is applied to the electrodes to electrostatically hold the substrate to the electrostatic chuck.
覆蓋環、沉積環及接地屏蔽係設置在真空腔室中,以在真空腔室內相對於基板來界定處理區域。接地屏蔽與覆蓋環交錯以限制電漿。限制至處理區域之電漿及噴射原子限制了靶材在腔室中之其他部件上的沉積,並促成更高效地使用靶材,因為相對較高百分比之噴射原子被沉積在基板上。The cover ring, deposition ring, and ground shield are disposed in the vacuum chamber to define the processing area relative to the substrate within the vacuum chamber. Ground shields are interleaved with cover rings to confine plasma. The confinement of the plasma and ejected atoms to the processing area limits the deposition of the target material on other components in the chamber and facilitates more efficient use of the target material because a relatively high percentage of the ejected atoms are deposited on the substrate.
靜電吸盤(ESC)支撐沉積環且藉由升舉機構耦接至真空腔室之底部,此升舉機構用以使靜電吸盤(ESC)及沉積環在上部與下部位置之間移動。在操作期間,覆蓋環亦被升高及降低。當升高時,覆蓋環與接地屏蔽垂直分離開。當降低時,覆蓋環的部分被接收在接地屏蔽的部分內。當靜電吸盤處於上升位置時,覆蓋環及接地屏蔽彼此垂直地分離。在處理操作期間,來自靶材之沉積材料亦沉積在沉積環上。An electrostatic chuck (ESC) supports the deposition ring and is coupled to the bottom of the vacuum chamber by a lift mechanism for moving the electrostatic chuck (ESC) and deposition ring between upper and lower positions. During operation, the cover ring is also raised and lowered. When raised, the cover ring separates vertically from the ground shield. When lowered, the portion of the cover ring is received within the portion of the ground shield. When the electrostatic chuck is in the raised position, the cover ring and ground shield are vertically separated from each other. During processing operations, deposition material from the target is also deposited on the deposition ring.
第1圖繪示半導體處理腔室100,其包含一片式接地屏蔽160及覆蓋環170。接地屏蔽160及覆蓋環170包含用以處理設置在處理區域110或電漿區域中之基板105的處理套組,其亦包含支撐在底座組件120上之沉積環180。在一些實施方式中,半導體處理腔室100包含用於在基板105上沉積來自靶材132之單一成分或多成分材料之濺射腔室,亦稱為物理氣相沉積或PVD腔室。半導體處理腔室100亦可用以沉積鋁、銅、鎳、鉑、鉿、銀、鉻、金、鉬、矽、釕、鉭、氮化鉭、碳化鉭、氮化鈦、鎢、氮化鎢、鑭、氧化鋁、氧化鑭、鎳鉑合金,及鈦,及/或其組合。預期其他處理腔室亦可適於受益於所揭露實施方式。沉積環180具有環繞基板支撐件126之環形形狀,並將在後續作更深入討論。在部分實施例中,沉積環180可由陶瓷或金屬材料製成,像是,石英、氧化鋁、不銹鋼、鈦或其他適當材料。覆蓋環170由抗濺射電漿的侵蝕之材料製成,例如,金屬材料或陶瓷材料。FIG. 1 shows a
半導體處理腔室100包含腔室主體101,其具有封閉處理區域110之側壁104、底壁106及上部處理組件108。將處理區域110定義為在處理期間在基板支撐件126上方之區域(例如,當處於處理位置時在靶材132與基板支撐件126之間)。藉由機械加工及焊接不銹鋼板或藉由機械加工單個鋁塊來製造腔室主體101。在一個實施方式中,側壁104包含鋁或電鍍有鋁,且底壁106包含或電鍍有不銹鋼。側壁104通常含有狹縫閥,以提供基板105自半導體處理腔室100進出。與接地屏蔽160、底座組件120及覆蓋環170協作之在半導體處理腔室100之上部處理組件108中的部件將在處理區域110中形成之電漿限制在基板105上方的區域中。The
自半導體處理腔室100之底壁106支撐底座組件120。底座組件120在處理期間支撐沉積環180連同基板105。底座組件120藉由升舉機構122耦接至半導體處理腔室100之底壁106,此升舉機構122用以在基板105上之靶材在沉積期間的上部處理位置與基板105被傳送至底座組件120上的下部傳送位置之間升高及降低底座組件120。另外,在下部傳送位置處,升舉銷123移動經過底座組件120,以使基板105與底座組件120分隔開,以便於藉由設置在半導體處理腔室100外部之基板傳送機構(像是,單片機器人)來交換基板105。波紋管124通常設置在底座組件120與底壁106之間,以將腔室主體101之處理區域110與底座組件120之內部及腔室之外部隔離開。The
底座組件120包含密封地耦接至平臺外殼128之基板支撐件126。平臺外殼128通常由金屬材料製成,像是,不銹鋼或鋁。冷卻板通常設置在平臺外殼128內以熱調節基板支撐件126。基板支撐件126由鋁或陶瓷製成。基板支撐件126具有基板接收表面127,其在處理期間接收並支撐基板105,此基板接收表面127大體上平行於靶材132之濺射表面133。基板支撐件126亦具有周邊邊緣129,此周邊邊緣129在基板105之伸出邊緣之前終止。The
在一些實施方式中,基板支撐件126為靜電吸盤、陶瓷主體、加熱器或其組合。在一個實施方式中,基板支撐件126為包含介電主體之靜電吸盤,此介電主體具有內嵌於其中之電極126A或導電層。介電主體由高熱導率之介電材料製成,像是,熱解氮化硼、氮化鋁、氮化矽、氧化鋁或均等材料。在一些實施方式中,電極126A經配置以使得當藉由靜電吸盤電源143將DC電壓施加至電極126A時,設置在基板接收表面127上之基板105將以靜電方式夾持至此些電極126A,以提高基板105與基板支撐件126之間的傳熱。在其他實施方式中,阻抗控制器141亦耦接至電極(導電層)126A,以使得可在處理期間維持基板上之電壓以影響與基板105之表面的電漿相互作用。In some embodiments, the
在部分實施例中,基板支撐件126中具有導管137,導管137的一端經由基板支撐件126的表面曝露,而導管137的另一端連接至氣源138。在部分實施例中,導管137上配置有閥V1,閥V1配置於限制氣體自氣源138經由導管137流入至處理區域110中。舉例而言,當閥V1為「打開」狀態,則允許氣體自氣源138經由導管137流入至處理區域110中。若閥V1為「關閉」狀態,則氣體將被閥V1限制而無法進入處理區域110中。In some embodiments, the
在一些實施方式中,平臺外殼128包含具有適當地與上覆基板支撐件126之熱性質匹配的材料。舉例來說,平臺外殼128包含陶瓷與金屬之複合物(像是,鋁矽碳化物),其與陶瓷相比提供了改良的強度及耐久性,且亦具有改良的傳熱性質。複合材料具有與基板支撐件126的材料匹配之熱膨脹係數,以減少熱膨脹失配。在一些實施方式中,複合材料包含具有被金屬滲透之孔的陶瓷,此金屬至少部分地填充此些孔以形成複合材料。陶瓷包含例如碳化矽、氮化鋁、氧化鋁或堇青石中之至少一者。陶瓷包含為總體積的約20體積%至約80體積%之孔體積,其餘體積屬於滲透金屬。滲透金屬包含添加有矽的鋁,且亦含有銅。在一些實施方式中,複合物包含陶瓷及金屬之不同成分,像是,具有分散的陶瓷顆粒之金屬,或平臺外殼128可僅由金屬製成,像是,不銹鋼或鋁。冷卻板設置在平臺外殼128內以熱調節基板支撐件126。In some embodiments, the
半導體處理腔室100受系統控制器190控制,此系統控制器190促進半導體處理腔室100之控制及自動化,且通常包含中央處理單元(CPU)、記憶體及支援電路(或I/O)。CPU可為用於工業設置中之任何形式的電腦處理器中之一者,用於控制各種系統功能、基板移動、腔室處理及支援硬體(例如,感測器、機器人、馬達等)並監控製程(例如,基板支持溫度、電源變量、腔室製程時間、I/O信號,等等)。記憶體連接至CPU,且可為易獲記憶體中之一或更多者,像是,隨機存取記憶體(RAM)、唯讀記憶體(ROM)、軟碟、硬碟,或任何其他形式之數位儲存器,本端的或遠端的。軟體指令及資料可被編碼並儲存在記憶體內,用於指示CPU。支援電路亦連接至CPU,用於以習知方式支援處理器。支援電路包含快取記憶體、電源、時鐘電路、輸入/輸出電路系統、子系統,及其類似者。可由系統控制器190讀取之程式(或電腦指令)決定在基板上執行哪些任務。此程式為可由系統控制器190讀取之軟體,其包含用以執行與運動之監控、執行及控制有關的任務之代碼,及要在半導體處理腔室100中執行之各種製程配方任務及配方步驟。舉例來說,系統控制器190包含程式碼,其包含:基板定位指令集,用以操作底座組件120;氣體流量控制指令集,用以操作氣體流量控制閥以設定至半導體處理腔室100之濺射氣體的流量;氣體壓力控制指令集,用以操作節流閥或閘閥以維持半導體處理腔室100中之壓力;溫度控制指令集,用以控制在底座組件120或側壁104中之溫度控制系統以分別設定基板或側壁104之溫度;及製程監控指令集,用以監控半導體處理腔室100中之製程。The
上部處理組件108包含射頻(Radio frequency;RF)源181、直流(DC)源182、配接器102、馬達193及蓋組件130。蓋組件130包含靶材132、磁控系統189及蓋殼191。如第1圖中所示,當處於關閉位置時,上部處理組件108由側壁104支撐。陶瓷靶材隔離件136設置在靶材132與蓋組件130的配接器102之間,以限制其間之真空洩漏。配接器102密封地耦接至側壁104,且用以幫助移除上部處理組件108。The
靶材132被設置成與配接器相鄰,且暴露於半導體處理腔室100之處理區域110。靶材132提供了在PVD製程期間沉積於基板上之材料。The
在處理期間,藉由設置在RF源181及/或DC源182中之功率源140相對於地(例如,腔室主體101)用RF及/或DC功率將靶材132偏壓。在一個實施方式中,RF源181包含RF功率源181A及RF匹配器181B,其用以高效地將RF能量傳遞至靶材132。During processing,
在處理期間,自氣源142經由導管144將氣體(例如,氬氣)供應至處理區域110。在部分實施例中,氣源142包含像是氬氣或氙氣之非反應性氣體,其能夠以能量的方式撞擊靶材132並自靶材132濺射材料。氣源142亦包含反應性氣體(例如,含氧氣體、含氮氣體、含甲烷氣體中之一或更多者),其與濺射材料反應以在基板上形成層。廢製程氣體及副產物經由排氣埠146自半導體處理腔室100排出,此些排氣埠146接收廢製程氣體並將廢製程氣體導向至排氣導管148,此些排氣導管148具有可調整位置之閘閥147以控制半導體處理腔室100中之處理區域110中的壓力。排氣導管148連接至一或更多個排氣泵149。通常,將半導體處理腔室100中之濺射氣體的壓力設定為次大氣壓水平(像是,真空環境),例如,約0.6 毫托至約400毫托之壓力。由基板105與靶材132之間的氣體形成電漿。電漿內之離子朝向靶材132加速,並導致材料自靶材132脫落。脫落之靶材料沉積在基板105上。在部分實施例中,導管144上配置有閥V2,閥V2配置於限制氣體自氣源142經由導管144流入至處理區域110中。舉例而言,當閥V2為「打開」狀態,則允許氣體自氣源142經由導管144流入至處理區域110中。若閥V2為「關閉」狀態,則氣體將被閥V2限制而無法進入處理區域110中。During processing, a gas (eg, argon) is supplied to
蓋殼191包含導電壁185、中心饋電184及屏蔽罩186。在此配置中,導電壁185、中心饋電184、靶材132及馬達193的一部分封閉並形成背面區域134。背面區域134係設置在靶材132之背側上的密封區域,且在處理期間通常填充有流動液體以移除處理期間在靶材132處所產生之熱。在一個實施方式中,導電壁185及中心饋電184用以支持馬達193及磁控系統189,以使得馬達193可在處理期間使磁控系統189旋轉。在一些實施方式中,馬達193與自電源傳遞之RF或DC功率電隔離。屏蔽罩186包含一或更多種介電材料,其被定位成封閉並限制傳遞至靶材132之RF能量以免干擾並影響設置在群集工具103中之其他處理腔室。Cover 191 includes
接地屏蔽160由腔室主體101支撐,並圍繞面向基板支撐件126之濺射靶材132的濺射表面133。接地屏蔽160亦環繞基板支撐件126之周邊邊緣129。接地屏蔽160覆蓋半導體處理腔室100的側壁104,以減少源自濺射靶材132之濺射表面133的濺射沉積物至接地屏蔽160背後之部件及表面上的沉積。A
當基板支撐件126處於下部的裝載位置(如第1圖中所繪示)時,覆蓋環170靠在接地屏蔽160上。當基板支撐件126處於上部(升高的)沉積位置時,覆蓋環170緊鄰沉積環180並與其分離。在沉積位置處,覆蓋環170保護基板支撐件126免於濺射沉積。When the
第2圖為本揭露之部分實施例之基板支撐件的俯視圖。詳細來說,第2圖為第1圖的基板支撐件126的俯視圖,其中第2圖中的部分元件並未在第1圖中繪製。在第2圖的實施例中,基板支撐件126為可為靜電吸盤(E-chuck)。FIG. 2 is a top view of a substrate support member according to some embodiments of the disclosure. In detail, FIG. 2 is a top view of the
如圖所示,導管137的一端經由基板支撐件126的表面曝露。更詳細來說,導管137實質上曝露於基板支撐件126的表面的圓心部分。另一方面,基板支撐件126可具有開口以容許升舉銷123通過。當升舉銷123抬升時,升舉銷123可以穿越基板支撐件126的開口並向上延伸並接收基板105(請參照第1圖)。而升舉銷123可進一步下降以將基板105移動至基板支撐件126的表面。電極126A亦曝露於基板支撐件126的表面。在部分實施例中,電極126A為均勻散佈在基板支撐件126的表面的點狀結構,以均勻地提供靜電將基板105夾持至此些電極126A。As shown, one end of the
基板支撐件126還包含偏壓感測器202。偏壓感測器202是用於在沉積製程期間感應基板支撐件126的表面和基板105的背面之間的電壓。在部分實施例中,偏壓感測器202是嵌入在基板支撐件126中。在部分實施例中,偏壓感測器202的形狀為「C」形,且圍繞著導管137。然應了解,偏壓感測器202亦可有其他形狀以及配置方式。The
第3A圖至第3D圖為本揭露之部分實施例之製造半導體結構在不同階段的剖面圖。參照第3A圖,第3A圖圖示了基板302。此處,基板302可以類似於第1圖所示的基板105。然而,基板302並不限於常規的上意指的基板。在部分實施例中,基板302可包括諸如矽的單一半導體材料,並用於支撐半導體元件,例如電晶體。在其他實施例中,基板302可以包括大範圍的結構。舉例來說,基板302可包括一個或多個分隔互連層的層間介電層。或者,基板302可以包括幾層先前形成的內連接線和/或金屬製成的通孔/觸點,用於連接到下面的其他層或半導體器件的內連接線。FIGS. 3A to 3D are cross-sectional views at different stages of manufacturing a semiconductor structure according to some embodiments of the present disclosure. Referring to FIG. 3A , FIG. 3A illustrates a
接著,在基板302上形成蝕刻停止層304。蝕刻停止層304可用於防止將在其上形成的銅互連線擴散到下面的基板的介電材料中,或是用於停止蝕刻。蝕刻停止層304可以是用於那些目的的任何非導電材料,例如氮化鈦(TiN)、氮化鉭(TaN) 、氮化鎢(WN) 、氮化鈦矽(TiSiN)或氮化鉭矽(TaSiN) 、碳化矽(SiC) 、氮化矽(SiN) 、NDC(氮摻雜碳化物)或ODC(氧摻雜碳化物)。Next, an
接著,在蝕刻停止層304上方形成絕緣層306。在部分實施例中,絕緣層306可為介電材料。在部分實施例中,介電材料可以是k值小於3.9的低k(介電常數)材料,例如氟化石英玻璃(FSG,k = 2.8)、氫倍半矽氧烷(HSQ,k = 2.9)、碳摻雜矽、氧化物,等等。在其它實施例中,電介質材料可以是典型的未摻雜和摻雜的二氧化矽(SiO
2),氮氧化矽(SiON)和氮化矽(Si
3N
4)。可以通過旋塗或旋塗電介質製程、CVD或任何其他合適的沉積工藝來沉積低k電介質材料。在沉積之後,在一個實施例中,可以通過CMP工藝去除沉積的介電層的上部。在一些實施例中,絕緣層可以包括多於一層的不同介電材料。
Next, an insulating
接著,在絕緣層306上方形成硬遮罩308。在部分實施例中,硬遮罩308的材料可為氮化鈦(TiN),或者其他適合的材料。在部分實施例中,氮化鈦可以應用第1圖所示的沉積室來沉積。請一併參照第1圖,舉例來說,在製程操作期間,靶材132的材料可為鈦(Ti)。於此同時,氣源142包含像是氬氣或氙氣之非反應性氣體,其能夠以能量的方式撞擊靶材132並自靶材132濺射材料。氣源142亦包含反應性氣體,例如氮氣,藉以提供氮源。而濺射的鈦可與氮氣反應,形成氮化鈦並落在基板302上以形成硬遮罩308。Next, a
接著,在硬遮罩308上方形成光阻層310。光阻可以是本領域中使用的合適的材料,例如聚(甲基丙烯酸甲酯)(PMMA)、聚(戊二酸甲酯)(PMGI)、苯酚甲醛樹脂,且可以是正光阻或是負光阻。光阻層310可以藉由沉積製程形成,並藉由光微影製程圖案化。Next, a
參照第3B圖,在光阻層310上方沉積間隔物層320。在部分實施例中,間隔物層320可為SiO
2、SiC或Si
3N
4,或其他適合的介電材料。間隔物層320可通過適當的沉積製程,例如化學氣相沉積(CVD),物理氣相沉積(PVD)或分子束外磊晶MBE)形成。
Referring to FIG. 3B , a
參照第3C圖,執行蝕刻製程以將間隔物層320的水平部分移除,使得間隔物層320的垂直部分遺留在光阻層310的側表面。接著,在蝕刻製程之後,移除光阻層310,使得的間隔物層320的垂直部分遺留在硬遮罩308的上表面。在部分實施例中,可以使用已知的蝕刻製程移除間隔物層320的水平部分,例如濕蝕刻或乾蝕刻。在部分實施例中,可使用適當的方法移除光阻層310,例如剝離或是灰化。Referring to FIG. 3C , an etching process is performed to remove the horizontal portion of the
參照第3D圖,將間隔物層320作為蝕刻遮罩,對絕緣層306進行蝕刻,以在絕緣層306內形成溝槽325。同樣地,可以使用適合的蝕刻製程,例如濕蝕刻或乾蝕刻。可以使用的蝕刻劑可以包括但不限於濕蝕刻劑,例如氫氧化鉀(KOH)、乙二胺和鄰苯二酚(EDP),或四甲基氫氧化銨(TMAH),或等離子蝕刻劑,例如Cl2、CCl
4、SiCl
2、BCl
3、CCl
2F
2、CF
4、SF
6或NF
3。在蝕刻完絕緣層306之後,可藉由另一蝕刻製程移除間隔物層320。
Referring to FIG. 3D , the insulating
第4圖為本揭露之部分實施例之操作半導體處理腔室的方法M1。儘管將方法M1示出及/或描述為一系列動作或事件,將瞭解方法不限於所示出的次序或動作。因此,在一些實施例中,動作可以與所示出者不同的次序執行、及/或可同時執行。另外,在一些實施例中,所示出的動作或事件可分為多個動作或事件,此等動作或事件可分多次執行或與其他動作或子動作同時。在一些實施例中,一些示出的動作或事件可省去,並且其他未示出的動作或事件可包括在內。FIG. 4 is a method M1 of operating a semiconductor processing chamber according to some embodiments of the present disclosure. Although method M1 is shown and/or described as a series of acts or events, it is to be understood that the method is not limited to the order or acts shown. Thus, in some embodiments, the actions may be performed in a different order than shown, and/or may be performed concurrently. Additionally, in some embodiments, the illustrated actions or events may be divided into multiple actions or events, such actions or events may be performed multiple times or concurrently with other actions or sub-actions. In some embodiments, some actions or events shown may be omitted, and other actions or events not shown may be included.
請參照第4圖及第5圖。方法M1起始於操作S101,執行一沉積製程。如第5圖所示,將基板105移動至半導體處理腔室100的基板支撐件126上方,並在基板105上方沉積一材料層。在部分實施例中,基板105可以如第3A圖所示的基板302。此外,材料層可以例如為第3A圖所示的硬遮罩308。Please refer to Figure 4 and Figure 5. The method M1 begins with operation S101 , performing a deposition process. As shown in FIG. 5 , the
請繼續參照第4圖及第5圖。方法M1進行至操作S102,確認基板支撐件與基板之間的偏壓是否正常。在部分實施例中,可以藉由如第2圖所示的偏壓感測器202量測基板支撐件126與基板105之間的偏壓,並藉由系統控制器190判斷此偏壓是否正常。偏壓不正常的原因為基板支撐件126表面有髒汙或是有機物質附著,就會發生偏壓過高且不穩定的情況。在部分實施例中,操作S102是在操作S101的沉積製程期間進行。Please continue to refer to Figures 4 and 5. The method M1 proceeds to operation S102 to confirm whether the bias voltage between the substrate supporter and the substrate is normal. In some embodiments, the bias voltage between the
若基板支撐件與基板之間的偏壓為正常,則方法M1進行至操作S103,繼續執行沉積製程。在部分實施例中,若基板支撐件與基板之間的偏壓為正常,則判斷沉積製程的條件為穩定,因此沉積製程將繼續執行至材料層達到所希望的厚度即停止。接著,可將基板105移出半導體處理腔室100外,以進行其他製程,或者可在半導體處理腔室100外另外沉積一材料層。If the bias voltage between the substrate supporter and the substrate is normal, the method M1 proceeds to operation S103 to continue the deposition process. In some embodiments, if the bias voltage between the substrate supporter and the substrate is normal, the conditions of the deposition process are determined to be stable, and thus the deposition process will continue to execute until the material layer reaches a desired thickness and then stops. Next, the
若基板支撐件與基板之間的偏壓為異常,則方法M1進行至操作S104,發出警報並停止沉積製程。在部分實施例中,若基板支撐件與基板之間的偏壓為異常,則代表基板支撐件126的表面可能有過多的髒污,使得基板支撐件與基板之間的偏壓異常,進而造成沉積的品質不佳 。在部分實施例中,發出警報並停止沉積製程可藉由系統控制器190執行。If the bias voltage between the substrate supporter and the substrate is abnormal, the method M1 proceeds to operation S104 to issue an alarm and stop the deposition process. In some embodiments, if the bias voltage between the substrate support member and the substrate is abnormal, it means that the surface of the
請參照第4圖、第6A圖,及第6B圖。方法M1進行至操作S105,執行第一清潔製程。詳細而言,第一清潔製程是用於清潔基板支撐件126的上表面。在部分實施例中,在執行第一清潔製程之前,先將基板105移出半導體處理腔室100外,藉以曝露基板支撐件126的上表面。Please refer to Figure 4, Figure 6A, and Figure 6B. The method M1 proceeds to operation S105 to perform the first cleaning process. In detail, the first cleaning process is used to clean the upper surface of the
執行第一清潔製程包括,打開連接氣源138的閥V1,使得氣體,例如氬氣(Ar),經由導管137,藉由基板支撐件126的上表面進入半導體處理腔室100的處理區域110內。接著,開啟RF源181,以在半導體處理腔室100內產生電漿。當RF源181應用時,蓋殼191包含導電壁185可以作為陽極,而基板支撐件126可以作為陰極。正電荷的氣體離子(例如氬離子)被吸引至負電荷的基板支撐件126,使得離子可以轟擊基板支撐件126的表面,並藉此清除、或是蝕刻掉基板支撐件126表面上的髒污。Performing the first cleaning process includes opening the valve V1 connected to the
在部分實施例中,第一清潔製程是在以下條件下執行:RF能量為約為90W至約110W;氣體流量為約16sccm至約20sccm;氣體壓力為約6.5mtorr至約8.5mtorr;清潔時間為約8 min 至約12 min (例如約10min)。在部分實施例中,清潔時間可以視為第一清潔製程期間打開RF源181和關閉RF源181之間的時間間隔。In some embodiments, the first cleaning process is performed under the following conditions: RF energy is about 90W to about 110W; gas flow is about 16 seem to about 20 seem; gas pressure is about 6.5 mtorr to about 8.5 mtorr; cleaning time is About 8 min to about 12 min (eg, about 10 min). In some embodiments, the cleaning time may be regarded as the time interval between turning on the
請參照第6B圖,在第一清潔製程中,由於用於清潔的氣體經由導管137,藉由基板支撐件126的中心進入至半導體處理腔室100內 (如第6A圖的虛線箭頭所示)。因此,氣體在基板支撐件126的中心部分126C的濃度將會大於在基板支撐件126的周邊部分126P的濃度。由於在中心部分126C的濃度較高,所產生的氣體離子也較多,因此在第一清潔製程期間,基板支撐件126的中心部分126C的髒污的被清潔速率(或者被蝕刻的速率)將會高於基板支撐件126的周邊部分126P的髒污的被清潔速率(或者被蝕刻的速率)。此處,基板支撐件126的「中心部分」可以視為以基板支撐件126的圓心至約半徑的1/2所涵蓋的範圍。另一方面,基板支撐件126的「周邊部分」可以視為以基板支撐件126的半徑的1/2延伸至基板支撐件126的圓周所涵蓋的範圍。在部分實施例中,周邊部分126P環繞中心部分126C。Referring to FIG. 6B, in the first cleaning process, the cleaning gas enters the
請參照第4圖、第7A圖,及第7B圖。方法M1進行至操作S106,執行第二清潔製程。執行第二清潔製程包括,打開連接氣源142的閥V2,使得氣體,例如氬氣(Ar),進入半導體處理腔室100的處理區域110內。接著,開啟RF源181,以在半導體處理腔室100內產生電漿。當RF源181應用時,蓋殼191包含導電壁185可以作為陽極,而基板支撐件126可以作為陰極。正電荷的氣體離子(例如氬離子)被吸引至負電荷的基板支撐件126,使得離子可以轟擊基板支撐件126的表面,並藉此清除、或是蝕刻掉基板支撐件126表面上的髒污。Please refer to Figure 4, Figure 7A, and Figure 7B. The method M1 proceeds to operation S106 to perform the second cleaning process. Performing the second cleaning process includes opening the valve V2 connected to the
在部分實施例中,第二清潔製程是在以下條件下執行:RF能量為約為90W至約110W;氣體流量為約7.5 sccm至約9.5 sccm;氣體壓力為約3.5 mtorr至約4.5 mtorr;清潔時間約為55 min 至約65 min (例如約60 min)。在部分實施例中,清潔時間可以視為第二清潔製程期間打開RF源181和關閉RF源181之間的時間間隔。In some embodiments, the second cleaning process is performed under the following conditions: RF energy is about 90W to about 110W; gas flow is about 7.5 sccm to about 9.5 sccm; gas pressure is about 3.5 mtorr to about 4.5 mtorr; cleaning The time is about 55 minutes to about 65 minutes (eg, about 60 minutes). In some embodiments, the cleaning time may be regarded as the time interval between turning on the
請參照第7B圖,在第一清潔製程中,由於用於清潔的氣體經由導管144,藉由半導體處理腔室100的側壁104進入至半導體處理腔室100內。接著,氣體將會自基板支撐件126和接地屏蔽160及/或覆蓋環170之間的間隙逐漸擴散至基板支撐件126的上方(如第7A圖的虛線箭頭所示)。因此,氣體在基板支撐件126的周邊部分126P的濃度將會大於在基板支撐件126的中心部分126C的濃度。由於在周邊部分126P的濃度較高,所產生的氣體離子也較多,因此在第二清潔製程期間,基板支撐件126的周邊部分126P的髒污的被清潔速率(或者被蝕刻的速率)將會高於基板支撐件126的中心部分126C的髒污的被清潔速率(或者被蝕刻的速率)。Referring to FIG. 7B , in the first cleaning process, the gas for cleaning enters the
在部分實施例中,第一清潔製程的氣體流量可大於第二清潔製程的氣體流量。舉例來說,在第一清潔製程期間,經由導管137流入的氣體的流量可以大於在第二清潔製程期間,經由導管144流入的氣體的流量。另一方面,在第一清潔製程的氣體的壓力可以大於第二清潔製程的氣體壓力。舉例來說,在第一清潔製程期間,經由導管137流入的氣體的壓力可以大於在第二清潔製程期間,經由導管144流入的氣體的壓力。這是由於髒汙較容易堆積在基板支撐件126的中心部分126C,因此在第一清潔製程期間藉由導管137流入較高流量的氣體將有助於快速的清潔基板支撐件126的中心部分126C。在部分實施例中,第一清潔製程的持續時間可以短於第二清潔製程的持續時間。如前述所提及,由於第一清潔製程期間的氣體流量較高,所第一清潔製程的持續時間太長 (例如長於第二清潔製程的時間),則可能會對半導體處理腔室100的其他組件造成不必要的蝕刻或破壞。In some embodiments, the gas flow rate of the first cleaning process may be greater than the gas flow rate of the second cleaning process. For example, during the first cleaning process, the flow rate of gas flowing in via
在部分實施例中,在第一清潔製程進行時,可先關閉閥V2,以避免氣體自導管144流入至半導體處理腔室100內。也就是說,在第一清潔製程進行時,氣體僅經由基板支撐件126內的導管137流入至半導體處理腔室100。另一方面,在第二清潔製程進行時,可先關閉閥V1,以避免氣體自導管137流入至半導體處理腔室100內。也就是說,在第二清潔製程進行時,氣體僅經由半導體處理腔室100的側壁104的導管144流入至半導體處理腔室100。In some embodiments, during the first cleaning process, the valve V2 may be closed first to prevent gas from flowing into the
在第4圖的實施例中, 操作S105是在操作106前執行,即第一清潔製程是在第二清潔製程之前執行。在其他實施例中,操作S106可在操作105前執行,即第二清潔製程是在第一清潔製程之前執行。In the embodiment of FIG. 4, operation S105 is performed before
第8A圖為用作控制器(例如,系統控制器190)之電腦系統的示意圖,此控制器用於執行與運動的監控、執行及控制有關之任務,以及在半導體處理腔室100中執行之各種製程配方任務及配方步驟。可使用電腦硬體及在其上執行之電腦程式實現前述實施方式。在第8A圖中,電腦系統600具備電腦601,此電腦601包含光碟唯讀記憶體(例如,CD-ROM或DVD-ROM)驅動器(光碟機)605及磁碟驅動器(磁碟機)606、鍵盤602、滑鼠603及顯示器604。FIG. 8A is a schematic diagram of a computer system used as a controller (eg, system controller 190 ) for performing tasks related to the monitoring, execution, and control of motion, as well as various tasks performed in
第8B圖為繪示電腦系統600之內部配置的圖式。在第8B圖中,除了光碟機605及磁碟機606以外,電腦601還具備一或更多個處理器611,像是,微處理單元(micro processing unit; MPU);ROM 612,其中儲存有像是啟動程式之程式;隨機存取記憶體(random access memory; RAM)613,其連接至MPU 611且其中臨時儲存應用程式之命令並提供臨時儲存區域;硬碟614,其中儲存有應用程式、系統程式及資料;及匯流排615,其連接MPU 611、ROM 612等。應注意,電腦601可包含用於提供與LAN之連接的網路卡(未繪示)。FIG. 8B is a diagram showing the internal configuration of the
用於使電腦系統600執行前述實施方式中所論述之操作/任務的程式碼可被儲存在光碟621或磁碟622中,其被***至光碟機605或磁碟機606中並被傳輸至硬碟614。或者,可經由網路(未繪示)將程式傳輸至電腦601並將其儲存在硬碟614中。在執行時,程式被加載至RAM 613中。可自光碟621或磁碟622或直接自網路加載程式。The code for causing the
在程式中,程式所實現之功能不包含在一些實施方式中可僅藉由硬體實現之功能。舉例來說,在藉由上述程式所實現之功能中不包含在獲取資訊之獲取單元或輸出資訊之輸出單元中可僅藉由硬體(像是,網路介面)實現的功能。另外,執行程式之電腦可為單個電腦或可為多個電腦。In the program, the functions implemented by the program do not include functions that can be implemented only by hardware in some embodiments. For example, the functions implemented by the above programs do not include functions that can be implemented only by hardware (eg, a network interface) in an acquisition unit for acquiring information or an output unit for outputting information. In addition, the computer executing the program may be a single computer or may be multiple computers.
本揭露的一實施例為一種沉積室的清潔方法,包含將基板移動至半導體處理腔室的基板支撐件上;執行沉積製程,以在基板上沉積材料層;將基板移出半導體處理腔室;執行第一清潔製程,其中執行第一清潔製程包括經由基板支撐件內的第一導管提供第一氣體至半導體處理腔室內,以及開啟射頻源以產生第一氣體的電漿以清潔基板支撐件的表面;以及執行第二清潔製程,其中執行第二清潔製程包括經由配置於半導體處理腔室的側壁的第二導管提供第二氣體至半導體處理腔室內,以及開啟射頻源以產生第二氣體的電漿以清潔基板支撐件的表面。An embodiment of the present disclosure is a method of cleaning a deposition chamber, including moving a substrate onto a substrate support of a semiconductor processing chamber; performing a deposition process to deposit a material layer on the substrate; moving the substrate out of the semiconductor processing chamber; performing a first cleaning process, wherein performing the first cleaning process includes providing a first gas into the semiconductor processing chamber through a first conduit in the substrate support, and turning on a radio frequency source to generate a plasma of the first gas to clean the surface of the substrate support and performing a second cleaning process, wherein performing the second cleaning process includes providing a second gas into the semiconductor processing chamber through a second conduit disposed on a sidewall of the semiconductor processing chamber, and turning on a radio frequency source to generate a plasma of the second gas to clean the surface of the substrate support.
根據部分實施例,方法還包含在執行第二清潔製程前,停止提供第一氣體至半導體處理腔室內。According to some embodiments, the method further includes stopping supplying the first gas into the semiconductor processing chamber before performing the second cleaning process.
根據部分實施例,其中第一氣體的流量大於第二氣體的流量。According to some embodiments, the flow rate of the first gas is greater than the flow rate of the second gas.
根據部分實施例,其中第二清潔製程在第一清潔製程之前執行。According to some embodiments, wherein the second cleaning process is performed before the first cleaning process.
本揭露的一實施例為一種沉積室的清潔方法,包含將一基板移動至一半導體處理腔室的基板支撐件上;執行一沉積製程,以在基板上沉積材料層;將基板移出半導體處理腔室;執行第一清潔製程,其中執行第一清潔製程包括在半導體處理腔室內產生第一電漿以清潔基板支撐件的表面,第一電漿在基板支撐件的表面的中心部分的清潔速率大於在表面的周邊部分的清潔速率;以及執行第二清潔製程,其中執行第二清潔製程包括在半導體處理腔室內產生第二電漿以清潔基板支撐件的表面,第二電漿在基板支撐件的表面的周邊部分的清潔速率大於在表面的中心部分的清潔速率。An embodiment of the present disclosure is a method for cleaning a deposition chamber, including moving a substrate onto a substrate support of a semiconductor processing chamber; performing a deposition process to deposit a material layer on the substrate; and moving the substrate out of the semiconductor processing chamber a chamber; performing a first cleaning process, wherein performing the first cleaning process includes generating a first plasma within the semiconductor processing chamber to clean the surface of the substrate support, the first plasma cleaning at a central portion of the surface of the substrate support at a rate greater than a cleaning rate at a peripheral portion of the surface; and performing a second cleaning process, wherein performing the second cleaning process includes generating a second plasma within the semiconductor processing chamber to clean the surface of the substrate support, the second plasma at the surface of the substrate support The cleaning rate of the peripheral portion of the surface is greater than the cleaning rate of the central portion of the surface.
根據部分實施例,其中產生第一電漿包括自基板支撐件的第一導管輸入第一氣體至半導體處理腔室內,而產生第二電漿包括自半導體處理腔室的側壁一第二導管輸入第二氣體至半導體處理腔室內。According to some embodiments, wherein generating the first plasma includes introducing a first gas from a first conduit of the substrate support into the semiconductor processing chamber, and generating the second plasma includes introducing a second gas from a sidewall of the semiconductor processing chamber through a second conduit. Two gases into the semiconductor processing chamber.
根據部分實施例,其中第一氣體的壓力大於第二氣體的壓力。According to some embodiments, the pressure of the first gas is greater than the pressure of the second gas.
本揭露的一實施例為一種沉積室的清潔方法,包含在一半導體處理腔室內執行沉積製程,以在基板支撐件上方的基板上沉積材料層;確認基板與基板支撐件之間的一偏壓是否正常;若偏壓不正常,則執行第一清潔製程,其中執行第一清潔製程包括在半導體處理腔室內產生第一電漿以清潔基板支撐件的表面,第一電漿在基板支撐件的表面的一中心部分的濃度大於在表面的一周邊部分的濃度;以及執行第二清潔製程,其中執行第二清潔製程包括在半導體處理腔室內產生第二電漿以清潔基板支撐件的表面,第二電漿在基板支撐件的表面的周邊部分的濃度大於在表面的中心部分的濃度。An embodiment of the present disclosure is a method of cleaning a deposition chamber, including performing a deposition process in a semiconductor processing chamber to deposit a material layer on a substrate above a substrate support; confirming a bias voltage between the substrate and the substrate support Whether it is normal; if the bias voltage is abnormal, perform a first cleaning process, wherein performing the first cleaning process includes generating a first plasma in the semiconductor processing chamber to clean the surface of the substrate support, and the first plasma is in the substrate support. a central portion of the surface has a greater concentration than a peripheral portion of the surface; and performing a second cleaning process, wherein performing the second cleaning process includes generating a second plasma within the semiconductor processing chamber to clean the surface of the substrate support, the first The concentration of the second plasma is greater in the peripheral portion of the surface of the substrate support than in the central portion of the surface.
根據部分實施例,其中產生第一電漿包括自基板支撐件的第一導管輸入第一氣體至半導體處理腔室內,而產生第二電漿包括自半導體處理腔室的側壁第二導管輸入第二氣體至半導體處理腔室內。According to some embodiments, wherein generating the first plasma includes feeding a first gas into the semiconductor processing chamber from a first conduit of the substrate support, and generating the second plasma includes feeding a second gas from a second conduit in a sidewall of the semiconductor processing chamber gas into the semiconductor processing chamber.
根據部分實施例,其中在執行第一清潔製程期間,關閉第二導管的閥以停止輸入第二氣體至半導體處理腔室內,而在執行第二製程期間,關閉第一導管的閥以停止輸入第一氣體至半導體處理腔室內。According to some embodiments, during the execution of the first cleaning process, the valve of the second conduit is closed to stop the input of the second gas into the semiconductor processing chamber, and during the execution of the second process, the valve of the first conduit is closed to stop the input of the second gas. A gas is injected into the semiconductor processing chamber.
前文概括了若干實施例的特徵,使得熟習此項技術者可更好地理解本揭露內容的態樣。熟習此項技術者應瞭解,其可易於將本揭露內容用作用於設計或修改其他處理程序及結構以用於實行相同目的及/或達成本文中介紹的實施例的相同優勢的基礎。熟習此項技術者亦應認識到,此等等效構造不脫離本揭露內容的精神及範疇,且在不脫離本揭露內容的精神及範疇的情況下,其可進行各種改變、取代及更改。The foregoing summarizes features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments presented herein. Those skilled in the art should also realize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions and alterations may be made therein without departing from the spirit and scope of the present disclosure.
100:半導體處理腔室 101:腔室主體 102:配接器 103:群集工具 104:側壁 105:基板 106:底壁 108:上部處理組件 110:處理區域 120:底座組件 122:升舉機構 123:升舉銷 124:波紋管 126:基板支撐件 126A:電極 126C:中心部分 126P:周邊部分 127:基板接收表面 128:平臺外殼 129:周邊邊緣 130:蓋組件 132:靶材 133:濺射表面 134:背面區域 136:陶瓷靶材隔離件 137:導管 138:氣源 140:功率源 141:阻抗控制器 142:氣源 143:靜電吸盤電源 144:導管 146:排氣埠 147:閘閥 148:排氣導管 149:排氣泵 151:內環 152:外環 154:座 156:錐形部分 157:內圓周端部 159:外圓周表面 160:接地屏蔽 162:內部表面 170:交錯覆蓋環 171:唇部 173:塗層 180:沉積環 181:RF源 181A:RF功率源 181B:RF匹配器 182:DC源 182A:DC電源 184:中心饋電 185:導電壁 186:屏蔽罩 189:磁控系統 190:系統控制器 191:蓋殼 193:馬達 202:偏壓感測器 302:基板 304:蝕刻停止層 306:絕緣層 308:硬遮罩 310:光阻層 320:間隔物層 325:溝槽 600:電腦系統 601:電腦 602:鍵盤 603:滑鼠 604:顯示器 605:光碟機 606:磁碟機 611:MPU 612:ROM 613:RAM 614:硬碟 615:匯流排 621:光碟 622:磁碟 M1:方法 S101,S102,S103,S104,S105,S106:操作 100: Semiconductor processing chamber 101: Chamber body 102: Adapter 103: Cluster Tools 104: Sidewall 105: Substrate 106: Bottom Wall 108: Upper processing assembly 110: Processing area 120: Base assembly 122: Lifting mechanism 123: Lifting Pin 124: Bellows 126: substrate support 126A: Electrode 126C: Center Section 126P: Peripheral part 127: Substrate receiving surface 128: Platform Shell 129: Perimeter Edge 130: Cover assembly 132: Target 133: Sputtering Surface 134: Back area 136: Ceramic target spacer 137: Catheter 138: Air source 140: Power source 141: Impedance Controller 142: Air source 143: Electrostatic chuck power supply 144: Catheter 146: exhaust port 147: Gate valve 148: Exhaust duct 149: Exhaust pump 151: inner ring 152: Outer Ring 154: Block 156: Tapered part 157: End of inner circumference 159: Outer circumference surface 160: Ground Shield 162: Internal Surface 170: Staggered Cover Rings 171: Lips 173: Coating 180: Deposition Ring 181: RF Source 181A: RF Power Source 181B: RF Matcher 182: DC source 182A: DC power 184: Center Feed 185: Conductive Wall 186: Shield 189: Magnetic Control System 190: System Controller 191: cover shell 193: Motor 202: Bias sensor 302: Substrate 304: etch stop layer 306: Insulation layer 308: hard mask 310: photoresist layer 320: Spacer Layer 325: Groove 600: Computer System 601: Computer 602: Keyboard 603: Mouse 604: Display 605: CD player 606: Disk Drive 611: MPU 612: ROM 613: RAM 614: Hard Disk 615: Busbar 621: CD 622: Disk M1: Method S101, S102, S103, S104, S105, S106: Operation
當藉由附圖閱讀時,自以下詳細描述,最佳地理解本揭露內容的態樣。注意,根據該行業中的標準實務,各種特徵未按比例繪製。事實上,為了論述的清晰起見,可任意地增大或減小各種特徵的尺寸。 第1圖為本揭露之部分實施例之半導體處理腔室的示意圖。 第2圖為本揭露之部分實施例之基板支撐件的俯視圖。 第3A圖至第3D圖為本揭露之部分實施例之製造半導體結構在不同階段的剖面圖。 第4圖為本揭露之部分實施例之操作半導體處理腔室的方法。 第5圖至第7B圖為本揭露之部分實施例之操作半導體處理腔室的方法在不同階段的示意圖。 第8A圖及第8B圖為本揭露之部分實施例之電腦系統的示意圖。 Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Note that in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 is a schematic diagram of a semiconductor processing chamber according to some embodiments of the disclosure. FIG. 2 is a top view of a substrate support member according to some embodiments of the disclosure. FIGS. 3A to 3D are cross-sectional views at different stages of manufacturing a semiconductor structure according to some embodiments of the present disclosure. FIG. 4 is a method of operating a semiconductor processing chamber according to some embodiments of the present disclosure. FIGS. 5-7B are schematic views at different stages of a method of operating a semiconductor processing chamber according to some embodiments of the present disclosure. 8A and 8B are schematic diagrams of computer systems according to some embodiments of the present disclosure.
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無 Domestic storage information (please note in the order of storage institution, date and number) none Foreign deposit information (please note in the order of deposit country, institution, date and number) none
M1:方法 M1: Method
S101,S102,S103,S104,S105,S106:操作 S101, S102, S103, S104, S105, S106: Operation
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TW201027603A (en) * | 2009-01-08 | 2010-07-16 | United Microelectronics Corp | Method for cleaning semiconductor equipment |
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