TWI771821B

TWI771821B - Memory device

Info

Publication number: TWI771821B
Application number: TW109143041A
Authority: TW
Inventors: 胡志瑋; 葉騰豪
Original assignee: 旺宏電子股份有限公司
Priority date: 2020-12-07
Filing date: 2020-12-07
Publication date: 2022-07-21
Also published as: TW202224153A

Abstract

A memory device includes a stacked structure and at least one first element structure. The stacked structure is in a memory array region and a staircase contact region. The stacked structure includes first conductive layers and a second conductive layer arranged in a longitudinal direction. The memory array region and the staircase contact region are arranged in a first lateral direction. The at least one first element structure passes through the first conductive layers and the second conductive layer along the longitudinal direction. The first conductive layers surround a sidewall surface of the at least one first element structure. The second conductive layer includes conductive portions arranged in a second lateral direction. The conductive portions are completely separated from each other by the at least one first element structure. The first lateral direction is different from the second lateral direction.

Description

記憶體裝置 memory device

本發明是有關於一種記憶體裝置，且特別是有關於一種三維記憶體裝置。 The present invention relates to a memory device, and more particularly, to a three-dimensional memory device.

近年來，記憶體裝置的尺寸已逐漸縮小。在記憶體技術中，特徵尺寸的縮小、速度、效能、密度與每單位積體電路之成本的改良皆為相當重要的目標。在實際應用上，裝置尺寸縮小的同時，仍須保持裝置的電性以符合商業需求。 In recent years, the size of memory devices has been gradually reduced. In memory technology, feature size reduction, speed, performance, density, and cost per unit of integrated circuit improvement are all important goals. In practical applications, while the size of the device is reduced, the electrical properties of the device must still be maintained to meet commercial requirements.

本發明係有關於一種記憶體裝置。 The present invention relates to a memory device.

根據本揭露之一方面，提出一種記憶體裝置。記憶體裝置包括一堆疊結構及至少一個第一元件結構。堆疊結構在一記憶體陣列區與一階梯狀接觸區中，並包括排列在一縱方向上的數個第一導電層與一第二導電層。記憶體陣列區與階梯狀接觸區排列在一第一橫方向上。至少一個第一元件結構沿縱方向穿過此些第一導電層與第二導電層。此些第一導電層環繞至少一個第一元件結構的側壁表面。第二導電層包括排列在一第二橫方向上的數個導電部，此些導電部藉由至少一個第一元件結構彼此完全分開。第一橫方向不同於第二橫方向。 According to an aspect of the present disclosure, a memory device is provided. The memory device includes a stack structure and at least one first element structure. The stacked structure includes a plurality of first conductive layers and a second conductive layer arranged in a longitudinal direction in a memory array region and a stepped contact region. The memory array area and the stepped contact area are arranged in a first lateral direction. At least one first element structure passes through the first conductive layers and the second conductive layers in the longitudinal direction. The first conductive layers surround at least one first Sidewall surface of the element structure. The second conductive layer includes a plurality of conductive parts arranged in a second lateral direction, and the conductive parts are completely separated from each other by at least one first element structure. The first lateral direction is different from the second lateral direction.

為了對本發明之上述及其他方面有更佳的瞭解，下文特舉實施例，並配合所附圖式詳細說明如下： In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given and described in detail in conjunction with the accompanying drawings as follows:

100:記憶體裝置 100: Memory device

102:堆疊結構 102: Stacked Structure

104:第一元件結構 104: First element structure

104a:絕緣牆 104a: Insulated Walls

104b:導電元件 104b: Conductive elements

104s1:第一側壁表面 104s1: First sidewall surface

104s2:第二側壁表面 104s2: Second sidewall surface

104s3:第三側壁表面 104s3: Third sidewall surface

104s4:第四側壁表面 104s4: Fourth sidewall surface

106,106A~106D:第一導電層 106, 106A~106D: the first conductive layer

108:第二導電層 108: the second conductive layer

108a~108d:導電部 108a~108d: Conductive part

110:第二元件結構 110: Second element structure

110a:絕緣牆 110a: Insulated Walls

110b:導電元件 110b: Conductive elements

112:導電柱 112: Conductive column

114:接觸柱 114: Contact Column

116,116’:柱元件 116, 116': Column element

116a:通道柱 116a: Channel column

116b:記憶材料層 116b: Memory Material Layer

120,120P,120Q:第三元件結構 120, 120P, 120Q: The third element structure

120a:絕緣牆 120a: Insulated Walls

120b:導電元件 120b: Conductive elements

204:介電元件 204: Dielectric Components

222:導電元件 222: Conductive elements

402:堆疊結構 402: Stacked Structure

416,416’:柱元件 416, 416': Column element

416a:通道柱 416a: Channel column

416b:記憶材料層 416b: Memory Material Layer

418:絕緣層 418: Insulation layer

432:基板 432: Substrate

434:絕緣膜 434: insulating film

438,440,442:開口 438, 440, 442: Openings

502:堆疊結構 502: Stacked Structure

536:狹縫 536: Slit

606,606A~606D:第一導電層 606, 606A~606D: The first conductive layer

608:第二導電層 608: Second conductive layer

608a~608d:導電部 608a~608d: Conductive part

704a,710a,720a:絕緣牆 704a, 710a, 720a: Insulation Walls

704c,710c,720c:開口 704c, 710c, 720c: Opening

804b,810b,820b:導電元件 804b, 810b, 820b: Conductive elements

B:區塊 B: block

B1~B4:次區塊 B1~B4: Sub-block

GSL:接地選擇線 GSL: Ground Selection Line

SSL:串列選擇線 SSL: Serial select line

WL:字元線 WL: word line

M:記憶體陣列區 M: Memory array area

SC:階梯狀接觸區 SC: stepped contact area

X:第一橫方向 X: the first horizontal direction

Y:第二橫方向 Y: the second horizontal direction

Z:縱方向 Z: vertical direction

第1A圖繪示根據一實施例之記憶體裝置之上視圖。 Figure 1A shows a top view of a memory device according to one embodiment.

第1B圖繪示第1A圖之記憶體裝置之堆疊結構之立體示意圖。 FIG. 1B is a three-dimensional schematic view of the stacked structure of the memory device of FIG. 1A .

第1C圖繪示第1A圖之記憶體裝置之第一導電層及對應第一導電層的其他元件的橫向剖面圖。 FIG. 1C is a lateral cross-sectional view of the first conductive layer of the memory device of FIG. 1A and other elements corresponding to the first conductive layer.

第2圖繪示一比較例中記憶體裝置對應一個記憶區塊部分的上視圖。 FIG. 2 is a top view of a portion of the memory device corresponding to one memory block in a comparative example.

第3圖至第7圖繪示根據一實施例之記憶體裝置的製造方法。 3 to 7 illustrate a method of fabricating a memory device according to an embodiment.

以下係以一些實施例做說明。須注意的是，本揭露並非顯示出所有可能的實施例，未於本揭露提出的其他實施態樣也可能可以應用。再者，圖式上的尺寸比例並非按照實際產品等比例繪製。因此，說明書和圖示內容僅作敘述實施例之用，而非作為限縮本揭露保護範圍之用。另外，實施例中之敘述，例如細部結構、製程步驟和材料應用等等，僅為舉例說明之用，並非對本揭露欲保護之範圍做限縮。實施例之步驟和結構各自細節可在不脫離本揭露之精神和範圍內根據實際應用製程之需要而加以變化與修飾。以下是以相同/類似的符號表示相同/類似的元件做說明。 The following are some examples to illustrate. It should be noted that this disclosure does not show all possible embodiments, and other implementation aspects not proposed in this disclosure may also be applicable. Furthermore, the size ratios in the drawings are not drawn according to the actual product scale. Therefore, the contents of the description and illustrations are only used to describe the embodiments, not It is used to limit the scope of protection of this disclosure. In addition, the descriptions in the embodiments, such as detailed structures, process steps, and material applications, etc., are for illustrative purposes only, and are not intended to limit the scope of protection of the present disclosure. The details of the steps and structures of the embodiments can be changed and modified according to the needs of the actual application process without departing from the spirit and scope of the present disclosure. In the following, the same/similar symbols are used to represent the same/similar elements for description.

說明書與請求項中所使用的序數例如「第一」、「第二」、「第三」等之用詞，以修飾請求項之元件，其本身並不意含及代表此元件有任何之前的序數，也不代表某一元件與另一元件的順序、或是製造方法上的順序，此些序數的使用僅用來使具有某命名的一元件得以和另一具有相同命名的元件能作出清楚區分。 The ordinal numbers used in the specification and the claims, such as "first", "second", "third", etc., are used to modify the elements of the claim, and they do not imply and represent that this element has any previous ordinal numbers. , does not represent the order of a certain element and another element, or the order of the manufacturing method, the use of these ordinal numbers is only used to make an element with a certain name and another element with the same name can be clearly distinguished .

第1A圖繪示根據一實施例之記憶體裝置100之上視圖。第1B圖繪示第1A圖之記憶體裝置100之堆疊結構102之立體示意圖。 FIG. 1A illustrates a top view of a memory device 100 according to one embodiment. FIG. 1B is a three-dimensional schematic diagram of the stacked structure 102 of the memory device 100 of FIG. 1A.

請參照第1A圖及第1B圖。記憶體裝置100可包括堆疊結構102及第一元件結構104。舉例而言，記憶體裝置100可包括反及閘快閃記憶體(NAND flash memory)。 Please refer to Figure 1A and Figure 1B. The memory device 100 may include a stack structure 102 and a first device structure 104 . For example, the memory device 100 may include NAND flash memory.

堆疊結構102在一記憶體陣列區M與一階梯狀接觸區SC中，且記憶體陣列區M與階梯狀接觸區SC排列在一第一橫方向X上。堆疊結構102包括在一縱方向Z(例如垂直方向)上交錯堆疊在基板432(如第1B圖及第3圖所示)上的導電層與絕緣層(如第4圖所示，絕緣層418)。導電層包括第一導電層106(例如第一導電層106A~106D)與一第二導電層108。第二導電層108在第一導電層106上方。舉例而言，基板432可包括半導體材料，例如矽或多晶矽(poly-silicon)，但本揭露不以此為限。堆疊結構102的下階層(lower level)(或階梯狀接觸區SC中堆疊結構102的下階梯階層(lower stair level))可包括一第一導電層106與一絕緣層418在第一導電層106下方。堆疊結構102的上階層(upper level)(或階梯狀接觸區SC中堆疊結構102的上階梯階層(upper stair level))可包括一第二導電層108與一絕緣層418在第二導電層108下方。 The stacked structure 102 is in a memory array region M and a stepped contact region SC, and the memory array region M and the stepped contact region SC are arranged in a first lateral direction X. The stacked structure 102 includes conductive layers and insulating layers stacked on a substrate 432 (as shown in FIGS. 1B and 3 ) staggered in a longitudinal direction Z (eg, a vertical direction). layer (as shown in Figure 4, insulating layer 418). The conductive layers include a first conductive layer 106 (eg, first conductive layers 106A˜ 106D ) and a second conductive layer 108 . The second conductive layer 108 is over the first conductive layer 106 . For example, the substrate 432 may include a semiconductor material, such as silicon or poly-silicon, but the disclosure is not limited thereto. The lower level of the stacked structure 102 (or the lower stair level of the stacked structure 102 in the stepped contact area SC) may include a first conductive layer 106 and an insulating layer 418 on the first conductive layer 106 below. The upper level of the stacked structure 102 (or the upper stair level of the stacked structure 102 in the stepped contact area SC) may include a second conductive layer 108 and an insulating layer 418 on the second conductive layer 108 below.

第一元件結構104延伸在第一橫方向X上。第一元件結構104可包括一絕緣牆104a及一導電元件104b。絕緣牆104a具有封閉的矩形狀，且絕緣牆104a環繞導電元件104b。導電元件104b藉由絕緣牆104a電性絕緣第一導電層106A~106D與第二導電層108。一實施例中，導電元件104b可用作一共同源極線(CSL)。舉例而言，導電元件104b可包括導電材料，例如鎢(W)，但本揭露不以此為限。 The first element structure 104 extends in the first lateral direction X. The first element structure 104 may include an insulating wall 104a and a conductive element 104b. The insulating wall 104a has a closed rectangular shape, and the insulating wall 104a surrounds the conductive element 104b. The conductive element 104b electrically insulates the first conductive layers 106A- 106D from the second conductive layer 108 by the insulating wall 104a. In one embodiment, the conductive element 104b can be used as a common source line (CSL). For example, the conductive element 104b may include a conductive material, such as tungsten (W), but the present disclosure is not limited thereto.

第一元件結構104的絕緣牆104a包括一第一側壁表面104s1、一第二側壁表面104s2、一第三側壁表面104s3及一第四側壁表面104s4。第二側壁表面104s2相對於第一側壁表面104s1。第三側壁表面104s3在第一側壁表面104s1與第二側壁表面104s2之間。第四側壁表面104s4相對於第三側壁表面104s3，且第四側壁表面104s4在第一側壁表面104s1與第二側壁表面104s2之間。 The insulating wall 104a of the first element structure 104 includes a first sidewall surface 104s1, a second sidewall surface 104s2, a third sidewall surface 104s3 and a fourth sidewall surface 104s4. The second sidewall surface 104s2 is opposite to the first sidewall surface 104s1. The third sidewall surface 104s3 is between the first sidewall surface 104s1 and the second sidewall surface 104s2. The fourth sidewall surface 104s4 is opposite to the third sidewall surface 104s3, And the fourth sidewall surface 104s4 is between the first sidewall surface 104s1 and the second sidewall surface 104s2.

絕緣層418(如第4圖所示)環繞第一元件結構104的側壁表面。絕緣層418可環繞第一元件結構104的絕緣牆104a的第一側壁表面104s1、第二側壁表面104s2、第三側壁表面104s3及第四側壁表面104s4。 An insulating layer 418 (shown in FIG. 4 ) surrounds the sidewall surfaces of the first element structure 104 . The insulating layer 418 may surround the first sidewall surface 104s1 , the second sidewall surface 104s2 , the third sidewall surface 104s3 and the fourth sidewall surface 104s4 of the insulating wall 104 a of the first device structure 104 .

第二導電層108包括排列在第二橫方向Y上的導電部(例如導電部108a~108d)。導電部108a~108d藉由第一元件結構104彼此完全分開。導電部(例如導電部108a~108d)位於第一導電層106(例如第一導電層106A~106D)的上方。第一橫方向X可實質上垂直於第二橫方向Y。 The second conductive layer 108 includes conductive parts (eg, the conductive parts 108 a to 108 d ) arranged in the second lateral direction Y. The conductive parts 108 a - 108 d are completely separated from each other by the first element structure 104 . The conductive parts (eg, the conductive parts 108a - 108d ) are located above the first conductive layer 106 (eg, the first conductive layers 106A - 106D). The first lateral direction X may be substantially perpendicular to the second lateral direction Y.

第一導電層106包括數個字元線(WL)及一接地選擇線(GSL)。一實施例中，第一導電層106A用作接地選擇線，第一導電層106B~106D用作字元線，且第二導電層108的導電部(例如導電部108a~108d)用作串列選擇線(SSL)。用作字元線之第一導電層106B~106D位於用作接地選擇線之第一導電層106A與用作串列選擇線之導電部108a~108d之間。圖式雖僅畫出3層字元線(第一導電層106B~106D)，但本發明不限於此，接地選擇線(第一導電層106A)與串列選擇線(導電部)之間可配置其它更多數目的字元線。 The first conductive layer 106 includes several word lines (WL) and a ground select line (GSL). In one embodiment, the first conductive layer 106A is used as a ground select line, the first conductive layers 106B to 106D are used as word lines, and the conductive parts of the second conductive layer 108 (eg, conductive parts 108a to 108d ) are used as tandem Select Line (SSL). The first conductive layers 106B to 106D used as word lines are located between the first conductive layers 106A used as ground select lines and the conductive portions 108a to 108d used as string select lines. Although only three layers of word lines (the first conductive layers 106B to 106D) are shown in the drawings, the invention is not limited to this. The ground selection line (the first conductive layer 106A) and the string selection line (conductive portion) may be Configure another larger number of word lines.

第一元件結構104沿縱方向Z穿過記憶體陣列區M的第一導電層106、第二導電層108與絕緣層418。第一元件結構104可延伸至部分的階梯狀接觸區SC，在縱方向Z上穿過部分的階梯狀接觸區SC的第一導電層106與絕緣層418。 The first device structure 104 passes through the first conductive layer 106 , the second conductive layer 108 and the insulating layer 418 of the memory array region M along the longitudinal direction Z. first element junction The structure 104 may extend to a portion of the stepped contact area SC, and pass through the first conductive layer 106 and the insulating layer 418 of the portion of the stepped contact area SC in the longitudinal direction Z. As shown in FIG.

第1C圖繪示第1A圖之記憶體裝置100之第一導電層106D及對應第一導電層106D的其它元件的橫向剖面圖。 FIG. 1C is a lateral cross-sectional view of the first conductive layer 106D of the memory device 100 of FIG. 1A and other elements corresponding to the first conductive layer 106D.

請參照第1A圖至第1C圖。第一導電層106環繞第一元件結構104的側壁表面。第一導電層106可環繞第一元件結構104的第一側壁表面104s1、第二側壁表面104s2、第三側壁表面104s3及第四側壁表面104s4。第一導電層106(例如第一導電層106A~106D)直接接觸絕緣牆104a的第一側壁表面104s1、第二側壁表面104s2、第三側壁表面104s3及第四側壁表面104s4。 Please refer to Figures 1A to 1C. The first conductive layer 106 surrounds the sidewall surface of the first element structure 104 . The first conductive layer 106 may surround the first sidewall surface 104s1 , the second sidewall surface 104s2 , the third sidewall surface 104s3 and the fourth sidewall surface 104s4 of the first device structure 104 . The first conductive layer 106 (eg, the first conductive layers 106A to 106D) directly contacts the first sidewall surface 104s1 , the second sidewall surface 104s2 , the third sidewall surface 104s3 and the fourth sidewall surface 104s4 of the insulating wall 104a.

第二導電層108的導電部108a、108b分別在第一元件結構104的第二側壁表面104s2與第一側壁表面104s1上。 The conductive portions 108a and 108b of the second conductive layer 108 are respectively on the second sidewall surface 104s2 and the first sidewall surface 104s1 of the first element structure 104 .

請參照第1A圖及第1B圖。一實施例中，記憶體裝置100可選擇性地包括第二元件結構110。另一實施例中，記憶體裝置100可省略第二元件結構110。 Please refer to Figure 1A and Figure 1B. In one embodiment, the memory device 100 may optionally include the second device structure 110 . In another embodiment, the memory device 100 may omit the second element structure 110 .

第二元件結構110可包括一絕緣牆110a及一導電元件110b。第二元件結構110位於階梯狀接觸區SC中。第一元件結構104係分離於第二元件結構110。第二元件結構110沿縱方向Z穿過階梯狀接觸區SC中的第一導電層106A~106C與絕緣層418。絕緣牆110a具有封閉的矩形狀，且絕緣牆110a環繞導電元件110b。第二元件結構110的導電元件110b藉由絕緣牆110a電性絕緣第一導電層106。舉例而言，導電元件110b可包括導電材料，例如鎢(W)，但本揭露不以此為限。 The second element structure 110 may include an insulating wall 110a and a conductive element 110b. The second element structure 110 is located in the stepped contact region SC. The first element structure 104 is separated from the second element structure 110 . The second element structure 110 passes through the first conductive layers 106A to 106C and the insulating layer 418 in the stepped contact region SC along the longitudinal direction Z. The insulating wall 110a has a closed rectangular shape, and the insulating wall 110a surrounds the conductive element 110b. The conductive element 110b of the second element structure 110 is electrically insulated from the first conductive layer 106 by the insulating wall 110a. For example, the conductive element 110b may include a conductive material material, such as tungsten (W), but the present disclosure is not limited thereto.

請參照第1A圖及第1B圖。記憶體裝置100可更包括導電柱112及接觸柱114。 Please refer to Figure 1A and Figure 1B. The memory device 100 may further include conductive pillars 112 and contact pillars 114 .

導電柱112及接觸柱114位於階梯狀接觸區SC之中。導電柱112電性連接在第一導電層106上。接觸柱114電性連接在第二導電層108的導電部(例如導電部108a~108d)上。導電柱112的縱向尺寸係大於接觸柱114的縱向尺寸。電性連接第二導電層108的接觸柱114的數量可不同於導電柱112中電性連接一個第一導電層106(例如第一導電層106A~106D其中一個第一導電層)的部分的數量。一實施例中，電性連接第二導電層108的接觸柱114的數量(例如於第1A圖、第1B圖所示，數量為4個)可大於電性連接一個第一導電層106的導電柱112的數量(例如於第1A圖、第1B圖所示，導電柱數量為1個)。另一實施例中，電性連接一個第一導電層106的導電柱112的數量亦可為其他合適的數量。 The conductive pillars 112 and the contact pillars 114 are located in the stepped contact area SC. The conductive pillars 112 are electrically connected to the first conductive layer 106 . The contact pillars 114 are electrically connected to the conductive parts (eg, the conductive parts 108 a - 108 d ) of the second conductive layer 108 . The longitudinal dimension of the conductive post 112 is larger than the longitudinal dimension of the contact post 114 . The number of the contact pillars 114 electrically connected to the second conductive layer 108 may be different from the number of portions of the conductive pillars 112 that are electrically connected to a first conductive layer 106 (eg, one of the first conductive layers 106A to 106D). . In one embodiment, the number of the contact pillars 114 electrically connected to the second conductive layer 108 (for example, as shown in FIG. 1A and FIG. 1B , the number is 4) may be greater than the number of conductive columns 114 electrically connected to one first conductive layer 106 The number of the pillars 112 (for example, as shown in FIG. 1A and FIG. 1B , the number of conductive pillars is one). In another embodiment, the number of the conductive pillars 112 electrically connected to one of the first conductive layers 106 may also be other suitable numbers.

根據本實施例，由於電性連接一個第一導電層106(例如第一導電層106A~106D其中一個第一導電層)的導電柱112的數量係小於電性連接第二導電層108的接觸柱114的數量，可進一步減少導電柱112的數量，從而具有製程簡化、降低製造成本等優點。 According to the present embodiment, the number of conductive pillars 112 electrically connected to one first conductive layer 106 (eg, one of the first conductive layers 106A to 106D) is smaller than the number of contact pillars electrically connected to the second conductive layer 108 The number of 114 can further reduce the number of conductive pillars 112, which has the advantages of simplifying the process and reducing the manufacturing cost.

請參照第1A圖及第1B圖。記憶體裝置100可更包括柱元件116及柱元件116’。 Please refer to Figure 1A and Figure 1B. The memory device 100 may further include a pillar element 116 and a pillar element 116'.

柱元件116位於記憶體陣列區M之中。柱元件116可包括一通道柱116a及一記憶材料層116b，且記憶材料層116b位於通道柱116a的側壁表面上。柱元件116可在縱方向Z上穿過堆疊結構102至最底階層。通道柱116a的上端可電性連接至位元線(BL)。通道柱116a的下端可經過基板432電性連接至共同源極線(CSL)。通道柱116a亦可稱為主動柱(active pillar)。通道柱116a位於記憶體陣列區M之中，且穿過堆疊結構102。數個記憶胞定義在用作字元線的第一導電層106(例如第一導電層106B~106D)與通道柱116a的交錯處的記憶材料層116b中。 The pillar elements 116 are located in the memory array region M. As shown in FIG. The pillar element 116 may include a channel pillar 116a and a memory material layer 116b, and the memory material layer 116b is located on the sidewall surface of the channel pillar 116a. The column elements 116 can pass through the stack structure 102 in the longitudinal direction Z to the bottommost level. The upper end of the channel pillar 116a may be electrically connected to the bit line (BL). The lower ends of the channel pillars 116a may be electrically connected to the common source line (CSL) through the substrate 432 . The channel pillar 116a may also be referred to as an active pillar. The channel pillars 116 a are located in the memory array region M and pass through the stack structure 102 . Several memory cells are defined in the memory material layer 116b at the intersection of the first conductive layer 106 (eg, the first conductive layers 106B to 106D) serving as word lines and the channel pillars 116a.

柱元件116’位於階梯狀接觸區SC之中。柱元件116’可包括一通道柱及一記憶材料層，且記憶材料層位於通道柱的側壁表面上。柱元件116’可在縱方向Z上穿過堆疊結構102至最底階梯層。柱元件116’(通道柱)可為電性浮接，並用作虛置柱元件(dummy pillar element)。一實施例中，柱元件116’的材料組合係相同於柱元件116的材料組合。另一實施例中，柱元件116’的材料組合係不同於柱元件116的材料組合。 The column element 116' is located in the stepped contact area SC. The pillar element 116' may include a channel pillar and a memory material layer, and the memory material layer is located on the sidewall surface of the channel pillar. The pillar elements 116' may pass through the stack structure 102 in the longitudinal direction Z to the bottommost stepped layer. The pillar elements 116' (channel pillars) may be electrically floating and function as dummy pillar elements. In one embodiment, the material combination of the column elements 116' is the same as the material combination of the column elements 116. In another embodiment, the material combination of the column elements 116' is different from the material combination of the column elements 116.

請參照第1A圖及第1B圖。記憶體裝置100可更包括第三元件結構120(例如第三元件結構120P與第三元件結構120Q)。 Please refer to Figure 1A and Figure 1B. The memory device 100 may further include a third element structure 120 (eg, a third element structure 120P and a third element structure 120Q).

第三元件結構120可包括一絕緣牆120a及一導電元件120b。第三元件結構120沿第一橫方向X穿過記憶體陣列區M與階梯狀接觸區SC。絕緣牆120a具有封閉的矩形狀，且絕緣牆 120a環繞導電元件120b。導電元件120b藉由絕緣牆120a電性絕緣第一導電層106A~106D與第二導電層108。 The third element structure 120 may include an insulating wall 120a and a conductive element 120b. The third device structure 120 passes through the memory array region M and the stepped contact region SC along the first lateral direction X. The insulating wall 120a has a closed rectangular shape, and the insulating wall 120a surrounds conductive element 120b. The conductive element 120b electrically insulates the first conductive layers 106A- 106D from the second conductive layer 108 by the insulating wall 120a.

一個區塊(one block)B(或者，一個記憶區塊(one memory block))的數個記憶胞位於第三元件結構120P與第三元件結構120Q之間的記憶體陣列區M中的堆疊結構102中。一個區塊B的記憶胞可由對應的一個字元線驅動器(未顯示)選擇或控制，或同時進行抹除。第1A圖顯示兩個記憶區塊。第1B圖顯示一個記憶區塊。 A stack structure in which several memory cells of one block B (or, one memory block) are located in the memory array region M between the third element structure 120P and the third element structure 120Q 102. A memory cell of block B can be selected or controlled by a corresponding word line driver (not shown), or erased at the same time. Figure 1A shows two memory blocks. Figure 1B shows a memory block.

一個區塊B包括數個次區塊(sub-blocks)(例如4個次區塊B1~B4)的數個記憶胞。次區塊B1~B4的記憶胞分別在第一元件結構104的兩側。一個次區塊(或者，一個次記憶區塊)的記憶胞可由對應的一個串列選擇線(導電部108a~108d其中一個)控制選擇/未選擇。舉例而言，導電元件120b可包括導電材料，例如鎢(W)，但本揭露不以此為限。 A block B includes several memory cells of several sub-blocks (for example, four sub-blocks B1-B4). The memory cells of the sub-blocks B1 to B4 are respectively located on both sides of the first element structure 104 . The memory cells of a sub-block (or, a sub-memory block) can be controlled to be selected/unselected by a corresponding serial selection line (one of the conductive parts 108a-108d). For example, the conductive element 120b may include a conductive material, such as tungsten (W), but the present disclosure is not limited thereto.

第一元件結構104在第一橫方向X上的長度係小於第三元件結構120在第一橫方向X上的長度。第二元件結構110在第一橫方向X上的長度係小於第三元件結構120在第一橫方向X上的長度。 The length of the first element structure 104 in the first lateral direction X is smaller than the length of the third element structure 120 in the first lateral direction X. The length of the second element structure 110 in the first lateral direction X is smaller than the length of the third element structure 120 in the first lateral direction X.

請參照第2圖，其繪示一比較例中記憶體裝置對應一個記憶區塊部分的上視圖。介電元件204延伸穿過記憶體陣列區M與階梯狀接觸區SC中堆疊結構的接地選擇線GSL、字元線WL、與對應於次記憶區塊的串列選擇線SSL。藉由介電元件204 彼此電性絕緣的字元線WL與接地選擇線GSL上各具有一個導電柱112。電性連接相同階層的字元線WL(或接地選擇線GSL)的導電柱112是藉由延伸在介電元件204上方的導電元件222(包括例如金屬層，例如第零層金屬層(ML0))彼此電性連接。如第2圖所示的比較例中，對應於一個記憶區塊的相同階層的字元線WL(或接地選擇線GSL)上的導電柱112的數量為4個，等於電性連接串列選擇線SSL的接觸柱114的數量(即4個)。 Please refer to FIG. 2 , which shows a top view of a portion of the memory device corresponding to one memory block in a comparative example. The dielectric element 204 extends through the ground select line GSL, the word line WL, and the string select line SSL corresponding to the sub-memory block in the stacked structure in the memory array region M and the stepped contact region SC. Via the dielectric element 204 The word line WL and the ground selection line GSL, which are electrically insulated from each other, each have a conductive column 112 . Conductive pillars 112 electrically connected to word lines WL (or ground select lines GSL) at the same level are provided by conductive elements 222 (including, for example, metal layers such as metal layer zero (ML0) extending over dielectric element 204 ). ) are electrically connected to each other. In the comparative example shown in FIG. 2, the number of conductive pillars 112 on the word line WL (or the ground selection line GSL) of the same level corresponding to one memory block is 4, which is equal to the electrical connection string selection The number of contact posts 114 of the line SSL (ie, 4).

相較於比較例，本揭露之實施例中，對應於一個記憶區塊的記憶體裝置，其電性連接其中一個第一導電層106(即一個字元線或一個接地選擇線)上的導電柱112的數量(例如於第1A圖、第1B圖所示，數量為1個)少於電性連接第二導電層108(串列選擇線)的接觸柱114的數量(例如於第1A圖、第1B圖所示，數量為4個)。換句話說，對應於一個記憶區塊的記憶體裝置可具有較少數量的導電柱112。此外，本揭露的實施例中，並不需要如比較例延伸在介電元件204上方、用以電性連接在相同階層的字元線WL的導電元件222。因此，本揭露的實施例的記憶體裝置可具有較簡單的製程、較大的製程窗(larger process window)、較低的製造成本。 Compared with the comparative example, in the embodiment of the present disclosure, the memory device corresponding to one memory block is electrically connected to the conductive layer on one of the first conductive layers 106 (ie, a word line or a ground selection line). The number of pillars 112 (eg, as shown in FIG. 1A and FIG. 1B , the number is one) is less than the number of contact pillars 114 electrically connected to the second conductive layer 108 (string select line) (eg, as shown in FIG. 1A ) , as shown in Figure 1B, the number is 4). In other words, a memory device corresponding to one memory block may have a smaller number of conductive pillars 112 . In addition, in the embodiment of the present disclosure, the conductive element 222 extending above the dielectric element 204 and electrically connected to the word line WL at the same level is not required as in the comparative example. Therefore, the memory device of the embodiments of the present disclosure can have a simpler manufacturing process, a larger process window, and a lower manufacturing cost.

請參照第3圖。在一基板432上交錯堆疊絕緣層418與絕緣膜434以形成堆疊結構402。舉例而言，基板432可包括半導體材料，例如矽或多晶矽(poly-silicon)，但本揭露不以此為限。一實施例中，絕緣層418的材質係不同於絕緣膜434的材質。絕緣層418可包括氧化物，例如氧化矽，但本揭露不以此為限。絕緣膜434可包括氮化物，例如氮化矽，但本揭露不以此為限。絕緣層418與絕緣膜434亦可使用其它絕緣材質。可利用黃光微影蝕刻方式從堆疊結構402的頂表面削減階梯狀接觸區SC的厚度。一實施例中，可形成絕緣元件(可包括氧化物，例如氧化矽，未繪示)在堆疊結構402的記憶體陣列區M與階梯狀接觸區SC上。可進行例如化學機械研磨步驟將堆疊結構402上的絕緣元件(未繪示)平坦化。 Please refer to Figure 3. The insulating layers 418 and the insulating films 434 are alternately stacked on a substrate 432 to form the stacked structure 402 . For example, the substrate 432 may include Semiconductor materials, such as silicon or poly-silicon, but the disclosure is not limited thereto. In one embodiment, the material of the insulating layer 418 is different from the material of the insulating film 434 . The insulating layer 418 may include oxide, such as silicon oxide, but the disclosure is not limited thereto. The insulating film 434 may include nitride, such as silicon nitride, but the present disclosure is not limited thereto. Other insulating materials may also be used for the insulating layer 418 and the insulating film 434 . The thickness of the stepped contact region SC may be cut from the top surface of the stacked structure 402 by using a yellow lithography method. In one embodiment, insulating elements (which may include oxide, such as silicon oxide, not shown) may be formed on the memory array region M and the stepped contact region SC of the stacked structure 402 . The insulating elements (not shown) on the stacked structure 402 may be planarized by, for example, a chemical mechanical polishing step.

一實施例中，形成柱元件416與柱元件416’分別穿過堆疊結構402的記憶體陣列區M與階梯狀接觸區SC。柱元件416與柱元件416’亦可穿過堆疊結構402上的絕緣元件(未繪示)。另一實施例中，柱元件416與柱元件416’的形成方法可包括利用黃光微影蝕刻步驟形成開孔於堆疊結構402與絕緣元件(未繪示)中，然後以合適的柱材料填充開孔。柱元件416與柱元件416’可同時形成，並可包括通道柱416a與記憶材料層416b。記憶材料層416b形成在開孔的側壁表面上。記憶材料層416b可包括任意的電荷捕捉結構，例如一氧化物-氮化物-氧化物(ONO)結構、ONONO結構、ONONONO結構、或一氧化物-氮化物-氧化物-氮化物-氧化物(BE-SONOS)結構等。舉例而言，電荷捕捉層可使用氮化物(例如氮化矽)，或是其他類似的高介電常數物質包括金屬氧化物，例如三氧化二鋁(Al₂O₃)、氧化鋯(HfO₂)等。通道柱416a形成在開孔中。又一實施例中，柱元件416與柱元件416’可使用不同的製程步驟分開形成。柱元件416與柱元件416’可使用不同的材料組合。 In one embodiment, the pillar elements 416 and the pillar elements 416 ′ are formed through the memory array region M and the stepped contact region SC of the stacked structure 402 , respectively. The pillar elements 416 and the pillar elements 416 ′ can also pass through insulating elements (not shown) on the stacked structure 402 . In another embodiment, the method of forming the pillar elements 416 and the pillar elements 416 ′ may include forming openings in the stack structure 402 and the insulating element (not shown) using a yellow lithography etching step, and then filling the openings with a suitable pillar material. . Pillar element 416 and pillar element 416' may be formed simultaneously and may include channel pillar 416a and memory material layer 416b. The memory material layer 416b is formed on the sidewall surface of the opening. The memory material layer 416b may include any charge trapping structure, such as an oxide-nitride-oxide (ONO) structure, an ONONO structure, an ONONONO structure, or an oxide-nitride-oxide-nitride-oxide ( BE-SONOS) structure, etc. For example, the charge trapping layer can use nitride (eg, silicon nitride), or other similar high dielectric constant materials including metal oxides, such as aluminum oxide (Al ₂ O ₃ ), zirconium oxide (HfO _{2 )} )Wait. Channel posts 416a are formed in the openings. In yet another embodiment, the pillar elements 416 and the pillar elements 416' may be formed separately using different process steps. Post elements 416 and post elements 416' may use different combinations of materials.

一實施例中，可利用黃光微影蝕刻方式在堆疊結構402中形成開口438及開口442，並且，在階梯狀接觸區SC中的堆疊結構402中形成開口440。開口438與開口440的底部可露出基板432的上表面。 In one embodiment, the opening 438 and the opening 442 may be formed in the stacked structure 402 by using yellow photolithography, and the opening 440 may be formed in the stacked structure 402 in the stepped contact region SC. Bottoms of the opening 438 and the opening 440 may expose the upper surface of the substrate 432 .

請參照第4圖。可進行選擇性蝕刻步驟移除堆疊結構502之記憶體陣列區M與階梯狀接觸區SC之絕緣膜434(可包括氮化物，例如氮化矽)，從而形成狹縫536在絕緣層418(可包括氧化物，例如氧化矽)之間。一實施例中，蝕刻步驟可包含溼式蝕刻方式，例如使用熱磷酸等合適的方法。狹縫536露出柱元件416與柱元件416’的側壁表面。露出狹縫536的柱元件416與柱元件416’可穩固支撐曝露出的絕緣層418。 Please refer to Figure 4. A selective etching step may be performed to remove the insulating film 434 (which may include nitride, such as silicon nitride) of the memory array region M and the stepped contact region SC of the stack structure 502, thereby forming slits 536 in the insulating layer 418 (which may be including oxides, such as silicon oxide). In one embodiment, the etching step may include a wet etching method, such as using a suitable method such as hot phosphoric acid. Slot 536 exposes sidewall surfaces of pillar element 416 and pillar element 416'. The pillar elements 416 and the pillar elements 416' of the exposed slits 536 can stably support the exposed insulating layer 418.

請參照第5圖。一實施例中，填充導電材料(可包括例如鎢)於狹縫536中，以形成導電層，包括第一導電層606(例如包括第一導電層606A~606D)及第二導電層608(例如包括導電部608a~608d)。另一實施例中，沉積一氧化物(例如是氧化鋁(Al₂O₃))於狹縫536中，接著以導電材料(可包括例如鎢)填充狹縫536，以形成導電層，包括第一導電層606(例如包括第一導電層606A~606D)及第二導電層608(例如包括導電部608a~608d)。 Please refer to Figure 5. In one embodiment, a conductive material (which may include, for example, tungsten) is filled in the slit 536 to form a conductive layer, including a first conductive layer 606 (for example, including first conductive layers 606A-606D) and a second conductive layer 608 (for example, including first conductive layers 606A-606D) Including conductive parts 608a-608d). In another embodiment, an oxide (eg, aluminum oxide (Al ₂ O ₃ )) is deposited in the slit 536 , and then the slit 536 is filled with a conductive material (which may include, for example, tungsten) to form a conductive layer, including the first A conductive layer 606 (for example, including first conductive layers 606A-606D) and a second conductive layer 608 (for example, including conductive parts 608a-608d).

請參照第6圖。形成絕緣材料於開口438、開口440及開口442的側壁表面上，以分別形成絕緣牆704a、絕緣牆710a、絕緣牆720a。舉例而言，絕緣牆704a、絕緣牆710a及絕緣牆720a可包括氧化物，例如氧化矽，但本揭露不以此為限。 Please refer to Figure 6. An insulating material is formed on the sidewall surfaces of the opening 438, the opening 440, and the opening 442 to form the insulating wall 704a, the insulating wall 710a, and the insulating wall 720a, respectively. For example, the insulating wall 704a, the insulating wall 710a, and the insulating wall 720a may include oxide, such as silicon oxide, but the present disclosure is not limited thereto.

請參照第7圖。填充導電材料在絕緣牆704a、絕緣牆710a、絕緣牆720a所環繞之開口704c、開口710c及開口720c內，以分別形成導電元件804b、導電元件810b及導電元件820b。 Please refer to Figure 7. The insulating wall 704a, the insulating wall 710a, the opening 704c surrounded by the insulating wall 720a, the opening 710c and the opening 720c are filled with conductive material to form the conductive element 804b, the conductive element 810b and the conductive element 820b, respectively.

請參照第1A圖及第1B圖。形成導電柱112及接觸柱114，分別著陸在第一導電層106(例如第一導電層106A~106D)及第二導電層108上。導電柱112及接觸柱114可穿過階梯狀接觸區SC上方的絕緣元件(未繪示)。導電柱112與接觸柱114可利用包含以黃光微影蝕刻製程形成孔洞，然後以導電材料填充孔洞的方法形成。 Please refer to Figure 1A and Figure 1B. Conductive pillars 112 and contact pillars 114 are formed and landed on the first conductive layer 106 (eg, the first conductive layers 106A˜106D) and the second conductive layer 108, respectively. The conductive pillars 112 and the contact pillars 114 may pass through insulating elements (not shown) above the stepped contact regions SC. The conductive pillars 112 and the contact pillars 114 can be formed by a method including forming a hole by a yellow photolithography process, and then filling the hole with a conductive material.

綜上所述，雖然本發明已以實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。 To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

100:記憶體裝置 100: Memory device

102:堆疊結構 102: Stacked Structure

104:第一元件結構 104: First element structure

104a:絕緣牆 104a: Insulated Walls

104b:導電元件 104b: Conductive elements

104s1:第一側壁表面 104s1: First sidewall surface

104s2:第二側壁表面 104s2: Second sidewall surface

104s3:第三側壁表面 104s3: Third sidewall surface

104s4:第四側壁表面 104s4: Fourth sidewall surface

106,106A~106D:第一導電層 106, 106A~106D: the first conductive layer

108:第二導電層 108: the second conductive layer

108a~108d:導電部 108a~108d: Conductive part

110:第二元件結構 110: Second element structure

110a:絕緣牆 110a: Insulated Walls

110b:導電元件 110b: Conductive elements

112:導電柱 112: Conductive column

114:接觸柱 114: Contact Column

116,116’:柱元件 116, 116': Column element

120,120P,120Q:第三元件結構 120, 120P, 120Q: The third element structure

120a:絕緣牆 120a: Insulated Walls

120b:導電元件 120b: Conductive elements

B:區塊 B: block

B1~B4:次區塊 B1~B4: Sub-block

M:記憶體陣列區 M: Memory array area

SC:階梯狀接觸區 SC: stepped contact area

X:第一橫方向 X: the first horizontal direction

Y:第二橫方向 Y: the second horizontal direction

Z:縱方向 Z: vertical direction

Claims

一種記憶體裝置，包括一個記憶區塊，該一個記憶區塊包括：一堆疊結構，在一記憶體陣列區與一階梯狀接觸區中，並包括排列在一縱方向上的數個第一導電層與一第二導電層，其中該記憶體陣列區與該階梯狀接觸區排列在一第一橫方向上，該第二導電層包括排列在一第二橫方向上的數個導電部；至少一個第一元件結構，沿該縱方向穿過該些第一導電層與該第二導電層；數個第二元件結構，各包括一絕緣牆在該階梯狀接觸區中沿該縱方向穿過該些第一導電層的其中至少一個第一導電層，該絕緣牆為矩形狀且具有四個側壁表面，該第二導電層未接觸該絕緣牆的該四個側壁表面，該至少一個第一導電層接觸該絕緣牆的該四個側壁表面；數個導電柱，其中該些第一導電層各具有該些導電柱的其中至少一個導電柱電性連接於其上；以及數個接觸柱，分別電性連接在該些導電部上，其中：該些第一導電層環繞該至少一個第一元件結構的側壁表面，該第二導電層的該些導電部藉由該至少一個第一元件結構彼此完全分開，該第一橫方向不同於該第二橫方向，電性連接在每個該些第一導電層上的該至少一個導電柱排列在該第二橫方向上的數量是小於該些接觸柱排列在該第二橫方向上的數量。 A memory device includes a memory block, the memory block includes: a stack structure, in a memory array area and a stepped contact area, and includes a plurality of first conductive lines arranged in a longitudinal direction layer and a second conductive layer, wherein the memory array area and the stepped contact area are arranged in a first lateral direction, the second conductive layer includes a plurality of conductive parts arranged in a second lateral direction; at least A first element structure, passing through the first conductive layers and the second conductive layer along the longitudinal direction; a plurality of second element structures, each including an insulating wall passing through the longitudinal direction in the stepped contact area In at least one of the first conductive layers, the insulating wall is rectangular and has four sidewall surfaces, the second conductive layer does not contact the four sidewall surfaces of the insulating wall, the at least one first a conductive layer contacts the four sidewall surfaces of the insulating wall; a plurality of conductive pillars, wherein each of the first conductive layers has at least one of the conductive pillars electrically connected thereon; and a plurality of contact pillars, are respectively electrically connected to the conductive parts, wherein: the first conductive layers surround the sidewall surface of the at least one first element structure, and the conductive parts of the second conductive layer are formed by the at least one first element structure completely separated from each other, the first transverse direction is different from the second transverse direction, The number of the at least one conductive column electrically connected to each of the first conductive layers arranged in the second lateral direction is smaller than the number of the contact columns arranged in the second lateral direction.

如請求項1所述之記憶體裝置，其中該至少一個第一元件結構包括另一絕緣牆，該另一絕緣牆具有封閉的矩形狀。 The memory device of claim 1, wherein the at least one first element structure includes another insulating wall having a closed rectangular shape.

如請求項1所述之記憶體裝置，其中該至少一個第一元件結構包括另一絕緣牆，該另一絕緣牆包括：一第一側壁表面；一第二側壁表面，相對於該第一側壁表面；一第三側壁表面，在該第一側壁表面與該第二側壁表面之間；及一第四側壁表面，相對於該第三側壁表面，並在該第一側壁表面與該第二側壁表面之間；其中該些第一導電層直接接觸該另一絕緣牆之該第一側壁表面、該第二側壁表面、該第三側壁表面及該第四側壁表面。 The memory device of claim 1, wherein the at least one first element structure comprises another insulating wall, and the other insulating wall comprises: a first side wall surface; a second side wall surface, opposite to the first side wall surface; a third sidewall surface between the first sidewall surface and the second sidewall surface; and a fourth sidewall surface opposite the third sidewall surface and between the first sidewall surface and the second sidewall surface between the surfaces; wherein the first conductive layers directly contact the first sidewall surface, the second sidewall surface, the third sidewall surface and the fourth sidewall surface of the other insulating wall.

如請求項1所述之記憶體裝置，其中，該至少一個第一元件結構係分離於該些第二元件結構。 The memory device of claim 1, wherein the at least one first element structure is separated from the second element structures.

如請求項1所述之記憶體裝置，更包括：一通道柱，位於該記憶體陣列區之中且穿過該堆疊結構；及一記憶材料層，在該通道柱的側壁表面上，其中數個記憶胞定義在部份的該些第一導電層與該通道柱的交錯處的該記憶材料層中。 The memory device of claim 1, further comprising: a channel pillar located in the memory array region and passing through the stacked structure; and a memory material layer, on the sidewall surface of the channel pillar, a number of which A memory cell is defined in the memory material layer at the intersection of a portion of the first conductive layers and the channel column.

如請求項1所述之記憶體裝置，其中該堆疊結構更包括排列在該縱方向上的數個絕緣層，該些第一導電層與該第二導電層藉由該些絕緣層彼此分離，該些絕緣層環繞該至少一個第一元件結構的該側壁表面。 The memory device of claim 1, wherein the stacked structure further comprises a plurality of insulating layers arranged in the longitudinal direction, the first conductive layers and the second conductive layers are separated from each other by the insulating layers, The insulating layers surround the sidewall surface of the at least one first element structure.

如請求項1所述之記憶體裝置，其中該些第一導電層包括數個字元線及一接地選擇線，該些導電部用作串列選擇線，該些字元線在該接地選擇線與該些串列選擇線之間。 The memory device of claim 1, wherein the first conductive layers include a plurality of word lines and a ground select line, the conductive portions are used as string select lines, and the word lines are at the ground select line line and the serial selection lines.

如請求項1所述之記憶體裝置，其中該至少一個第一元件結構包括一導電元件及另一絕緣牆，該另一絕緣牆環繞該導電元件，該導電元件藉由該另一絕緣牆電性絕緣該些第一導電層與該第二導電層。 The memory device of claim 1, wherein the at least one first element structure includes a conductive element and another insulating wall, the other insulating wall surrounds the conductive element, and the conductive element is electrically connected by the other insulating wall The first conductive layers and the second conductive layers are electrically insulated.

如請求項1所述之記憶體裝置，更包括：一第三元件結構與另一第三元件結構，沿該第一橫方向穿過該記憶體陣列區與該階梯狀接觸區；及一個區塊的數個記憶胞(memory cells of one block)，在該記憶體陣列區中的該堆疊結構中，並在該第三元件結構與該另一第三元件結構之間，其中該一個區塊的該些記憶胞包括數個次區塊的數個記憶胞，分別在該至少一個第一元件結構的兩側。 The memory device of claim 1, further comprising: a third element structure and another third element structure passing through the memory array region and the stepped contact region along the first lateral direction; and a region a plurality of memory cells of one block, in the stacked structure in the memory array region, and between the third element structure and the other third element structure, wherein the one block The memory cells include a plurality of memory cells of a plurality of sub-blocks, which are respectively on both sides of the at least one first element structure.