TWI771458B - Display driving device and display device including the same - Google Patents

Display driving device and display device including the same Download PDF

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TWI771458B
TWI771458B TW107125778A TW107125778A TWI771458B TW I771458 B TWI771458 B TW I771458B TW 107125778 A TW107125778 A TW 107125778A TW 107125778 A TW107125778 A TW 107125778A TW I771458 B TWI771458 B TW I771458B
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clock signal
display
clock
signal
period
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TW107125778A
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TW201911002A (en
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崔何娜
朴鍾旼
林憲用
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南韓商矽工廠股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G06F3/04184—Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

A display driving device may include: a clock data recovery circuit configured to recover a first clock signal from an input signal having a clock embedded in data; a readout circuit configured to sense a touch of a display panel; and a selector configured to provide any one of the first clock signal recovered by the clock data recovery circuit and an internally generated second clock signal as a third clock signal to the readout circuit, in order to drive the readout circuit.

Description

顯示驅動裝置及包含該顯示驅動裝置的顯示裝置 Display driving device and display device including the same

本發明涉及一種顯示裝置，更具體地，涉及一種用於驅動觸控感應顯示面板的顯示驅動裝置以及包含該顯示驅動裝置的顯示裝置。 The present invention relates to a display device, and more particularly, to a display driving device for driving a touch-sensitive display panel and a display device including the display driving device.

觸控感應顯示面板不僅可用於例如智慧終端設備的行動終端設備，亦可用於例如筆記型電腦、螢幕及家用電器的各式電子裝置。此種顯示面板根據觸控感測器的位置可分成附加式(add-on)和內嵌式(in-cell)。為了減少顯示面板的厚度，使用例如共同電極之已存在元件作為觸控感測電極的內嵌式顯示面板係應用至顯示裝置。 The touch-sensitive display panel can be used not only in mobile terminal equipment such as smart terminal equipment, but also in various electronic devices such as notebook computers, monitors and household appliances. Such a display panel can be classified into an add-on type and an in-cell type according to the position of the touch sensor. In order to reduce the thickness of the display panel, an in-cell display panel using an existing element such as a common electrode as a touch sensing electrode is applied to a display device.

用於驅動上述顯示面板的顯示驅動裝置可包括：讀出電路，用以感測顯示面板的觸控。傳統的顯示驅動裝置接收時脈訊號ECLK作為來自外部的單端型的電晶體-電晶體邏輯(Transistor-Transistor Logic,TTL)輸入，並驅動該讀出電路。然而，由於該傳統的顯示驅動裝置使用作為TTL輸入的時脈訊號來驅動讀出電路，該顯示驅動裝置可能容易受到電磁干擾(Electro Magnetic Interference,EMI)的影響。 The display driving device for driving the above-mentioned display panel may include: a readout circuit for sensing the touch of the display panel. The conventional display driving device receives the clock signal ECLK as an external single-ended transistor-transistor logic (TTL) input, and drives the readout circuit. However, since the conventional display driving device uses a clock signal as a TTL input to drive the readout circuit, the display driving device may be susceptible to electromagnetic interference (EMI).

各種實施例係涉及顯示驅動裝置及包含該顯示驅動裝置的顯示裝置。 Various embodiments relate to display driving devices and display devices including the same.

在一實施例中，一種顯示驅動裝置可包括：一時脈資料恢復電路，被配置以從一輸入訊號恢復一第一時脈訊號，該輸入訊號具有嵌入在資料中的一時脈；一讀出電路，被配置以感測一顯示面板的觸控；以及一選擇器，被配置以將由該時脈資料恢復電路恢復的該第一時脈訊號和內部產生的一第二 時脈訊號的其中任一者作為一第三時脈訊號，提供給該讀出電路，以驅動該讀出電路。 In one embodiment, a display driving apparatus may include: a clock data recovery circuit configured to recover a first clock signal from an input signal having a clock embedded in data; a readout circuit , configured to sense a touch of a display panel; and a selector configured to convert any one of the first clock signal recovered by the clock data recovery circuit and a second clock signal generated internally It is provided as a third clock signal to the readout circuit to drive the readout circuit.

在另一實施例中，一種顯示驅動裝置可包括：一第一時脈來源，被配置以從一輸入訊號產生一第一時脈訊號，該輸入訊號具有嵌入在資料中的一時脈；一第二時脈來源，被配置以透過內部振盪以一預設頻率產生一第二時脈訊號；以及一選擇器，被配置以選擇該第一時脈訊號及該第二時脈訊號的其中任一者作為一第三時脈訊號，並提供該第三時脈訊號給一讀出電路，以用於觸控感測。 In another embodiment, a display driving apparatus may include: a first clock source configured to generate a first clock signal from an input signal having a clock embedded in data; a first clock signal Two clock sources configured to generate a second clock signal at a predetermined frequency through internal oscillation; and a selector configured to select any one of the first clock signal and the second clock signal It is used as a third clock signal, and the third clock signal is provided to a readout circuit for touch sensing.

在另一實施例中，一種顯示驅動裝置可包括：一時序控制器，被配置以提供具有嵌入於資料中的一時脈的一輸入訊號；以及一顯示驅動裝置，被配置以從該輸入訊號恢復一第一時脈訊號，基於一顯示開啟週期/一顯示關閉週期提供該第一時脈訊號和內部產生的一第二時脈訊號的其中任一者作為一第三時脈訊號，並使用該第三時脈訊號感測觸控。 In another embodiment, a display driver may include: a timing controller configured to provide an input signal having a clock embedded in data; and a display driver configured to recover from the input signal a first clock signal, based on a display-on period/a display-off period, providing either the first clock signal or an internally generated second clock signal as a third clock signal, and using the The third clock signal senses touch.

10‧‧‧時序控制器 10‧‧‧Sequence Controller

20‧‧‧顯示驅動裝置 20‧‧‧Display driver

22‧‧‧時脈資料恢復電路 22‧‧‧Clock data recovery circuit

24‧‧‧資料驅動電路 24‧‧‧Data driver circuit

30‧‧‧微控制器 30‧‧‧Microcontroller

32‧‧‧振盪器 32‧‧‧Oscillator

34‧‧‧選擇器 34‧‧‧Selector

36‧‧‧讀出電路 36‧‧‧Readout circuit

40‧‧‧顯示面板 40‧‧‧Display panel

CEDA、CEDB‧‧‧輸入訊號 CEDA, CEDB‧‧‧input signal

CLK‧‧‧第三時脈訊號 CLK‧‧‧The third clock signal

CK‧‧‧時脈 CK‧‧‧clock

CS‧‧‧控制訊號 CS‧‧‧Control Signal

DATA‧‧‧資料 DATA‧‧‧Data

DMY‧‧‧虛位 DMY‧‧‧virtual seat

LOCK‧‧‧鎖定訊號 LOCK‧‧‧lock signal

OCS_CLK‧‧‧第二時脈訊號 OCS_CLK‧‧‧Second clock signal

PCLK‧‧‧第一時脈訊號 PCLK‧‧‧first clock signal

Rx‧‧‧回饋訊號 Rx‧‧‧ feedback signal

Sn‧‧‧源極訊號 Sn‧‧‧source signal

Tdata‧‧‧感測資料 Tdata‧‧‧Sensing data

Tx‧‧‧觸控驅動訊號 Tx‧‧‧touch driving signal

圖1為說明根據本發明一實施例之顯示驅動裝置及包含該顯示驅動裝置的顯示裝置的方塊圖。 1 is a block diagram illustrating a display driving apparatus and a display apparatus including the display driving apparatus according to an embodiment of the present invention.

圖2為說明圖1之顯示驅動裝置的操作的時序圖。 FIG. 2 is a timing chart illustrating the operation of the display driving apparatus of FIG. 1 .

圖3為說明根據本發明另一實施例之顯示驅動裝置及包含該顯示驅動裝置的顯示裝置的方塊圖。 3 is a block diagram illustrating a display driving apparatus and a display apparatus including the display driving apparatus according to another embodiment of the present invention.

圖4說明在圖1及圖3中的時脈嵌入輸入訊號。 FIG. 4 illustrates the clock embedded input signal in FIGS. 1 and 3 .

接下來，本發明的例示性實施例將參照附加圖式詳述。本說明書及申請專利範圍中使用的術語不限於典型字面解釋，而必須用符合本發明的技術理念理解涵義及概念。 Next, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The terms used in this specification and the scope of the patent application are not limited to typical literal interpretations, but the meanings and concepts must be understood with the technical ideas consistent with the present invention.

在圖式中說明的本說明書及配置中的實施例係本發明的較佳實施例，其不代表本發明的全部技術理念。因此，可以在提交本申請的時間點提供能夠替換實施例和配置的各種等同物和修改。 The embodiments in this specification and configurations illustrated in the drawings are preferred embodiments of the present invention, and do not represent the entire technical idea of the present invention. Accordingly, various equivalents and modifications capable of replacing the embodiments and configurations may be provided at the time of filing this application.

圖1為說明根據本發明一實施例之顯示驅動裝置20及包含該顯示驅動裝置20的顯示裝置的方塊圖。 FIG. 1 is a block diagram illustrating a display driving device 20 and a display device including the display driving device 20 according to an embodiment of the present invention.

參照圖1，該顯示裝置可包括：時序控制器10；顯示驅動裝置20；微控制器30；以及顯示面板40。 1 , the display device may include: a timing controller 10 ; a display driving device 20 ; a microcontroller 30 ; and a display panel 40 .

時序控制器10從主機系統(圖中未示)接收影像資料及時序訊號，執行例如影像品質補償的影像處理，以及提供差分輸入訊號CEDA和CEDB給顯示驅動裝置20，所述差分輸入訊號CEDA和CEDB藉由將時脈嵌入於資料(影像及控制資料)中來配置。 The timing controller 10 receives image data and timing signals from a host system (not shown), performs image processing such as image quality compensation, and provides differential input signals CEDA and CEDB to the display driving device 20, the differential input signals CEDA and CEDB is configured by embedding the clock in the data (image and control data).

顯示驅動裝置20從輸入訊號CEDA/CEDB恢復第一時脈訊號PCLK及資料DATA，使用恢復的第一時脈訊號PCLK及資料DATA驅動顯示面板40，以及使用恢復的第一時脈訊號PCLK感測顯示面板40的觸控。顯示面板40係觸控感應顯示面板，其可透過像素陣列顯示影像，其中像素以矩陣形狀佈置，並使用作為共同電極之觸控電極以電容式的方式感測觸控。顯示驅動裝置20可包括：時脈資料恢復電路22；資料驅動電路24；振盪器32；選擇器34；以及讀出電路36。 The display driving device 20 recovers the first clock signal PCLK and the data DATA from the input signals CEDA/CEDB, uses the recovered first clock signal PCLK and the data DATA to drive the display panel 40, and uses the recovered first clock signal PCLK for sensing Touch of the display panel 40 . The display panel 40 is a touch-sensitive display panel, which can display an image through a pixel array, wherein the pixels are arranged in a matrix shape, and the touch electrodes are capacitively sensed using the touch electrodes as common electrodes. The display driving device 20 may include: a clock data recovery circuit 22 ; a data driving circuit 24 ; an oscillator 32 ; a selector 34 ;

時脈資料恢復電路22從輸入訊號CEDA/CEDB恢復第一時脈訊號PCLK、影像及控制資料DATA，提供恢復的第一時脈訊號、恢復的影像及控制資料DATA給資料驅動電路24，並提供恢復的時脈訊號PCLK給選擇器34。 The clock data recovery circuit 22 recovers the first clock signal PCLK, the image and control data DATA from the input signals CEDA/CEDB, provides the recovered first clock signal, the recovered image and control data DATA to the data driving circuit 24, and provides The recovered clock signal PCLK is supplied to the selector 34 .

資料驅動電路24提供對應於影像資料的灰階值的源極訊號Sn給顯示面板40。資料驅動電路24包括：鎖存單元(圖中未示)，用於鎖存影像資料；類比至數位轉換器(圖中未示)，用於將影像資料轉換為對應於影像資料的灰階值的源極訊號Sn；以及輸出緩衝器(圖中未示)，用於緩衝源極訊號Sn並輸出緩衝的訊號給顯示面板40。 The data driving circuit 24 provides the display panel 40 with the source signal Sn corresponding to the grayscale value of the image data. The data driving circuit 24 includes: a latch unit (not shown in the figure) for latching image data; an analog-to-digital converter (not shown in the figure) for converting the image data into grayscale values corresponding to the image data and an output buffer (not shown) for buffering the source signal Sn and outputting the buffered signal to the display panel 40 .

振盪器32透過內部振盪以一預設頻率產生第二時脈訊號OSC_CLK，並提供第二時脈訊號OSC_CLK給選擇器34。振盪器32於顯示關閉週期產生第二時脈訊號OSC_CLK，並於顯示開啟週期中停用。顯示關閉週期為一停機週期，在該停機週期中，時序控制器10被關閉，且可定義為輸入訊號CEDA和CEDB未輸入給顯示驅動裝置20的週期。該顯示開啟週期可定義為輸入訊號CEDA及CEDB從時序控制器10輸入以在顯示面板40上顯示影像的週期。例如，振盪器32可被配置以從微控制器30接收控制訊號CS。振盪器32 可被啟用或停用以響應控制訊號CS。控制訊號CS具有在顯示開啟週期中停用振盪器32的邏輯位準，以及具有在顯示關閉週期中啟用振盪器32的邏輯位準。 The oscillator 32 generates the second clock signal OSC_CLK at a predetermined frequency through internal oscillation, and provides the second clock signal OSC_CLK to the selector 34 . The oscillator 32 generates the second clock signal OSC_CLK during the display off period and is disabled during the display on period. The display shutdown period is a shutdown period in which the timing controller 10 is turned off, and can be defined as a period in which the input signals CEDA and CEDB are not input to the display driving device 20 . The display turn-on period can be defined as the period during which the input signals CEDA and CEDB are input from the timing controller 10 to display images on the display panel 40 . For example, oscillator 32 may be configured to receive control signal CS from microcontroller 30 . The oscillator 32 can be enabled or disabled in response to the control signal CS. The control signal CS has a logic level to disable the oscillator 32 during the display on period and a logic level to enable the oscillator 32 during the display off period.

選擇器34選擇由時脈資料恢復電路22恢復的第一時脈訊號PCLK及由振盪器32產生的第二時脈訊號OSC_CLK中的其中之一，作為第三時脈訊號CLK，用於感測顯示面板40的觸控，並提供第三時脈訊號CLK給讀出電路36。選擇器34在顯示開啟週期中選擇第一時脈訊號PCLK作為第三時脈訊號CLK，以及在顯示關閉週期中選擇第二時脈訊號OSC_CLK作為第三時脈訊號CLK。 The selector 34 selects one of the first clock signal PCLK recovered by the clock data recovery circuit 22 and the second clock signal OSC_CLK generated by the oscillator 32 as the third clock signal CLK for sensing The touch control of the display panel 40 is provided, and the third clock signal CLK is provided to the readout circuit 36 . The selector 34 selects the first clock signal PCLK as the third clock signal CLK during the display-on period, and selects the second clock signal OSC_CLK as the third clock signal CLK during the display-off period.

例如，選擇器34選擇第一時脈訊號PCLK和第二時脈訊號OSC_CLK的其中之一作為第三時脈訊號CLK，以響應微控制器30的控制訊號CS，並提供第三時脈訊號CLK給讀出電路36。控制訊號CS具有在顯示開啟週期中用於選擇第一時脈訊號PCLK的邏輯位準，以及在顯示關閉週期中用於選擇第二時脈訊號OSC_CLK的邏輯位準。亦即，選擇器34在顯示開啟週期中將從輸入訊號恢復的第一時脈訊號PCLK作為第三時脈訊號CLK提供給讀出電路36，並在顯示關閉週期中將以預設頻率產生的第二時脈訊號OSC_CLK作為第三時脈訊號CLK提供給讀出電路36。 For example, the selector 34 selects one of the first clock signal PCLK and the second clock signal OSC_CLK as the third clock signal CLK to respond to the control signal CS of the microcontroller 30 and provide the third clock signal CLK to the readout circuit 36 . The control signal CS has a logic level for selecting the first clock signal PCLK in the display-on period, and a logic level for selecting the second clock signal OSC_CLK in the display-off period. That is, the selector 34 supplies the first clock signal PCLK recovered from the input signal to the readout circuit 36 as the third clock signal CLK during the display-on period, and generates the first clock signal PCLK at the preset frequency during the display-off period. The second clock signal OSC_CLK is provided to the readout circuit 36 as the third clock signal CLK.

讀出電路36利用從選擇器34提供的第三時脈訊號CLK感測顯示面板40的觸控，並輸出感測資料Tdata。感測資料Tdata可提供給微控制器30。顯示面板40可具有觸控及顯示功能，並包括包含在像素陣列中的觸控電極。例如，該等觸控電極可分別透過訊號線連接至讀出電路36，並鑒於觸控點尺寸，設定包含複數個像素的一預設尺寸。讀出電路36可提供觸控驅動訊號Tx給顯示面板40的觸控電極，以響應選擇器34的時脈訊號CLK，並從對應的觸控電極接收回饋訊號Rx。讀出訊號36可對每一個觸控電極差動地放大觸控驅動訊號Tx及回饋訊號Rx，並基於觸控所引起的電容改變，感測觸控是否發生。 The readout circuit 36 senses the touch of the display panel 40 by using the third clock signal CLK provided from the selector 34, and outputs the sensing data Tdata. The sensing data Tdata can be provided to the microcontroller 30 . The display panel 40 may have touch and display functions, and includes touch electrodes included in a pixel array. For example, the touch electrodes can be respectively connected to the readout circuit 36 through signal lines, and a predetermined size including a plurality of pixels is set in view of the size of the touch point. The readout circuit 36 can provide the touch driving signal Tx to the touch electrodes of the display panel 40 in response to the clock signal CLK of the selector 34 and receive the feedback signal Rx from the corresponding touch electrodes. The readout signal 36 can differentially amplify the touch driving signal Tx and the feedback signal Rx for each touch electrode, and sense whether a touch occurs based on the capacitance change caused by the touch.

讀出電路36提供感測驅動訊號Tx給顯示面板40的觸控電極，以響應在顯示開啟週期中被選擇作為第三時脈訊號的第一時脈訊號PCLK，並從顯示面板40的觸控電極接收回饋訊號Rx。讀出電路36將回饋訊號Rx轉換為感測資料Tdata以作為數位訊號，並提供感測資料Tdata給微控制器30。微控制器30可通過基於觸控所引起的電容變化之感測資料Tdata的改變，感測觸控是否發生和觸控的座標。例如，讀出電路36可包括分頻器，其用一預設值分頻恢 復的第一時脈訊號PCLK，並使用分頻的內部時脈訊號，提供觸控驅動訊號Tx給顯示面板40的觸控電極。 The readout circuit 36 provides the sensing drive signal Tx to the touch electrodes of the display panel 40 in response to the first clock signal PCLK selected as the third clock signal during the display turn-on period, and transmits the sensing drive signal Tx from the touch electrode of the display panel 40 . The electrodes receive the feedback signal Rx. The readout circuit 36 converts the feedback signal Rx into sensing data Tdata as a digital signal, and provides the sensing data Tdata to the microcontroller 30 . The microcontroller 30 can sense whether the touch occurs and the coordinates of the touch through the change of the sensing data Tdata based on the capacitance change caused by the touch. For example, the readout circuit 36 may include a frequency divider, which divides the recovered first clock signal PCLK with a preset value, and uses the divided internal clock signal to provide the touch driving signal Tx to the display panel 40 . touch electrodes.

讀出電路36可提供感測驅動訊號Tx給顯示面板40的觸控電極，以響應在顯示關閉週期中被選擇作為第三時脈訊號CLK的第二時脈訊號OSC_CLK，從顯示面板40的觸控電極接收回饋訊號Rx，並基於觸控所引起的電容改變感測顯示面板40的觸控。在顯示關閉週期中，讀出電路36僅感測顯示面板40的觸控是否發生。因此，即使振盪器32的第二時脈訊號OSC_CLK被改變，讀出電路36仍能可信賴地感測觸控。例如，在顯示關閉週期中的觸控感測功能可用於執行如智慧型手機等的敲擊功能，藉此，使用者藉由敲擊液晶螢幕來開啟液晶螢幕。 The readout circuit 36 can provide the sensing drive signal Tx to the touch electrodes of the display panel 40, in response to the second clock signal OSC_CLK selected as the third clock signal CLK in the display off period, from the touch electrodes of the display panel 40. The control electrode receives the feedback signal Rx, and senses the touch of the display panel 40 based on the capacitance change caused by the touch. During the display off period, the readout circuit 36 only senses whether a touch of the display panel 40 occurs. Therefore, even if the second clock signal OSC_CLK of the oscillator 32 is changed, the readout circuit 36 can still reliably sense the touch. For example, the touch sensing function in the display off period can be used to perform a tapping function such as a smart phone, whereby the user turns on the LCD screen by tapping the LCD screen.

讀出電路36可感測顯示面板40的觸控以響應在顯示開啟週期中被選擇作為第三時脈訊號CLK的第一時脈訊號PCLK，並感測顯示面板40的觸控以響應在顯示關閉週期中被選擇作為第三時脈訊號CLK的第二時脈訊號OSC_CLK。第一時脈訊號PCLK可在顯示開啟週期中以一預設值分頻。該預設值可依據資料傳輸率來設定。 The readout circuit 36 can sense the touch of the display panel 40 in response to the first clock signal PCLK selected as the third clock signal CLK in the display on period, and sense the touch of the display panel 40 in response to the display The second clock signal OSC_CLK is selected as the third clock signal CLK in the off period. The first clock signal PCLK can be frequency-divided by a predetermined value during the display turn-on period. The default value can be set according to the data transmission rate.

微控制器30提供控制訊號CS給顯示驅動裝置20的選擇器34。微控制器30控制選擇器34，以選擇在顯示關閉週期中由振盪器產生的第二時脈訊號OCS_CLK。並且，微控制器30控制選擇器34，以選擇在顯示開啟週期中由時脈資料恢復電路22恢復的第一時脈訊號PCLK。例如，微控制器30可在顯示開啟週期中提供低位準的控制訊號CS，並在顯示關閉週期中提供高位準的控制訊號CS。接著，選擇器34可在顯示開啟週期中選擇第一時脈訊號PCLK，以響應低位準的控制訊號CS，並在顯示關閉週期中選擇第二時脈訊號OSC_CLK，以響應高位準的控制訊號CS。控制訊號CS可作為控制封包傳送，其傳送係藉由在微控制器30與顯示驅動裝置20之間的介面，例如序列周邊介面(Serial Peripheral Interface Bus,SPI)。微控制器30可從讀出電路36接收感測資料Tdata，並基於由觸控所引起的感測資料Tdata的改變，判斷顯示面板40的觸控是否發生和觸控的座標。 The microcontroller 30 provides the control signal CS to the selector 34 of the display driving device 20 . The microcontroller 30 controls the selector 34 to select the second clock signal OCS_CLK generated by the oscillator during the display off period. Furthermore, the microcontroller 30 controls the selector 34 to select the first clock signal PCLK recovered by the clock data recovery circuit 22 during the display-on period. For example, the microcontroller 30 may provide a low-level control signal CS during a display-on period and a high-level control signal CS during a display-off period. Next, the selector 34 can select the first clock signal PCLK in the display-on period to respond to the low-level control signal CS, and select the second clock signal OSC_CLK in the display-off period to respond to the high-level control signal CS . The control signal CS can be transmitted as a control packet through an interface between the microcontroller 30 and the display driving device 20 , such as a Serial Peripheral Interface Bus (SPI). The microcontroller 30 may receive the sensing data Tdata from the readout circuit 36, and determine whether the touch of the display panel 40 occurs and the coordinates of the touch based on the change of the sensing data Tdata caused by the touch.

根據本實施例，用於從輸入訊號CEDA/CEDB恢復第一時脈訊號PCLK的時脈資料恢復電路22被用為在顯示開啟週期中的第一時脈來源，以 及用於以預設頻率產生第二時脈訊號OSC_CLK的振盪器32被用為在顯示關閉週期中的第二時脈來源。 According to the present embodiment, the clock data recovery circuit 22 for recovering the first clock signal PCLK from the input signal CEDA/CEDB is used as the first clock source in the display on period and for generating at a preset frequency The oscillator 32 of the second clock signal OSC_CLK is used as the second clock source during the display off period.

圖2為說明圖1之操作的時序圖。 FIG. 2 is a timing diagram illustrating the operation of FIG. 1 .

參照圖1及圖2，顯示驅動裝置20在顯示開啟週期中使用從輸入訊號CEDA/CEDB恢復的第一訊號PCLK驅動讀出電路36，並在顯示關閉週期中使用振盪器32的第二時脈訊號OSC_CLK驅動讀出電路36。例如，顯示面板40的感測觸控功能在顯示關閉週期中可被用於執行如智慧型手機等的敲擊功能，藉此，使用者藉由敲擊液晶螢幕開啟該液晶螢幕。在顯示關閉週期中，顯示驅動裝置20僅感測顯示面板40的觸控是否發生。因此，讀出電路20使用振盪器32的第二時脈訊號OSC_CLK能可信賴地感測觸控。 1 and 2 , the display driving device 20 uses the first signal PCLK recovered from the input signals CEDA/CEDB to drive the readout circuit 36 during the display on period, and uses the second clock of the oscillator 32 during the display off period The signal OSC_CLK drives the readout circuit 36 . For example, the touch sensing function of the display panel 40 can be used to perform a tapping function such as a smart phone during the display off period, whereby the user turns on the liquid crystal screen by tapping the liquid crystal screen. In the display off period, the display driving device 20 only senses whether the touch of the display panel 40 occurs. Therefore, the readout circuit 20 can reliably sense the touch by using the second clock signal OSC_CLK of the oscillator 32 .

在本實施例中，顯示驅動裝置20可在顯示開啟週期中分頻從輸入訊號CEDA/CEDB恢復的第一時脈訊號PCLK，並使用分頻的內部時脈訊號(圖中未示)感測顯示面板40的觸控和觸控的座標。觸控座標可以用於主機系統以執行與觸控座標相關的命令或應用。主機系統可包含平板或智慧型手機的系統、電腦、電視系統、機上盒等。用於分頻恢復的第一時脈訊號PCLK的分頻器(圖中未示)可包含在讀出電路36中。或者，該分頻器可包含在時脈資料恢復電路22中，或是設置在時脈資料恢復電路22與讀出電路36之間。 In this embodiment, the display driving device 20 may divide the first clock signal PCLK recovered from the input signal CEDA/CEDB by frequency during the display turn-on period, and use the divided internal clock signal (not shown in the figure) to sense the frequency The touch and the coordinates of the touch on the display panel 40 are displayed. The touch coordinates can be used by the host system to execute commands or applications related to the touch coordinates. The host system may include a tablet or smartphone system, a computer, a TV system, a set-top box, and the like. A frequency divider (not shown) for the frequency-divided recovered first clock signal PCLK may be included in the readout circuit 36 . Alternatively, the frequency divider may be included in the clock data recovery circuit 22 , or disposed between the clock data recovery circuit 22 and the readout circuit 36 .

圖3為說明根據本發明另一實施例之顯示驅動裝置及包含該顯示驅動裝置的顯示裝置的方塊圖。與圖1的實施例相同的元件的描述將替換為圖1的描述或簡單描述。 3 is a block diagram illustrating a display driving apparatus and a display apparatus including the display driving apparatus according to another embodiment of the present invention. Descriptions of the same elements as in the embodiment of FIG. 1 will be replaced with descriptions or brief descriptions of FIG. 1 .

參照圖3，該顯示裝置可包括：時序控制器10；顯示驅動裝置20；以及顯示面板40。 3 , the display device may include: a timing controller 10 ; a display driving device 20 ; and a display panel 40 .

時序控制器10執行影像處理，例如用於影像資料的影像品質補償，並產生用於控制顯示驅動裝置20的操作時序的控制資料，並將影像及控制資料與時脈嵌入至差分輸入訊號CEDA和CEDB中。時序控制器10提供藉由嵌入時脈於資料中所配置的差分輸入訊號CEDA和CEDB給顯示驅動裝置20。 The timing controller 10 performs image processing, such as image quality compensation for image data, and generates control data for controlling the operation timing of the display driving device 20, and embeds the image and control data and clocks into the differential input signals CEDA and in CEDB. The timing controller 10 provides the differential input signals CEDA and CEDB configured in the data by the embedded clock to the display driving device 20 .

顯示驅動裝置20從輸入訊號CEDA/CEDB恢復一第一時脈訊號PCLK及資料DATA，使用恢復的第一時脈訊號PCLK及資料DATA驅動顯示面板40，並使用第一時脈訊號PCLK感測顯示面板40的觸控是否發生。顯示驅 動裝置20可包括：時脈資料恢復電路22；資料驅動電路24；振盪器32；選擇器34；以及讀出電路36。 The display driving device 20 recovers a first clock signal PCLK and data DATA from the input signals CEDA/CEDB, uses the recovered first clock signal PCLK and data DATA to drive the display panel 40, and uses the first clock signal PCLK to sense the display Whether the touch of the panel 40 occurs. Display driver 20 may include: clock data recovery circuit 22; data driver circuit 24; oscillator 32; selector 34;

時脈資料恢復電路22從輸入訊號CEDA/CEDB恢復第一時脈訊號PCLK及資料DATA，提供恢復的第一時脈訊號及資料DATA給資料驅動電路24，並提供恢復的第一時脈訊號PCLK給選擇器34。 The clock data recovery circuit 22 recovers the first clock signal PCLK and the data DATA from the input signals CEDA/CEDB, provides the recovered first clock signal and the data DATA to the data driving circuit 24, and provides the recovered first clock signal PCLK to selector 34.

時脈資料恢復電路22提供鎖定訊號LOCK給選擇器34。該鎖定訊號基於顯示開啟週期及顯示關閉週期具有不同的邏輯位準。例如，時脈資料恢復電路22可在接收到差分輸入訊號CEDA和CEDB的顯示開啟週期中提供高位準的鎖定訊號LOCK給選擇器34，並在顯示關閉週期中提供低位準的鎖定訊號LOCK給選擇器34。 The clock data recovery circuit 22 provides the lock signal LOCK to the selector 34 . The lock signal has different logic levels based on the display on period and the display off period. For example, the clock data recovery circuit 22 can provide a high-level lock signal LOCK to the selector 34 during the display-on period when the differential input signals CEDA and CEDB are received, and provide a low-level lock signal LOCK to the selector 34 during the display-off period device 34.

振盪器32透過內部振盪以一預設頻率產生第二時脈訊號OSC_CLK，並提供第二時脈訊號OSC_CLK給選擇器34。例如，振盪器32可在顯示開啟週期中停用，並在顯示關閉週期中啟用。例如，振盪器32可被配置以從微控制器30接收控制訊號CS。振盪器32可被啟用或停用以響應控制訊號CS。控制訊號CS具有在顯示開啟週期中停用振盪器32的邏輯位準，以及具有在顯示關閉週期中啟用振盪器32的邏輯位準。選擇器34選擇第一時脈訊號PCLK和第二時脈訊號OSC_CLK的其中之一作為第三時脈訊號CLK，以響應鎖定訊號LOCK，並提供第三時脈訊號CLK給讀出電路36。例如，選擇器34在顯示開啟週期中選擇第一時脈訊號PCL，以響應高位準的鎖定訊號LOCK，並在顯示關閉週期中選擇第二時脈訊號OSC_CLK，以響應低位準的鎖定訊號LOCK。亦即，選擇器34在顯示開啟週期中選擇由時脈資料恢復電路22恢復的第一時脈訊號PCLK作為第三時脈訊號CLK，或者在顯示關閉週期中選擇第二時脈訊號OSC_CLK作為第三時脈訊號CLK，並提供第三時脈訊號CLK給讀出電路36。 The oscillator 32 generates the second clock signal OSC_CLK at a predetermined frequency through internal oscillation, and provides the second clock signal OSC_CLK to the selector 34 . For example, oscillator 32 may be disabled during display on periods and enabled during display off periods. For example, oscillator 32 may be configured to receive control signal CS from microcontroller 30 . The oscillator 32 can be enabled or disabled in response to the control signal CS. The control signal CS has a logic level to disable the oscillator 32 during the display on period and a logic level to enable the oscillator 32 during the display off period. The selector 34 selects one of the first clock signal PCLK and the second clock signal OSC_CLK as the third clock signal CLK in response to the lock signal LOCK, and provides the third clock signal CLK to the readout circuit 36 . For example, the selector 34 selects the first clock signal PCL in the display-on period in response to the high-level lock signal LOCK, and selects the second clock signal OSC_CLK in the display-off period in response to the low-level lock signal LOCK. That is, the selector 34 selects the first clock signal PCLK recovered by the clock data recovery circuit 22 as the third clock signal CLK during the display on period, or selects the second clock signal OSC_CLK as the third clock signal CLK during the display off period. Three clock signals CLK are provided, and the third clock signal CLK is provided to the readout circuit 36 .

讀出電路36感測顯示面板40的觸控，以響應從選擇器34提供作為第三時脈訊號CLK的第一時脈訊號PCLK或第二時脈訊號OSC_CLK。例如，讀出電路36在顯示開啟週期中提供觸控驅動訊號Tx給顯示面板40的觸控電極，以響應第一時脈訊號PCLK，並在顯示關閉週期中提供觸控驅動訊號Tx給顯示面板40的觸控電極，以響應第二時脈訊號OSC_CLK。讀出電路36從顯 示面板40的觸控電極接收回饋訊號Rx，並基於觸控所引起的電容變化感測顯示面板40的觸控。 The readout circuit 36 senses the touch of the display panel 40 in response to the first clock signal PCLK or the second clock signal OSC_CLK being supplied from the selector 34 as the third clock signal CLK. For example, the readout circuit 36 provides the touch driving signal Tx to the touch electrodes of the display panel 40 during the display on period in response to the first clock signal PCLK, and provides the touch driving signal Tx to the display panel during the display off period The touch electrode of 40 responds to the second clock signal OSC_CLK. The readout circuit 36 receives the feedback signal Rx from the touch electrodes of the display panel 40, and senses the touch of the display panel 40 based on the capacitance change caused by the touch.

讀出電路36可在顯示開啟週期中感測顯示面板40的觸控，以響應被選擇作為第三時脈訊號CLK的第一時脈訊號PCLK，並在顯示關閉週期中感測顯示面板40的觸控，以響應被選擇作為第三時脈訊號CLK的第二時脈訊號OSC_CLK。第一時脈訊號PCLK可在顯示開啟週期中以一週期值分頻。 The readout circuit 36 can sense the touch of the display panel 40 during the display-on period, in response to the first clock signal PCLK selected as the third clock signal CLK, and sense the touch of the display panel 40 during the display-off period. touch, in response to the second clock signal OSC_CLK selected as the third clock signal CLK. The first clock signal PCLK may be frequency-divided by a period value in the display turn-on period.

圖4說明在圖1及圖3中嵌入時脈的輸入訊號CEDA/CEDB。 FIG. 4 illustrates the input signals CEDA/CEDB of the embedded clocks in FIGS. 1 and 3 .

在時序控制器10與顯示驅動裝置20之間的資料通訊可以各種方式實施。在本實施例中，輸入訊號CEDA/CEDB可透過時脈嵌入資料傳訊(Clock Embedded Data Signaling，CEDS)傳送。CEDS可定義為一種將資料封包化以獲得有時脈CK嵌入於資料內的格式的通訊方法。 The data communication between the timing controller 10 and the display driving device 20 can be implemented in various ways. In this embodiment, the input signals CEDA/CEDB can be transmitted through Clock Embedded Data Signaling (CEDS). CEDS can be defined as a communication method for packetizing data to obtain a format in which the clock CK is embedded in the data.

如圖4中所示，具有時脈CK嵌入在其中的輸入訊號CEDA/CEDB可作為資料封包被傳送。例如，一個封包可具有28單元區間(Unit Interval,UI)，且每一個封包可包含4UI的定界符以及24UI的資料。4UI的定界符可包含虛位DMY和時脈CK，且24UI的資料可包括影像及控制資料。在圖4中，定界符是由「0011」表示的4位元資料，4位元資料的「00」對應於虛位DMY，「11」對應於時脈CK。定界符可以以相同位元數及相同資料值應用於所有封包。 As shown in FIG. 4, the input signals CEDA/CEDB with the clock CK embedded therein can be transmitted as data packets. For example, one packet may have 28 unit intervals (UI), and each packet may include 4UI of delimiters and 24UI of data. The delimiter of 4UI may include dummy DMY and clock CK, and the data of 24UI may include image and control data. In FIG. 4, the delimiter is 4-bit data represented by "0011", "00" of the 4-bit data corresponds to the dummy bit DMY, and "11" corresponds to the clock CK. The delimiter can be applied to all packets with the same number of bits and the same data value.

時脈資料恢復電路22可透過輸入為「00」的虛位DMY分頻封包資料，透過輸入為「11」的時脈CK恢復第一時脈訊號PCLK的邊緣，並透過內部邏輯電路恢復28UI的第一時脈訊號PCLK。此外，時脈資料恢復電路22可使用第一時脈訊號PCKL產生取樣時脈訊號，並使用該取樣時脈訊號恢復該資料。 The clock data recovery circuit 22 can recover the edge of the first clock signal PCLK through the dummy DMY frequency-divided packet data input as "00", recover the edge of the first clock signal PCLK through the clock CK input as "11", and recover the 28UI through the internal logic circuit. The first clock signal PCLK. In addition, the clock data recovery circuit 22 can use the first clock signal PCKL to generate a sample clock signal, and use the sample clock signal to recover the data.

由時脈資料恢復電路22恢復的第一時脈訊號PCLK可在顯示開啟週期中提供給讀出電路36，並用於感測顯示面板40是否發生觸控和觸控的座標。第一時脈訊號PCLK可以以週期值分頻，以用於感測顯示面板40是否發生觸控和觸控的座標。該預設值可依據該資料傳輸率設定。例如，當資料傳輸率為2.0Gb/s時，第一時脈訊號PCLK具有71.4Mhz的頻率，並可被分頻為對應於四分時脈的17.85Mhz的內部時脈訊號。當該資料傳輸率為1.2Gb/s時，第一時 脈訊號PCLK具有42.8Mhz的頻率，並可被分頻為對應於二分時脈的21.4Mhz的內部時脈訊號，或是對應於四分時脈的10.4Mhz的內部時脈訊號。 The first clock signal PCLK recovered by the clock data recovery circuit 22 can be provided to the readout circuit 36 during the display turn-on period and used to sense whether the display panel 40 is touched and the coordinates of the touch. The first clock signal PCLK can be frequency-divided by a period value to sense whether a touch occurs on the display panel 40 and the coordinates of the touch. The default value can be set according to the data transmission rate. For example, when the data transfer rate is 2.0Gb/s, the first clock signal PCLK has a frequency of 71.4Mhz, and can be divided into an internal clock signal of 17.85Mhz corresponding to a quarter clock. When the data transfer rate is 1.2Gb/s, the first clock signal PCLK has a frequency of 42.8Mhz, and can be divided into an internal clock signal of 21.4Mhz corresponding to a divided clock, or corresponding to a divided four 10.4Mhz internal clock signal of the clock.

根據本發明的實施例，顯示驅動裝置20可使用從具有時脈嵌入資料的輸入訊號CEDA/CEDB恢復的第一時脈訊號PCLK或是由內部產生的第二時脈訊號OSC_CLK，感測顯示面板40的觸控，從而減少由作為單端型TTL輸入的時脈訊號ECLK所造成的EMI。 According to an embodiment of the present invention, the display driving device 20 can sense the display panel by using the first clock signal PCLK recovered from the input signal CEDA/CEDB with clock embedded data or the second clock signal OSC_CLK generated internally 40 touches, thereby reducing the EMI caused by the clock signal ECLK as a single-ended TTL input.

各式實施例如以上所述，通常知識者將理解為該實施例僅為舉例說明。因此，此文所述之本發明不應受限於所述實施例。 Various embodiments are described above, and those skilled in the art will understand that the embodiments are only illustrative. Therefore, the invention described herein should not be limited to the embodiments described.

10‧‧‧時序控制器 10‧‧‧Sequence Controller

20‧‧‧顯示驅動裝置 20‧‧‧Display driver

22‧‧‧時脈資料恢復電路 22‧‧‧Clock data recovery circuit

24‧‧‧資料驅動電路 24‧‧‧Data driver circuit

30‧‧‧微控制器 30‧‧‧Microcontroller

32‧‧‧振盪器 32‧‧‧Oscillator

34‧‧‧選擇器 34‧‧‧Selector

36‧‧‧讀出電路 36‧‧‧Readout circuit

40‧‧‧顯示面板 40‧‧‧Display panel

CEDA、CEDB‧‧‧輸入訊號 CEDA, CEDB‧‧‧input signal

CLK‧‧‧第三時脈訊號 CLK‧‧‧The third clock signal

CS‧‧‧控制訊號 CS‧‧‧Control Signal

DATA‧‧‧資料 DATA‧‧‧Data

OCS_CLK‧‧‧第二時脈訊號 OCS_CLK‧‧‧Second clock signal

PCLK‧‧‧第一時脈訊號 PCLK‧‧‧first clock signal

Rx‧‧‧回饋訊號 Rx‧‧‧ feedback signal

Sn‧‧‧源極訊號 Sn‧‧‧source signal

Tdata‧‧‧感測資料 Tdata‧‧‧Sensing data

Tx‧‧‧觸控驅動訊號 Tx‧‧‧touch driving signal

Claims (15)

一種顯示驅動裝置，包括：一時脈資料恢復電路，被配置以從一輸入訊號恢復一第一時脈訊號，該輸入訊號具有嵌入在資料中的一時脈；一讀出電路，被配置以感測一顯示面板的觸控；以及一選擇器，被配置以將由該時脈資料恢復電路恢復的該第一時脈訊號和內部產生的一第二時脈訊號的其中任一者作為一第三時脈訊號，提供給該讀出電路，以驅動該讀出電路，其中，該顯示驅動裝置將該第一時脈訊號以一預設值分頻，且使用該分頻的內部時脈訊號驅動該讀出電路。 A display driving device includes: a clock data recovery circuit configured to recover a first clock signal from an input signal, the input signal having a clock embedded in data; a readout circuit configured to sense touch control of a display panel; and a selector configured to use any one of the first clock signal recovered by the clock data recovery circuit and a second clock signal generated internally as a third clock A pulse signal is provided to the readout circuit to drive the readout circuit, wherein the display driving device divides the frequency of the first clock signal by a preset value, and uses the divided internal clock signal to drive the readout circuit. 根據申請專利範圍第1項所述的顯示驅動裝置，其中，該選擇器選擇該第二時脈訊號作為該第三時脈訊號，以響應未接收到該時脈的一週期。 The display driving device according to claim 1, wherein the selector selects the second clock signal as the third clock signal in response to a period in which the clock is not received. 根據申請專利範圍第1項所述的顯示驅動裝置，其中，該選擇器在一顯示開啟週期中選擇該第一時脈訊號作為該第三時脈訊號，並在一顯示關閉週期中選擇該第二時脈訊號作為該第三時脈訊號。 The display driving device according to claim 1, wherein the selector selects the first clock signal as the third clock signal in a display on period, and selects the first clock signal in a display off period Two clock signals are used as the third clock signal. 根據申請專利範圍第1項所述的顯示驅動裝置，進一步包括：一振盪器，被配置以一預設頻率產生該第二時脈訊號，並提供該第二時脈訊號給該選擇器。 The display driving device according to claim 1, further comprising: an oscillator configured to generate the second clock signal at a predetermined frequency and provide the second clock signal to the selector. 根據申請專利範圍第1項所述的顯示驅動裝置，其中，該選擇器從一微控制器接收一控制訊號，該控制訊號基於一顯示開啟週期及一顯示關閉週期具有不同的邏輯位準。 The display driving device of claim 1, wherein the selector receives a control signal from a microcontroller, and the control signal has different logic levels based on a display-on period and a display-off period. 根據申請專利範圍第5項所述的顯示驅動裝置，其中，該選擇器選擇該第一時脈訊號，以響應具有對應於該顯示開啟週期的一邏輯位準的該控制訊號，以及選擇該第二時脈訊號，以響應具有對應於該顯示關閉週期的一邏輯位準的該控制訊號。 The display driving device according to claim 5, wherein the selector selects the first clock signal in response to the control signal having a logic level corresponding to the display turn-on period, and selects the first clock signal Two clock signals, in response to the control signal having a logic level corresponding to the display off period. 根據申請專利範圍第1項所述的顯示驅動裝置，其中，在一顯示開啟週期中，該顯示驅動裝置將從該輸入訊號恢復的該第一時脈訊號以該預設 值分頻，並使用該分頻的內部時脈訊號驅動該讀出電路，該預設值可根據資料傳輸率設定。 The display driving device according to claim 1, wherein, in a display turn-on period, the display driving device uses the preset first clock signal recovered from the input signal to The value is frequency-divided, and the divided internal clock signal is used to drive the readout circuit, and the preset value can be set according to the data transmission rate. 根據申請專利範圍第1項所述的顯示驅動裝置，其中，該時脈資料恢復電路提供一鎖定訊號給該選擇器，該鎖定訊號基於一顯示開啟週期及一顯示關閉週期具有不同的邏輯位準，以及該選擇器選擇該第一時脈訊號，以響應具有對應於該顯示開啟週期的一邏輯位準的該鎖定訊號，以及選擇該第二時脈訊號，以響應具有對應於該顯示關閉週期的一邏輯位準的該鎖定訊號。 The display driving device according to claim 1, wherein the clock data recovery circuit provides a lock signal to the selector, and the lock signal has different logic levels based on a display on period and a display off period , and the selector selects the first clock signal in response to the lock signal having a logic level corresponding to the display on period, and selects the second clock signal in response to the display off period of the lock signal at a logic level. 一種顯示驅動裝置，包括：一第一時脈來源，被配置以從一輸入訊號產生一第一時脈訊號，該輸入訊號具有嵌入在資料中的一時脈；一第二時脈來源，被配置以透過內部振盪以一預設頻率產生一第二時脈訊號；以及一選擇器，被配置以選擇該第一時脈訊號及該第二時脈訊號的其中任一者作為一第三時脈訊號，並提供該第三時脈訊號給一讀出電路，以用於觸控感測，其中，該顯示驅動裝置將從該輸入訊號恢復的該第一時脈訊號以一預設值分頻，且使用該分頻的內部時脈訊號驅動該讀出電路。 A display driving device includes: a first clock source configured to generate a first clock signal from an input signal, the input signal having a clock embedded in data; a second clock source configured generating a second clock signal at a predetermined frequency through internal oscillation; and a selector configured to select any one of the first clock signal and the second clock signal as a third clock signal, and provide the third clock signal to a readout circuit for touch sensing, wherein the display driving device divides the frequency of the first clock signal recovered from the input signal by a preset value , and use the divided internal clock signal to drive the readout circuit. 根據申請專利範圍第9項所述的顯示驅動裝置，其中，該選擇器選擇該第二時脈訊號作為該第三時脈訊號，以響應未接收到該時脈的一週期。 The display driving device according to claim 9, wherein the selector selects the second clock signal as the third clock signal in response to a period in which the clock is not received. 根據申請專利範圍第9項所述的顯示驅動裝置，其中，該選擇器在一顯示開啟週期中選擇該第一時脈訊號作為該第三時脈訊號，並在一顯示關閉週期中選擇該第二時脈訊號作為該第三時脈訊號。 The display driving device according to claim 9, wherein the selector selects the first clock signal as the third clock signal in a display on period, and selects the first clock signal in a display off period Two clock signals are used as the third clock signal. 一種顯示裝置，包括：一時序控制器，被配置以提供具有嵌入於資料中的一時脈的一輸入訊號；一顯示驅動裝置，被配置以從該輸入訊號恢復一第一時脈訊號，基於一顯示開啟週期/一顯示關閉週期提供該第一時脈訊號和內部產生的一第二時脈訊號的其中任一者作為一第三時脈訊號，並使用該第三時脈訊號感測觸控；以及一讀出電路，被配置以感測一顯示面板的觸控， 其中，該顯示驅動裝置將從該輸入訊號恢復的該第一時脈訊號以一預設值分頻，且使用該分頻的內部時脈訊號驅動該讀出電路。 A display device comprising: a timing controller configured to provide an input signal with a clock embedded in data; a display driving device configured to recover a first clock signal from the input signal based on a A display-on period/a display-off period provides either the first clock signal or an internally generated second clock signal as a third clock signal, and uses the third clock signal to sense touch ; and a readout circuit configured to sense touch on a display panel, Wherein, the display driving device divides the frequency of the first clock signal recovered from the input signal by a preset value, and uses the divided internal clock signal to drive the readout circuit. 根據申請專利範圍第12項所述的顯示裝置，進一步包括：一微控制器，被配置以提供一控制訊號給該顯示驅動裝置，該控制訊號基於該顯示開啟週期及該顯示關閉週期具有不同的邏輯位準，其中，該顯示驅動裝置在該顯示開啟週期中選擇該第一時脈訊號作為該第三時脈訊號或者在該顯示關閉週期中選擇該第二時脈訊號作為該第三時脈訊號，以響應該控制訊號。 The display device according to claim 12, further comprising: a microcontroller configured to provide a control signal to the display driving device, the control signal having different values based on the display on period and the display off period logic level, wherein the display driving device selects the first clock signal as the third clock signal during the display on period or selects the second clock signal as the third clock during the display off period signal in response to the control signal. 根據申請專利範圍第12項所述的顯示裝置，其中，該顯示裝置包括：一時脈資料恢復電路，被配置以從該輸入訊號恢復該第一時脈訊號和資料；一資料驅動電路，被配置以提供對應於該資料的灰階值的源極訊號給該顯示面板；以及一選擇器，被配置以選擇由該時脈資料電路恢復的該第一時脈訊號和內部產生的該第二時脈訊號的其中任一者作為該第三時脈訊號，並提供該第三時脈訊號給該讀出電路，以驅動該讀出電路。 The display device according to claim 12, wherein the display device comprises: a clock data recovery circuit configured to recover the first clock signal and data from the input signal; a data driving circuit configured providing a source signal corresponding to the grayscale value of the data to the display panel; and a selector configured to select the first clock signal recovered by the clock data circuit and the second clock generated internally One of the pulse signals is used as the third clock signal, and the third clock signal is provided to the readout circuit to drive the readout circuit. 根據申請專利範圍第14項所述的顯示裝置，其中，該時脈資料恢復電路提供一鎖定訊號給該選擇器，該鎖定訊號基於該顯示開啟週期及該顯示關閉週期具有不同的邏輯位準，以及該選擇器在該顯示開啟週期中選擇該第一時脈訊號作為該第三時脈訊號或者在該顯示關閉週期中選擇該第二時脈訊號作為該第三時脈訊號，以響應該鎖定訊號。 The display device according to claim 14, wherein the clock data recovery circuit provides a lock signal to the selector, and the lock signal has different logic levels based on the display on period and the display off period, and the selector selects the first clock signal as the third clock signal during the display on period or selects the second clock signal as the third clock signal during the display off period in response to the locking signal.
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TW201911002A (en) 2019-03-16
KR102383301B1 (en) 2022-04-05
CN109389956B (en) 2022-02-01

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