TWI771219B

TWI771219B - A VCSEL device manufacturing method using surface mount technology to simplify the packaging process and a VCSEL device structure fabricated by this method

Info

Publication number: TWI771219B
Application number: TW110140373A
Authority: TW
Inventors: 張席寧; 潘德烈
Original assignee: 兆勁科技股份有限公司
Priority date: 2021-10-29
Filing date: 2021-10-29
Publication date: 2022-07-11
Also published as: TW202318746A

Abstract

本發明係一種VCSEL元件製程方法及其結構，包含呈一T型柱態樣且其上覆設有一藍寶石層之雙異質半導體，該T型柱具有相互連接之一柱體與一橫體，該柱體由下至上為一N-DBR層、一主動層及一P-DBR層之部分，該橫體由下至上為部分該P-DBR層及該藍寶石層，該藍寶石層表面對應該柱體位置形成有一微結構。該柱體之該N-DBR層設有一N型金屬電極；該柱體兩側之該P-DBR層分別設有一P型金屬電極。該橫體表面設一抗反射膜，該橫體下表面及該柱體表面未設有電極處披覆一保護膜，各該P型金屬電極向下延伸至與該N型金屬電極底部齊平之位置而連接一封裝基板，以實現SMT封裝。 The present invention relates to a VCSEL device manufacturing method and structure, comprising a double hetero semiconductor in the form of a T-shaped column and a sapphire layer covering the T-shaped column, the T-shaped column has a column body and a transverse body connected to each other, the The pillar is part of an N-DBR layer, an active layer and a P-DBR layer from bottom to top, the transverse body is part of the P-DBR layer and the sapphire layer from bottom to top, and the surface of the sapphire layer corresponds to the pillar The location forms a microstructure. The N-DBR layer of the column is provided with an N-type metal electrode; the P-DBR layers on both sides of the column are respectively provided with a P-type metal electrode. An anti-reflection film is arranged on the surface of the horizontal body, and a protective film is covered on the lower surface of the horizontal body and the surface of the cylindrical body without electrodes, and each of the P-type metal electrodes extends downward to be flush with the bottom of the N-type metal electrodes. The position is connected to a package substrate to realize SMT package.

Description

採用表面貼合技術簡化封裝工序之VCSEL元件製程方法及利用此方法所製成之VCSEL元件結構 A VCSEL device manufacturing method using surface mount technology to simplify the packaging process and a VCSEL device structure fabricated by this method

本發明係與VCSEL元件有關，尤其是一種採用表面貼合技術簡化封裝工序之VCSEL元件製程方法及利用此方法所製成之VCSEL元件結構。 The present invention relates to a VCSEL element, in particular to a VCSEL element fabrication method using surface-mounting technology to simplify the packaging process and a VCSEL element structure fabricated by the method.

VCSEL(Vertical Cavity Surface Emitting Laser，垂直共振腔面射型雷射)元件泛屬LD(Laser Diode，半導體雷射)元件的一種，其係利用高反射率之分佈式布拉格反射鏡層(Distributed Bragg Reflector,DBR)產生共振腔而使雷射光由晶粒表面垂直發射出來。只是，高反射率之DBR是用兩種不同折射率的材料交互堆疊而成，除有反射率分布曲線尖銳的問題外，亦有因晶體介面上明顯能隙差異而造成串聯電阻過大的情況存在，且P型DBR(P-DBR)的電洞具有較大有效質量而反應有較大電阻的問題，造成VCSEL的晶圓芯片轉化效率低而存在有嚴重的散熱問題。為解決此問題，習知技藝多從晶圓芯片的材質著手來提升散熱率，只是，由於功率密度極高的VCSEL元件結構是垂直結構，且850nmVCSEL元件無法由基板方向出光，因此元件封裝製程一般係使晶圓芯片上方架設透鏡並與基板做成三維腔室的架構來進行。如此，若芯片與基板間熱膨脹系數失配，將於封裝製程中出現脫層或翹曲等應力現象，導致製程效率低落及良率不佳等問題。 VCSEL (Vertical Cavity Surface Emitting Laser, Vertical Resonant Cavity Surface Emitting Laser) element is a kind of LD (Laser Diode, semiconductor laser) element, which uses a distributed Bragg reflector layer with high reflectivity (Distributed Bragg Reflector) , DBR) to generate a resonant cavity so that the laser light is emitted vertically from the surface of the grain. However, the high reflectivity DBR is made of two materials with different refractive indices stacked alternately. In addition to the problem of sharp reflectivity distribution curve, there are also cases where the series resistance is too large due to the obvious energy gap difference on the crystal interface. , and the hole of P-type DBR (P-DBR) has a large effective mass and has a large resistance problem, resulting in a low conversion efficiency of the VCSEL wafer chip and a serious heat dissipation problem. In order to solve this problem, the conventional techniques mostly start from the material of the wafer chip to improve the heat dissipation rate. However, since the VCSEL element structure with extremely high power density is a vertical structure, and the 850nm VCSEL element cannot emit light from the direction of the substrate, the device packaging process is generally It is carried out by setting up a lens above the wafer chip and forming a three-dimensional chamber structure with the substrate. In this way, if the thermal expansion coefficient between the chip and the substrate is mismatched, stress phenomena such as delamination or warpage will occur in the packaging process, resulting in problems such as low process efficiency and poor yield.

有感於此，如何實現晶圓貼合基板的元件結構而製成SMT(Surface Mount Technology，表面貼合技術)元件，藉以增加散熱面積而降低元件熱阻的同時，減少封裝體積並改善上述習知技術之缺失，即本發明所欲探究之課題。 In view of this, how to realize the component structure of wafer bonding substrate to make SMT (Surface Mount Technology, surface mount technology) components, so as to increase the heat dissipation area and reduce the thermal resistance of components, reduce the package volume and improve the above-mentioned conventional The lack of known technology is the subject of the present invention.

有鑑於上述問題，本發明之目的旨在提供一種採用表面貼合技術簡化封裝工序之VCSEL元件製程方法及利用此方法所製成之VCSEL元件結構，以透過晶圓貼合的方式減少封裝體積並簡化封裝製程之製程時間。 In view of the above-mentioned problems, the purpose of the present invention is to provide a VCSEL device manufacturing method that simplifies the packaging process by using surface bonding technology and a VCSEL device structure fabricated by using the method, so as to reduce the packaging volume and reduce the packaging volume through wafer bonding. Simplifies the process time of the packaging process.

為達上述目的，本發明係揭露一種採用表面貼合技術簡化封裝工序之VCSEL元件製程方法，係針對一雙異質半導體結構進行加工處理，以製成一VCSEL元件結構，且該雙異質半導體結構由下而上至少具有一半導體基材、一N-DBR層、一主動層及一P-DBR層，其特徵在於：設置一藍寶石層於該雙異質半導體結構上而使該藍寶石層鄰接於該P-DBR層上後，移除該半導體基材；由該N-DBR層朝該P-DBR層方向蝕刻該雙異質半導體結構，使移除部份之該N-DBR層、該主動層及該P-DBR層而形成一T型柱，該T型柱具有相互連接之一柱體與一橫體，且由該藍寶石層向下延伸一段距離之該P-DBR層未受蝕刻移除；對應該T型柱之該柱體位置進行氧化而形成至少一環形氧化層，其中，該環形氧化層係由該柱體側面向內延伸設置；於該藍寶石層表面形成一微結構，且該微結構係對應成型於該T型柱之該柱體位置，以供控制激發光光源角度；披覆一抗反射膜(Anti-Reflection Film,AR Film)於該T型柱之該橫體上表面上而包覆該微結構及該藍寶石層，且披覆一保護膜(Passivation)於該T型柱之該橫體下表面及該柱體表面上而包覆該P-DBR層、該主動層及該N-DBR層；蝕刻披覆該T型柱之該柱體端部之該保護膜，而使部分之該N-DBR層露出，並鄰接設置一N型金屬電極於露出之該N-DBR層；蝕刻披覆T型柱之該柱體兩側旁之該橫體的該保護膜，而使部分之該P-DBR層露出，分別鄰接設置一P型金屬電極於該柱體兩側之該橫體露出之該P-DBR層，且各該P型金屬電極係向下延伸至與該N型金屬電極底部齊平之位置；及設置一封裝基板而鄰接於該N型金屬電極及該等P型金屬電極下。 In order to achieve the above-mentioned object, the present invention discloses a VCSEL device manufacturing method using surface-mounting technology to simplify the packaging process, which is to process a double hetero semiconductor structure to make a VCSEL device structure, and the double hetero semiconductor structure is composed of There is at least a semiconductor substrate, an N-DBR layer, an active layer and a P-DBR layer from bottom to top, and it is characterized in that: a sapphire layer is arranged on the double hetero semiconductor structure so that the sapphire layer is adjacent to the P-DBR layer. - After the DBR layer is placed, the semiconductor substrate is removed; the double hetero semiconductor structure is etched from the N-DBR layer toward the P-DBR layer, so that part of the N-DBR layer, the active layer and the The P-DBR layer forms a T-shaped column, the T-shaped column has a column body and a transverse body connected to each other, and the P-DBR layer extending downward from the sapphire layer for a distance is not removed by etching; The position of the column body of the T-shaped column should be oxidized to form at least one annular oxide layer, wherein the annular oxide layer is extended inward from the side surface of the column body; a microstructure is formed on the surface of the sapphire layer, and the microstructure It is correspondingly formed on the position of the column body of the T-shaped column for controlling the angle of the excitation light source; an anti-reflection film (Anti-Reflection Film, AR Film) is coated on the upper surface of the transverse body of the T-shaped column to Coating the microstructure and the sapphire layer, and coating a protective film (Passivation) on the transverse body of the T-shaped column Covering the P-DBR layer, the active layer and the N-DBR layer on the lower surface and the surface of the column; etching the protective film covering the end of the column of the T-shaped column, so that part of the The N-DBR layer is exposed, and an N-type metal electrode is disposed adjacent to the exposed N-DBR layer; the protective film covering the transverse body on both sides of the column body of the T-type column is etched, so that part of the The P-DBR layer is exposed, and a P-type metal electrode is disposed adjacent to the P-DBR layer exposed by the transverse body on both sides of the column, and each of the P-type metal electrodes extends downward to the N-type metal electrode. a position where the bottom is flush; and a package substrate is disposed adjacent to the N-type metal electrodes and the P-type metal electrodes.

其中，該VCSEL元件係為850nm雷射光源，且該半導體基材係採用GaAs材料，該抗反射膜採用SiOxNy或SiNx材料。該微結構係利用光阻轉印而成型於該藍寶石層；或該微結構係利用蝕刻工序加工該藍寶石層而成型。該雙異質半導體結構數量為二個以上時，係共用單一之該藍寶石層覆設於陣列排置之該等雙異質半導體結構上以進行製程，而形成陣列出光並控制激發光發射方向。 Wherein, the VCSEL element is an 850nm laser light source, the semiconductor substrate is made of GaAs material, and the anti-reflection film is made of SiOxNy or SiNx material. The microstructure is formed on the sapphire layer by photoresist transfer printing; or the microstructure is formed by processing the sapphire layer by an etching process. When the number of the double-hetero semiconductor structures is more than two, a single sapphire layer is shared on the double-hetero semiconductor structures arranged in an array to perform a process to form an array to emit light and control the emission direction of the excitation light.

另外，本發明之次一目的係揭示一種採用表面貼合技術簡化封裝工序之VCSEL元件結構，係包含一雙異質半導體結構，且該雙異質半導體結構由下而上至少具有一半導體基材、一N-DBR層、一主動層及一P-DBR層，其特徵在於：該P-DBR層上覆設有一藍寶石層，該雙異質半導體結構係呈一T型柱之設置態樣，該T型柱具有相互連接之一柱體與一橫體，該柱體由下至上為該N-DBR層、該主動層及部分該P-DBR層，該橫體由下至上為部分該P-DBR層及該藍寶石層，該藍寶石層表面對應該柱體位置形成有一微結構，且該柱體側面向內延伸設置有至少一環形氧化層；該柱體之該N-DBR層係連接設有一N型金屬電極；該柱體兩側旁之該橫體之該P-DBR層，係分別連接設有一P型金屬電極；其中，該橫體之該藍寶石層表面係披覆有一抗反射膜，該柱體表面及該橫體之該P-DBR層表面未設有該N型金屬電極及該P型金屬電極處，係披覆有一保護膜，且各該P型金屬電極係向下延伸至與該N型金屬電極底部齊平之位置而連接於一封裝基板。 In addition, another object of the present invention is to disclose a VCSEL device structure using surface-mounting technology to simplify the packaging process, which includes a double hetero semiconductor structure, and the double hetero semiconductor structure has at least a semiconductor substrate, a The N-DBR layer, an active layer and a P-DBR layer are characterized in that: the P-DBR layer is covered with a sapphire layer, the double hetero semiconductor structure is in the form of a T-shaped column, and the T-shaped The column has a column body and a transverse body connected to each other, the column body is the N-DBR layer, the active layer and part of the P-DBR layer from bottom to top, and the transverse body is part of the P-DBR layer from bottom to top and the sapphire layer, a microstructure is formed on the surface of the sapphire layer corresponding to the position of the column, and at least one annular oxide layer is arranged on the side of the column to extend inward; the N-DBR layer of the column is connected with an N-type metal electrodes; the P-DBR layers of the transverse body on both sides of the cylinder are respectively connected with a P-type metal electrode; Wherein, the surface of the sapphire layer of the horizontal body is covered with an anti-reflection film, the surface of the cylindrical body and the surface of the P-DBR layer of the horizontal body are not provided with the N-type metal electrode and the P-type metal electrode. A protective film is covered, and each of the P-type metal electrodes extends downward to a position flush with the bottom of the N-type metal electrodes and is connected to a package substrate.

其中，該VCSEL元件結構係為850nm雷射光源，該半導體基材係採用GaAs材料，該抗反射膜採用SiOxNy或SiNx材料。 Wherein, the VCSEL element structure is an 850nm laser light source, the semiconductor substrate is made of GaAs material, and the anti-reflection film is made of SiOxNy or SiNx material.

再者，本發明之再一目的係揭示一種採用表面貼合技術簡化封裝工序之VCSEL元件結構，係包含複數個雙異質半導體結構，且各該雙異質半導體結構由下而上至少具有一半導體基材、一N-DBR層、一主動層及一P-DBR層，其特徵在於：該等雙異質半導體結構之P-DBR層上係覆設共用之一藍寶石層，其中各該雙異質半導體結構係分別呈一T型柱之設置態樣，各該T型柱具有相互連接之一柱體與一橫體，該柱體由下至上為該N-DBR層、該主動層及部分該P-DBR層，該橫體由下至上為部分該P-DBR層及該藍寶石層，該藍寶石層表面對應該柱體位置分別形成有一微結構，且該柱體側面向內延伸設置有至少一環形氧化層；該柱體之該N-DBR層係連接設有一N型金屬電極；該柱體兩側旁之該橫體之該P-DBR層，係分別連接設有一P型金屬電極；其中，該橫體之該藍寶石層表面係披覆有一抗反射膜，該T型柱之未設有該N型金屬電極及該P型金屬電極之該柱體表面及該橫體之該P-DBR層表面處，係披覆有一保護膜，且各該P型金屬電極係向下延伸至與該N型金屬電極底部齊平之位置而連接於一封裝基板。 Furthermore, another object of the present invention is to disclose a VCSEL device structure using surface mount technology to simplify the packaging process, which includes a plurality of double hetero semiconductor structures, and each of the double hetero semiconductor structures has at least one semiconductor base from bottom to top. material, an N-DBR layer, an active layer and a P-DBR layer, characterized in that: a common sapphire layer is covered on the P-DBR layers of the double hetero semiconductor structures, wherein each of the double hetero semiconductor structures They are respectively in the configuration of a T-shaped column. Each of the T-shaped columns has a column body and a transverse body connected to each other. The column body is the N-DBR layer, the active layer and part of the P-DBR layer from bottom to top. DBR layer, the transverse body is part of the P-DBR layer and the sapphire layer from bottom to top, a microstructure is formed on the surface of the sapphire layer corresponding to the position of the column, and at least one annular oxide layer is formed on the side of the column extending inward layer; the N-DBR layer of the column is connected with an N-type metal electrode; the P-DBR layer of the transverse body on both sides of the column is connected with a P-type metal electrode respectively; wherein, the The surface of the sapphire layer of the transverse body is covered with an anti-reflection film, the surface of the column body of the T-type pillar without the N-type metal electrode and the P-type metal electrode and the surface of the P-DBR layer of the transverse body At the place, a protective film is covered, and each of the P-type metal electrodes extends downward to a position flush with the bottom of the N-type metal electrodes and is connected to a package substrate.

其中，該VCSEL元件結構係為850nm雷射光源，該半導體基材係採用GaAs材料，該抗反射膜採用SiOxNy或SiNx材料 Wherein, the VCSEL element structure is an 850nm laser light source, the semiconductor substrate is made of GaAs material, and the anti-reflection film is made of SiOxNy or SiNx material

綜上所述，本發明係採用移除該半導體基材後由下而上蝕刻該雙異質半導體結構，再於該柱體底部設置該N型金屬電極；及於該柱體兩側旁設置向下延伸至與該N型金屬電極底部齊平位置之該等P型金屬電極而形成晶圓貼合該封裝基板的形式，使增加散熱面積並降低元件熱阻，以增加光輸出效率並減少波長紅移熱效應的同時，實現SMT封裝技術而減少整體封裝製程時間，達增加生產速率之效果。再者，本發明係將一次性蝕刻形成該微結構之該藍寶石層作為架設於晶圓芯片上方之透鏡之用而降低發散角度並改變出光方向，進而調整激發光光源角度，且於該橫體表面上鍍佈該抗反射膜而減少不必要的光反射，以實現增加光耦合效率的效益。 To sum up, in the present invention, the double hetero semiconductor structure is etched from bottom to top after removing the semiconductor substrate, and then the N-type metal electrode is arranged at the bottom of the column; The P-type metal electrodes extending down to the bottom of the N-type metal electrode are formed to form a form in which the wafer is attached to the packaging substrate, so as to increase the heat dissipation area and reduce the thermal resistance of the components, so as to increase the light output efficiency and reduce the wavelength. At the same time of red-shifting the thermal effect, SMT packaging technology is realized to reduce the overall packaging process time, and achieve the effect of increasing the production rate. Furthermore, in the present invention, the sapphire layer formed by one-time etching to form the microstructure is used as a lens mounted on the top of the wafer chip to reduce the divergence angle and change the light output direction, thereby adjusting the angle of the excitation light source, and in the horizontal body The anti-reflection film is coated on the surface to reduce unnecessary light reflection, so as to realize the benefit of increasing the light coupling efficiency.

1:VCSEL元件結構 1: VCSEL element structure

10:雙異質半導體結構 10: Double hetero semiconductor structure

100:半導體基材 100: Semiconductor substrate

101:N-DBR層 101: N-DBR Layer

102:主動層 102: Active layer

103:P-DBR層 103: P-DBR layer

11:藍寶石層 11: Sapphire layer

110:微結構 110: Microstructure

12:環形氧化層 12: Annular oxide layer

130:抗反射膜 130: Anti-reflection film

131:保護膜 131: Protective film

14:N型金屬電極 14: N-type metal electrode

15:P型金屬電極 15: P-type metal electrode

16:封裝基板 16: Package substrate

S1~S16:步驟 S1~S16: Steps

第1圖，為本發明一較佳實施例之流程圖。 FIG. 1 is a flow chart of a preferred embodiment of the present invention.

第2A、2B圖，為本發明二較佳實施例之狀態流程示意圖。 Figures 2A and 2B are schematic diagrams of the state flow of the second preferred embodiment of the present invention.

第3圖，為本發明三較佳實施例之結構示意圖。 FIG. 3 is a schematic structural diagram of three preferred embodiments of the present invention.

為使本領域具有通常知識者能清楚了解本發明之內容，謹以下列說明搭配圖式，敬請參閱。 In order to enable those skilled in the art to clearly understand the content of the present invention, please refer to the following descriptions and drawings.

請參閱第1、2A、2B圖，其係分別為本發明一較佳實施例之流程圖及二較佳實施例之狀態流程示意圖。如圖所示，採用表面貼合技術簡化封裝工序之VCSEL元件製程方法係針對一雙異質半導體結構10進行加工處理而製成一VCSEL元件結構1，其包含下列步驟。其中，該雙異質半導體結構10由下而上至少具有一半導體基材100、一N-DBR層101、一主動層102及一P-DBR層103，且該半導體基材100可採用GaAs材料。 Please refer to Figures 1, 2A, and 2B, which are respectively a flow chart of a preferred embodiment and a state flow diagram of two preferred embodiments of the present invention. As shown in the figure, the VCSEL device manufacturing method using the surface mount technology to simplify the packaging process is fabricated by processing a double hetero semiconductor structure 10 A VCSEL device structure 1 includes the following steps. The double hetero semiconductor structure 10 has at least a semiconductor substrate 100 , an N-DBR layer 101 , an active layer 102 and a P-DBR layer 103 from bottom to top, and the semiconductor substrate 100 can be made of GaAs material.

步驟S10，設置一藍寶石層11於該雙異質半導體結構10上而使該藍寶石層11鄰接於該P-DBR層103上後，移除該半導體基材100。步驟S11，由該N-DBR層101朝該P-DBR層103方向蝕刻該雙異質半導體結構10，使移除部份之該N-DBR層101、該主動層102及該P-DBR層103而形成一T型柱，該T型柱具有相互連接之一柱體與一橫體，且由該藍寶石層11向下延伸一段距離之該P-DBR層103未受蝕刻移除。步驟S12，對應該T型柱之該柱體位置進行氧化而形成至少一環形氧化層12，且該環形氧化層12係由該柱體側面向內延伸設置。其中，當該環形氧化層12為複數型態時，該等環形氧化層12中最接近該主動層102之一者，其向內延伸長度係大於其餘之該等環形氧化層12。製程上，係將欲氧化處材料設置為高含鋁層，並在利用氧化製程技術後形成該環形氧化層12，由於高含鋁層氧化速度較快，故因此產生之該環形氧化層12由該柱體側面向內延伸之長度較長，藉此以形成侷限作用。相較之下，其餘處之該等環形氧化層12則透過低含鋁層所氧化製成，故氧化速率較慢，其向內延伸長度即相對較短。 In step S10 , after disposing a sapphire layer 11 on the double hetero semiconductor structure 10 so that the sapphire layer 11 is adjacent to the P-DBR layer 103 , the semiconductor substrate 100 is removed. Step S11, the double hetero semiconductor structure 10 is etched from the N-DBR layer 101 toward the P-DBR layer 103, so as to remove part of the N-DBR layer 101, the active layer 102 and the P-DBR layer 103 A T-shaped column is formed, the T-shaped column has a column body and a transverse body connected to each other, and the P-DBR layer 103 extending downward for a distance from the sapphire layer 11 is not removed by etching. In step S12, at least one annular oxide layer 12 is formed by oxidizing the position of the column body of the T-shaped column, and the annular oxide layer 12 is extended inward from the side surface of the column body. Wherein, when the annular oxide layers 12 are plural types, the inward extension length of the annular oxide layers 12 closest to the active layer 102 is greater than that of the other annular oxide layers 12 . In the process, the material to be oxidized is set as a high aluminum-containing layer, and the annular oxide layer 12 is formed after using the oxidation process technology. Since the oxidation rate of the high aluminum-containing layer is relatively fast, the annular oxide layer 12 produced is formed by The length of the inward extension of the side surface of the column is relatively long, thereby forming a confinement effect. In contrast, the rest of the annular oxide layers 12 are formed by oxidizing the low aluminum-containing layer, so the oxidation rate is slow, and the inward extension length thereof is relatively short.

步驟S13，於該藍寶石層11表面形成一微結構110，且該微結構110係對應成型於該T型柱之該柱體位置，並且，該微結構110對應該柱體位置係不限定於對應該柱體正中間位置而亦可依光源需求設計為偏右或偏左之位置，以供改變出光方向而控制激發光光源角度。於本實施列中，該微結構110可利用光阻轉印而成型於該藍寶石層11，或者，該微結構110可利用蝕刻工序加工該藍寶石層11而製成成型。步驟S14，披覆採用SiOxNy或SiNx材料之一抗反射膜130於該T型柱之該橫體上表面上而包覆該微結構110及該藍寶石層11，且披覆一保護膜131於該T型柱之該橫體下表面及該柱體表面上而包覆該P-DBR層103、該主動層102及該N-DBR層101。步驟S15，蝕刻披覆該T型柱之該柱體端部之該保護膜131，而使部分之該N-DBR層101露出，並鄰接設置一N型金屬電極14於露出之該N-DBR層101；蝕刻披覆T型柱之該柱體兩側旁之該橫體的該保護膜131，而使部分之該P-DBR層103露出，分別鄰接設置一P型金屬電極15於該柱體兩側之該橫體露出之該P-DBR層103，且各該P型金屬電極15係向下延伸至與該N型金屬電極14底部齊平之位置。步驟S16，設置一封裝基板16而鄰接於該N型金屬電極14及該等P型金屬電極15下，以製成該VCSEL元件結構1，且該VCSEL元件結構1可為850nm雷射光源。 In step S13, a microstructure 110 is formed on the surface of the sapphire layer 11, and the microstructure 110 is formed corresponding to the position of the column of the T-shaped column, and the position of the microstructure 110 corresponding to the column is not limited to The position of the center of the column should be right or left according to the requirements of the light source, so as to change the direction of light output and control the angle of the excitation light source. In this embodiment, the microstructure 110 can be formed on the sapphire layer 11 by photoresist transfer printing, or the microstructure 110 can be formed by processing the sapphire layer 11 by an etching process. Step S14, coating an anti-reflection film 130 made of SiOxNy or SiNx material on the The microstructure 110 and the sapphire layer 11 are covered on the upper surface of the transverse body of the T-shaped column, and a protective film 131 is coated on the lower surface of the transverse body of the T-shaped column and the surface of the column body to cover the microstructure 110 and the sapphire layer 11 The P-DBR layer 103 , the active layer 102 and the N-DBR layer 101 are covered. Step S15, etching the protective film 131 covering the end of the column body of the T-type column to expose a part of the N-DBR layer 101, and adjacently disposing an N-type metal electrode 14 on the exposed N-DBR layer 101; etching the protective film 131 covering the transverse body on both sides of the column body of the T-type column to expose a part of the P-DBR layer 103, respectively setting a P-type metal electrode 15 adjacent to the column The P-DBR layer 103 is exposed by the lateral bodies on both sides of the body, and each of the P-type metal electrodes 15 extends downward to a position flush with the bottom of the N-type metal electrode 14 . In step S16, a package substrate 16 is disposed adjacent to the N-type metal electrodes 14 and the P-type metal electrodes 15 to form the VCSEL element structure 1, and the VCSEL element structure 1 can be an 850 nm laser light source.

如此，該VCSEL元件結構1係包含該雙異質半導體結構10，該雙異質半導體結構10由下而上至少具有該N-DBR層101、該主動層102及該P-DBR層103，且該P-DBR層103上覆設該藍寶石層11。該雙異質半導體結構10係呈該T型柱之設置態樣，該T型柱具有相互連接之該柱體與該橫體，該柱體由下至上為該N-DBR層101、該主動層102及部分該P-DBR層103，該橫體由下至上為部分該P-DBR層103及該藍寶石層11。該藍寶石層11表面對應該柱體位置形成有該微結構110，以供單顆之該VCSEL元件結構1控制激發光源角度而使發散角度降低並增加光耦合效率。 In this way, the VCSEL device structure 1 includes the double hetero semiconductor structure 10 , and the double hetero semiconductor structure 10 has at least the N-DBR layer 101 , the active layer 102 and the P-DBR layer 103 from bottom to top, and the P The sapphire layer 11 is overlaid on the DBR layer 103 . The double hetero semiconductor structure 10 is in the configuration of the T-type pillar. The T-type pillar has the pillar body and the transverse body connected to each other. The pillar body is the N-DBR layer 101 and the active layer from bottom to top. 102 and part of the P-DBR layer 103 , the transverse body is part of the P-DBR layer 103 and the sapphire layer 11 from bottom to top. The microstructure 110 is formed on the surface of the sapphire layer 11 corresponding to the position of the column, for the single VCSEL element structure 1 to control the angle of the excitation light source to reduce the divergence angle and increase the light coupling efficiency.

並且，該柱體側面向內延伸設置有至少一該環形氧化層12，該柱體之該N-DBR層101係連接設有該N型金屬電極14，該柱體兩側旁之該橫體之該P-DBR層103係分別連接設有該P型金屬電極15。該橫體之該藍寶石層11表面係披覆有該抗反射膜130，以供作為抗反射之用，且受該VCSEL元件結構1之該 P-DBR層103及該N-DBR層101的反射率設計結構所致，激光係僅由該P-DBR層103出光，故該T型柱之該柱體表面及該橫體之該P-DBR層103表面未設有該N型金屬電極14及該P型金屬電極15處係披覆有該保護膜131，以供作包覆而保護元件之用，使實現提高產品可靠度之效果。各該P型金屬電極15係向下延伸至與該N型金屬電極14底部齊平之位置而連接於該封裝基板16，如此，即減少封裝體積並簡化封裝製程。 In addition, at least one annular oxide layer 12 is disposed on the side surface of the column body, the N-DBR layer 101 of the column body is connected with the N-type metal electrode 14, and the horizontal body on both sides of the column body is connected with the N-type metal electrode 14. The P-DBR layers 103 are respectively connected with the P-type metal electrodes 15 . The surface of the sapphire layer 11 of the transverse body is covered with the anti-reflection film 130 for anti-reflection and is affected by the VCSEL element structure 1 Due to the reflectivity design structure of the P-DBR layer 103 and the N-DBR layer 101, the laser is only emitted from the P-DBR layer 103, so the surface of the column of the T-shaped column and the P- The surface of the DBR layer 103 is not provided with the N-type metal electrode 14 and the P-type metal electrode 15 is covered with the protective film 131 for cladding and protecting components, so as to achieve the effect of improving product reliability. Each of the P-type metal electrodes 15 extends downward to a position flush with the bottom of the N-type metal electrode 14 and is connected to the package substrate 16 , thus reducing the package volume and simplifying the packaging process.

另外，本發明之另一實施例可為採用二個以上數量之該等雙異質半導體結構10而共用單一之該藍寶石層11之設置態樣，如圖3所示，以使該藍寶石層11覆設於陣列排置之該等雙異質半導體結構10上而進行製程，據此形成陣列出光並控制激發光發射方向。換言之，該VCSEL元件結構1係包含複數之該等雙異質半導體結構10，且各該雙異質半導體結構10由下而上至少具有該N-DBR層101、該主動層102及該P-DBR層103。該等雙異質半導體結構10之P-DBR層103上係覆設共用之該藍寶石層11，其中各該雙異質半導體結構10分別呈該T型柱之設置態樣，各該T型柱具有相互連接之該柱體與該橫體，該柱體由下至上為該N-DBR層101、該主動層102及部分該P-DBR層103，該橫體由下至上為部分該P-DBR層103及該藍寶石層11。該藍寶石層11表面對應該柱體位置分別形成有該微結構110而可控制激發光發射方向，且該柱體側面向內延伸設置有至少一該環形氧化層12。該柱體之該N-DBR層101連接設有該N型金屬電極14，且該柱體兩側旁之該橫體之該P-DBR層103係分別連接設有該P型金屬電極15，其中，該橫體之該藍寶石層11表面係披覆有該抗反射膜130，該T型柱之未設有該N型金屬電極14及該P型金屬電極15之該柱體表面及該橫體之該P-DBR層103表面處，係披覆有該保護膜131，且各該P型金屬電極15係向下延伸至與該N型金屬電極14底部齊平之位置而連接於該封裝基板16。如此，即形成陣列出光之該VCSEL元件結構1，可減少封裝製程之製作時間並增加生產速度，且各該微結構110並不限定一致於對應該柱體正中間位置而亦可依光源需求設計分別為偏右或偏左之位置，以達改變陣列出光方向之效果。 In addition, another embodiment of the present invention may use two or more of the double hetero semiconductor structures 10 to share a single sapphire layer 11 , as shown in FIG. 3 , so that the sapphire layer 11 covers the A process is performed on the double hetero semiconductor structures 10 arranged in an array, thereby forming an array to emit light and controlling the emission direction of the excitation light. In other words, the VCSEL device structure 1 includes a plurality of the double hetero semiconductor structures 10 , and each of the double hetero semiconductor structures 10 has at least the N-DBR layer 101 , the active layer 102 and the P-DBR layer from bottom to top 103. The P-DBR layer 103 of the double hetero semiconductor structures 10 is covered with the common sapphire layer 11 , wherein the double hetero semiconductor structures 10 are respectively in the configuration of the T-type pillars, and the T-type pillars have mutual The column and the cross body are connected, the column body is the N-DBR layer 101, the active layer 102 and part of the P-DBR layer 103 from bottom to top, the cross body is part of the P-DBR layer from bottom to top 103 and the sapphire layer 11. The microstructures 110 are formed on the surface of the sapphire layer 11 corresponding to the positions of the pillars to control the emission direction of excitation light, and at least one annular oxide layer 12 is disposed on the side surfaces of the pillars extending inward. The N-DBR layer 101 of the pillar is connected with the N-type metal electrode 14, and the P-DBR layer 103 of the transverse body on both sides of the pillar is connected with the P-type metal electrode 15, respectively. Wherein, the surface of the sapphire layer 11 of the horizontal body is covered with the anti-reflection film 130, and the surface of the cylindrical body and the horizontal surface of the T-type column without the N-type metal electrode 14 and the P-type metal electrode 15 are not provided. The surface of the P-DBR layer 103 of the body is covered with the protective film 131 , and each of the P-type metal electrodes 15 extends downward to the bottom of the N-type metal electrode 14 It is connected to the package substrate 16 in a flush position. In this way, the VCSEL device structure 1 for emitting light in an array can be formed, which can reduce the fabrication time of the packaging process and increase the production speed. Moreover, the microstructures 110 are not limited to correspond to the center position of the column, but can also be designed according to the requirements of the light source. The positions are to the right or left, respectively, to achieve the effect of changing the light output direction of the array.

惟，以上所述者，僅為本發明之較佳實施例而已，並非用以限定本發明實施之範圍；故在不脫離本發明之精神與範圍下所作之均等變化與修飾，皆應涵蓋於本發明之專利範圍內。 However, the above descriptions are only preferred embodiments of the present invention, and are not intended to limit the scope of implementation of the present invention; therefore, equivalent changes and modifications made without departing from the spirit and scope of the present invention should be included in the within the scope of the patent of the present invention.

S1~S16:步驟 S1~S16: Steps

Claims

一種採用表面貼合技術簡化封裝工序之VCSEL元件製程方法，係針對一雙異質半導體結構進行加工處理，且該雙異質半導體結構由下而上至少具有一半導體基材、一N-DBR層、一主動層及一P-DBR層，其特徵在於：設置一藍寶石層於該雙異質半導體結構上而使該藍寶石層鄰接於該P-DBR層上後，移除該半導體基材；由該N-DBR層朝該P-DBR層方向蝕刻該雙異質半導體結構，使移除部份之該N-DBR層、該主動層及該P-DBR層而形成一T型柱，該T型柱具有相互連接之一柱體與一橫體，且由該藍寶石層向下延伸一段距離之該P-DBR層未受蝕刻移除；對應該T型柱之該柱體位置進行氧化而形成至少一環形氧化層，其中，該環形氧化層係由該柱體側面向內延伸設置；於該藍寶石層表面形成一微結構，且該微結構係對應成型於該T型柱之該柱體位置，以供控制激發光光源角度；披覆一抗反射膜於該T型柱之該橫體上表面上而包覆該微結構及該藍寶石層，且披覆一保護膜於該T型柱之該橫體下表面及該柱體表面上而包覆該P-DBR層、該主動層及該N-DBR層；蝕刻披覆該T型柱之該柱體端部之該保護膜，而使部分之該N-DBR層露出，並鄰接設置一N型金屬電極於露出之該N-DBR層；蝕刻披覆T型柱之該柱體兩側旁之該橫體的該保護膜，而使部分之該P-DBR層露出，分別鄰接設置一P型金屬電極於該柱體兩側之該橫體露出之該P-DBR層，且各該P型金屬電極係向下延伸至與該N型金屬電極底部齊平之位置；及設置一封裝基板而鄰接於該N型金屬電極及該等P型金屬電極下。 A method for manufacturing a VCSEL element using surface bonding technology to simplify the packaging process, which is to process a double-heterogeneous semiconductor structure, and the double-heterogeneous semiconductor structure has at least a semiconductor substrate, an N-DBR layer, a The active layer and a P-DBR layer are characterized in that: after disposing a sapphire layer on the double hetero semiconductor structure so that the sapphire layer is adjacent to the P-DBR layer, the semiconductor substrate is removed; The DBR layer is etched toward the P-DBR layer to etch the double hetero semiconductor structure, so that part of the N-DBR layer, the active layer and the P-DBR layer is removed to form a T-type pillar, and the T-type pillar has mutual A pillar is connected with a transverse, and the P-DBR layer extending downward for a distance from the sapphire layer is not removed by etching; the position of the pillar of the T-type pillar is oxidized to form at least one annular oxide layer, wherein the annular oxide layer is extended inward from the side surface of the column body; a microstructure is formed on the surface of the sapphire layer, and the microstructure is formed corresponding to the position of the column body of the T-shaped column for control The angle of excitation light source; Coating an anti-reflection film on the upper surface of the transverse body of the T-shaped column to cover the microstructure and the sapphire layer, and coating a protective film under the transverse body of the T-shaped column Cover the P-DBR layer, the active layer and the N-DBR layer on the surface and the surface of the column; etch the protective film covering the end of the column of the T-type column, so that part of the N-DBR layer is - The DBR layer is exposed, and an N-type metal electrode is placed adjacent to the exposed N-DBR layer; the protective film of the transverse body on both sides of the column body of the T-type column is etched to make part of the P - The DBR layer is exposed, and a P-type metal electrode is disposed adjacent to the P-DBR layer exposed by the transverse body on both sides of the column, and each of the P-type metal electrodes extends downward to the bottom of the N-type metal electrode a flush position; and a package substrate is arranged adjacent to the N-type metal electrodes and the P-type metal electrodes.

如請求項1所述之採用表面貼合技術簡化封裝工序之VCSEL元件製程方法，其中，該VCSEL元件係為850nm雷射光源，且該半導體基材係採用GaAs材料，該抗反射膜採用SiOxNy或SiNx材料。 The method for manufacturing a VCSEL element using surface bonding technology to simplify the packaging process as described in claim 1, wherein the VCSEL element is an 850nm laser light source, the semiconductor substrate is made of GaAs material, and the anti-reflection film is made of SiOxNy or SiNx material.

如請求項1所述之採用表面貼合技術簡化封裝工序之VCSEL元件製程方法，其中，該微結構係利用光阻轉印而成型於該藍寶石層；或該微結構係利用蝕刻工序加工該藍寶石層而成型。 The VCSEL device manufacturing method using surface bonding technology to simplify the packaging process as described in claim 1, wherein the microstructure is formed on the sapphire layer by photoresist transfer printing; or the microstructure is processed by etching the sapphire layer layered.

如請求項3所述之採用表面貼合技術簡化封裝工序之VCSEL元件製程方法，其中，該雙異質半導體結構數量為二個以上時，係共用單一之該藍寶石層覆設於陣列排置之該等雙異質半導體結構上以進行製程，而形成陣列出光並控制激發光發射方向。 The method for manufacturing a VCSEL device using surface-mounting technology to simplify the packaging process as described in claim 3, wherein when the number of the double-hetero semiconductor structures is two or more, a single sapphire layer is shared on the array-arranged sapphire layer. A process is performed on the double hetero semiconductor structure to form an array to emit light and to control the emission direction of the excitation light.

一種利用如請求項1~4其中任一項所述之採用表面貼合技術簡化封裝工序之VCSEL元件製程方法所製成之VCSEL元件結構。 A VCSEL device structure fabricated by using the VCSEL device process method for simplifying the packaging process by using the surface mount technology as described in any one of claims 1 to 4.

一種採用表面貼合技術簡化封裝工序之VCSEL元件結構，係包含一雙異質半導體結構，且該雙異質半導體結構由下而上至少具有一半導體基材、一N-DBR層、一主動層及一P-DBR層，其特徵在於：該P-DBR層上覆設有一藍寶石層，該雙異質半導體結構係呈一T型柱之設置態樣，該T型柱具有相互連接之一柱體與一橫體，該柱體由下至上為該N-DBR層、該主動層及部分該P-DBR層，該橫體由下至上為部分該P-DBR層及該藍寶石層，該藍寶石層表面對應該柱體位置形成有一微結構，且該柱體側面向內延伸設置有至少一環形氧化層；該柱體之該N-DBR層係連接設有一N型金屬電極；該柱體兩側旁之該橫體之該P-DBR層，係分別連接設有一P型金屬電極；其中，該橫體之該藍寶石層表面係披覆有一抗反射膜，該柱體表面及該橫體之該P-DBR層表面未設有該N型金屬電極及該P型金屬電極處，係披覆有一保護膜，且各該P型金屬電極係向下延伸至與該N型金屬電極底部齊平之位置而連接於一封裝基板。 A VCSEL element structure using surface bonding technology to simplify the packaging process, comprising a double hetero semiconductor structure, and the double hetero semiconductor structure has at least a semiconductor substrate, an N-DBR layer, an active layer and a The P-DBR layer is characterized in that: the P-DBR layer is covered with a sapphire layer, the double hetero semiconductor structure is in the form of a T-shaped column, and the T-shaped column has a column connected to each other and a Cross body, the column body is the N-DBR layer, the active layer and part of the P-DBR layer from bottom to top, the cross body is part of the P-DBR layer and the sapphire layer from bottom to top, the surface of the sapphire layer is opposite A microstructure should be formed at the position of the column, and at least one annular oxide layer is arranged on the side of the column to extend inward; the N-DBR layer of the column is connected with an N-type metal electrode; The P-DBR layer of the transverse body is respectively connected with a P-type metal electrode; wherein, the surface of the sapphire layer of the transverse body is covered with an anti-reflection film, and the surface of the column and the transverse body are The surface of the P-DBR layer without the N-type metal electrode and the P-type metal electrode is covered with a protective film, and each of the P-type metal electrodes extends downward to be flush with the bottom of the N-type metal electrode The position is connected to a package substrate.

如請求項6所述之VCSEL元件結構，係為850nm雷射光源，其中，該半導體基材係採用GaAs材料，該抗反射膜採用SiOxNy或SiNx材料。 The VCSEL element structure according to claim 6 is an 850 nm laser light source, wherein the semiconductor substrate is made of GaAs material, and the anti-reflection film is made of SiOxNy or SiNx material.

一種採用表面貼合技術簡化封裝工序之VCSEL元件結構，係包含複數個雙異質半導體結構，且各該雙異質半導體結構由下而上至少具有一半導體基材、一N-DBR層、一主動層及一P-DBR層，其特徵在於：該等雙異質半導體結構之P-DBR層上係覆設共用之一藍寶石層，其中各該雙異質半導體結構係分別呈一T型柱之設置態樣，各該T型柱具有相互連接之一柱體與一橫體，該柱體由下至上為該N-DBR層、該主動層及部分該P-DBR層，該橫體由下至上為部分該P-DBR層及該藍寶石層，該藍寶石層表面對應該柱體位置分別形成有一微結構，且該柱體側面向內延伸設置有至少一環形氧化層；該柱體之該N-DBR層係連接設有一N型金屬電極；該柱體兩側旁之該橫體之該P-DBR層，係分別連接設有一P型金屬電極；其中，該橫體之該藍寶石層表面係披覆有一抗反射膜，該T型柱之未設有該N型金屬電極及該P型金屬電極之該柱體表面及該橫體之該P-DBR層表面處，係披覆有一保護膜，且各該P型金屬電極係向下延伸至與該N型金屬電極底部齊平之位置而連接於一封裝基板。 A VCSEL element structure using surface bonding technology to simplify the packaging process, comprising a plurality of double-hetero semiconductor structures, and each of the double-hetero semiconductor structures has at least a semiconductor substrate, an N-DBR layer, and an active layer from bottom to top And a P-DBR layer, characterized in that: a common sapphire layer is covered on the P-DBR layers of the double-hetero semiconductor structures, wherein each of the double-hetero-semiconductor structures is in the configuration of a T-column respectively , each of the T-shaped columns has a column body and a transverse body connected to each other, the column body is the N-DBR layer, the active layer and part of the P-DBR layer from bottom to top, and the transverse body is part from bottom to top In the P-DBR layer and the sapphire layer, a microstructure is formed on the surface of the sapphire layer corresponding to the position of the column, and at least one annular oxide layer is formed on the side of the column to extend inward; the N-DBR layer of the column is An N-type metal electrode is connected to each other; the P-DBR layers of the transverse body on both sides of the cylinder are respectively connected to a P-type metal electrode; wherein, the surface of the sapphire layer of the transverse body is covered with a Anti-reflection film, the T-type pillar is not provided with the N-type metal electrode and the P-type metal electrode on the surface of the pillar body and the surface of the P-DBR layer of the cross body, is covered with a protective film, and each The P-type metal electrode extends downward to a position flush with the bottom of the N-type metal electrode and is connected to a package substrate.

如請求項8所述之VCSEL元件結構，係為850nm雷射光源，其中，該半導體基材係採用GaAs材料，該抗反射膜採用SiOxNy或SiNx材料。 The VCSEL element structure according to claim 8 is an 850 nm laser light source, wherein the semiconductor substrate is made of GaAs material, and the anti-reflection film is made of SiOxNy or SiNx material.