TWI767724B - Display device - Google Patents
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Description
本發明是有關於一種顯示裝置,且特別是有關於一種藉由對母板進行切割製程而形成的顯示裝置。The present invention relates to a display device, and more particularly, to a display device formed by cutting a motherboard.
在一些習知製作顯示裝置的方法中,會先在母板上製作好畫素陣列以及用於驅動此畫素陣列的驅動電路,之後對母板進行切割製程以形成所需的一個或多個顯示裝置。在製作的此顯示裝置為長條式顯示裝置(特別是直立式顯示裝置)的情況時,設置於此顯示裝置上的對位標記的對位精度會明顯地下降,其因閘極驅動電路是設置於直立式顯示裝置的長邊側,而使得對位標記僅能設置於顯示裝置的短邊側。基於此,當須利用對位標記以將偏光片等構件貼附於此顯示裝置時易產生偏離的現象。In some conventional methods of manufacturing display devices, a pixel array and a driving circuit for driving the pixel array are first fabricated on a motherboard, and then a cutting process is performed on the motherboard to form one or more desired ones display device. When the manufactured display device is a bar display device (especially a vertical display device), the alignment accuracy of the alignment marks provided on the display device will be significantly reduced, because the gate driving circuit is It is arranged on the long side of the vertical display device, so that the alignment mark can only be arranged on the short side of the display device. Based on this, when the alignment marks are used to attach components such as polarizers to the display device, deviations are likely to occur.
本發明提供一種顯示裝置,其可提升將構件設置於此顯示裝置上時的對位精度。The present invention provides a display device, which can improve the alignment accuracy when a component is arranged on the display device.
本發明的顯示裝置包括畫素陣列、閘極驅動電路以及對位標記。畫素陣列設置於主動區中。閘極驅動電路至少設置於周邊區的第一側中,且包括多個移位暫存單元以及多條時脈訊號線,其中相鄰的移位暫存單元之間具有間隙。多條時脈訊號線用以提供時脈訊號至多個移位暫存單元。對位標記設置於周邊區中,且設置於多個間隙的至少一者中。The display device of the present invention includes a pixel array, a gate driving circuit and an alignment mark. The pixel array is arranged in the active area. The gate driving circuit is disposed at least in the first side of the peripheral region, and includes a plurality of shift register units and a plurality of clock signal lines, wherein adjacent shift register units have gaps. A plurality of clock signal lines are used for providing clock signals to a plurality of shift register units. The alignment marks are disposed in the peripheral region and in at least one of the plurality of gaps.
在本發明的一實施例中,上述的顯示裝置更包括第一共用電壓接墊。第一共用電壓接墊設置於周邊區中,其中第一共用電壓接墊設置於多個間隙的至少一者中,且用以提供共用電壓訊號至畫素陣列。In an embodiment of the present invention, the above-mentioned display device further includes a first common voltage pad. The first common voltage pad is disposed in the peripheral region, wherein the first common voltage pad is disposed in at least one of the plurality of gaps, and is used for providing the common voltage signal to the pixel array.
在本發明的一實施例中,上述的顯示裝置更包括共用電壓線。共用電壓線與第一共用電壓接墊電性連接,且共用電壓訊號經由共用電壓線傳遞至畫素陣列。In an embodiment of the present invention, the above-mentioned display device further includes a common voltage line. The common voltage line is electrically connected to the first common voltage pad, and the common voltage signal is transmitted to the pixel array through the common voltage line.
在本發明的一實施例中,上述的多個移位暫存單元中的一者包括多個移位暫存器。多個移位暫存器的數量為多條時脈訊號線的數量的整數倍。In an embodiment of the present invention, one of the above-mentioned shift register units includes a plurality of shift registers. The number of the shift registers is an integer multiple of the number of the clock signal lines.
在本發明的一實施例中,上述的顯示裝置更包括多條時脈訊號傳遞線。多條時脈訊號傳遞線與多條時脈訊號線以及多個移位暫存單元電性連接,且時脈訊號經由多條時脈訊號傳遞線傳遞至多個移位暫存單元。In an embodiment of the present invention, the above-mentioned display device further includes a plurality of clock signal transmission lines. The plurality of clock signal transmission lines are electrically connected to the plurality of clock signal lines and the plurality of shift register units, and the clock signal is transmitted to the plurality of shift register units through the plurality of clock signal transmission lines.
在本發明的一實施例中,上述的顯示裝置更包括源極驅動電路。源極驅動電路至少設置於所述周邊區的第二側中。In an embodiment of the present invention, the above-mentioned display device further includes a source driving circuit. A source driving circuit is disposed at least in the second side of the peripheral region.
在本發明的一實施例中,上述的對位標記更設置於周邊區的第二側中。In an embodiment of the present invention, the above-mentioned alignment mark is further disposed on the second side of the peripheral area.
在本發明的一實施例中,上述的顯示裝置更包括第二共用電壓接墊。第二共用電壓接墊設置於所述周邊區中的第二側中,且用以提供共用電壓訊號至畫素陣列。In an embodiment of the present invention, the above-mentioned display device further includes a second common voltage pad. The second common voltage pad is disposed in the second side of the peripheral region and used for providing the common voltage signal to the pixel array.
在本發明的一實施例中,上述的第一側為顯示裝置的長邊側,且第二側為顯示裝置的短邊側。In an embodiment of the present invention, the first side is the long side of the display device, and the second side is the short side of the display device.
在本發明的一實施例中,上述的間隙為200微米~800微米。In an embodiment of the present invention, the above-mentioned gap is 200 μm˜800 μm.
基於上述,本發明的顯示裝置藉由使設置於顯示裝置一側且彼此相鄰的移位暫存單元之間具有間隙,因此,對位標記與其餘構件可設置於此間隙中,從而提升了當構件設置於此顯示裝置上時的對位精度。Based on the above, in the display device of the present invention, there is a gap between the shift temporary storage units disposed on one side of the display device and adjacent to each other, so the alignment marks and other components can be arranged in the gap, thereby improving the performance of the display device. Alignment accuracy when components are placed on this display device.
圖1為本發明的一實施例的顯示裝置的俯視示意圖,且圖2為本發明的一實施例的顯示裝置的周邊區的放大示意圖。FIG. 1 is a schematic top view of a display device according to an embodiment of the present invention, and FIG. 2 is an enlarged schematic view of a peripheral area of the display device according to an embodiment of the present invention.
請同時參照圖1以及圖2,本實施例的顯示裝置100包括基板SB、畫素陣列PX、閘極驅動電路GOA以及對位標記AM。在一些實施例中,顯示裝置100具有主動區AR以及周邊區PR,其中周邊區PR位於主動區AR的至少一側。顯示裝置100具有第一側S1以及第二側S2,其中第一側S1為長邊側,且第二側S2為短邊側。在本實施例中,顯示裝置100為直立式顯示裝置,即,閘極驅動電路GOA是設置於顯示裝置100的第一側S1,但本發明不以此為限。在其他的實施例中,閘極驅動電路GOA可設置於顯示裝置100的第二側S2。Please refer to FIG. 1 and FIG. 2 at the same time, the
基板SB例如為可撓性基板,其可為聚合物基板或塑膠基板,但本發明不限於此。在其他實施例中,基板SB也可例如為剛性基板,其可為玻璃基板、石英基板或矽基板。The substrate SB is, for example, a flexible substrate, which can be a polymer substrate or a plastic substrate, but the present invention is not limited thereto. In other embodiments, the substrate SB can also be, for example, a rigid substrate, which can be a glass substrate, a quartz substrate or a silicon substrate.
畫素陣列PX例如設置於基板SB上且位於顯示裝置100的主動區AR中。在一些實施例中,畫素陣列PX可包括多個陣列排布的畫素單元SPX。畫素單元SPX可例如包括主動元件(未繪示)以及畫素電極(未繪示),其中主動元件與畫素電極電性連接。在本實施例中,主動元件為所屬領域中具有通常知識者所周知的任一種底部閘極型薄膜電晶體,但本發明不限於此。在其他實施例中,主動元件也可以是頂部閘極型薄膜電晶體或是其它合適類型的薄膜電晶體。The pixel array PX is, for example, disposed on the substrate SB and located in the active area AR of the
閘極驅動電路GOA例如設置於基板SB上且位於顯示裝置100的周邊區PR中,如前所述,本實施例的閘極驅動電路GOA是位於顯示裝置100的第一側S1。在本實施例中,閘極驅動電路GOA包括多個移位暫存單元SR以及多條時脈訊號線HC。每一移位暫存單元SR中例如包括彼此串接的多個移位暫存器,且每一移位暫存器與相應的時脈訊號線HC電性連接。舉例而言,本實施例的一組移位暫存單元SR可包括八個移位暫存器SR1~SR8,如圖2所示,但需注意此僅為示例,本發明不限於此。移位暫存器SR1~SR8可各自至相應的時脈訊號線HC接收時脈訊號,並藉由此時脈訊號輸出相應的閘極訊號,之後移位暫存器SR1~SR8可藉由相應的閘極線GL將相應的閘極訊號傳遞至畫素陣列PX,以使相應畫素單元SPX中的主動元件開啟。在一些實施例中,每一移位暫存器SR1~SR8可包括有驅動電路(未繪示)、上拉電路(未繪示)以及下拉電路(未繪示),但本發明不限於此。多條時脈訊號線HC在本實施例的數量為八條,即,本實施例的移位暫存器是以8級作為一個循環,但需注意本發明不限於此。詳細地說,本實施例的時脈訊號線HC包括八條時脈訊號線HC1~HC8,其各自與相應的移位暫存器SR1~SR8電性連接。舉例而言,時脈訊號線HC1與1級移位暫存器SR1電性連接,時脈訊號線HC2與2級移位暫存器SR2電性連接,且時脈訊號線HC8與8級移位暫存器SR8電性連接,以此類推,因此以下不予以贅述。基於此,在本實施例中,移位暫存器SR1~SR8的總數量會是時脈訊號線HC1~HC8的數量的整數倍。另外,在一些實施例中,時脈訊號線HC1~HC8彼此平行地設置。The gate driving circuit GOA is, for example, disposed on the substrate SB and located in the peripheral region PR of the
在一些實施例中,本實施例的顯示裝置100更包括有源極驅動電路SOA。源極驅動電路SOA例如設置於基板SB上且位於顯示裝置100的周邊區PR中,其中本實施例的源極驅動電路SOA是位於顯示裝置100的第二側S2。源極驅動電路SOA例如藉由資料線(未繪示)輸出相應的資料訊號至畫素陣列PX,以使畫素陣列PX相應於資料訊號進行顯示。In some embodiments, the
在一些實施例中,本實施例的顯示裝置100更包括有多條時脈訊號傳遞線HCT。多條時脈訊號傳遞線HCT中的一者例如與相應的時脈訊號線HC與相應的移位暫存單元SR電性連接。詳細地說,本實施例的時脈訊號傳遞線HCT亦包括八條時脈訊號傳遞線HCT1~HCT8,其各自與相應的時脈訊號線HC1~HC8以及移位暫存器SR1~SR8電性連接,藉此以將時脈訊號經由時脈訊號線HC傳遞至移位暫存單元SR。在一些實施例中,時脈訊號傳遞線HCT1~HCT8彼此平行地設置,且與時脈訊號線HC1~HC8彼此垂直地設置。In some embodiments, the
在本實施例中,相鄰的移位暫存單元SR之間具有間隙G,其中間隙G可視欲在顯示裝置100的周邊區PR中設置的構件種類或其他製程條件決定其具有的寬度。在較佳的實施例中,上述的間隙G為200微米~800微米。基於此,可將本實施例的顯示裝置100的必要構件設置於間隙G中,藉此以提升顯示裝置100的效能且減小顯示裝置100的尺寸。舉例而言,本實施例的顯示裝置100更包括有第一共用電壓接墊CP1,其與共用電壓線CL連接,藉此將共用電壓提供至畫素陣列PX。詳細地說,本實施例的顯示裝置100包括有第一基板(未繪示)以及與其對向設置的第二基板(未繪示),其中第一基板與第二基板各自包括的一電極層可被第一共用電壓接墊CP1經由共用電壓線CL施予共用電壓。在一些實施例中,多個第一共用電壓接墊CP1可在顯示裝置100的第一側S1(長邊側)平均分佈於間隙G中,藉此以使畫素陣列PX中的每一畫素單元SPX接收到實質相同的訊號位準。舉例而言,如圖1所示,第一共用電壓接墊CP1設置於相鄰的兩個間隙G中的一者,使得每一組相鄰的第一共用電壓接墊CP1之間具有實質相同的距離,藉此可避免因距離較第一共用電壓接墊CP1遠的畫素單元SPX接收不同的訊號位準。另外,本實施例的顯示裝置100還包括有第二共用電壓接墊CP2,第二共用電壓接墊CP2設置於顯示裝置100的第二側S2(短邊側),以將共用電壓提供至畫素陣列PX。In this embodiment, there is a gap G between adjacent shift register units SR, wherein the width of the gap G can be determined by the types of components to be arranged in the peripheral region PR of the
對位標記AM例如設置於基板SB上且位於顯示裝置100的周邊區PR中。在本實施例中,對位標記AM的數量為多個,且各自設置於多個間隙G的至少一者中。在一些實施例中,多個對位標記AM可在顯示裝置100的第一側S1(長邊側)平均分佈於間隙G中,但本發明不以此為限。對位標記AM可例如不與前述的第一共用電壓接墊CP1或其餘構件設置於同一間隙G中,如圖1所示,但本發明不以此為限。即,對位標記AM亦可與前述的第一共用電壓接墊CP1或其餘構件設置於同一間隙G中,如圖2所示。對位標記AM的形狀例如可設計為十字型,但本發明不以此為限。在其他的實施例中,對位標記AM的形狀可為矩形、圓形或其他形狀。對位標記AM的材料並無特別限制,只要在辨識效果上符合所需的材料即可。The alignment mark AM is, for example, disposed on the substrate SB and located in the peripheral region PR of the
圖3為本發明的一實施例的貼附有偏光片的顯示裝置的俯視示意圖。FIG. 3 is a schematic top view of a display device attached with a polarizer according to an embodiment of the present invention.
在本實施例中,對位標記AM可用於將偏光片P貼附於顯示裝置100上,如圖3所示。基於此,比起僅將多個對位標記AM設置於顯示裝置100的第二側S2(短邊側),將多個對位標記AM設置在位於顯示裝置100的第一側S1(長邊側)的間隙G中可明顯地增加對位精度,以降低例如將偏光片P貼附至顯示裝置100上時產生偏移的風險。另外,多個對位標記AM亦可更設置於顯示裝置100的第二側S2,以進一步增加對位精度。In this embodiment, the alignment mark AM can be used to attach the polarizer P to the
圖4為本發明的一實施例的包括有顯示裝置的母板的俯視示意圖。FIG. 4 is a schematic top view of a motherboard including a display device according to an embodiment of the present invention.
請同時參照圖1與圖4,在一些實施例中,可藉由同一光罩PS1或光罩PS2對母板10進行切割而製得所需尺寸的一個或多個顯示裝置100,其中經切割後的多個顯示裝置皆可用於獨立顯示。在本實施例中,母板10具有的畫素單元(未繪示)的寬度尺寸約為200微米,移位暫存器的寬度尺寸約為198微米,其中240個移位暫存器分組成一個移位暫存單元SR,則相鄰的移位暫存單元SR之間可形成尺寸為480微米的間隙G,其可用於設置第一共用電壓接墊CP1、對位標記AM或其他構件。另外,母板10具有的間隙G是藉由將多個移位暫存器分組成一個移位暫存單元SR,並縮減各個移位暫存單元SR的寬度以形成,使得閘極線GL例如是以扇出型的方式設置。就上面的示例而言,若沿著顯示裝置100的第一側S1的方向需設置有2880個畫素單元,則需利用光罩PS1以切割出顯示裝置100的第一側S1上具有12組移位暫存單元SR的長度。另外,若沿著顯示裝置100的第一側S1的方向需設置有3840個畫素單元,則需利用光罩PS2以切割出顯示裝置100的第一側S1上具有16組移位暫存單元SR的長度。Please refer to FIG. 1 and FIG. 4 at the same time. In some embodiments, one or
綜上所述,本發明藉由使設置於顯示裝置的長邊側且彼此相鄰的移位暫存單元之間具有間隙,因此,對位標記與第一共用電壓接墊等其餘構件可設置於此間隙中,從而提升了當構件設置於此顯示裝置上時的對位精度,且亦避免各畫素單元接收到的訊號位準產生偏差,使得本發明的顯示裝置的效能可明顯地提升。To sum up, in the present invention, there are gaps between the shift register units disposed on the long side of the display device and adjacent to each other, so the alignment marks and the first common voltage pads and other components can be disposed In this gap, the alignment accuracy when the components are arranged on the display device is improved, and the deviation of the signal level received by each pixel unit is also avoided, so that the performance of the display device of the present invention can be significantly improved .
10:母板 100:顯示裝置 AM:對位標記 AR:主動區 CL:共用電壓線 CP1:第一共用電壓接墊 CP2:第二共用電壓接墊 G:間隙 GL:閘極線 GOA:閘極驅動電路 HC、HC1、HC2、HC3、HC4、HC5、HC6、HC7、HC8:時脈訊號線 HCT、HCT1、HCT2、HCT3、HCT4、HCT5、HCT6、HCT7、HCT8:時脈訊號傳遞線 P:偏光片 PR:周邊區 PS1、PS2:光罩 PX:畫素陣列 S1:第一側 S2:第二側 SB:基板 SOA:源極驅動電路 SPX:畫素單元 SR:移位暫存單元 SR1、SR2、SR3、SR4、SR5、SR6、SR7、SR8:移位暫存器 10: Motherboard 100: Display device AM: registration mark AR: Active area CL: Common voltage line CP1: The first common voltage pad CP2: Second common voltage pad G: Gap GL: gate line GOA: Gate Drive Circuit HC, HC1, HC2, HC3, HC4, HC5, HC6, HC7, HC8: clock signal line HCT, HCT1, HCT2, HCT3, HCT4, HCT5, HCT6, HCT7, HCT8: clock signal transmission line P: polarizer PR: Surrounding area PS1, PS2: Photomask PX: pixel array S1: first side S2: Second side SB: Substrate SOA: source driver circuit SPX: pixel unit SR: shift temporary storage unit SR1, SR2, SR3, SR4, SR5, SR6, SR7, SR8: Shift register
圖1為本發明的一實施例的顯示裝置的俯視示意圖。 圖2為本發明的一實施例的顯示裝置的周邊區的放大示意圖。 圖3為本發明的一實施例的貼附有偏光片的顯示裝置的俯視示意圖。 圖4為本發明的一實施例的包括顯示裝置的母板的俯視示意圖。 FIG. 1 is a schematic top view of a display device according to an embodiment of the present invention. FIG. 2 is an enlarged schematic view of a peripheral area of a display device according to an embodiment of the present invention. FIG. 3 is a schematic top view of a display device attached with a polarizer according to an embodiment of the present invention. 4 is a schematic top view of a motherboard including a display device according to an embodiment of the present invention.
100:顯示裝置 100: Display device
AM:對位標記 AM: registration mark
AR:主動區 AR: Active area
CP1:第一共用電壓接墊 CP1: The first common voltage pad
CP2:第二共用電壓接墊 CP2: Second common voltage pad
G:間隙 G: Gap
GL:閘極線 GL: gate line
GOA:閘極驅動電路 GOA: Gate Drive Circuit
PR:周邊區 PR: Surrounding area
PX:畫素陣列 PX: pixel array
S1:第一側 S1: first side
S2:第二側 S2: Second side
SB:基板 SB: Substrate
SOA:源極驅動電路 SOA: source driver circuit
SR:移位暫存單元 SR: shift temporary storage unit
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