TWI766291B - Display apparatus - Google Patents

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TWI766291B
TWI766291B TW109118552A TW109118552A TWI766291B TW I766291 B TWI766291 B TW I766291B TW 109118552 A TW109118552 A TW 109118552A TW 109118552 A TW109118552 A TW 109118552A TW I766291 B TWI766291 B TW I766291B
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common
gate lines
gate
lines
substrate
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TW109118552A
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TW202109155A (en
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鄭聖諺
李珉澤
廖鴻嘉
翁嘉鴻
陳品妏
鍾岳宏
徐雅玲
廖烝賢
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友達光電股份有限公司
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Priority to US16/939,072 priority Critical patent/US11586085B2/en
Priority to CN202010785527.5A priority patent/CN112415824B/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G09G3/3629—Control of matrices with row and column drivers using a passive matrix using liquid crystals having memory effects, e.g. ferroelectric liquid crystals
    • G09G3/3637—Control of matrices with row and column drivers using a passive matrix using liquid crystals having memory effects, e.g. ferroelectric liquid crystals with intermediate tones displayed by domain size control
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
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  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
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  • Optics & Photonics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

A display apparatus includes data lines, first gate lines, pixel structures, second gate lines and first common lines. The data lines are arranged in a first direction. The first gate lines are arranged in a second direction. The pixel structures are electrically connected to the data lines and the first gate lines. The data lines and the second gate lines are arranged in the first direction, and the second gate lines are electrically connected to the first gate lines. The pixel structures are arranged in pixel columns, and the pixel columns are arranged in the first direction. Each of the first common line and a corresponding second gate line are disposed between two adjacent pixel columns. Each of the first common line and the corresponding second gate line are respectively disposed on opposite sides of the first gate line electrically connected to the corresponding second gate line, and each of the first common line and the corresponding second gate line are structurally separated.

Description

顯示裝置display device

本發明是有關於一種電子裝置，且特別是有關於一種顯示裝置。 The present invention relates to an electronic device, and more particularly, to a display device.

隨著顯示科技的發達，人們對顯示裝置的需求，不再滿足於高解析度、高對比、廣視角等光學特性，人們還期待顯示裝置具有優雅的外觀。舉例而言，人們期待顯示裝置的邊框窄，甚至無邊框。 With the development of display technology, people's demands for display devices are no longer satisfied with optical characteristics such as high resolution, high contrast, and wide viewing angle. People also expect display devices to have an elegant appearance. For example, people expect a display device with a narrow bezel or even no bezel.

一般而言，顯示裝置包括設置於顯示區的多個畫素結構、設置於顯示區之下方的資料驅動電路以及設置於顯示區之左側、右側或左右兩側的閘極驅動電路。為減少顯示裝置之邊框的左右兩側的寬度，可將閘極驅動電路與資料驅動電路均設置於顯示區的下側。當閘極驅動電路設置於顯示區的下側時，在水平閘極線須透過垂直閘極線方能電性連接至閘極驅動電路。然而，垂直閘極線的閘極開啟脈衝訊號會影響還在部分畫素結構的電位，進而造成顯示異常。 Generally speaking, a display device includes a plurality of pixel structures disposed in the display area, a data driving circuit disposed below the display area, and gate driving circuits disposed on the left, right or left and right sides of the display area. In order to reduce the width of the left and right sides of the frame of the display device, both the gate driving circuit and the data driving circuit can be arranged on the lower side of the display area. When the gate driving circuit is arranged on the lower side of the display area, the horizontal gate line must be electrically connected to the gate driving circuit through the vertical gate line. However, the gate turn-on pulse signal of the vertical gate line will affect the potential of some pixel structures, thereby causing abnormal display.

本發明提供一種顯示裝置，性能佳。 The present invention provides a display device with good performance.

本發明提供另一種顯示裝置，性能也佳。 The present invention provides another display device with good performance.

本發明的一種顯示裝置，包括第一基板、多條資料線、多條第一閘極線、多個畫素結構、多條第二閘極線、多條第一共用線、第二基板以及顯示介質。多條資料線設置於第一基板上，且在第一方向上排列。多條第一閘極線設置於第一基板上，且在第二方向上排列，其中第一方向與第二方向交錯。多個畫素結構設置於第一基板上，且電性連接多條資料線及多條第一閘極線。多條第二閘極線設置於第一基板上，其中多條資料線及多條第二閘極線在第一方向上排列，且多條第二閘極線電性連接至多條第一閘極線。多條第一共用線設置於第一基板上，其中多個畫素結構排成多個畫素行，多個畫素行在第一方向上排列，每一第一共用線與對應的一第二閘極線設置於多個畫素行的相鄰兩者之間，第一共用線及對應的第二閘極線分別設置於與第二閘極線電性連接之一第一閘極線的相對兩側，且第一共用線與對應的第二閘極線於結構上分離。第二基板設置於第一基板的對向。顯示介質設置於第一基板與第二基板之間。 A display device of the present invention includes a first substrate, a plurality of data lines, a plurality of first gate lines, a plurality of pixel structures, a plurality of second gate lines, a plurality of first common lines, a second substrate, and Display medium. A plurality of data lines are arranged on the first substrate and are arranged in the first direction. The plurality of first gate lines are disposed on the first substrate and arranged in a second direction, wherein the first direction and the second direction are staggered. A plurality of pixel structures are disposed on the first substrate, and are electrically connected to a plurality of data lines and a plurality of first gate lines. A plurality of second gate lines are disposed on the first substrate, wherein a plurality of data lines and a plurality of second gate lines are arranged in a first direction, and a plurality of second gate lines are electrically connected to the plurality of first gates polar line. A plurality of first common lines are arranged on the first substrate, wherein a plurality of pixel structures are arranged into a plurality of pixel rows, and the plurality of pixel rows are arranged in a first direction, and each first common line corresponds to a second gate The pole lines are arranged between adjacent two of the plurality of pixel rows, and the first common line and the corresponding second gate line are respectively arranged on the opposite two sides of a first gate line that is electrically connected to the second gate line. side, and the first common line is structurally separated from the corresponding second gate line. The second substrate is disposed opposite to the first substrate. The display medium is arranged between the first substrate and the second substrate.

本發明的一種顯示裝置，包括第一基板、多條資料線、多條第一閘極線、多個畫素結構、多條第二閘極線、第二基板及顯示介質。多條資料線設置於第一基板上，且在第一方向上排列。多條第一閘極線設置於第一基板上，且在第二方向上排列，其中 第一方向與第二方向交錯。多個畫素結構設置於第一基板上，電性連接多條資料線及多條第一閘極線，且在排成x個畫素行及y個畫素列。x個畫素行在第一方向上排列，y個畫素列在第二方向上排列，x及y為大於2的正整數，一畫素結構在第一方向及第二方向上分別具有第一寬度a1及第二寬度a2。多條第二閘極線設置於第一基板上，其中資料線及第二閘極線在第一方向上排列，且第二閘極線電性連接至第一閘極線。第二基板設置於第一基板的對向。顯示介質設置於第一基板與第二基板之間。每一第一閘極線與n條第二閘極線電性連接。(a1．x+a2．y)<2000000，且n=2；或2000000<(a1．x+a2．y)<2400000，且n=3；或2400000<(a1．x+a2．y)<3000000，且n=4；或(a1．x+a2．y)>3000000，且n=5。 A display device of the present invention includes a first substrate, a plurality of data lines, a plurality of first gate lines, a plurality of pixel structures, a plurality of second gate lines, a second substrate and a display medium. A plurality of data lines are arranged on the first substrate and are arranged in the first direction. A plurality of first gate lines are disposed on the first substrate and are arranged in the second direction, wherein The first direction is interleaved with the second direction. A plurality of pixel structures are disposed on the first substrate, are electrically connected to a plurality of data lines and a plurality of first gate lines, and are arranged in x pixel rows and y pixel columns. x pixel rows are arranged in the first direction, y pixel columns are arranged in the second direction, x and y are positive integers greater than 2, and a pixel structure has a first The width a1 and the second width a2. A plurality of second gate lines are disposed on the first substrate, wherein the data lines and the second gate lines are arranged in a first direction, and the second gate lines are electrically connected to the first gate lines. The second substrate is disposed opposite to the first substrate. The display medium is arranged between the first substrate and the second substrate. Each of the first gate lines is electrically connected to n second gate lines. (a1.x+a2.y)<2000000, and n=2; or 2000000<(a1.x+a2.y)<2400000, and n=3; or 2400000<(a1.x+a2.y)< 3000000, and n=4; or (a1.x+a2.y)>3000000, and n=5.

在本發明的一實施例中，上述的一第一共用線的訊號與一第二閘極線的一閘極關閉訊號實質上相同。 In an embodiment of the present invention, a signal of the above-mentioned first common line and a gate-off signal of a second gate line are substantially the same.

在本發明的一實施例中，上述的每一第一閘極線與n條第二閘極線電性連接，n為正整數，每一第一閘極線與n條第二閘極線具有在第一方向上依序排列的第1~n個連接點，多條第二閘極線包括在第一方向上依序排列的第1~n個第二閘極線群，第1~n個第二閘極線群之第m個第二閘極線群的多條第二閘極線與對應的多條第一閘極線具有第1~n個連接點的第m個連接點，m為正整數，n

Figure 109118552-A0305-02-0006-1
m
Figure 109118552-A0305-02-0006-2
1。顯示裝置更包括共用電極、多個共用墊組、多個第一轉接元件、n個第二共用墊以及n個第二轉接元件。共用電 極設置於第二基板上，且位於第二基板與顯示介質之間。多個共用墊組設置於第一基板上，且分別對應第1~n個第二閘極線群設置，其中多個畫素結構具有相對的第一側及第二側，多個共用墊組設置於多個畫素結構的第二側，且每一共用墊組包括多個第一共用墊。多個第一轉接元件分別設置於多個共用墊組的多個第一共用墊上，且電性連接至多個共用墊組的多個第一共用墊及共用電極。n個第二共用墊設置於第一基板上，分別對應第1~n個第二閘極線群設置，且位於多個畫素結構的第一側。n個第二轉接元件分別設置於n個第二共用墊上，且電性連接至n個第二共用墊及共用電極。一共用墊組及一第二共用墊對應同一個第二閘極線群，且第二共用墊的電位大於共用墊組之多個第一共用墊的電位。 In an embodiment of the present invention, each of the above-mentioned first gate lines is electrically connected to n second gate lines, n is a positive integer, and each first gate line and n second gate lines There are 1st to nth connection points arranged in sequence in the first direction, the plurality of second gate lines include 1st to nth second gate line groups arranged in sequence in the first direction, and the first to nth gate lines are arranged in sequence in the first direction. The plurality of second gate lines of the m th second gate line group of the n second gate line groups and the corresponding plurality of first gate lines have the m th connection point of the 1 th to n th connection points , m is a positive integer, n
Figure 109118552-A0305-02-0006-1
m
Figure 109118552-A0305-02-0006-2
1. The display device further includes a common electrode, a plurality of common pad groups, a plurality of first transfer elements, n second common pads and n second transfer elements. The common electrode is arranged on the second substrate and is located between the second substrate and the display medium. A plurality of common pad groups are disposed on the first substrate, and are respectively disposed corresponding to the 1st to nth second gate line groups, wherein the plurality of pixel structures have opposite first sides and second sides, and the plurality of common pad groups It is disposed on the second side of the plurality of pixel structures, and each common pad group includes a plurality of first common pads. The plurality of first transfer elements are respectively disposed on the plurality of first common pads of the plurality of common pad groups, and are electrically connected to the plurality of first common pads and the common electrodes of the plurality of common pad groups. The n second common pads are disposed on the first substrate, respectively corresponding to the first to n second gate line groups, and are located on the first sides of the plurality of pixel structures. The n second transfer elements are respectively disposed on the n second common pads, and are electrically connected to the n second common pads and the common electrodes. A common pad group and a second common pad correspond to the same second gate line group, and the potential of the second common pad is greater than that of the first common pads of the common pad group.

在本發明的一實施例中，上述的顯示裝置，更包括第三共用墊，設置於第一基板上，且位於多個畫素結構的第一側。第三共用墊及多個第二共用墊在第一方向上依序排列且於結構上彼此分離，第三共用墊對應第1~n個第二閘極線群的第1個第二閘極線群設置，而第三共用墊的電位大於對應多個第二共用墊的電位。 In an embodiment of the present invention, the above-mentioned display device further includes a third common pad disposed on the first substrate and located on the first side of the plurality of pixel structures. The third common pad and the plurality of second common pads are sequentially arranged in the first direction and are separated from each other in structure, and the third common pad corresponds to the first second gate of the first to nth second gate line groups The line group is arranged, and the potential of the third common pad is greater than the potential of the corresponding plurality of second common pads.

在本發明的一實施例中，上述的顯示裝置更包括多條第二共用線、第一周邊走線以及第二周邊走線。多條第二共用線設置於第一基板上，多條第二閘極線及多條第二共用線在第一方向上排列，其中每一第二共用線設置於多個畫素行的相鄰兩者之間。 第一周邊走線設置於第一基板上且位於多個畫素結構的一第一側，其中多條第一共用線電性連接至第一周邊走線。第二周邊走線設置於第一基板上且位於多個畫素結構的第二側，其中每一第二共用線的兩端分別電性連接至第一周邊走線及第二周邊走線。 In an embodiment of the present invention, the above-mentioned display device further includes a plurality of second common lines, first peripheral wirings, and second peripheral wirings. A plurality of second common lines are disposed on the first substrate, a plurality of second gate lines and a plurality of second common lines are arranged in a first direction, wherein each second common line is disposed adjacent to a plurality of pixel rows in between. The first peripheral wirings are disposed on the first substrate and located on a first side of the plurality of pixel structures, wherein the plurality of first common lines are electrically connected to the first peripheral wirings. The second peripheral wirings are disposed on the first substrate and located on the second side of the plurality of pixel structures, wherein two ends of each second common wiring are electrically connected to the first peripheral wirings and the second peripheral wirings, respectively.

在本發明的一實施例中，上述的多條第一閘極線包括奇數條第一閘極線及偶數條第一閘極線，奇數條第一閘極線包括第(1+2．K)條第一閘極線，K=0,1,…,p，p為大於或等於2的正整數，偶數條第一閘極線包括第2L條第一閘極線，L=1,2,…,q，q為大於或等於3的正整數；多條第二閘極線包括在第一方向上依序排列的第1~(p+1)條第二閘極線及第(p+2)~(p+q+1)條第二閘極線；第1~(p+1)條第二閘極線電性連接至第(1+2．K)條第一閘極線，且第(p+2)~(p+q+1)條第二閘極線電性連接至第2L條第一閘極線。 In an embodiment of the present invention, the above-mentioned plurality of first gate lines include odd-numbered first gate lines and even-numbered first gate lines, and the odd-numbered first gate lines include (1+2.Kth) ) first gate lines, K=0,1,...,p, p is a positive integer greater than or equal to 2, the even-numbered first gate lines include the 2L first gate lines, L=1,2 ,...,q, q are positive integers greater than or equal to 3; the plurality of second gate lines include the first to (p+1) second gate lines and the (p +2)~(p+q+1) second gate lines; 1~(p+1) second gate lines are electrically connected to (1+2.K) first gate lines , and the (p+2)-(p+q+1)th second gate lines are electrically connected to the 2Lth first gate lines.

在本發明的一實施例中，上述的第1~(p+1)條第二閘極線與第(1+2．K)條第一閘極線的多個連接點以及第(p+2)~(p+q+1)條第二閘極線與第2L條的多個連接點大致上沿著互相平行的多條斜線分佈。 In an embodiment of the present invention, a plurality of connection points of the first to (p+1) second gate lines and the (1+2.K) first gate lines and the (p+ 2) The connection points of the second gate lines to (p+q+1) and the 2L line are generally distributed along a plurality of diagonal lines parallel to each other.

在本發明的一實施例中，上述的第1~(p+1)條第二閘極線與第(1+2．K)條第一閘極線的多個連接點以及第(p+2)~(p+q+1)條第二閘極線與第2L條的多個連接點大致上呈V字型分佈。 In an embodiment of the present invention, a plurality of connection points of the first to (p+1) second gate lines and the (1+2.K) first gate lines and the (p+ 2) The connection points of the second gate lines to (p+q+1) and the 2L line are roughly distributed in a V-shape.

在本發明的一實施例中，上述的顯示裝置更包括多條第一共用線，設置於第一基板上。每一第一共用線與對應的一第二閘極線設置於x個畫素行的相鄰兩者之間，第一共用線及對應的 第二閘極線分別設置於與第二閘極線電性連接之一第一閘極線的相對兩側，且第一共用線與對應的第二閘極線於結構上分離。 In an embodiment of the present invention, the above-mentioned display device further includes a plurality of first common lines disposed on the first substrate. Each first common line and a corresponding second gate line are arranged between adjacent two of the x pixel rows, the first common line and the corresponding The second gate lines are respectively disposed on opposite sides of a first gate line electrically connected to the second gate line, and the first common line and the corresponding second gate line are structurally separated.

10:顯示裝置 10: Display device

100、100A、100B、100C、100D:畫素陣列基板 100, 100A, 100B, 100C, 100D: pixel array substrate

110:第一基板 110: The first substrate

120:元件層 120: Component layer

200:對向基板 200: Opposite substrate

210:第二基板 210: Second substrate

220:共用電極 220: Common electrode

221:第一部 221: Part 1

222:第二部 222: Part II

223:第三部 223: Part 3

300:顯示介質 300: Display medium

a1:第一寬度 a1: first width

a2:第二寬度 a2: second width

Cpx:畫素行 Cpx: pixel row

C、C1、C2、C3:連接點 C, C1, C2, C3: connection points

CL1、CL11、CL12、CL13、CL14、CL15、CL16:第一共用線 CL1, CL11, CL12, CL13, CL14, CL15, CL16: first common line

CL2:第二共用線 CL2: Second common line

D1:第一方向 D1: first direction

D2:第二方向 D2: Second direction

DL:資料線 DL: data line

Gvg、Gvg1、Gvg2、Gvg3:第二閘極線群 Gvg, Gvg1, Gvg2, Gvg3: the second gate line group

Gp1a、Gp1b、Gp1c:共用墊組 Gp1a, Gp1b, Gp1c: common pad groups

HG、HG1、HG2、HG3、HG4、HG5、HG6:第一閘極線 HG, HG1, HG2, HG3, HG4, HG5, HG6: first gate line

K:斜線 K: slash

L1:第一周邊走線 L1: The first peripheral trace

L2:第二周邊走線 L2: Second peripheral trace

Lp1a、Lp1b、Lp1c、Lp2a、Lp2b、Lp2c、Lp3、Ll1、Ll2:導線 Lp1a, Lp1b, Lp1c, Lp2a, Lp2b, Lp2c, Lp3, Ll1, Ll2: wires

PX:畫素結構 PX: pixel structure

p1a、p1b、p1c:第一共用墊 p1a, p1b, p1c: first common pad

p2a、p2b、p2c:第二共用墊 p2a, p2b, p2c: second common pad

p3:第三共用墊 p3: Third Common Pad

Rpx:畫素列 Rpx: pixel column

S1:第一側 S1: first side

S2:第二側 S2: Second side

T1:第一轉接元件 T1: The first transfer element

T2:第二轉接元件 T2: The second switching element

T3:第三轉接元件 T3: The third transfer element

VG、VG1、VG2、VG3、VG4、VG5、VG6:第二閘極線 VG, VG1, VG2, VG3, VG4, VG5, VG6: the second gate line

圖1為本發明一實施例之顯示裝置10的剖面示意圖。 FIG. 1 is a schematic cross-sectional view of a display device 10 according to an embodiment of the present invention.

圖2為本發明一實施例之畫素陣列基板100、第一轉接元件T1、第二轉接元件T2及第三轉接元件T3的俯視示意圖。 FIG. 2 is a schematic top view of the pixel array substrate 100 , the first transfer element T1 , the second transfer element T2 and the third transfer element T3 according to an embodiment of the present invention.

圖3為本發明一實施例之對向基板200、第一轉接元件T1、第二轉接元件T2及第三轉接元件T3的俯視示意圖。 3 is a schematic top view of the opposite substrate 200 , the first transfer element T1 , the second transfer element T2 and the third transfer element T3 according to an embodiment of the present invention.

圖4為本發明一實施例之畫素陣列基板100A、第一轉接元件T1、第二轉接元件T2及第三轉接元件T3的俯視示意圖。 4 is a schematic top view of a pixel array substrate 100A, a first transition element T1 , a second transition element T2 and a third transition element T3 according to an embodiment of the present invention.

圖5為本發明一實施例之畫素陣列基板100B及第一轉接元件T1的俯視的上視示意圖。 FIG. 5 is a schematic top view of the pixel array substrate 100B and the first transition element T1 in plan view according to an embodiment of the present invention.

圖6為本發明一實施例之畫素陣列基板100C及第一轉接元件T1的俯視示意圖。 FIG. 6 is a schematic top view of the pixel array substrate 100C and the first transition element T1 according to an embodiment of the present invention.

圖7為本發明一實施例之畫素陣列基板100D及第一轉接元件T1的俯視示意圖。 FIG. 7 is a schematic top view of the pixel array substrate 100D and the first transition element T1 according to an embodiment of the present invention.

現將詳細地參考本發明的示範性實施例，示範性實施例的實例說明於附圖中。只要有可能，相同元件符號在圖式和描述 中用來表示相同或相似部分。 Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and descriptions used to indicate the same or similar parts.

應當理解，當諸如層、膜、區域或基板的元件被稱為在另一元件“上”或“連接到”另一元件時，其可以直接在另一元件上或與另一元件連接，或者中間元件可以也存在。相反，當元件被稱為“直接在另一元件上”或“直接連接到”另一元件時，不存在中間元件。如本文所使用的，“連接”可以指物理及/或電性連接。再者，“電性連接”或“耦合”可以是二元件間存在其它元件。 It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may refer to the existence of other elements between the two elements.

本文使用的“約”、“近似”、或“實質上”包括所述值和在本領域普通技術人員確定的特定值的可接受的偏差範圍內的平均值，考慮到所討論的測量和與測量相關的誤差的特定數量(即，測量系統的限制)。例如，“約”可以表示在所述值的一個或多個標準偏差內，或±30%、±20%、±10%、±5%內。再者，本文使用的“約”、“近似”或“實質上”可依光學性質、蝕刻性質或其它性質，來選擇較可接受的偏差範圍或標準偏差，而可不用一個標準偏差適用全部性質。 As used herein, "about," "approximately," or "substantially" includes the stated value and the average within an acceptable deviation from the particular value as determined by one of ordinary skill in the art, given the measurement in question and the A specified amount of measurement-related error (ie, a limitation of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, "about", "approximately" or "substantially" may be used to select a more acceptable range of deviation or standard deviation depending on optical properties, etching properties or other properties, and not one standard deviation may apply to all properties. .

除非另有定義，本文使用的所有術語(包括技術和科學術語)具有與本發明所屬領域的普通技術人員通常理解的相同的含義。將進一步理解的是，諸如在通常使用的字典中定義的那些術語應當被解釋為具有與它們在相關技術和本發明的上下文中的含義一致的含義，並且將不被解釋為理想化的或過度正式的意義，除非本文中明確地這樣定義。 Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed as having meanings consistent with their meanings in the context of the related art and the present invention, and are not to be construed as idealized or excessive Formal meaning, unless expressly defined as such herein.

圖1為本發明一實施例之顯示裝置10的剖面示意圖。 FIG. 1 is a schematic cross-sectional view of a display device 10 according to an embodiment of the present invention.

請參照圖1，顯示裝置10包括畫素陣列基板100、對向基板200及顯示介質300，其中顯示介質300設置於畫素陣列基板100與對向基板200之間。畫素陣列基板100包括第一基板110及元件層120，其中元件層120設置於第一基板110上且位於顯示介質300與第一基板110之間。對向基板200包括第二基板210，其中第二基板210設置於第一基板110的對向，且顯示介質300位於第一基板110與第二基板210之間。 Referring to FIG. 1 , the display device 10 includes a pixel array substrate 100 , an opposite substrate 200 and a display medium 300 , wherein the display medium 300 is disposed between the pixel array substrate 100 and the opposite substrate 200 . The pixel array substrate 100 includes a first substrate 110 and an element layer 120 , wherein the element layer 120 is disposed on the first substrate 110 and located between the display medium 300 and the first substrate 110 . The opposite substrate 200 includes a second substrate 210 , wherein the second substrate 210 is disposed opposite to the first substrate 110 , and the display medium 300 is located between the first substrate 110 and the second substrate 210 .

在本實施例中，第一基板110的材質可為玻璃、石英、有機聚合物、或是其它可適用的材料；第二基板210的材質可為玻璃、石英、有機聚合物、或是其它可適用的材料。 In this embodiment, the material of the first substrate 110 can be glass, quartz, organic polymer, or other applicable materials; the material of the second substrate 210 can be glass, quartz, organic polymer, or other suitable materials applicable material.

在本實施例中，顯示介質300例如是液晶。然而，本發明不限於此，在其它實施例中，顯示介質300也可以是有機電致發光層或其它可適用的材料。 In this embodiment, the display medium 300 is, for example, liquid crystal. However, the present invention is not limited thereto, and in other embodiments, the display medium 300 may also be an organic electroluminescent layer or other applicable materials.

圖2為本發明一實施例之畫素陣列基板100、第一轉接元件T1、第二轉接元件T2及第三轉接元件T3的俯視示意圖。 FIG. 2 is a schematic top view of the pixel array substrate 100 , the first transfer element T1 , the second transfer element T2 and the third transfer element T3 according to an embodiment of the present invention.

請參照圖1及圖2，畫素陣列基板100的元件層120包括多條資料線DL、多條第一閘極線HG、多個畫素結構PX及多條第二閘極線VG。 1 and 2 , the element layer 120 of the pixel array substrate 100 includes a plurality of data lines DL, a plurality of first gate lines HG, a plurality of pixel structures PX and a plurality of second gate lines VG.

請參照圖2，多條資料線DL設置於第一基板110上且在第一方向D1上排列。多條第一閘極線HG設置於第一基板110上且在第二方向D2上排列，其中第一方向D1與第二方向D2交錯。舉例而言，在本實施例中，第一方向D1與第二方向D2實質上可 垂直，但本發明不以此為限。 Referring to FIG. 2 , a plurality of data lines DL are disposed on the first substrate 110 and arranged in the first direction D1. The plurality of first gate lines HG are disposed on the first substrate 110 and arranged in the second direction D2, wherein the first direction D1 and the second direction D2 are staggered. For example, in this embodiment, the first direction D1 and the second direction D2 can be substantially Vertical, but the present invention is not limited to this.

在本實施例中，資料線DL與第一閘極線HG是屬於不同的膜層。舉例而言，在本實施例中，第一閘極線HG可屬於第一金屬層，資料線DL可屬於第二金屬層，但本發明不以此為限。基於導電性的考量，在本實施例中，資料線DL與第一閘極線HG是使用金屬材料；但本發明不限於此，在其他實施例中，資料線DL及/或第一閘極線HG也可以使用其他導電材料，例如：合金、金屬材料的氮化物、金屬材料的氧化物、金屬材料的氮氧化物、或是金屬材料與其它導電材料的堆疊層。 In this embodiment, the data line DL and the first gate line HG belong to different layers. For example, in this embodiment, the first gate line HG may belong to the first metal layer, and the data line DL may belong to the second metal layer, but the invention is not limited thereto. Based on the consideration of conductivity, in this embodiment, the data line DL and the first gate line HG are made of metal materials; however, the invention is not limited to this. In other embodiments, the data line DL and/or the first gate line HG are made of metal materials. The wire HG can also use other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or stacked layers of metal materials and other conductive materials.

多個畫素結構PX設置於第一基板110上，且電性連接多條資料線DL及多條第一閘極線HG。具體而言，在本實施例中，每一畫素結構PX可包括一薄膜電晶體(未繪示)和一畫素電極(未繪示)，其中所述薄膜電晶體具有第一端、第二端及控制端，所述薄膜電晶體的第一端電性連接至對應的一條資料線DL，所述薄膜電晶體的控制端電性連接至對應的一第一閘極線HG，且所述薄膜電晶體的第二端電性連接至所述畫素電極。 The plurality of pixel structures PX are disposed on the first substrate 110 and are electrically connected to the plurality of data lines DL and the plurality of first gate lines HG. Specifically, in this embodiment, each pixel structure PX may include a thin film transistor (not shown) and a pixel electrode (not shown), wherein the thin film transistor has a first end, a second Two terminals and a control terminal, the first terminal of the thin film transistor is electrically connected to a corresponding data line DL, the control terminal of the thin film transistor is electrically connected to a corresponding first gate line HG, and the The second end of the thin film transistor is electrically connected to the pixel electrode.

多條第二閘極線VG設置於第一基板110上，其中多條資料線DL及多條第二閘極線VG在第一方向D1上排列，且多條第二閘極線VG電性連接至多條第一閘極線HG。 A plurality of second gate lines VG are disposed on the first substrate 110, wherein a plurality of data lines DL and a plurality of second gate lines VG are arranged in the first direction D1, and the plurality of second gate lines VG are electrically connected to a plurality of first gate lines HG.

具體而言，在本實施例中，多個畫素結構PX排成多個畫素行Cpx及多個畫素列Rpx，多個畫素行Cpx在第一方向D1上排列，每一畫素行Cpx的多個畫素PX在第二方向D2上排列，多 個畫素列Rpx在第二方向D2上排列，每一畫素列Rpx的多個畫素PX在第一方向D1上排列；在畫素陣列基板100的俯視圖中，每一第二閘極線VG是設置於相鄰兩畫素行Cpx之間。也就是說，多條第二閘極線VG是穿插在畫素陣列基板100的主動區(active area)內，且每一第二閘極線VG是在所述主動區內與對應的至少一條第一閘極線HG電性連接。 Specifically, in this embodiment, a plurality of pixel structures PX are arranged into a plurality of pixel rows Cpx and a plurality of pixel columns Rpx, the plurality of pixel rows Cpx are arranged in the first direction D1, and the A plurality of pixels PX are arranged in the second direction D2. The pixel rows Rpx are arranged in the second direction D2, and the pixels PX of each pixel row Rpx are arranged in the first direction D1; in the top view of the pixel array substrate 100, each second gate line VG is set between two adjacent pixel rows Cpx. That is to say, a plurality of second gate lines VG are interspersed in the active area of the pixel array substrate 100 , and each second gate line VG corresponds to at least one corresponding to the active area. The first gate line HG is electrically connected.

舉例而言，在本實施例中，多條第一閘極線HG包括在第二方向D2上依序排列的第一閘極線HG1、第一閘極線HG2、第一閘極線HG3、第一閘極線HG4、第一閘極線HG5及第一閘極線HG6，多條第二閘極線VG包括在第一方向D1上依序排列的第二閘極線VG1、第二閘極線VG2、第二閘極線VG3、第二閘極線VG4、第二閘極線VG5及第二閘極線VG6，第二閘極線VG1、第二閘極線VG2、第二閘極線VG3、第二閘極線VG4、第二閘極線VG5及第二閘極線VG6可分別與第一閘極線HG1、第一閘極線HG2、第一閘極線HG3、第一閘極線HG4、第一閘極線HG5及第一閘極線HG6電性連接。然而，本發明不限於此，在其它實施例中，多條第二閘極線VG與多條第一閘極線HG也可利用其它方式彼此連接。 For example, in this embodiment, the plurality of first gate lines HG include first gate lines HG1, first gate lines HG2, first gate lines HG3, The first gate line HG4, the first gate line HG5 and the first gate line HG6, the plurality of second gate lines VG include the second gate lines VG1 and the second gate lines VG1 and the second gate lines arranged in sequence in the first direction D1 The pole line VG2, the second gate line VG3, the second gate line VG4, the second gate line VG5 and the second gate line VG6, the second gate line VG1, the second gate line VG2, the second gate line The line VG3, the second gate line VG4, the second gate line VG5, and the second gate line VG6 may be respectively connected with the first gate line HG1, the first gate line HG2, the first gate line HG3, the first gate line The pole line HG4, the first gate line HG5 and the first gate line HG6 are electrically connected. However, the present invention is not limited thereto, and in other embodiments, the plurality of second gate lines VG and the plurality of first gate lines HG may also be connected to each other in other manners.

請參照圖1及圖2，值得注意的是，畫素陣列基板100的元件層120還包括多條第一共用線CL1。請參照圖2，多條第一共用線CL1設置於第一基板110上。在畫素陣列基板100的俯視圖中，每一第一共用線CL1與對應的一條第二閘極線VG設置於 相鄰的兩畫素行Cpx之間，每一第一共用線CL1及對應的一條第二閘極線VG分別設置於與第二閘極線VG電性連接之一第一閘極線HG的相對兩側，且每一第一共用線CL1與對應的一條第二閘極線VG於結構上分離。 Referring to FIG. 1 and FIG. 2 , it should be noted that the element layer 120 of the pixel array substrate 100 further includes a plurality of first common lines CL1 . Referring to FIG. 2 , a plurality of first common lines CL1 are disposed on the first substrate 110 . In the top view of the pixel array substrate 100 , each first common line CL1 and a corresponding second gate line VG are disposed on the Between two adjacent pixel rows Cpx, each first common line CL1 and a corresponding second gate line VG are respectively disposed opposite to a first gate line HG electrically connected to the second gate line VG. On both sides, each first common line CL1 is structurally separated from a corresponding second gate line VG.

舉例而言，在本實施例中，多條第二閘極線VG包括分別與第一閘極線HG1、第一閘極線HG2、第一閘極線HG3、第一閘極線HG4、第一閘極線HG5及第一閘極線HG6電性連接的第二閘極線VG1、第二閘極線VG2、第二閘極線VG3、第二閘極線VG4、第二閘極線VG5及第二閘極線VG6；多條第一共用線CL1包括分別與第二閘極線VG1、第二閘極線VG2、第二閘極線VG3、第二閘極線VG4、第二閘極線VG5及第二閘極線VG6對應的第一共用線CL11、第一共用線CL12、第一共用線CL13、第一共用線CL14、第一共用線CL15及第一共用線CL16；在畫素陣列基板100的俯視圖中，第一共用線CL11及第二閘極線VG1分別設置於與第二閘極線VG1電性連接之第一閘極線HG1的相對兩側，且第一共用線CL11與第二閘極線VG1於結構上分離；第一共用線CL12及第二閘極線VG2分別設置於與第二閘極線VG2電性連接之第一閘極線HG2的相對兩側，且第一共用線CL12與第二閘極線VG2於結構上分離；第一共用線CL13及第二閘極線VG3分別設置於與第二閘極線VG3電性連接之第一閘極線HG3的相對兩側，且第一共用線CL13與第二閘極線VG3於結構上分離；第一共用線CL14及第二閘極線VG4分別設置於與第二閘極線VG4電性連 接之第一閘極線HG4的相對兩側，且第一共用線CL14與第二閘極線VG4於結構上分離；第一共用線CL15及第二閘極線VG5分別設置於與第二閘極線VG5電性連接之第一閘極線HG5的相對兩側，且第一共用線CL15與第二閘極線VG5於結構上分離；第一共用線CL16及第二閘極線VG6分別設置於與第二閘極線VG6電性連接之第一閘極線HG6的相對兩側，且第一共用線CL16與第二閘極線VG6於結構上分離。 For example, in this embodiment, the plurality of second gate lines VG include a first gate line HG1 , a first gate line HG2 , a first gate line HG3 , a first gate line HG4 , a first gate line HG2 , a first gate line HG4 A second gate line VG1, a second gate line VG2, a second gate line VG3, a second gate line VG4, a second gate line VG5 electrically connected to a gate line HG5 and a first gate line HG6 and the second gate line VG6; the plurality of first common lines CL1 respectively include the second gate line VG1, the second gate line VG2, the second gate line VG3, the second gate line VG4, the second gate line The first common line CL11, the first common line CL12, the first common line CL13, the first common line CL14, the first common line CL15 and the first common line CL16 corresponding to the line VG5 and the second gate line VG6; In the top view of the array substrate 100, the first common line CL11 and the second gate line VG1 are respectively disposed on opposite sides of the first gate line HG1 electrically connected to the second gate line VG1, and the first common line CL11 The structure is separated from the second gate line VG1; the first common line CL12 and the second gate line VG2 are respectively disposed on opposite sides of the first gate line HG2 electrically connected to the second gate line VG2, and The first common line CL12 and the second gate line VG2 are separated in structure; the first common line CL13 and the second gate line VG3 are respectively disposed on the first gate line HG3 electrically connected to the second gate line VG3 On opposite sides, and the first common line CL13 and the second gate line VG3 are structurally separated; the first common line CL14 and the second gate line VG4 are respectively disposed in electrical connection with the second gate line VG4 It is connected to opposite sides of the first gate line HG4, and the first common line CL14 and the second gate line VG4 are separated in structure; the first common line CL15 and the second gate line VG5 are respectively arranged on the second gate line The pole line VG5 is electrically connected to opposite sides of the first gate line HG5, and the first common line CL15 and the second gate line VG5 are structurally separated; the first common line CL16 and the second gate line VG6 are respectively provided On opposite sides of the first gate line HG6 electrically connected to the second gate line VG6, the first common line CL16 and the second gate line VG6 are structurally separated.

值得一提的是，透過第一共用線CL1的設置，無論畫素結構PX旁是否設有第二閘極線VG，多個畫素結構PX可感受到相同或相近的電場分佈，進而能提升顯示品質。 It is worth mentioning that, through the arrangement of the first common line CL1, regardless of whether there is a second gate line VG beside the pixel structure PX, the plurality of pixel structures PX can feel the same or similar electric field distribution, which can improve the Display quality.

在本實施例中，第一共用線CL1的訊號與第二閘極線VG的閘極關閉訊號實質上相同。具體而言，在本實施例中，無論是在第二閘極線VG的訊號為閘極關閉訊號或閘極開啟訊號時，第一共用線CL1的訊號都可固定為所述閘極關閉訊號。舉例而言，在本實施例中，所述閘極關閉訊號可是-9伏特~-10伏特之間的一直流電訊號，但本發明不以此為限。 In this embodiment, the signal of the first common line CL1 is substantially the same as the gate-off signal of the second gate line VG. Specifically, in this embodiment, no matter when the signal of the second gate line VG is the gate close signal or the gate open signal, the signal of the first common line CL1 can be fixed as the gate close signal . For example, in this embodiment, the gate closing signal may be a DC signal between -9 volts and -10 volts, but the invention is not limited to this.

在本實施例中，第一共用線CL1與第一閘極線HG屬於不同的膜層。舉例而言，在本實施例中，第一閘極線HG可屬於第一金屬層，第一共用線CL1可屬於第二金屬層，但本發明不以此為限。基於導電性的考量，在本實施例中，第一共用線CL1是使用金屬材料。但本發明不限於此，在其他實施例中，第一共用線CL1也可以使用其他導電材料，例如：合金、金屬材料的氮化 物、金屬材料的氧化物、金屬材料的氮氧化物、或是金屬材料與其它導電材料的堆疊層。 In this embodiment, the first common line CL1 and the first gate line HG belong to different layers. For example, in this embodiment, the first gate line HG may belong to the first metal layer, and the first common line CL1 may belong to the second metal layer, but the invention is not limited thereto. Based on the consideration of conductivity, in this embodiment, the first common line CL1 is made of a metal material. However, the present invention is not limited to this. In other embodiments, the first common line CL1 may also use other conductive materials, such as alloys, nitridation of metal materials , oxides of metal materials, oxynitrides of metal materials, or stacked layers of metal materials and other conductive materials.

請參照圖1及圖2，在本實施例中，畫素陣列基板100的元件層120還包括一第一周邊走線L1。請參照圖2，第一周邊走線L1設置於第一基板110上且位於多個畫素結構PX的第一側S1。多條第一共用線CL1電性連接至第一周邊走線L1。 Referring to FIG. 1 and FIG. 2 , in this embodiment, the element layer 120 of the pixel array substrate 100 further includes a first peripheral line L1 . Referring to FIG. 2 , the first peripheral wiring L1 is disposed on the first substrate 110 and located on the first side S1 of the plurality of pixel structures PX. The plurality of first common lines CL1 are electrically connected to the first peripheral lines L1.

請參照圖1及圖2，在本實施例中，畫素陣列基板100的元件層120還包括多條第二共用線CL2。請參照圖2，多條第二共用線CL2設置於第一基板110上，多個第二閘極線VG及多條第二共用線CL2在第一方向D1上排列，且每一第二共用線CL2設置於相鄰兩畫素行Cpx之間。具體而言，多個畫素行Cpx之間具有多個佈局面積，而第二共用線CL2是設置於未設有第二閘極線VG及第一共用線CL1的所述佈局面積上。 Referring to FIG. 1 and FIG. 2 , in this embodiment, the element layer 120 of the pixel array substrate 100 further includes a plurality of second common lines CL2 . 2, a plurality of second common lines CL2 are disposed on the first substrate 110, a plurality of second gate lines VG and a plurality of second common lines CL2 are arranged in the first direction D1, and each second common line The line CL2 is arranged between two adjacent pixel lines Cpx. Specifically, there are a plurality of layout areas among the plurality of pixel rows Cpx, and the second common line CL2 is disposed on the layout area where the second gate line VG and the first common line CL1 are not provided.

在本實施例中，第二共用線CL2與第一閘極線HG屬於不同的膜層。舉例而言，在本實施例中，第一閘極線HG可屬於第一金屬層，第二共用線CL2可屬於第二金屬層，但本發明不以此為限。基於導電性的考量，在本實施例中，第二共用線CL2是使用金屬材料。但本發明不限於此，在其他實施例中，第二共用線CL2也可以使用其他導電材料，例如：合金、金屬材料的氮化物、金屬材料的氧化物、金屬材料的氮氧化物、或是金屬材料與其它導電材料的堆疊層。 In this embodiment, the second common line CL2 and the first gate line HG belong to different layers. For example, in this embodiment, the first gate line HG may belong to the first metal layer, and the second common line CL2 may belong to the second metal layer, but the invention is not limited thereto. Based on the consideration of conductivity, in this embodiment, the second common line CL2 is made of a metal material. However, the present invention is not limited thereto. In other embodiments, the second common line CL2 may also use other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or Stacked layers of metallic materials and other conductive materials.

請參照圖1及圖2，在本實施例中，畫素陣列基板100 的元件層120還包括一第二周邊走線L2。請參照圖2，第二周邊走線L2設置於第一基板110上且位於多個畫素結構PX的第二側S2，多條第二共用線CL2電性連接至第二周邊走線L2。 Please refer to FIG. 1 and FIG. 2 , in this embodiment, the pixel array substrate 100 The device layer 120 further includes a second peripheral wiring L2. Referring to FIG. 2 , the second peripheral lines L2 are disposed on the first substrate 110 and located on the second side S2 of the plurality of pixel structures PX, and the plurality of second common lines CL2 are electrically connected to the second peripheral lines L2.

在本實施例中，每一第二共用線CL2之靠近第二周邊走線L2的一端是電性連接至第二周邊走線L2，而每一第二共用線CL2之遠離第二周邊走線L2的另一端可選擇性地與第一周邊走線L1分離，但本發明不以此為限。 In this embodiment, one end of each second common line CL2 close to the second peripheral wiring L2 is electrically connected to the second peripheral wiring L2, and each second common line CL2 is far from the second peripheral wiring The other end of L2 can be selectively separated from the first peripheral wiring L1, but the invention is not limited to this.

請參照圖2，每一第一閘極線HG與n條第二閘極線VG電性連接，n為正整數，每一第一閘極線HG與n條第二閘極線VG具有在第一方向D1上依序排列的第1~n個連接點(或稱接觸點)C，多條第二閘極線VG包括在第一方向D1上依序排列的第1~n個第二閘極線群Gvg，第1~n個第二閘極線群Gvg之第m個第二閘極線群Gvg的多條第二閘極線VG與對應的多條第一閘極線HG具有第1~n個連接點C的第m個連接點C，m為正整數，且n

Figure 109118552-A0305-02-0017-3
m
Figure 109118552-A0305-02-0017-4
1。 Please refer to FIG. 2 , each first gate line HG is electrically connected to n second gate lines VG, n is a positive integer, each first gate line HG and n second gate lines VG have The 1st to nth connection points (or contact points) C arranged in sequence in the first direction D1, the plurality of second gate lines VG include the 1st to nth second gate lines arranged in sequence in the first direction D1 The gate line group Gvg, the plurality of second gate lines VG of the m-th second gate line group Gvg of the 1st to nth second gate line groups Gvg and the corresponding plurality of first gate lines HG have The mth connection point C of the 1st~nth connection point C, m is a positive integer, and n
Figure 109118552-A0305-02-0017-3
m
Figure 109118552-A0305-02-0017-4
1.

舉例而言，在本實施例中，n=3，每一第一閘極線HG與對應的3條第二閘極線VG電性連接，每一第一閘極線HG與對應的3條第二閘極線VG具有在第一方向D1上依序排列的第1~3個連接點C1、C2、C3，多條第二閘極線VG包括在第一方向D1上依序排列的第1~3個第二閘極線群Gvg1、Gvg2、Gvg3，第1個第二閘極線群Gvg1的多條第二閘極線VG1~VG6與對應的多條第一閘極線HG1~HG6具有多個第1個連接點C1，第2個第二 閘極線群Gvg2的多條第二閘極線VG1~VG6與對應的多條第一閘極線HG1~HG6具有多個第2個連接點C2，且第3個第二閘極線群Gvg3的多條第二閘極線VG1~VG6與對應的多條第一閘極線HG1~HG6具有多個第3個連接點C3。 For example, in this embodiment, n=3, each first gate line HG is electrically connected to the corresponding three second gate lines VG, and each first gate line HG is electrically connected to the corresponding three The second gate line VG has the first to third connection points C1, C2, C3 arranged in sequence in the first direction D1, and the plurality of second gate lines VG include the first to third connection points arranged in sequence in the first direction D1. 1~3 second gate line groups Gvg1, Gvg2, Gvg3, a plurality of second gate lines VG1~VG6 of the first second gate line group Gvg1 and a plurality of corresponding first gate lines HG1~HG6 With multiple 1st connection point C1, 2nd second The plurality of second gate lines VG1 to VG6 of the gate line group Gvg2 and the corresponding plurality of first gate lines HG1 to HG6 have a plurality of second connection points C2, and the third second gate line group Gvg3 The plurality of second gate lines VG1 to VG6 and the corresponding plurality of first gate lines HG1 to HG6 have a plurality of third connection points C3.

圖3為本發明一實施例之對向基板200、第一轉接元件T1、第二轉接元件T2及第三轉接元件T3的俯視示意圖。 3 is a schematic top view of the opposite substrate 200 , the first transfer element T1 , the second transfer element T2 and the third transfer element T3 according to an embodiment of the present invention.

請參照圖1及圖3，在本實施例中，顯示裝置10的對向基板200可選擇性地包括共用電極220，其中共用電極220設置於第二基板210上且位於第二基板210與顯示介質300之間。請參照圖2及圖3，在本實施例中，共用電極220是一整面電極，且重疊於所有的畫素結構PX，但本發明不以此為限。 Referring to FIG. 1 and FIG. 3 , in this embodiment, the opposite substrate 200 of the display device 10 can selectively include a common electrode 220 , wherein the common electrode 220 is disposed on the second substrate 210 and located between the second substrate 210 and the display between medium 300. Please refer to FIG. 2 and FIG. 3 , in this embodiment, the common electrode 220 is a whole-surface electrode and overlaps all the pixel structures PX, but the present invention is not limited to this.

在本實施例中，共用電極220例如是透明導電層，其包括金屬氧化物，例如：銦錫氧化物、銦鋅氧化物、鋁錫氧化物、鋁鋅氧化物、銦鍺鋅氧化物、或其它合適的氧化物、或者是上述至少二者之堆疊層，但本發明不以此為限。 In this embodiment, the common electrode 220 is, for example, a transparent conductive layer, which includes metal oxides, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, or Other suitable oxides, or a stacked layer of at least the above two, but the present invention is not limited thereto.

請參照圖1及圖2，在本實施例中，畫素陣列基板100的元件層120還包括多個共用墊組Gp1a、Gp1b、Gp1c及n個第二共用墊p2a、p2b、p2c。請參照圖2，多個共用墊組Gp1a、Gp1b、Gp1c設置於第一基板110上，分別對應第1~n個第二閘極線群Gvg1、Gvgl2、Gvgl3設置，且位於多個畫素結構PX的第二側S2。每一共用墊組Gp1a、Gp1b、Gp1c包括於結構上分離的多個第一共用墊p1a、p1b、p1c。n個第二共用墊p2a、p2b、p2c設置於第 一基板110上，分別對應第1~n個第二閘極線群Gvg1、Gvgl2、Gvgl3設置，且位於多個畫素結構PX的第一側S1。 1 and FIG. 2, in this embodiment, the element layer 120 of the pixel array substrate 100 further includes a plurality of common pad groups Gp1a, Gp1b, Gp1c and n second common pads p2a, p2b, p2c. Please refer to FIG. 2 , a plurality of common pad groups Gp1a, Gp1b, Gp1c are disposed on the first substrate 110, corresponding to the first to nth second gate line groups Gvg1, Gvgl2, Gvgl3, respectively, and located in a plurality of pixel structures The second side S2 of the PX. Each common pad group Gp1a, Gp1b, Gp1c includes a plurality of first common pads p1a, p1b, p1c separated in structure. n second common pads p2a, p2b, p2c are arranged on the On a substrate 110 , the first to n second gate line groups Gvg1 , Gvgl2 , and Gvgl3 are respectively disposed and located on the first side S1 of the plurality of pixel structures PX.

舉例而言，在本實施例中，n=3，畫素陣列基板100包括3個共用墊組Gp1a、Gp1b、Gp1c及3個第二共用墊p2a、p2b、p2c。3個共用墊組Gp1a、Gp1b、Gp1c分別對應第1~3個第二閘極線群Gvg1、Gvg2、Gvg3設置，且位於多個畫素結構PX的第二側S2。3個第二共用墊p2a、p2b、p2c設置於第一基板110上，分別對應第1~3個第二閘極線群Gvg1、Gvg2、Gvg3設置，且位於多個畫素結構PX的第一側S1。 For example, in this embodiment, n=3, and the pixel array substrate 100 includes three common pad groups Gp1a, Gp1b, Gp1c and three second common pads p2a, p2b, p2c. The three common pad groups Gp1a, Gp1b, Gp1c are respectively disposed corresponding to the first to third second gate line groups Gvg1, Gvg2, Gvg3, and are located on the second side S2 of the plurality of pixel structures PX. The three second common pads p2a, p2b, p2c are disposed on the first substrate 110, corresponding to the first to third second gate line groups Gvg1, Gvg2, Gvg3, respectively, and are located on the first side S1 of the plurality of pixel structures PX.

在本實施例中，同一共用墊組Gp1a的多個第一共用墊p1a分散在對應之一第二閘極線群Gvg1的多條第二閘極線VG1~VG6的一側，與第二閘極線群Gvg1對應之一第二共用墊p2a設置在第二閘極線群Gvg1的多條第二閘極線VG1~VG6的另一側，且第二共用墊p2a可位於第二閘極線群Gvg1中最長的一條第二閘極線VG6旁。 In this embodiment, the plurality of first common pads p1a of the same common pad group Gp1a are scattered on one side of the plurality of second gate lines VG1 to VG6 corresponding to a second gate line group Gvg1, and the second gate lines A second common pad p2a corresponding to the pole line group Gvg1 is disposed on the other side of the plurality of second gate lines VG1 to VG6 of the second gate line group Gvg1, and the second common pad p2a may be located on the second gate line Next to the longest second gate line VG6 in the group Gvg1.

請參照圖1、圖2及圖3，在本實施例中，顯示裝置10還包括多個第一轉接元件T1，設置於畫素陣列基板100的元件層120與對向基板200的共用電極220之間。多個第一轉接元件T1分別設置於多個共用墊組Gp1a、Gp1b、Gp1c的多個第一共用墊p1a、p1b、p1c上，且電性連接至多個第一共用墊p1a、p1b、p1c及共用電極220的第一部221。 Referring to FIG. 1 , FIG. 2 and FIG. 3 , in this embodiment, the display device 10 further includes a plurality of first transition elements T1 , which are disposed on the element layer 120 of the pixel array substrate 100 and the common electrode of the opposite substrate 200 between 220. The plurality of first transition elements T1 are respectively disposed on the plurality of first common pads p1a, p1b, p1c of the plurality of common pad groups Gp1a, Gp1b, Gp1c, and are electrically connected to the plurality of first common pads p1a, p1b, p1c and the first portion 221 of the common electrode 220 .

在本實施例中，顯示裝置10還包括n個第二轉接元件T2， 設置於畫素陣列基板100的元件層120與對向基板200的共用電極220之間。n個第二轉接元件T2分別設置於n個第二共用墊p2a、p2b、p2c上，且電性連接至n個第二共用墊p2a、p2b、p2c及共用電極220的第二部222。 In this embodiment, the display device 10 further includes n second switching elements T2, It is disposed between the element layer 120 of the pixel array substrate 100 and the common electrode 220 of the opposite substrate 200 . The n second transition elements T2 are respectively disposed on the n second common pads p2a, p2b, p2c, and are electrically connected to the n second common pads p2a, p2b, p2c and the second portion 222 of the common electrode 220 .

在本實施例中，一共用墊組Gp1a及一第二共用墊p2a對應同一個第二閘極線群Gvg1，且第二共用墊p2a的電位大於共用墊組Gp1a之多個第一共用墊p1a的電位。藉此，分別與設置於第一共用墊p1a上之第一轉接元件T1及設置於第二共用墊p2a上之第二轉接元件T2電性連接的共用電極220的第一部221與第二部222之間會形成一電位分佈，所述電位分佈能補償因第二閘極線群Gvg1之多條第二閘極線VG1~VG6的阻抗不一所造成的亮度差異。 In this embodiment, a common pad group Gp1a and a second common pad p2a correspond to the same second gate line group Gvg1, and the potential of the second common pad p2a is greater than that of the first common pads p1a of the common pad group Gp1a the potential. Thereby, the first portion 221 of the common electrode 220 and the first portion 221 of the common electrode 220 electrically connected to the first transfer element T1 disposed on the first common pad p1a and the second transfer element T2 disposed on the second common pad p2a respectively A potential distribution is formed between the two parts 222 , and the potential distribution can compensate the difference in brightness caused by the different impedances of the plurality of second gate lines VG1 - VG6 of the second gate line group Gvg1 .

在本實施例中，多個第一共用墊p1a、p1b、p1c是分別透過多條導線Lp1a、Lp1b、Lp1c電性連接至一驅動元件(未繪示)，多個第二共用墊p2a、p2b、p2c是分別透過多條導線Lp2a、Lp2b、Lp2c電性連接至一驅動元件(未繪示)，且多條導線Lp1a、Lp1b、Lp1c、Lp2a、Lp2b、Lp2c於結構上彼此分離。換言之，多個第一共用墊p1a、p1b、p1c及多個第二共用墊p2a、p2b、p2c的多個電位可被獨立控制，多個第一共用墊p1a、p1b、p1c及多個第二共用墊p2a、p2b、p2c的電位大小可視實際需求調整之。 In this embodiment, the plurality of first common pads p1a, p1b, p1c are electrically connected to a driving element (not shown) through a plurality of wires Lp1a, Lp1b, Lp1c, respectively, and the plurality of second common pads p2a, p2b , p2c are respectively electrically connected to a driving element (not shown) through a plurality of wires Lp2a, Lp2b, Lp2c, and the plurality of wires Lp1a, Lp1b, Lp1c, Lp2a, Lp2b, Lp2c are separated from each other in structure. In other words, the potentials of the plurality of first common pads p1a, p1b, p1c and the plurality of second common pads p2a, p2b, p2c can be independently controlled, the plurality of first common pads p1a, p1b, p1c and the plurality of second common pads p1a, p1b, p1c The potentials of the shared pads p2a, p2b, and p2c can be adjusted according to actual needs.

請參照圖1及圖2，在本實施例中，畫素陣列基板100的元件層120還包括第三共用墊p3。請參照圖2，第三共用墊p3 設置於第一基板110上，且位於多個畫素結構PX的第一側S1。第三共用墊p3及多個第二共用墊p2a、p2b、p2c在第一方向D1上依序排列且於結構上彼此分離，第三共用墊p3對應第1個第二閘極線群Gvg1設置，而第三共用墊p3的電位大於多個第二共用墊p2a、p2b、p2c的電位。在本實施例中，第三共用墊p3的電位也大於第一共用墊p1a、p1b、p1c的電位；舉例而言，第三共用墊p3與第一共用墊p1a、p1b、p1c之任一者的電位差可相差1伏特或1伏特以上，但本發明不以此為限。 Referring to FIG. 1 and FIG. 2 , in this embodiment, the element layer 120 of the pixel array substrate 100 further includes a third common pad p3 . Please refer to FIG. 2, the third common pad p3 It is disposed on the first substrate 110 and located on the first side S1 of the plurality of pixel structures PX. The third common pad p3 and the plurality of second common pads p2a, p2b, p2c are sequentially arranged in the first direction D1 and are structurally separated from each other, and the third common pad p3 is disposed corresponding to the first second gate line group Gvg1 , and the potential of the third common pad p3 is greater than the potential of the plurality of second common pads p2a, p2b, p2c. In this embodiment, the potential of the third common pad p3 is also greater than the potential of the first common pads p1a, p1b, p1c; for example, the third common pad p3 and any one of the first common pads p1a, p1b, p1c The potential difference may differ by 1 volt or more, but the present invention is not limited to this.

請參照圖1、圖2及圖3，在本實施例中，顯示裝置10還包括第三轉接元件T3，設置於畫素陣列基板100的元件層120與對向基板200的共用電極220之間。第三轉接元件T3設置於第三共用墊p3上，且電性連接至第三共用墊p3及共用電極220的第三部223。 Referring to FIGS. 1 , 2 and 3 , in this embodiment, the display device 10 further includes a third switching element T3 , which is disposed between the element layer 120 of the pixel array substrate 100 and the common electrode 220 of the opposite substrate 200 . between. The third transition element T3 is disposed on the third common pad p3 and is electrically connected to the third common pad p3 and the third portion 223 of the common electrode 220 .

在本實施例中，第三共用墊p3是透過導線Lp3電性連接至所述驅動元件，且導線Lp3和與第一共用墊p1a、p1b、p1c及第二共用墊p2a、p2b、p2c電性連接的多條導線Lp1a、Lp1b、Lp1c、Lp2a、Lp2b、Lp2c於結構上彼此分離。換言之，第三共用墊p3的電位可被獨立控制，第三共用墊p3的電位大小可視實際需求調整之。 In this embodiment, the third common pad p3 is electrically connected to the driving element through the wire Lp3, and the wire Lp3 is electrically connected to the first common pads p1a, p1b, p1c and the second common pads p2a, p2b, p2c The plurality of connected wires Lp1a, Lp1b, Lp1c, Lp2a, Lp2b, Lp2c are structurally separated from each other. In other words, the potential of the third common pad p3 can be independently controlled, and the potential of the third common pad p3 can be adjusted according to actual needs.

在本實施例中，第一轉接元件T1、第二轉接元件T2及第三轉接元件T3包括導電球(例如：金球)，但本發明不以此為限。 In this embodiment, the first transfer element T1 , the second transfer element T2 and the third transfer element T3 include conductive balls (eg, gold balls), but the invention is not limited thereto.

在此必須說明的是，下述實施例沿用前述實施例的元件標號與部分內容，其中採用相同的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，下述實施例不再重述。 It must be noted here that the following embodiments use the element numbers and part of the contents of the previous embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

圖4為本發明一實施例之畫素陣列基板100A、第一轉接元件T1、第二轉接元件T2及第三轉接元件T3的俯視示意圖。 4 is a schematic top view of the pixel array substrate 100A, the first transition element T1 , the second transition element T2 and the third transition element T3 according to an embodiment of the present invention.

圖4的畫素陣列基板100A與圖2的畫素陣列基板100類似，兩者的差異在於：在圖4的實施例中，每一第二共用線CL2的兩端可分別電性連接至第一周邊走線L1及第二周邊走線L2。 The pixel array substrate 100A of FIG. 4 is similar to the pixel array substrate 100 of FIG. 2 . The difference between the two is that in the embodiment of FIG. 4 , both ends of each second common line CL2 can be electrically connected to the second common line CL2 A peripheral wiring L1 and a second peripheral wiring L2.

請參照圖4，在本實施例中，輸入至第一周邊走線L1的訊號及輸入至第二周邊走線L2的訊號可被獨立控制。具體而言，第一周邊走線L1及第二周邊走線L2是分別透過各自的導線Ll1及導線Ll2電性連接至所述驅動元件，且導線Ll1及導線Ll2於結構上彼此分離。舉例而言，在本實施例中，輸入至第一周邊走線L1的訊號及輸入至第二周邊走線L2的訊號可以選擇性地相同。舉例而言，輸入至第一周邊走線L1的訊號及輸入至第二周邊走線L2的訊號可皆與第二閘極線VG的閘極關閉訊號相同。然而，本發明不限於此，在其它實施例中，輸入至第一周邊走線L1的訊號及輸入至第二周邊走線L2的訊號也可不同。 Referring to FIG. 4 , in this embodiment, the signal input to the first peripheral wiring L1 and the signal input to the second peripheral wiring L2 can be independently controlled. Specifically, the first peripheral wiring L1 and the second peripheral wiring L2 are electrically connected to the driving element through their respective wires L11 and L12, and the wires L11 and L12 are structurally separated from each other. For example, in this embodiment, the signal input to the first peripheral wiring L1 and the signal input to the second peripheral wiring L2 can be selectively the same. For example, the signal input to the first peripheral line L1 and the signal input to the second peripheral line L2 may be the same as the gate-off signal of the second gate line VG. However, the present invention is not limited thereto, and in other embodiments, the signal input to the first peripheral wiring L1 and the signal input to the second peripheral wiring L2 may also be different.

圖5為本發明一實施例之畫素陣列基板100B及第一轉接元件T1的俯視的上視示意圖。 FIG. 5 is a schematic top view of the pixel array substrate 100B and the first transition element T1 in plan view according to an embodiment of the present invention.

圖5的畫素陣列基板100B與圖2的畫素陣列基板100類 似，兩者的差異在於：在圖2的實施例中，n為3，亦即，每一第一閘極線HG與3條第二閘極線VG電性連接；但在圖5的實施例中，n為4，亦即，每一第一閘極線HG與4條第二閘極線VG電性連接。然而，本發明不限於此，與每一第一閘極線HG電性連接之第二閘極線VG的數量(即n)可視實際需求而定。 The pixel array substrate 100B of FIG. 5 is similar to the pixel array substrate 100 of FIG. 2 Similarly, the difference between the two is: in the embodiment of FIG. 2, n is 3, that is, each first gate line HG is electrically connected to three second gate lines VG; but in the implementation of FIG. 5 In the example, n is 4, that is, each first gate line HG is electrically connected to four second gate lines VG. However, the present invention is not limited thereto, and the number (ie, n) of the second gate lines VG electrically connected to each of the first gate lines HG may be determined according to actual requirements.

具體而言，多個畫素結構PX排成x個畫素行Cpx及y個畫素列Rpx，其中x個畫素行Cpx在第一方向D1上排列，y個畫素列Rpx在第二方向D2上排列，x及y為大於2的正整數。每一畫素結構PX在第一方向D1及第二方向D2上分別具有第一寬度a1及第二寬度a2。第一寬度a1可指分別位於同一畫素結構PX之左右兩側且相鄰之兩第二閘極線VG的距離，第一寬度a1可指分別位於同一畫素結構PX之左右兩側且相鄰之一第二閘極線VG及一第一共用線CL1的距離，第一寬度a1可指分別位於同一畫素結構PX之左右兩側且相鄰之兩第一共用線CL1的距離，第一寬度a1可指分別位於同一畫素結構PX之左右兩側且相鄰之一第一共用線CL1及一第二共用線CL2的距離，或者第一寬度a1可指分別位於同一畫素結構PX之兩側且相鄰之一第二閘極線VG及一第二共用線CL2的距離。第二寬度a2可指位於同一畫素結構PX之上下兩側且相鄰之兩第一閘極線HG的距離。若(a1．x+a2．y)<2000000，則n以等於2為佳。若2000000<(a1．x+a2．y)<2400000，則n以等於3為佳。若2400000<(a1．x+a2．y)<3000000，則n以等於4為佳。若 (a1．x+a2．y)>3000000，則n以等於5為佳。 Specifically, the plurality of pixel structures PX are arranged into x pixel rows Cpx and y pixel rows Rpx, wherein the x pixel rows Cpx are arranged in the first direction D1, and the y pixel rows Rpx are arranged in the second direction D2 Arranged above, x and y are positive integers greater than 2. Each pixel structure PX has a first width a1 and a second width a2 in the first direction D1 and the second direction D2, respectively. The first width a1 may refer to the distance between two adjacent second gate lines VG located on the left and right sides of the same pixel structure PX, respectively. The distance between an adjacent second gate line VG and a first common line CL1, the first width a1 may refer to the distance between two adjacent first common lines CL1 located on the left and right sides of the same pixel structure PX respectively, the first A width a1 may refer to the distance between a first common line CL1 and a second common line CL2 located on the left and right sides of the same pixel structure PX, respectively, or the first width a1 may refer to a distance between a first common line CL1 and a second common line CL2 located on the same pixel structure PX, respectively. The distance between a second gate line VG and a second common line CL2 on both sides and adjacent to it. The second width a2 may refer to the distance between two adjacent first gate lines HG located on the upper and lower sides of the same pixel structure PX. If (a1.x+a2.y)<2000000, then n is preferably equal to 2. If 2000000<(a1.x+a2.y)<2400000, then n is preferably equal to 3. If 2400000<(a1.x+a2.y)<3000000, then n is preferably equal to 4. like (a1.x+a2.y)>3000000, then n is preferably equal to 5.

圖6為本發明一實施例之畫素陣列基板100C及第一轉接元件T1的俯視示意圖。 FIG. 6 is a schematic top view of the pixel array substrate 100C and the first transition element T1 according to an embodiment of the present invention.

圖6的畫素陣列基板100C與圖2的畫素陣列基板100類似，兩者的差異在於：多條第二閘極線VG與多條第一閘極線HG的連接方式不同。 The pixel array substrate 100C of FIG. 6 is similar to the pixel array substrate 100 of FIG. 2 , and the difference between the two is that the connection manners of the plurality of second gate lines VG and the plurality of first gate lines HG are different.

請參照圖6，具體而言，在本實施例中，多條第一閘極線HG在第二方向D2上依序排列，且多條第一閘極線HG包括奇數條第一閘極線HG及偶數條第一閘極線HG。奇數條第一閘極線HG包括第(1+2．K)條第一閘極線HG，K=0,1,…,p，p為大於或等於2的正整數。偶數條第一閘極線HG包括第2L條第一閘極線HG，L=1,2,…,q，q為大於或等於3的正整數。多條第二閘極線VG包括在第一方向D1上依序排列的第1~(p+1)條第二閘極線VG及第(p+2)~(p+q+1)條第二閘極線VG。第1~(p+1)條第二閘極線VG分別電性連接至第(1+2．K)條第一閘極線HG，且第(p+2)~(p+q+1)條第二閘極線VG分別電性連接至第2L條第一閘極線HG。 Please refer to FIG. 6 . Specifically, in this embodiment, a plurality of first gate lines HG are arranged in sequence in the second direction D2 , and the plurality of first gate lines HG include an odd number of first gate lines HG and an even number of first gate lines HG. The odd-numbered first gate lines HG include (1+2.K)th first gate lines HG, where K=0,1,...,p, where p is a positive integer greater than or equal to 2. The even-numbered first gate lines HG include the 2Lth first gate lines HG, where L=1, 2, . . . , q, where q is a positive integer greater than or equal to 3. The plurality of second gate lines VG include the first to (p+1) second gate lines VG and the (p+2) to (p+q+1) second gate lines arranged in sequence in the first direction D1 The second gate line VG. The first to (p+1) second gate lines VG are respectively electrically connected to the (1+2.K) first gate lines HG, and the (p+2) to (p+q+1 ) of the second gate lines VG are respectively electrically connected to the 2Lth first gate lines HG.

舉例而言，在本實施例中，p=2，K=0,1,2，奇數條第一閘極線HG包括第1、3、5條第一閘極線HG1、HG3、HG5；q=3，L=1,2,3，偶數條第一閘極線HG包括第2、4、6條第一閘極線HG2、HG4、HG6；多條第二閘極線VG包括在第一方向D1上依序排列的第1~3條第二閘極線VG1~VG3及第4~6條第二閘極線 VG4~VG6；第1~3條第二閘極線VG1~VG3分別電性連接至第1、3、5條第一閘極線HG1、HG3、HG5，且第4~6條第二閘極線VG4~VG6分別電性連接至第2、4、6條第一閘極線HG2、HG4、HG6。換言之，在本實施例中，同一第二閘極線群Gvg之多條第二閘極線VG與多條第一閘極線HG的多個連接點C(例如：第1~3條第二閘極線VG1~VG3與第1、3、5條第一閘極線HG1、HG3、HG5的多個連接點C及第4~6條第二閘極線VG4~VG6與第2、4、6條第一閘極線HG2、HG4、HG6的多個連接點C)大致上可沿著互相平行的多條斜線K分佈。 For example, in this embodiment, p=2, K=0, 1, 2, and the odd-numbered first gate lines HG include the first, third, and fifth first gate lines HG1, HG3, and HG5; q =3, L=1, 2, 3, the even-numbered first gate lines HG include the 2nd, 4th, and 6th first gate lines HG2, HG4, HG6; a plurality of second gate lines VG are included in the first The 1st to 3rd second gate lines VG1 to VG3 and the 4th to 6th second gate lines arranged in sequence in the direction D1 VG4~VG6; the 1st~3rd second gate lines VG1~VG3 are electrically connected to the 1st, 3rd and 5th first gate lines HG1, HG3, HG5 respectively, and the 4th~6th second gate lines The lines VG4 to VG6 are electrically connected to the second, fourth, and sixth first gate lines HG2, HG4, and HG6, respectively. In other words, in this embodiment, a plurality of connection points C of a plurality of second gate lines VG of the same second gate line group Gvg and a plurality of first gate lines HG (for example, the first to third second gate lines The multiple connection points C of the gate lines VG1~VG3 and the first, third, and fifth gate lines HG1, HG3, and HG5, and the fourth to sixth second gate lines VG4~VG6 and the second, fourth, and third gate lines VG4~VG6. A plurality of connection points C) of the six first gate lines HG2, HG4, and HG6 may be distributed along a plurality of diagonal lines K that are parallel to each other.

圖7為本發明一實施例之畫素陣列基板100D及第一轉接元件T1的俯視示意圖。 FIG. 7 is a schematic top view of the pixel array substrate 100D and the first transition element T1 according to an embodiment of the present invention.

圖7的畫素陣列基板100D與圖2的畫素陣列基板100類似，兩者的差異在於：多條第二閘極線VG與多條第一閘極線HG的連接方式不同。 The pixel array substrate 100D of FIG. 7 is similar to the pixel array substrate 100 of FIG. 2 , and the difference between the two is that the connection manners of the plurality of second gate lines VG and the plurality of first gate lines HG are different.

請參照圖7，具體而言，具體而言，在本實施例中，多條第一閘極線HG在第二方向D2上依序排列，且多條第一閘極線HG包括奇數條第一閘極線HG及偶數條第一閘極線HG。奇數條第一閘極線HG包括第(1+2．K)條第一閘極線HG，K=0,1,…,p，p為大於或等於2的正整數。偶數條第一閘極線HG包括第2L條第一閘極線HG，L=1,2,…,q，q為大於或等於3的正整數。多條第二閘極線VG包括在第一方向D1上依序排列的第1~(p+1)條第二閘極線VG及第(p+2)~(p+q+1)條第二閘極線VG。第1~(p+1) 條第二閘極線VG分別電性連接至第(1+2．K)條第一閘極線HG，且第(p+q+1)~(p+2)條第二閘極線VG分別電性連接至第2L條第一閘極線HG。 Please refer to FIG. 7 , specifically, in this embodiment, a plurality of first gate lines HG are sequentially arranged in the second direction D2, and the plurality of first gate lines HG include an odd number of the first gate lines HG. A gate line HG and an even number of first gate lines HG. The odd-numbered first gate lines HG include (1+2.K)th first gate lines HG, where K=0,1,...,p, where p is a positive integer greater than or equal to 2. The even-numbered first gate lines HG include the 2Lth first gate lines HG, where L=1, 2, . . . , q, where q is a positive integer greater than or equal to 3. The plurality of second gate lines VG include the first to (p+1) second gate lines VG and the (p+2) to (p+q+1) second gate lines arranged in sequence in the first direction D1 The second gate line VG. 1st~(p+1) The second gate lines VG are respectively electrically connected to the (1+2.K)th first gate lines HG, and the (p+q+1)~(p+2)th second gate lines VG They are respectively electrically connected to the 2L first gate lines HG.

舉例而言，在本實施例中，p=2，K=0,1,2，奇數條第一閘極線HG包括第1、3、5條第一閘極線HG1、HG3、HG5；q=3，L=1,2,3，偶數條第一閘極線HG包括第2、4、6條第一閘極線HG2、HG4、HG6；多條第二閘極線VG包括在第一方向D1上依序排列的第1~3條第二閘極線VG1~VG3及第4~6條第二閘極線VG4~VG6；第1~3條第二閘極線VG1~VG3分別電性連接至第1、3、5條第一閘極線HG1、HG3、HG5，且第6~4條第二閘極線VG6~VG4分別電性連接至第2、4、6條第一閘極線HG2、HG4、HG6。換言之，在本實施例中，同一第二閘極線群Gvg之多條第二閘極線VG與多條第一閘極線HG的多個連接點C(例如：第1~3條第二閘極線VG1~VG3與第1、3、5條第一閘極線HG1、HG3、HG5的多個連接點C及第6~4條第二閘極線VG4~VG6與第2、4、6條第一閘極線HG2、HG4、HG6的多個連接點C)大致上呈V字型分佈。 For example, in this embodiment, p=2, K=0, 1, 2, and the odd-numbered first gate lines HG include the first, third, and fifth first gate lines HG1, HG3, and HG5; q =3, L=1, 2, 3, the even-numbered first gate lines HG include the 2nd, 4th, and 6th first gate lines HG2, HG4, HG6; a plurality of second gate lines VG are included in the first The 1st~3rd second gate lines VG1~VG3 and the 4th~6th second gate lines VG4~VG6 arranged in sequence in the direction D1; the 1st~3rd second gate lines VG1~VG3 are respectively electrically connected. are electrically connected to the 1st, 3rd, and 5th first gate lines HG1, HG3, and HG5, and the 6th to 4th second gate lines VG6 to VG4 are electrically connected to the 2nd, 4th, and 6th first gate lines, respectively. Polar lines HG2, HG4, HG6. In other words, in this embodiment, a plurality of connection points C of a plurality of second gate lines VG of the same second gate line group Gvg and a plurality of first gate lines HG (for example, the first to third second gate lines The multiple connection points C of the gate lines VG1~VG3 and the 1st, 3rd, 5th first gate lines HG1, HG3, HG5 and the 6th~4th second gate lines VG4~VG6 and the 2nd, 4th, The plurality of connection points C) of the six first gate lines HG2, HG4, and HG6 are generally distributed in a V-shape.

100:畫素陣列基板 100: pixel array substrate

110:第一基板 110: The first substrate

Cpx:畫素行 Cpx: pixel row

C、C1、C2、C3:連接點 C, C1, C2, C3: connection points

CL1、CL11、CL12、CL13、CL14、CL15、CL16:第一共用線 CL1, CL11, CL12, CL13, CL14, CL15, CL16: first common line

CL2:第二共用線 CL2: Second common line

D1:第一方向 D1: first direction

D2:第二方向 D2: Second direction

DL:資料線 DL: data line

Gvg、Gvg1、Gvg2、Gvg3:第二閘極線群 Gvg, Gvg1, Gvg2, Gvg3: the second gate line group

Gp1a、Gp1b、Gp1c:共用墊組 Gp1a, Gp1b, Gp1c: common pad groups

HG、HG1、HG2、HG3、HG4、HG5、HG6:第一閘極線 HG, HG1, HG2, HG3, HG4, HG5, HG6: first gate line

L1:第一周邊走線 L1: The first peripheral trace

L2:第二周邊走線 L2: Second peripheral trace

Lp1a、Lp1b、Lp1c、Lp2a、Lp2b、Lp2c、Lp3:導線 Lp1a, Lp1b, Lp1c, Lp2a, Lp2b, Lp2c, Lp3: wires

PX:畫素結構 PX: pixel structure

p1a、p1b、p1c:第一共用墊 p1a, p1b, p1c: first common pad

p2a、p2b、p2c:第二共用墊 p2a, p2b, p2c: second common pad

p3:第三共用墊 p3: Third Common Pad

Rpx:畫素列 Rpx: pixel column

S1:第一側 S1: first side

S2:第二側 S2: Second side

T1:第一轉接元件 T1: The first transfer element

T2:第二轉接元件 T2: The second switching element

T3:第三轉接元件 T3: The third transfer element

VG、VG1、VG2、VG3、VG4、VG5、VG6:第二閘極線 VG, VG1, VG2, VG3, VG4, VG5, VG6: the second gate line

Claims (16)

一種顯示裝置，包括：一第一基板；多條資料線，設置於該第一基板上，且在一第一方向上排列；多條第一閘極線，設置於該第一基板上，且在一第二方向上排列，其中該第一方向與該第二方向交錯；多個畫素結構，設置於該第一基板上，且電性連接該些資料線及該些第一閘極線；多條第二閘極線，設置於該第一基板上，其中該些資料線及該些第二閘極線在該第一方向上排列，且該些第二閘極線電性連接至該些第一閘極線；多條第一共用線，設置於該第一基板上，其中該些畫素結構排成多個畫素行，該些畫素行在該第一方向上排列，該些第一共用線的每一者與該些第二閘極線的對應的一個設置於該些畫素行的相鄰兩者之間，該第一共用線及對應的該第二閘極線分別設置於與該第二閘極線電性連接之該些第一閘極線的對應的一個的相對兩側，且該第一共用線與對應的該第二閘極線於結構上分離；一第二基板，設置於該第一基板的對向；以及一顯示介質，設置於該第一基板與該第二基板之間。 A display device includes: a first substrate; a plurality of data lines disposed on the first substrate and arranged in a first direction; a plurality of first gate lines disposed on the first substrate, and Arranged in a second direction, wherein the first direction and the second direction are staggered; a plurality of pixel structures are arranged on the first substrate and are electrically connected to the data lines and the first gate lines a plurality of second gate lines disposed on the first substrate, wherein the data lines and the second gate lines are arranged in the first direction, and the second gate lines are electrically connected to the first gate lines; a plurality of first common lines disposed on the first substrate, wherein the pixel structures are arranged in a plurality of pixel rows, the pixel rows are arranged in the first direction, the Each of the first common lines and the corresponding one of the second gate lines are disposed between two adjacent ones of the pixel rows, and the first common lines and the corresponding second gate lines are respectively disposed on opposite sides of the corresponding one of the first gate lines electrically connected to the second gate line, and the first common line and the corresponding second gate line are structurally separated; a first Two substrates are arranged opposite to the first substrate; and a display medium is arranged between the first substrate and the second substrate. 如申請專利範圍第1項所述的顯示裝置，其中一該第一共用線的訊號與一該第二閘極線的一閘極關閉訊號實質上相同。 The display device of claim 1, wherein a signal of the first common line and a gate-off signal of the second gate line are substantially the same. 如申請專利範圍第1項所述的顯示裝置，其中該些第一閘極線的每一者與n條第二閘極線電性連接，n為正整數，該些第一閘極線的每一個與該n條第二閘極線具有在該第一方向上依序排列的第1~n個連接點，該些第二閘極線包括在該第一方向上依序排列的第1~n個第二閘極線群，該第1~n個第二閘極線群之第m個第二閘極線群的該些第二閘極線與對應的該些第一閘極線具有該第1~n個連接點的第m個連接點，m為正整數，n
Figure 109118552-A0305-02-0030-5
m
Figure 109118552-A0305-02-0030-6
1，且該顯示裝置更包括：一共用電極，設置於該第二基板上，且位於該第二基板與該顯示介質之間；多個共用墊組，設置於該第一基板上，且分別對應該第1~n個第二閘極線群設置，其中該些畫素結構具有相對的一第一側及一第二側，該些共用墊組設置於該些畫素結構的該第二側，且該些共用墊組的每一者包括多個第一共用墊；多個第一轉接元件，分別設置於該些共用墊組的該些第一共用墊上，且電性連接至該些共用墊組的該些第一共用墊及該共用電極；n個第二共用墊，設置於該第一基板上，分別對應該第1~n個第二閘極線群設置，且位於該些畫素結構的該第一側；以及n個第二轉接元件，分別設置於該n個第二共用墊上，且電性連接至該n個第二共用墊及該共用電極； 其中該些共用墊組的一共用墊組及該n個第二共用墊的一第二共用墊對應同一個第二閘極線群，且該第二共用墊的電位大於該共用墊組之該些第一共用墊的電位。 The display device of claim 1, wherein each of the first gate lines is electrically connected to n second gate lines, n is a positive integer, and the first gate lines are Each of the n second gate lines has 1st to nth connection points arranged in sequence in the first direction, and the second gate lines include a first connection point arranged in sequence in the first direction ~n second gate line groups, the second gate lines of the m-th second gate line group of the 1-nth second gate line groups and the corresponding first gate lines The mth connection point with the 1st~nth connection point, m is a positive integer, n
Figure 109118552-A0305-02-0030-5
m
Figure 109118552-A0305-02-0030-6
1, and the display device further comprises: a common electrode disposed on the second substrate and located between the second substrate and the display medium; a plurality of common pad groups disposed on the first substrate and respectively Corresponding to the 1st to nth second gate line groups are arranged, wherein the pixel structures have a first side and a second side opposite to each other, and the common pad groups are arranged on the second side of the pixel structures side, and each of the shared pad sets includes a plurality of first shared pads; a plurality of first transfer elements are respectively disposed on the first shared pads of the shared pad sets and electrically connected to the the first common pads and the common electrode of the common pad groups; n second common pads, disposed on the first substrate, corresponding to the 1st to nth second gate line groups, respectively, and located in the the first side of the pixel structures; and n second switching elements, respectively disposed on the n second common pads and electrically connected to the n second common pads and the common electrode; wherein these A common pad group of the common pad group and a second common pad of the n second common pads correspond to the same second gate line group, and the potential of the second common pad is greater than the first ones of the common pad group Potential of the common pad. 如申請專利範圍第3項所述的顯示裝置，更包括：一第三共用墊，設置於該第一基板上，且位於該些畫素結構的該第一側，其中該第三共用墊及該些第二共用墊在該第一方向上依序排列且於結構上彼此分離，該第三共用墊對應該第1~n個第二閘極線群的第1個第二閘極線群設置，而該第三共用墊的電位大於對應該些第二共用墊的電位；以及一第三轉接元件，設置於該第三共用墊上，且電性連接至該第三共用墊及該共用電極。 The display device according to claim 3 of the claimed scope, further comprising: a third common pad disposed on the first substrate and located on the first side of the pixel structures, wherein the third common pad and The second common pads are sequentially arranged in the first direction and are structurally separated from each other, and the third common pad corresponds to the first second gate line group of the 1st to nth second gate line groups set up, and the potential of the third common pad is greater than the potential of the corresponding second common pads; and a third transfer element disposed on the third common pad and electrically connected to the third common pad and the common pad electrode. 如申請專利範圍第1項所述的顯示裝置，更包括：多條第二共用線，設置於該第一基板上，該些第二閘極線及該些第二共用線在該第一方向上排列，其中該些第二共用線的每一者設置於該些畫素行的相鄰兩者之間；一第一周邊走線，設置於該第一基板上且位於該些畫素結構的一第一側，其中該些第一共用線電性連接至該第一周邊走線；以及一第二周邊走線，設置於該第一基板上且位於該些畫素結構的一第二側，其中該些第二共用線的每一者的兩端分別電性連接至該第一周邊走線及該第二周邊走線。 The display device according to claim 1, further comprising: a plurality of second common lines disposed on the first substrate, the second gate lines and the second common lines on the first side Arranged upward, wherein each of the second common lines is disposed between two adjacent ones of the pixel rows; a first peripheral line is disposed on the first substrate and located at the edge of the pixel structures a first side, wherein the first common lines are electrically connected to the first peripheral wiring; and a second peripheral wiring disposed on the first substrate and located on a second side of the pixel structures , wherein two ends of each of the second common lines are respectively electrically connected to the first peripheral wiring and the second peripheral wiring. 如申請專利範圍第1項所述的顯示裝置，其中該些第一閘極線包括奇數條第一閘極線及偶數條第一閘極線，該奇數條第一閘極線包括第(1+2．K)條第一閘極線，K=0,1,…,p，p為大於或等於2的正整數，該偶數條第一閘極線包括第2L條第一閘極線，L=1,2,…,q，q為大於或等於3的正整數；該些第二閘極線包括在該第一方向上依序排列的第1~(p+1)條第二閘極線及第(p+2)~(p+q+1)條第二閘極線；該第1~(p+1)條第二閘極線電性連接至該第(1+2．K)條第一閘極線，且該第(p+2)~(p+q+1)條第二閘極線電性連接至該第2L條第一閘極線。 The display device according to claim 1, wherein the first gate lines include odd-numbered first gate lines and even-numbered first gate lines, and the odd-numbered first gate lines include (1) +2.K) first gate lines, K=0,1,...,p, p is a positive integer greater than or equal to 2, the even-numbered first gate lines include the 2L first gate lines, L=1, 2, . The pole line and the (p+2)~(p+q+1) second gate lines; the 1st~(p+1) second gate lines are electrically connected to the (1+2. K) first gate lines, and the (p+2)-(p+q+1)th second gate lines are electrically connected to the 2Lth first gate lines. 如申請專利範圍第6項所述的顯示裝置，其中該第1~(p+1)條第二閘極線與該第(1+2．K)條第一閘極線的多個連接點以及該第(p+2)~(p+q+1)條第二閘極線與該第2L條的多個連接點大致上沿著互相平行的多條斜線分佈。 The display device according to claim 6, wherein a plurality of connection points between the first to (p+1) second gate lines and the (1+2.K) first gate line And the connection points of the (p+2)-(p+q+1)th second gate lines and the 2Lth line are generally distributed along a plurality of diagonal lines parallel to each other. 如申請專利範圍第6項所述的顯示裝置，其中該第1~(p+1)條第二閘極線與該第(1+2．K)條第一閘極線的多個連接點以及該第(p+2)~(p+q+1)條第二閘極線與該第2L條的多個連接點大致上呈V字型分佈。 The display device according to claim 6, wherein a plurality of connection points between the first to (p+1) second gate lines and the (1+2.K) first gate line And the connection points of the (p+2)-(p+q+1)th second gate lines and the 2Lth line are generally V-shaped. 一種顯示裝置，包括：一第一基板；多條資料線，設置於該第一基板上，且在一第一方向上排列；多條第一閘極線，設置於該第一基板上，且在一第二方向上排列，其中該第一方向與該第二方向交錯； 多個畫素結構，設置於該第一基板上，電性連接該些資料線及該些第一閘極線，且在排成x個畫素行及y個畫素列，其中該x個畫素行在該第一方向上排列，該y個畫素列在該第二方向上排列，x及y為大於2的正整數，一該畫素結構在該第一方向及該第二方向上分別具有一第一寬度a1及一第二寬度a2；多條第二閘極線，設置於該第一基板上，其中該些資料線及該些第二閘極線在該第一方向上排列，且該些第二閘極線電性連接至該些第一閘極線；多條第一共用線，設置於該第一基板上；一第二基板，設置於該第一基板的對向；以及一顯示介質，設置於該第一基板與該第二基板之間；其中該些第一共用線的每一者與該些第二閘極線對應的一個設置於該x個畫素行的相鄰兩者之間，該第一共用線及對應的該第二閘極線分別設置於與該第二閘極線電性連接之該些第一閘極線的對應的一個的相對兩側，且該第一共用線與對應的該第二閘極線於結構上分離；其中，該些第一閘極線的每一者與n條第二閘極線電性連接；(a1．x+a2．y)<2000000，且n=2；或2000000<(a1．x+a2．y)<2400000，且n=3；或2400000<(a1．x+a2．y)<3000000，且n=4；或(a1．x+a2．y)>3000000，且n=5。 A display device includes: a first substrate; a plurality of data lines disposed on the first substrate and arranged in a first direction; a plurality of first gate lines disposed on the first substrate, and Arranged in a second direction, wherein the first direction and the second direction are staggered; A plurality of pixel structures are disposed on the first substrate, are electrically connected to the data lines and the first gate lines, and are arranged in x pixel rows and y pixel columns, wherein the x pixel structures are The pixel rows are arranged in the first direction, the y pixel columns are arranged in the second direction, x and y are positive integers greater than 2, and the pixel structure is arranged in the first direction and the second direction respectively having a first width a1 and a second width a2; a plurality of second gate lines disposed on the first substrate, wherein the data lines and the second gate lines are arranged in the first direction, and the second gate lines are electrically connected to the first gate lines; a plurality of first common lines are arranged on the first substrate; a second substrate is arranged opposite to the first substrate; and a display medium disposed between the first substrate and the second substrate; wherein each of the first common lines and one corresponding to the second gate lines are disposed in the phase of the x pixel rows Between the two adjacent ones, the first common line and the corresponding second gate line are respectively disposed on opposite sides of the corresponding one of the first gate lines electrically connected to the second gate line, And the first common line and the corresponding second gate line are structurally separated; wherein, each of the first gate lines is electrically connected to n second gate lines; (a1.x+ a2.y)<2000000, and n=2; or 2000000<(a1.x+a2.y)<2400000, and n=3; or 2400000<(a1.x+a2.y)<3000000, and n= 4; or (a1.x+a2.y)>3000000, and n=5. 如申請專利範圍第9項所述的顯示裝置，其中一該第一共用線的訊號與一該第二閘極線的一閘極關閉訊號實質上相同。 The display device of claim 9, wherein a signal of the first common line and a gate-off signal of the second gate line are substantially the same. 如申請專利範圍第9項所述的顯示裝置，其中該些第一閘極線的每一者與n條第二閘極線電性連接，n為正整數，該些第一閘極線的每一者與該n條第二閘極線具有在該第一方向上依序排列的第1~n個連接點，該些第二閘極線包括在該第一方向上依序排列的第1~n個第二閘極線群，該第1~n個第二閘極線群之第m個第二閘極線群的該些第二閘極線與對應的該些第一閘極線具有該第1~n個連接點的第m個連接點，m為正整數，n
Figure 109118552-A0305-02-0034-7
m
Figure 109118552-A0305-02-0034-8
1，且該顯示裝置更包括：一共用電極，設置於該第二基板上，且位於該第二基板與該顯示介質之間；多個共用墊組，設置於該第一基板上，且分別對應該第1~n個第二閘極線群設置，其中該些畫素結構具有相對的一第一側及一第二側，該些共用墊組設置於該些畫素結構的該第二側，且每一該共用墊組包括多個第一共用墊；多個第一轉接元件，分別設置於該些共用墊組的該些第一共用墊上，且電性連接至該些共用墊組的該些第一共用墊及該共用電極；n個第二共用墊，設置於該第一基板上，分別對應該第1~n個第二閘極線群設置，且位於該些畫素結構的該第一側；以及 n個第二轉接元件，分別設置於該n個第二共用墊上，且電性連接至該n個第二共用墊及該共用電極；其中該些共用墊組的一共用墊組及該n個第二共用墊的一第二共用墊對應同一個第二閘極線群，且該第二共用墊的電位大於該共用墊組之該些第一共用墊的電位。 The display device of claim 9, wherein each of the first gate lines is electrically connected to n second gate lines, n is a positive integer, and the first gate lines are Each of them and the n second gate lines have 1st to nth connection points arranged in sequence in the first direction, and the second gate lines include the 1st to nth connection points arranged in sequence in the first direction. 1 to n second gate line groups, the second gate lines of the mth second gate line group of the 1 to n second gate line groups and the corresponding first gates The line has the mth connection point of the 1st~nth connection point, m is a positive integer, n
Figure 109118552-A0305-02-0034-7
m
Figure 109118552-A0305-02-0034-8
1, and the display device further comprises: a common electrode disposed on the second substrate and located between the second substrate and the display medium; a plurality of common pad groups disposed on the first substrate and respectively Corresponding to the 1st to nth second gate line groups are arranged, wherein the pixel structures have a first side and a second side opposite to each other, and the common pad groups are arranged on the second side of the pixel structures side, and each of the shared pad sets includes a plurality of first shared pads; a plurality of first transfer elements are respectively disposed on the first shared pads of the shared pad sets and electrically connected to the shared pads the first common pads and the common electrodes of the group; n second common pads, disposed on the first substrate, corresponding to the first to n second gate line groups, respectively, and located in the pixels the first side of the structure; and n second transfer elements respectively disposed on the n second common pads and electrically connected to the n second common pads and the common electrode; wherein the common pad groups A common pad group and a second common pad of the n second common pads correspond to the same second gate line group, and the potential of the second common pad is greater than that of the first common pads of the common pad group potential. 如申請專利範圍第11項所述的顯示裝置，更包括：一第三共用墊，設置於該第一基板上，且位於該些畫素結構的該第一側，其中該第三共用墊及該些第二共用墊在該第一方向上依序排列且於結構上彼此分離，該第三共用墊對應該第1~n個第二閘極線群的該第1個第二閘極線群設置，而該第三共用墊的電位大於對應該些第二共用墊的電位；以及一第三轉接元件，分別設置於該第三共用墊上，且電性連接至該第三共用墊及該共用電極。 The display device of claim 11, further comprising: a third common pad disposed on the first substrate and located on the first side of the pixel structures, wherein the third common pad and The second common pads are sequentially arranged in the first direction and are structurally separated from each other, and the third common pad corresponds to the first second gate line of the 1st to nth second gate line groups group arrangement, and the potential of the third shared pads is greater than the potential of the corresponding second shared pads; and a third transfer element, respectively disposed on the third shared pads, and electrically connected to the third shared pads and the common electrode. 如申請專利範圍第9項所述的顯示裝置，更包括：多條第二共用線，設置於該第一基板上，該些第二閘極線及該些第二共用線在該第一方向上排列，其中該些第二共用線的每一者設置於該些畫素行的相鄰兩者之間；一第一周邊走線，設置於該第一基板上且位於該些畫素結構的一第一側，其中該些第一共用線電性連接至該第一周邊走線；以及 一第二周邊走線，設置於該第一基板上且位於該些畫素結構的一第二側，其中每一該第二共用線的兩端分別電性連接至該第一周邊走線及該第二周邊走線。 The display device according to claim 9, further comprising: a plurality of second common lines disposed on the first substrate, the second gate lines and the second common lines on the first side Arranged upward, wherein each of the second common lines is disposed between two adjacent ones of the pixel rows; a first peripheral line is disposed on the first substrate and located at the edge of the pixel structures a first side, wherein the first common lines are electrically connected to the first peripheral line; and A second peripheral wiring is disposed on the first substrate and located on a second side of the pixel structures, wherein two ends of each second common wiring are electrically connected to the first peripheral wiring and the The second peripheral trace. 如申請專利範圍第9項所述的顯示裝置，其中該些第一閘極線包括奇數條第一閘極線及偶數條第一閘極線，該奇數條第一閘極線包括第(1+2．K)條第一閘極線，K=0,1,…,p，p為大於或等於2的正整數，該偶數條第一閘極線包括第2L條第一閘極線，L=1,2,…,q，q為大於或等於3的正整數；該些第二閘極線包括在該第一方向上依序排列的第1~(p+1)條第二閘極線及第(p+2)~(p+q+1)條第二閘極線；該第1~(p+1)條第二閘極線電性連接至該第(1+2．K)條第一閘極線，且該第(p+2)~(p+q+1)條第二閘極線電性連接至該第2L條第一閘極線。 The display device according to claim 9, wherein the first gate lines include odd-numbered first gate lines and even-numbered first gate lines, and the odd-numbered first gate lines include (1 +2.K) first gate lines, K=0,1,...,p, p is a positive integer greater than or equal to 2, the even-numbered first gate lines include the 2L first gate lines, L=1, 2, . The pole line and the (p+2)~(p+q+1) second gate lines; the 1st~(p+1) second gate lines are electrically connected to the (1+2. K) first gate lines, and the (p+2)-(p+q+1)th second gate lines are electrically connected to the 2Lth first gate lines. 如申請專利範圍第14項所述的顯示裝置，其中該第1~(p+1)條第二閘極線與該第(1+2．K)條第一閘極線的多個連接點以及該第(p+2)~(p+q+1)條第二閘極線與該第2L條的多個連接點大致上沿互相平行的多條斜線分佈。 The display device according to claim 14, wherein a plurality of connection points between the 1st to (p+1) second gate lines and the (1+2.K)th first gate line And the connection points of the (p+2)-(p+q+1)th second gate lines and the 2Lth line are generally distributed along a plurality of diagonal lines parallel to each other. 如申請專利範圍第14項所述的顯示裝置，其中該第1~(p+1)條第二閘極線與該第(1+2．K)條第一閘極線的多個連接點以及該第(p+2)~(p+q+1)條第二閘極線與該第2L條的多個連接點大致上呈V字型分佈。 The display device according to claim 14, wherein a plurality of connection points between the 1st to (p+1) second gate lines and the (1+2.K)th first gate line And the connection points of the (p+2)-(p+q+1)th second gate lines and the 2Lth line are generally V-shaped.
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