TWI764388B - Integrated chip and method of forming the same - Google Patents

Integrated chip and method of forming the same

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Publication number
TWI764388B
TWI764388B TW109141132A TW109141132A TWI764388B TW I764388 B TWI764388 B TW I764388B TW 109141132 A TW109141132 A TW 109141132A TW 109141132 A TW109141132 A TW 109141132A TW I764388 B TWI764388 B TW I764388B
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Taiwan
Prior art keywords
interconnect
interlayer dielectric
barrier layer
layer
liner
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TW109141132A
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Chinese (zh)
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TW202141690A (en
Inventor
薛琇文
陳啟平
黃柏翔
曾雅晴
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台灣積體電路製造股份有限公司
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Priority claimed from US17/032,407 external-priority patent/US11694926B2/en
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202141690A publication Critical patent/TW202141690A/en
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Publication of TWI764388B publication Critical patent/TWI764388B/en

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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
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    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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    • H01L23/5329—Insulating materials
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Abstract

The present disclosure relates an integrated chip, The integrated chip includes a first interconnect disposed within an inter-level dielectric (ILD) structure over a substrate, A barrier layer is disposed along sidewalls of the ILD structure, The barrier layer has sidewalls defining an opening over the first interconnect, A second interconnect is disposed on the barrier layer, The second interconnect extends through the opening in the barrier layer and to the first interconnect.

Description

積體電路晶片及其形成方法 Integrated circuit chip and method of forming the same

本揭示案是關於一種積體電路晶片及其形成方法。 The present disclosure relates to an integrated circuit chip and a method for forming the same.

現代積體電路晶片包括形成在半導體基材(例如，矽基材)上之數百萬或數十億個半導體元件。半導體元件是藉由互連接電性地耦合在一起。互連接包括互連接線路及設置在半導體基材上之介電結構之中之互連接通孔。藉由使用互連接將半導體元件電性地耦合在一起，半導體元件能進行致能積體電路晶片的操作之邏輯性功能。 Modern integrated circuit chips include millions or billions of semiconductor elements formed on a semiconductor substrate (eg, a silicon substrate). The semiconductor elements are electrically coupled together by interconnections. The interconnection includes interconnection lines and interconnection vias disposed in the dielectric structure on the semiconductor substrate. By electrically coupling the semiconductor elements together using interconnects, the semiconductor elements can perform the logical function of enabling the operation of the integrated circuit chip.

在一些實施例中，一種積體電路晶片包含設置在基材上之層間介電結構之中的第一互連接、沿著層間介電結構的側壁設置並具有在第一互連接之上界定開口之側壁阻擋層，及設置在阻擋層上的第二互連接，其中第二互連接 延伸通過阻擋層中之開口延伸並到達第一互連接。 In some embodiments, an integrated circuit chip includes a first interconnect disposed in an interlayer dielectric structure on a substrate, disposed along sidewalls of the interlayer dielectric structure, and having an opening defining an opening over the first interconnect a sidewall barrier layer, and a second interconnection disposed on the barrier layer, wherein the second interconnection The extension extends through the opening in the barrier layer and reaches the first interconnect.

在一些實施例中，一種積體電路晶片包含設置在基材上之第一層間介電層之中的第一互連接、設置在第一層間介電層之上的第二層間介電層、沿第二層間介電層的側壁及沿著第一層間介電層的上表面延伸之阻擋層，及設置在阻擋層上並圍繞導電填充的第一襯裡。第一襯裡延伸通過阻擋層到達第一互連接。 In some embodiments, an integrated circuit chip includes a first interconnect disposed in a first interlayer dielectric layer on a substrate, a second interlayer dielectric disposed over the first interlayer dielectric layer layer, a barrier layer extending along sidewalls of the second interlayer dielectric layer and along the upper surface of the first interlayer dielectric layer, and a first liner disposed on the barrier layer and surrounding a conductive fill. The first liner extends through the barrier layer to the first interconnect.

在一些實施例中，本揭露內容關於形成積體電路晶片的方法。此方法包含：在基材之上之第一層間介電層之中形成第一互連接；在第一層間介電層之上形成第二層間介電層；圖案化第二層間介電層以形成界定互連接開口之側壁，互連接開口暴露第一互連接的上表面；將阻隔層在形成至第一互連接的上表面上，其中阻隔層與第二層間介電層的側壁橫向地分離；在互連接開口之中形成阻擋層；去除阻隔層以暴露第一互連接的上表面；及在互連接開口之中形成第二互連接。 In some embodiments, the present disclosure pertains to methods of forming integrated circuit chips. The method includes: forming a first interconnect in a first interlayer dielectric layer over a substrate; forming a second interlayer dielectric layer over the first interlayer dielectric layer; patterning the second interlayer dielectric layer to form sidewalls that define interconnection openings, the interconnection openings exposing the upper surface of the first interconnection; a barrier layer is formed on the upper surface of the first interconnection, wherein the barrier layer and the sidewalls of the second interlayer dielectric layer are lateral forming a barrier layer in the interconnect opening; removing the barrier layer to expose the upper surface of the first interconnect; and forming a second interconnect in the interconnect opening.

100~400,406:積體電路晶片 100~400,406: Integrated circuit chip

102:基材 102: Substrate

104:層間介電結構 104: Interlayer Dielectric Structure

105:下互連接 105: Down Interconnect

106:第一互連接 106: First Interconnect

108:第二互連接 108: Second Interconnect

108L:下表面 108L: lower surface

108P:突起 108P: Protrusion

110,1202:阻擋層 110, 1202: Barrier

110h:水平延伸區段 110h: Horizontal extension section

110v:垂直延伸區段 110v: Vertical extension section

202:電晶體元件 202: Transistor Components

204a:下層間介電層 204a: lower interlayer dielectric layer

204b:第一層間介電層 204b: first interlayer dielectric layer

204c:第二層間介電層 204c: Second interlayer dielectric layer

204d:上層間介電層 204d: upper interlayer dielectric layer

206:蝕刻停止層 206: Etch Stop Layer

206a:第一蝕刻停止層 206a: first etch stop layer

208:第一襯裡 208: First lining

210:第二襯裡 210: Second lining

212:導電填充 212: Conductive Fill

214:覆蓋層 214: Overlay

216:平面視圖 216: Plan View

301:接縫 301: Seams

302:凹陷區 302: Depressed area

304:第一上表面 304: First upper surface

306:第二上表面 306: Second upper surface

308:第一距離 308: First Distance

310:第二距離 310: Second distance

402:下阻擋層 402: Lower barrier layer

404:導電芯 404: Conductive core

408:界面 408: interface

502:上蝕刻停止層 502: upper etch stop layer

502a:第一材料 502a: First Material

502b:第二材料 502b: Second material

502c:第三材料 502c: Tertiary Materials

504:圍繞上互連接 504: Interconnect around the top

600-2100:截面視圖 600-2100: Sectional View

801:第一遮罩結構 801: First mask structure

802:介電遮罩層 802: Dielectric Mask Layer

804:硬質遮罩 804: Hardmask

806:中間互連接開口 806: Intermediate Interconnect Opening

808:第一蝕刻劑 808: First Etchant

1002:第二互連接開口 1002: Second interconnect opening

1004:第二蝕刻劑 1004: Second Etchant

1102:阻隔層 1102: Barrier Layer

1302:開口 1302: Opening

1402:第一襯裡層 1402: First lining layer

1502:第二襯裡層 1502: Second lining layer

1602:第三導電材料 1602: Third Conductive Material

1702:線 1702: Line

2002:上互連接開口 2002: Upper interconnect opening

2004:第三蝕刻劑 2004: Third Etchant

2006:第二遮罩結構 2006: Second mask structure

2200:方法 2200: Methods

2202~2226:動作 2202~2226: Action

A-A’:橫截面線 A-A': cross section line

θ,Φ:角度 θ, Φ: angle

當與隨附圖示一起閱讀時，可由後文實施方式最佳地理解本揭露內容的態樣。注意到根據此產業中之標準實務，各種特徵並未按比例繪製。實際上，為論述的清楚性，可任意增加或減少各種特徵的尺寸。 Aspects of the present disclosure are best understood from the following description when read in conjunction with the accompanying drawings. Note that in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

圖1例示具有在無阻擋界面處相遇之生產線後端(BEOL)互連接之積體電路晶片的一些實施例的截面視圖。 1 illustrates a cross-sectional view of some embodiments of integrated circuit wafers with back-of-line (BEOL) interconnects that meet at an unobstructed interface.

圖2A至2B例示具有在無阻擋界面處相遇之互連接之積體電路晶片的一些額外實施例。 2A-2B illustrate some additional embodiments of integrated circuit chips with interconnects that meet at unobstructed interfaces.

圖3例示具有在無阻擋界面處相遇之互連接之積體電路晶片的一些替代實施例的截面視圖。 3 illustrates a cross-sectional view of some alternative embodiments of integrated circuit chips with interconnects that meet at unobstructed interfaces.

圖4A至4B例示具有在無阻擋界面處相遇之互連接之積體電路晶片的一些替代實施例的截面視圖。 4A-4B illustrate cross-sectional views of some alternative embodiments of integrated circuit chips with interconnects that meet at unobstructed interfaces.

圖5例示具有在無阻擋界面處相遇之互連接之積體電路晶片的一些替代實施例的截面視圖。 5 illustrates a cross-sectional view of some alternative embodiments of integrated circuit chips with interconnects that meet at unobstructed interfaces.

圖6至21例示形成具有在無阻擋界面處相遇之互連接之積體電路晶片的方法的一些實施例的截面視圖。 6-21 illustrate cross-sectional views of some embodiments of a method of forming an integrated circuit die with interconnects that meet at an unobstructed interface.

圖22例示形成具有在無阻擋界面處相遇之互連接之積體電路晶片的方法的一些實施例的流程圖。 22 illustrates a flow diagram of some embodiments of a method of forming an integrated circuit die with interconnects that meet at an unobstructed interface.

後文揭露內容提供用於實行所提供的標的的不同特徵的許多不同的實施例或範例。後文描述組件及佈置之特定範例以簡化本揭露內容。當然，此等僅為範例且未意圖具限制性。舉例而言，在後文的描述中，在第二特徵之上或上之第一特徵的形成可包含以直接接觸方式形成第一特徵及第二特徵的實施例，且亦可包含在第一特徵與第二特徵間形成額外特徵，使得第一特徵及第二特徵可不直接接觸的實施例。此外，在各種範例中，本揭露內容可能重複元件符號及/或字母。此重複係出於簡單及清楚的目的，且重複本身並不規範所論述的各種實施例及/或配置間之 關係。 The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also be included in the first feature. Embodiments where an additional feature is formed between the feature and the second feature so that the first feature and the second feature may not be in direct contact. Furthermore, in various instances, the present disclosure may repeat reference numerals and/or letters. This repetition is for the purpose of simplicity and clarity, and the repetition itself does not standardize the differences between the various embodiments and/or configurations discussed. relation.

進一步，為便於描述，本文中可使用諸如「在...之下」、「在...下方」、「較低」、「在...上方」、「較高」、及類似者的空間相對術語，以描述圖示中所例示之一個元件或特徵與另一元件(等)或特徵(等)的關係。除圖示中所描繪之定向之外，空間相對術語亦意圖涵蓋元件在使用或操作中之不同定向。設備能以其他方式定向(旋轉90度或以其他定向)，且本文中使用之空間相對描述語可同樣以相應的方式解釋。 Further, for ease of description, terms such as "below", "below", "lower", "above", "higher", and the like may be used herein. Spatially relative term used to describe the relationship of one element or feature to another element (etc.) or feature (etc.) illustrated in the figures. In addition to the orientation depicted in the figures, spatially relative terms are also intended to encompass different orientations of elements in use or operation. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted in a corresponding manner.

積體電路晶片包括具有設置在基材之中之元件之生產線前端(front-end-of-the-line，FEOL)及具有設置在基材之上之層間介電結構之中之互連接(例如，互連接線路、互連接通孔等)之生產線後端(back-end-of-the-line，BEOL)。將互連接電性地耦合至電晶體元件。隨著時間的流逝，電晶體元件間之大小及距離已經減小。為了能連接至較小的電晶體元件，互連接的大小亦已經減小。 An integrated circuit chip includes a front-end-of-the-line (FEOL) with components disposed in a substrate and interconnects with interlayer dielectric structures disposed over the substrate (eg, , the back-end-of-the-line (BEOL) of the production line for interconnecting lines, interconnecting vias, etc. The interconnect is electrically coupled to the transistor element. Over time, the size and distance between transistor elements have decreased. The size of the interconnects has also been reduced in order to be able to connect to smaller transistor elements.

隨著互連接的大小變得更小，毗鄰的互連接間之距離亦變得更小。毗鄰的互連接間之較小的距離造成毗鄰的互連接間之電容增加。此外，隨著互連接的大小減小，亦使得電流變得更加難以移動通過互連接，且互連接的電阻增加。由於電阻及電容(RC)的乘積與積體電路晶片的速度成反比，因此互連接可能成為積體電路晶片速度的瓶頸。 As the size of the interconnects becomes smaller, the distance between adjacent interconnects also becomes smaller. Smaller distances between adjacent interconnects result in increased capacitance between adjacent interconnects. Furthermore, as the size of the interconnect decreases, it also becomes more difficult for current to move through the interconnect, and the resistance of the interconnect increases. Since the product of resistance and capacitance (RC) is inversely proportional to the speed of the integrated circuit die, the interconnection can become the bottleneck of the speed of the integrated circuit die.

為了提供具有低電阻的互連接，可使用低電阻金屬。 舉例而言，由於銅具有低電阻且易於操作使用，因此通常使用銅形成互連接線。然而，隨著時間的流逝，一些來自此類金屬之原子可能擴散至周圍的層間介電結構中。層間介電結構之中之金屬原子會造成通過層間介電結構的導電路徑，並導致毗鄰的互連接間之電性短路。為了防止金屬原子至周圍的層間介電結構中之擴散，可在金屬周圍形成阻擋層。已認知到，阻擋層可具有比金屬高得多的電阻，並因此可負面地影響互連接結構的電阻並導致積體電路晶片的性能下降。 To provide interconnects with low resistance, low resistance metals can be used. For example, copper is commonly used to form interconnects because of its low resistance and ease of use. However, over time, some atoms from such metals may diffuse into the surrounding interlayer dielectric structure. The metal atoms in the ILD structure can create conductive paths through the ILD structure and cause electrical shorts between adjacent interconnects. To prevent diffusion of metal atoms into the surrounding interlayer dielectric structure, a barrier layer may be formed around the metal. It has been recognized that barrier layers can have a much higher resistance than metals, and thus can negatively affect the resistance of the interconnect structure and result in reduced performance of the integrated circuit chip.

在一些實施例中，本揭露內容關於一種具有互連接結構之積體電路晶片，此互連接結構不具有將互連接與下層的互連接垂直分離之阻擋層。在一些實施例中，積體電路晶片可包括設置在基材之上之層間介電結構之中之第一互連接及設置在第一互連接之上之層間介電結構之中之第二互連接。阻擋層橫向地圍繞第二互連接並將第二互連接與層間介電結構分離。阻擋層具有側壁，此等側壁界定直接在第一互連接正上方之開口。第二互連接垂直地延伸通過藉由阻擋層的側壁所界定之開口以接觸第一互連接的上表面。由於第二互連接延伸通過阻擋層中之開口，因此阻擋層並未將第二互連接與第一互連接分離，且阻擋層並未顯著增加互連接結構的電阻。 In some embodiments, the present disclosure relates to an integrated circuit chip having an interconnect structure without a barrier layer that vertically separates the interconnect from underlying interconnects. In some embodiments, the integrated circuit chip may include a first interconnect in the interlayer dielectric structure disposed over the substrate and a second interconnect in the interlayer dielectric structure disposed over the first interconnect connect. The barrier layer laterally surrounds the second interconnect and separates the second interconnect from the interlayer dielectric structure. The barrier layer has sidewalls that define openings directly above the first interconnect. The second interconnect extends vertically through the opening defined by the sidewall of the barrier layer to contact the upper surface of the first interconnect. Because the second interconnect extends through the opening in the barrier layer, the barrier layer does not separate the second interconnect from the first interconnect, and the barrier layer does not significantly increase the resistance of the interconnect structure.

圖1例示具有在無阻擋界面處相遇之生產線後端(BEOL)互連接之積體電路晶片100的一些實施例的截面視圖。 1 illustrates a cross-sectional view of some embodiments of an integrated circuit die 100 with back-of-line (BEOL) interconnects that meet at a barrier-free interface.

積體電路晶片100包括設置在基材102之上之層間介電結構104。層間介電結構104圍繞複數個互連接106至108。複數個互連接106至108包括第一互連接106及在第一互連接106之上之第二互連接108。在一些實施例中，複數個互連接106至108可包括生產線中端(middle-end-of-the-line，MEOL)互連接、導電觸點、互連接線路、及/或互連接通孔。舉例而言，在一些實施例中，第一互連接106可包括互連接通孔，而第二互連接108可包括互連接線路。 The integrated circuit chip 100 includes an interlayer dielectric structure 104 disposed over the substrate 102 . The interlayer dielectric structure 104 surrounds the plurality of interconnects 106-108. The plurality of interconnects 106 - 108 include a first interconnect 106 and a second interconnect 108 over the first interconnect 106 . In some embodiments, the plurality of interconnects 106-108 may include middle-end-of-the-line (MEOL) interconnects, conductive contacts, interconnect lines, and/or interconnect vias . For example, in some embodiments, the first interconnect 106 may include interconnect vias and the second interconnect 108 may include interconnect lines.

阻擋層110沿著第二互連接108的側壁延伸，並將第二互連接108與層間介電結構104橫向地分離。將阻擋層110配置成防止原子從第二互連接108至層間介電結構104中之擴散。在一些實施例中，阻擋層110可進一步沿著第二互連接108的下表面延伸，並將第二互連接108與層間介電結構104垂直地分離。阻擋層110包括側壁，此等側壁界定延伸通過阻擋層110之開口。 The barrier layer 110 extends along the sidewalls of the second interconnect 108 and laterally separates the second interconnect 108 from the interlayer dielectric structure 104 . The barrier layer 110 is configured to prevent diffusion of atoms from the second interconnect 108 into the interlayer dielectric structure 104 . In some embodiments, the barrier layer 110 may further extend along the lower surface of the second interconnection 108 and vertically separate the second interconnection 108 from the interlayer dielectric structure 104 . The barrier layer 110 includes sidewalls that define openings extending through the barrier layer 110 .

第二互連接108垂直延伸通過阻擋層110中之開口，以物理地接觸第一互連接106的上表面。在一些實施例中，第二互連接108包括抵靠在阻擋層110上之下表面108L及從下表面108L向外延伸並通過阻擋層110之突起108P。阻擋層110可由具有比第二互連接108的第二導電材料更低的導電率(例如，較高的電阻率)的材料所構成。然而，由於第二互連接108垂直地延伸通過阻擋層110，因此阻擋層110並未將第一互連接106與第二互連接108 分離。由於阻擋層110並未將第一互連接106與第二互連接108分離，因此減少第一互連接106與第二互連接108間之電阻。舉例而言，相對於藉由阻擋層所分離之互連接，第一互連接106與第二互連接108間之電阻可減少大約20%或更多。減少第一互連接106與第二互連接108間之電阻可改善積體電路晶片100的性能(例如，環形振盪器可實現大約1.5%或更高在速度上的提高)。 The second interconnect 108 extends vertically through the opening in the barrier layer 110 to physically contact the upper surface of the first interconnect 106 . In some embodiments, the second interconnect 108 includes a protrusion 108P abutting the upper and lower surfaces 108L of the barrier layer 110 and extending outwardly from the lower surface 108L and through the barrier layer 110 . The barrier layer 110 may be composed of a material having a lower conductivity (eg, higher resistivity) than the second conductive material of the second interconnect 108 . However, since the second interconnect 108 extends vertically through the barrier layer 110, the barrier layer 110 does not connect the first interconnect 106 to the second interconnect 108 separation. Since the barrier layer 110 does not separate the first interconnection 106 and the second interconnection 108, the resistance between the first interconnection 106 and the second interconnection 108 is reduced. For example, the resistance between the first interconnect 106 and the second interconnect 108 may be reduced by about 20% or more relative to interconnects separated by a barrier layer. Reducing the resistance between the first interconnect 106 and the second interconnect 108 can improve the performance of the integrated circuit die 100 (eg, a ring oscillator can achieve an increase in speed of about 1.5% or more).

圖2A例示具有在無阻擋界面處相遇之互連接之積體電路晶片200的一些額外實施例的截面視圖。 2A illustrates a cross-sectional view of some additional embodiments of an integrated circuit die 200 with interconnects that meet at unobstructed interfaces.

積體電路晶片200包括設置在基材102之上之層間介電結構104之中之複數個互連接105至108。在一些實施例中，層間介電結構104包括複數個堆疊的層間介電層204a至204c。複數個堆疊的層間介電層204a至204c包括下層間介電層204a、在下層間介電層204a之上之第一層間介電層204b、及在第一層間介電層204b之上之第二層間介電層204c。在一些實施例中，複數個堆疊的層間介電層204a至204c可包括一種或更多種的二氧化矽、氮化矽、碳摻雜的二氧化矽、氮氧化矽、硼矽酸鹽玻璃(borosilicate glass，BSG)、磷矽酸鹽玻璃(phosphorus silicate glass，PSG)、硼磷矽酸鹽玻璃(borophosphosilicate glass，BPSG)、氟矽玻璃(fluorosilicate glass，FSG)、無摻雜矽酸鹽玻璃(undoped silicate glass，USG)、多孔介電材料、或類似物。在一些實施例中，可藉由蝕刻停止層206分離複 數個堆疊的層間介電層204a至204c的毗鄰的層。在各種實施例中，蝕刻停止層206可包括碳化物(例如，碳化矽、碳氧化矽、或類似物)、氮化物(例如，氮化矽、氮氧化矽、或類似物)、或類似物。 The integrated circuit chip 200 includes a plurality of interconnects 105 - 108 disposed in the interlayer dielectric structure 104 over the substrate 102 . In some embodiments, the interlayer dielectric structure 104 includes a plurality of stacked interlayer dielectric layers 204a-204c. The plurality of stacked interlayer dielectric layers 204a to 204c include a lower interlayer dielectric layer 204a, a first interlayer dielectric layer 204b above the lower interlayer dielectric layer 204a, and a layer above the first interlayer dielectric layer 204b The second interlayer dielectric layer 204c. In some embodiments, the plurality of stacked interlayer dielectric layers 204a-204c may include one or more of silicon dioxide, silicon nitride, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (borosilicate glass, BSG), phosphorous silicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (undoped silicate glass, USG), porous dielectric material, or the like. In some embodiments, the complex can be separated by the etch stop layer 206 Adjacent layers of several stacked interlayer dielectric layers 204a to 204c. In various embodiments, the etch stop layer 206 may include carbide (eg, silicon carbide, silicon oxycarbide, or the like), nitride (eg, silicon nitride, silicon oxynitride, or the like), or the like .

複數個堆疊的層間介電層204a至204c圍繞複數個互連接105至108。在一些實施例中，複數個互連接105至108包括下互連接105、在下互連接105之上之第一互連接106、及在第一互連接106之上之第二互連接108。在一些實施例中，複數個互連接105至108可包括一個或更多個的MEOL互連接、導電觸點、互連接線路、及/或互連接通孔。在一些實施例中，下層間介電層204a圍繞下互連接105、第一層間介電層204b圍繞第一互連接106、且第二層間介電層204c圍繞第二互連接108。在一些實施例中，將複數個互連接105至108耦合至佈置在基材102之中之電晶體元件202。在一些實施例中，電晶體元件202可包括金屬氧化物半導體場效應電晶體元件(metal oxide semiconductor field-effect transistor，MOSFET)、雙極性接面型電晶體(bipolar junction transistor，BJT)、接面型閘極場效應電晶體(junction gate field-effect transistor，JFET)、或類似物。 A plurality of stacked interlayer dielectric layers 204a-204c surround the plurality of interconnects 105-108. In some embodiments, the plurality of interconnects 105 - 108 includes a lower interconnect 105 , a first interconnect 106 over the lower interconnect 105 , and a second interconnect 108 over the first interconnect 106 . In some embodiments, the plurality of interconnects 105-108 may include one or more MEOL interconnects, conductive contacts, interconnect lines, and/or interconnect vias. In some embodiments, the lower interlayer dielectric layer 204a surrounds the lower interconnection 105 , the first interlayer dielectric layer 204b surrounds the first interconnection 106 , and the second interlayer dielectric layer 204c surrounds the second interconnection 108 . In some embodiments, a plurality of interconnects 105 - 108 are coupled to transistor elements 202 disposed within substrate 102 . In some embodiments, the transistor element 202 may include a metal oxide semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), a junction junction gate field-effect transistor (JFET), or the like.

在一些實施例中，第一互連接106可包括及/或為第一導電材料。在一些實施例中，第一導電材料可為至周圍的第一層間介電層204b中具有低擴散率之材料(例如， 至周圍的第一層間介電層204b中之擴散率小於銅的擴散率)。在一些此等實施例中，第一導電材料並非藉由阻擋層與層間介電結構104分離，因而第一互連接106直接接觸第一層間介電層204b。在一些此等實施例中，第一導電材料可包括或可為鎢、釕、鈷、或類似物。在其他實施例中(未圖示)，第一導電材料可藉由阻擋層與層間介電結構104分離。 In some embodiments, the first interconnect 106 may include and/or be a first conductive material. In some embodiments, the first conductive material may be a material with low diffusivity into the surrounding first interlayer dielectric layer 204b (eg, The diffusivity into the surrounding first interlayer dielectric layer 204b is lower than that of copper). In some of these embodiments, the first conductive material is not separated from the ILD structure 104 by a barrier layer, and thus the first interconnect 106 directly contacts the first ILD layer 204b. In some such embodiments, the first conductive material may include or may be tungsten, ruthenium, cobalt, or the like. In other embodiments (not shown), the first conductive material may be separated from the interlayer dielectric structure 104 by a barrier layer.

第二互連接108是藉由阻擋層110與第二層間介電層204c分離。阻擋層110沿著第二互連接108的側壁延伸並具有在第二互連接108正下方之側壁。阻擋層110的側壁在第一互連接106正上方之位置處界定通過阻擋層110的下表面延伸之開口。第二互連接108延伸通過開口以直接接觸第一互連接106的上表面。在一些實施例中，第二互連接108在阻擋層110的側壁間連續地延伸，因而第二互連接完全地填充開口。在一些實施例中，界定開口之阻擋層110的側壁以一距離分離，此距離大致地等於第一互連接106的頂部表面的寬度的距離。在一些此等實施例中，阻擋層110的底部角落可沿著垂直於基材102的上表面之假想線與第一互連接106的頂部角落對準。 The second interconnect 108 is separated from the second interlayer dielectric layer 204c by the barrier layer 110 . The barrier layer 110 extends along the sidewalls of the second interconnection 108 and has sidewalls directly below the second interconnection 108 . The sidewalls of barrier layer 110 define openings extending through the lower surface of barrier layer 110 at locations directly above first interconnect 106 . The second interconnect 108 extends through the opening to directly contact the upper surface of the first interconnect 106 . In some embodiments, the second interconnect 108 extends continuously between the sidewalls of the barrier layer 110 such that the second interconnect completely fills the opening. In some embodiments, the sidewalls of the barrier layer 110 that define the openings are separated by a distance that is approximately equal to the width of the top surface of the first interconnect 106 . In some such embodiments, the bottom corners of the barrier layer 110 may be aligned with the top corners of the first interconnect 106 along an imaginary line perpendicular to the upper surface of the substrate 102 .

圖2B例示積體電路晶片200的平面視圖216的一些實施例。如圖2B的平面視圖216(沿著圖2A的橫截面線A-A'截取)所圖示，阻擋層110圍繞第二互連接108以封閉環延伸。在一些實施例中，阻擋層110包括圍繞第二互連接108延伸之環形狀。 FIG. 2B illustrates some embodiments of a plan view 216 of the integrated circuit die 200 . As illustrated in plan view 216 of FIG. 2B (taken along cross-sectional line AA' of FIG. 2A ), barrier layer 110 extends in a closed loop around second interconnect 108 . In some embodiments, the barrier layer 110 includes a ring shape extending around the second interconnect 108 .

在一些實施例中，阻擋層110包括沿著第二層間介電層204c的側壁設置之垂直延伸區段110v及從垂直延伸區段110v的側壁朝向第二互連接108向外突出之水平延伸區段110h。在一些實施例中，垂直延伸區段110v可相對於水平延伸區段110h的上表面以大於90°之角度成角度。在各種實施例中，阻擋層110可包括鉭、氮化鉭、鈦、氮化鈦、或類似物。 In some embodiments, the barrier layer 110 includes a vertically extending section 110v disposed along the sidewall of the second interlayer dielectric layer 204c and a horizontally extending section projecting outwardly from the sidewall of the vertically extending section 110v toward the second interconnect 108 Segment 110h. In some embodiments, the vertically extending section 110v may be angled at an angle greater than 90° relative to the upper surface of the horizontally extending section 110h. In various embodiments, the barrier layer 110 may include tantalum, tantalum nitride, titanium, titanium nitride, or the like.

在一些實施例中，第二互連接108包括圍繞導電填充212之第一襯裡208。將第一襯裡208設置在阻擋層110上並垂直延地伸通過阻擋層110以接觸第一互連接106的上表面。在一些實施例中，第一襯裡208包括抵靠在阻擋層110上之下表面108L及從下表面108L向外沿伸並通過阻擋層110之突起108P。在一些實施例中，第一襯裡208完全地填充延伸通過阻擋層110之開口，因而導電填充212的最底部表面在阻擋層110的水平延伸區段110h的頂部表面上方。在一些實施例中，第一襯裡208可包括具有比阻擋層110更低的電阻率的材料。在一些實施例中，第一襯裡208可包括或為與第一互連接106相同的材料。舉例而言，在一些實施例中，第一襯裡208可包括釕、鈷、鎢、或類似物。在一些如此的實施例中，在第一互連接106與第一襯裡208間可存在接縫301。在其他實施例中，第一襯裡208可包括或為與第一互連接106不同的材料。在一些實施例中，導電填充212可包括銅、鋁、或類似物。 In some embodiments, the second interconnect 108 includes the first liner 208 surrounding the conductive fill 212 . The first liner 208 is disposed on the barrier layer 110 and extends vertically through the barrier layer 110 to contact the upper surface of the first interconnect 106 . In some embodiments, the first liner 208 includes a protrusion 108P that abuts the upper and lower surfaces 108L of the barrier layer 110 and extends outwardly from the lower surface 108L through the barrier layer 110 . In some embodiments, the first liner 208 completely fills the openings extending through the barrier layer 110 such that the bottommost surface of the conductive fill 212 is above the top surface of the horizontally extending section 110h of the barrier layer 110 . In some embodiments, the first liner 208 may include a material having a lower resistivity than the barrier layer 110 . In some embodiments, the first liner 208 may comprise or be the same material as the first interconnect 106 . For example, in some embodiments, the first liner 208 may include ruthenium, cobalt, tungsten, or the like. In some such embodiments, there may be a seam 301 between the first interconnect 106 and the first liner 208 . In other embodiments, the first liner 208 may comprise or be a different material than the first interconnect 106 . In some embodiments, the conductive fill 212 may include copper, aluminum, or the like.

在一些實施例中，可將第二襯裡210設置在第一襯裡208與導電填充212間。第二襯裡210橫向地及垂直地將第一襯裡208與導電填充212分離。在一些實施例中，第二襯裡210可包括及/或可為鈷、釕、鎢、或類似物。在一些實施例中，阻擋層110、第一襯裡208、第二襯裡210、及導電填充212垂直地延伸至第二層間介電層204c的上表面。在一些實施例中，第二襯裡210可包括或為與第一襯裡208不同的材料。 In some embodiments, the second liner 210 may be disposed between the first liner 208 and the conductive fill 212 . The second liner 210 laterally and vertically separates the first liner 208 from the conductive fill 212 . In some embodiments, the second liner 210 may include and/or may be cobalt, ruthenium, tungsten, or the like. In some embodiments, the barrier layer 110, the first liner 208, the second liner 210, and the conductive fill 212 extend vertically to the upper surface of the second interlayer dielectric layer 204c. In some embodiments, the second liner 210 may comprise or be a different material than the first liner 208 .

將覆蓋層214設置在第二互連接108上。在一些實施例中，覆蓋層214從導電填充212正上方延伸至第一襯裡208及/或第二襯裡210正上方。在一些實施例中，阻擋層110在覆蓋層214的橫向地外側。覆蓋層214可包括及/或可為鈷、釕、鎢、或類似物。在一些實施例中，第二襯裡210及覆蓋層214可包括及/或為相同的材料。在其他實施例中，第二襯裡210及覆蓋層214可包括或為不同的材料。在一些實施例中，覆蓋層214可包括相對於覆蓋層214的下表面以通過覆蓋層214所量測的角度成角度θ之側壁。在一些實施例中，角度θ可大於或等於大約90°。在一些實施例中，角度θ可大於90°。 A cover layer 214 is disposed over the second interconnect 108 . In some embodiments, the capping layer 214 extends from just above the conductive fill 212 to just above the first liner 208 and/or the second liner 210 . In some embodiments, barrier layer 110 is laterally outside of capping layer 214 . The capping layer 214 may include and/or may be cobalt, ruthenium, tungsten, or the like. In some embodiments, the second liner 210 and the cover layer 214 may comprise and/or be the same material. In other embodiments, the second liner 210 and cover layer 214 may comprise or be different materials. In some embodiments, the capping layer 214 may include sidewalls at an angle θ relative to the lower surface of the capping layer 214 at an angle measured through the capping layer 214 . In some embodiments, the angle θ may be greater than or equal to about 90°. In some embodiments, the angle θ may be greater than 90°.

圖3例示具有在無阻擋界面處相遇之互連接之積體電路晶片300的一些替代實施例的截面視圖。 3 illustrates a cross-sectional view of some alternative embodiments of an integrated circuit die 300 with interconnects that meet at unobstructed interfaces.

積體電路晶片300包括被設置在基材102之上之層間介電結構104。層間介電結構104圍繞被設置在下層間介電層204a之中之下互連接105、被設置在第一層間 介電層204b之中之第一互連接106、及設置在第二層間介電層204c之中之第二互連接108。 The integrated circuit die 300 includes an interlayer dielectric structure 104 disposed over the substrate 102 . The interlayer dielectric structure 104 surrounds the lower interconnect 105 disposed in the lower interlayer dielectric layer 204a, disposed in the first interlayer The first interconnect 106 in the dielectric layer 204b, and the second interconnect 108 disposed in the second interlayer dielectric layer 204c.

藉由沿著第二互連接108的相對側佈置的阻擋層110將第二互連接108與第二層間介電層204c分離。阻擋層110包括被設置在第二互連接108正下方的一個或更多個側壁。在一些實施例中，阻擋層110的一個或更多個側壁可包括相對於第一層間介電層204b的上表面以通過阻擋層110所量測的角度成角度Φ之側壁。在一些實施例中，角度Φ可大於或等於大約90°。在一些實施例中，角度Φ可大於90°。 The second interconnect 108 is separated from the second interlayer dielectric layer 204c by a barrier layer 110 disposed along opposite sides of the second interconnect 108 . The barrier layer 110 includes one or more sidewalls disposed directly below the second interconnect 108 . In some embodiments, one or more sidewalls of the barrier layer 110 may include sidewalls at an angle Φ relative to the upper surface of the first interlayer dielectric layer 204b at an angle measured through the barrier layer 110 . In some embodiments, the angle Φ may be greater than or equal to approximately 90°. In some embodiments, the angle Φ may be greater than 90°.

第二互連接108延伸通過阻擋層110以接觸第一互連接106的上表面。在一些實施例中，第二互連接108包括藉由第一襯裡208所圍繞之導電填充212。第一襯裡208將導電填充212與阻擋層110分離。在一些實施例中，第一襯裡208可包括在第一襯裡208的內部側壁間延伸之水平延伸區段。水平延伸區段包括在阻擋層110正上方之第一上表面304。在一些實施例中，水平延伸區段可進一步包括凹陷區302，藉由第一上表面304將凹陷區302與第一襯裡208的內部側壁橫向地分離。凹陷區302在第一互連接106正上方。在一些實施例中，凹陷區302由在第一上表面304下方凹陷之第二上表面306所界定。在一些實施例中，以第一距離308將第一上表面304與第一層間介電層204b分離，且以第二距離310將第二上表面306與第一互連接106分離，第二距離310小於第一距離 308。在一些實施例中，第二上表面306可包括彎曲表面。在一些實施例中，導電填充212與第一襯裡208共形，因而導電填充212沿著導電填充212的中心比沿著導電填充212底部外邊緣在垂直方向上更靠近第一互連接106。 The second interconnect 108 extends through the barrier layer 110 to contact the upper surface of the first interconnect 106 . In some embodiments, the second interconnect 108 includes conductive fill 212 surrounded by the first liner 208 . The first liner 208 separates the conductive fill 212 from the barrier layer 110 . In some embodiments, the first liner 208 may include a horizontally extending section extending between interior sidewalls of the first liner 208 . The horizontally extending section includes the first upper surface 304 directly above the barrier layer 110 . In some embodiments, the horizontally extending section may further include a recessed region 302 laterally separated from the inner sidewall of the first liner 208 by the first upper surface 304 . The recessed region 302 is directly above the first interconnect 106 . In some embodiments, the recessed region 302 is defined by a second upper surface 306 recessed below the first upper surface 304 . In some embodiments, the first upper surface 304 is separated from the first interlayer dielectric layer 204b by a first distance 308, and the second upper surface 306 is separated from the first interconnect 106 by a second distance 310, and the second Distance 310 is less than the first distance 308. In some embodiments, the second upper surface 306 may comprise a curved surface. In some embodiments, the conductive fill 212 is conformal to the first liner 208 such that the conductive fill 212 is vertically closer to the first interconnect 106 along the center of the conductive fill 212 than along the bottom outer edge of the conductive fill 212 .

圖4A例示具有在無阻擋界面處相遇之互連接之積體電路晶片400的一些替代實施例的截面視圖。 4A illustrates a cross-sectional view of some alternative embodiments of an integrated circuit die 400 with interconnects that meet at unobstructed interfaces.

積體電路晶片400包括被設置在基材102之上之下互連接105。在一些實施例中，下互連接105可包括與基材102的上表面接觸之下表面。在其他實施例中，可藉由一個或更多個額外互連接層將下互連接105與基材102的上表面分離。下互連接105包括圍繞導電芯404之下阻擋層402。下阻擋層402沿著導電芯404的側壁及下表面連續地延伸。下阻擋層402將導電芯404與周圍的下層間介電層204a橫向地分離。在一些實施例中，下阻擋層402可包括鉭、氮化鉭、鈦、氮化鈦、或類似物。在一些實施例中，導電芯404可包括/或可為釕、鎢、鈷、或類似物。在一些實施例中，下層間介電層204a可包括氮化矽、二氧化矽、或類似物。 The integrated circuit die 400 includes interconnects 105 disposed above and below the substrate 102 . In some embodiments, the lower interconnect 105 may include a lower surface in contact with the upper surface of the substrate 102 . In other embodiments, the lower interconnect 105 may be separated from the upper surface of the substrate 102 by one or more additional interconnect layers. Lower interconnect 105 includes lower barrier layer 402 surrounding conductive core 404 . The lower barrier layer 402 extends continuously along the sidewalls and the lower surface of the conductive core 404 . The lower barrier layer 402 laterally separates the conductive core 404 from the surrounding lower interlayer dielectric layer 204a. In some embodiments, the lower barrier layer 402 may include tantalum, tantalum nitride, titanium, titanium nitride, or the like. In some embodiments, the conductive core 404 may include/or may be ruthenium, tungsten, cobalt, or the like. In some embodiments, the lower interlayer dielectric layer 204a may include silicon nitride, silicon dioxide, or the like.

藉由第一蝕刻停止層206a將第一層間介電層204b與下層間介電層204a垂直地分離。第一層間介電層204b橫向地圍繞被設置在下互連接105之上之第一互連接106。在一些實施例中，第一互連接106可橫向地接觸第一蝕刻停止層206a及第一層間介電層204b的側壁。在一些實施例中，第一互連接106可包括與導電芯404相 同的材料(例如，釕、鎢、鈷、或類似物)。在一些實施例中，第一互連接106可包括在第一互連接106的最外側壁之間連續地延伸之單一材料。 The first interlayer dielectric layer 204b is vertically separated from the lower interlayer dielectric layer 204a by the first etch stop layer 206a. The first interlayer dielectric layer 204b laterally surrounds the first interconnect 106 disposed over the lower interconnect 105 . In some embodiments, the first interconnect 106 can laterally contact the sidewalls of the first etch stop layer 206a and the first interlayer dielectric layer 204b. In some embodiments, the first interconnect 106 may include a connection to the conductive core 404 the same material (eg, ruthenium, tungsten, cobalt, or the like). In some embodiments, the first interconnect 106 may comprise a single material extending continuously between the outermost sidewalls of the first interconnect 106 .

將第二互連接108設置在第一互連接106之上。藉由第二層間介電層204c將第二互連接108橫向地圍繞。在一些實施例中，藉由第二蝕刻停止層206b將第二層間介電層204c與第一層間介電層204b分離。第二互連接108包括第一襯裡208、藉由第一襯裡208所圍繞之第二襯裡210、藉由第二襯裡210所圍繞之導電填充212。在一些實施例中，第一襯裡208可包括與第一互連接106及導電芯404相同的材料。在一些此等實施例中，相同的材料從第二互連接108的上表面連續地延伸至導電芯404的最底部表面。 The second interconnect 108 is disposed over the first interconnect 106 . The second interconnection 108 is laterally surrounded by the second interlayer dielectric layer 204c. In some embodiments, the second interlayer dielectric layer 204c is separated from the first interlayer dielectric layer 204b by the second etch stop layer 206b. The second interconnect 108 includes a first liner 208 , a second liner 210 surrounded by the first liner 208 , and conductive filler 212 surrounded by the second liner 210 . In some embodiments, the first liner 208 may comprise the same material as the first interconnect 106 and the conductive core 404 . In some such embodiments, the same material extends continuously from the upper surface of the second interconnect 108 to the bottommost surface of the conductive core 404 .

圖4B例示具有在無阻擋界面處相遇之互連接之積體電路晶片406的一些替代實施例的截面視圖。 4B illustrates a cross-sectional view of some alternative embodiments of an integrated circuit die 406 with interconnects that meet at an unobstructed interface.

積體電路晶片406包括被設置在基材102之上之下互連接105。在一些實施例中，下互連接105可包括與基材102的上表面接觸之下表面。在其他實施例中，可藉由一個或更多個額外互連接層將下互連接105與基材102的上表面分離。在一些實施例中，下互連接105可橫向地接觸下層間介電層204a的側壁。在一些實施例中，下互連接105可包括在下互連接105的最外側壁之間連續地延伸之單一材料。在一些實施例中，單一材料可包括釕、鎢、鈷、或類似物。 The integrated circuit die 406 includes interconnects 105 disposed above and below the substrate 102 . In some embodiments, the lower interconnect 105 may include a lower surface in contact with the upper surface of the substrate 102 . In other embodiments, the lower interconnect 105 may be separated from the upper surface of the substrate 102 by one or more additional interconnect layers. In some embodiments, the lower interconnect 105 may laterally contact the sidewalls of the lower interlayer dielectric layer 204a. In some embodiments, the lower interconnects 105 may comprise a single material extending continuously between the outermost sidewalls of the lower interconnects 105 . In some embodiments, the single material may include ruthenium, tungsten, cobalt, or the like.

藉由第一蝕刻停止層206a將第一層間介電層204b與下層間介電層204a垂直地分離。第一層間介電層204b橫向地圍繞被設置在下互連接105之上之第一互連接106。在一些實施例中，第一互連接106可橫向地接觸第一蝕刻停止層206a及第一層間介電層204b的側壁。在一些實施例中，第一互連接106可包括與下互連接105相同的材料(例如，釕、鎢、鈷、或類似物)。在一些實施例中，第一互連接106可包括在第一互連接106的最外側壁之間連續地延伸之單一材料。 The first interlayer dielectric layer 204b is vertically separated from the lower interlayer dielectric layer 204a by the first etch stop layer 206a. The first interlayer dielectric layer 204b laterally surrounds the first interconnect 106 disposed over the lower interconnect 105 . In some embodiments, the first interconnect 106 can laterally contact the sidewalls of the first etch stop layer 206a and the first interlayer dielectric layer 204b. In some embodiments, the first interconnect 106 may comprise the same material as the lower interconnect 105 (eg, ruthenium, tungsten, cobalt, or the like). In some embodiments, the first interconnect 106 may comprise a single material extending continuously between the outermost sidewalls of the first interconnect 106 .

將第二互連接108設置在第一互連接106之上。藉由阻擋層110將第二互連接108與第二層間介電層204c橫向地分離。第二互連接108包括第一襯裡208、藉由第一襯裡208所圍繞之第二襯裡210、藉由第二襯裡210所圍繞之導電填充212。在一些實施例中，第一襯裡208可包括或為第一互連接106不同的材料。舉例而言，在一些實施例中，第一互襯裡可包括釕，而第一互連接可包括鎢。在一些此等實施例中，第一互連接106與第一襯裡208間之界面408與阻擋層110的底部表面大致地對準。 The second interconnect 108 is disposed over the first interconnect 106 . The second interconnect 108 is laterally separated from the second interlayer dielectric layer 204c by the barrier layer 110 . The second interconnect 108 includes a first liner 208 , a second liner 210 surrounded by the first liner 208 , and conductive filler 212 surrounded by the second liner 210 . In some embodiments, the first liner 208 may comprise or be a different material for the first interconnect 106 . For example, in some embodiments, the first interliner can include ruthenium and the first interconnect can include tungsten. In some such embodiments, the interface 408 between the first interconnect 106 and the first liner 208 is substantially aligned with the bottom surface of the barrier layer 110 .

圖5例示具有在無阻擋界面處相遇之互連接之積體電路晶片500的一些替代實施例的截面視圖。 5 illustrates a cross-sectional view of some alternative embodiments of an integrated circuit die 500 with interconnects that meet at unobstructed interfaces.

積體電路晶片500包括被設置在基材102上之下層間介電層204a之中之下互連接105。在一些實施例中，下互連接105接觸佈置在基材102的上表面上及/或之中 的電晶體元件202。將第一互連接106設置在下層間介電層204a之上之第一層間介電層204b之中。將第二互連接108設置在第一互連接106之上。藉由阻擋層110將第二互連接108與第二層間介電層204c橫向地分離。第二互連接108垂直地延伸通過阻擋層110的下表面以接觸第一互連接106的上表面。將覆蓋層214沿著第二互連接108的上表面設置。 The integrated circuit die 500 includes lower interconnects 105 disposed on the substrate 102 in the lower interlayer dielectric layer 204a. In some embodiments, lower interconnect 105 contacts are disposed on and/or in the upper surface of substrate 102 transistor element 202. The first interconnect 106 is disposed in the first interlayer dielectric layer 204b above the lower interlayer dielectric layer 204a. The second interconnect 108 is disposed over the first interconnect 106 . The second interconnect 108 is laterally separated from the second interlayer dielectric layer 204c by the barrier layer 110 . The second interconnect 108 extends vertically through the lower surface of the barrier layer 110 to contact the upper surface of the first interconnect 106 . The capping layer 214 is disposed along the upper surface of the second interconnect 108 .

藉由上蝕刻停止層502將上層間介電層204d與第二層間介電層204c垂直地分離。在一些實施例中，上蝕刻停止層502可包括多層蝕刻停止層。在一些此等實施例中，上蝕刻停止層502可包括第一材料502a、被設置在第一材料502a上之第二材料502b、及被設置在第二材料502b上之第三材料502c。在一些實施例中，第一材料502a可為與第三材料502c相同的材料，並可為與第二材料502b不同的材料。在一些實施例中，第一材料502a、第二材料502b、及第三材料502c可包括或可為氧化物(例如，氧化矽)、氮化物(例如，氮化矽)、碳化物(例如，碳化矽)、或類似物。 The upper interlayer dielectric layer 204d is vertically separated from the second interlayer dielectric layer 204c by the upper etch stop layer 502 . In some embodiments, the upper etch stop layer 502 may include multiple layers of etch stop layers. In some such embodiments, the upper etch stop layer 502 may include a first material 502a, a second material 502b disposed on the first material 502a, and a third material 502c disposed on the second material 502b. In some embodiments, the first material 502a may be the same material as the third material 502c, and may be a different material than the second material 502b. In some embodiments, the first material 502a, the second material 502b, and the third material 502c may include or may be oxides (eg, silicon oxide), nitrides (eg, silicon nitride), carbides (eg, silicon carbide), or the like.

上層間介電層204d圍繞上互連接504。上互連接504從上層間介電層204d的頂部垂直地延伸至覆蓋層214。在一些實施例中，上互連接504包括第一上襯裡508、藉由第一上襯裡508所圍繞之第二上襯裡510、及藉由第二上襯裡510所圍繞之上導電填充512。在一些實施例中，藉由上阻擋層506圍繞上互連接504。在一些實施例中， 上阻擋層506沿著上互連接504的底部表面並從上互連接504的第一側壁連續地延伸至上互連接504的相對的第二側壁。 The upper interlayer dielectric layer 204d surrounds the upper interconnect 504 . The upper interconnect 504 extends vertically from the top of the upper interlayer dielectric layer 204d to the capping layer 214 . In some embodiments, the upper interconnect 504 includes a first upper liner 508 , a second upper liner 510 surrounded by the first upper liner 508 , and an upper conductive fill 512 surrounded by the second upper liner 510 . In some embodiments, upper interconnect 504 is surrounded by upper barrier layer 506 . In some embodiments, The upper barrier layer 506 extends continuously along the bottom surface of the upper interconnection 504 and from the first sidewall of the upper interconnection 504 to the opposite second sidewall of the upper interconnection 504 .

圖6至21例示形成具有在無阻擋界面處相遇之互連接之積體電路晶片的方法的一些實施例的截面視圖600-2100。儘管相對於方法描述圖6至21，但應當認知，在圖6至21中所揭露之結構不限於此方法，而是可獨立地作為獨立於方法的結構。 6-21 illustrate cross-sectional views 600-2100 of some embodiments of a method of forming an integrated circuit die with interconnects that meet at an unobstructed interface. Although FIGS. 6-21 are described with respect to a method, it should be appreciated that the structures disclosed in FIGS. 6-21 are not limited to this method, but may stand alone as method-independent structures.

如圖6的截面視圖600所圖示，提供基材102。在各種實施例中，基材102可為任何類型的半導體主體(例如，矽、SiGe、SOI等)，諸如半導體晶圓及/或晶圓上之一個或更多個裸晶、暨與其相關聯之任何其他類型的半導體及/或晶磊層。在一些實施例中，在基材102上及/或之中形成電晶體元件202。在一些此等實施例中，可藉由在基材102之上沉積閘極介電膜及閘極電極膜，以形成電晶體元件202。隨後圖案化閘極介電膜及閘極電極膜以形成閘極介電202d及閘極電極202e。隨後可摻雜基材102以在基材102之中並在閘極電極202e的相對側上形成源極/汲極區202sd1至202sd2。 As illustrated in cross-sectional view 600 of FIG. 6, substrate 102 is provided. In various embodiments, substrate 102 may be any type of semiconductor body (eg, silicon, SiGe, SOI, etc.), such as a semiconductor wafer and/or one or more dies on a wafer, and associated therewith any other type of semiconductor and/or epitaxy. In some embodiments, transistor elements 202 are formed on and/or in substrate 102 . In some of these embodiments, the transistor element 202 may be formed by depositing a gate dielectric film and a gate electrode film over the substrate 102 . The gate dielectric film and gate electrode film are then patterned to form gate dielectric 202d and gate electrode 202e. Substrate 102 may then be doped to form source/drain regions 202sd1-202sd2 in substrate 102 and on opposite sides of gate electrode 202e.

在一些實施例中，可在被形成在基材102之上之下層間介電層204a之中形成下互連接105。在一些實施例中，下互連接105可包括MEOL互連接或導電觸點。在一些實施例中，可藉由在基材102之上形成下層間介電層204a、選擇性地蝕刻下層間介電層204a以在下層間介 電層204a之中形成下互連接開口602、在下互連接開口602之中形成第一導電材料(例如，銅、鋁，等)、並進行第一平坦化製程(例如，化學機械平坦化製程)以從下層間介電層204a之上去除多餘的第一導電材料，以形成下互連接105。 In some embodiments, the lower interconnect 105 may be formed in the lower interlayer dielectric layer 204a formed over the substrate 102 . In some embodiments, the lower interconnects 105 may comprise MEOL interconnects or conductive contacts. In some embodiments, the lower interlayer dielectric layer 204a may be formed by forming the lower interlayer dielectric layer 204a over the substrate 102 and selectively etching the lower interlayer dielectric layer 204a to A lower interconnection opening 602 is formed in the electrical layer 204a, a first conductive material (eg, copper, aluminum, etc.) is formed in the lower interconnection opening 602, and a first planarization process (eg, a chemical mechanical planarization process) is performed. The lower interconnect 105 is formed by removing excess first conductive material from above the lower interlayer dielectric layer 204a.

如圖7的截面視圖700所圖示，在下層間介電層204a之上形成第一層間介電層204b。隨後在第一層間介電層204a之中並在下互連接105之上形成第一互連接106。在一些實施例中，可藉由在下層間介電層204a之上形成第一層間介電層204b、選擇性地蝕刻第一層間介電層204b以在第一層間介電層204b之中形成第一互連接開口702、在第一互連接口702之中形成第二導電材料(例如，銅、鋁等)、並進行第二平坦化製程(例如，化學機械平坦化製程)以從第一層間介電層204b之上去除多餘的第二導電材料，以形成第一互連接106。在各種實施例中，第二導電材料可包括鎢、釕、鈷、或類似物。 As illustrated in the cross-sectional view 700 of FIG. 7, a first interlayer dielectric layer 204b is formed over the lower interlayer dielectric layer 204a. The first interconnect 106 is then formed in the first interlayer dielectric layer 204a and over the lower interconnect 105 . In some embodiments, the first interlayer dielectric layer 204b may be formed between the first interlayer dielectric layer 204b by selectively etching the first interlayer dielectric layer 204b by forming the first interlayer dielectric layer 204b over the lower interlayer dielectric layer 204a A first interconnect opening 702 is formed in the first interconnect interface 702, a second conductive material (eg, copper, aluminum, etc.) is formed in the first interconnect interface 702, and a second planarization process (eg, a chemical mechanical planarization process) is performed to remove the The excess second conductive material is removed over the first interlayer dielectric layer 204b to form the first interconnect 106 . In various embodiments, the second conductive material may include tungsten, ruthenium, cobalt, or the like.

如圖8的截面視圖800所圖示，在第一層間介電層204b之上形成第二層間介電層204c。在一些實施例中，可在形成第二層間介電層204c之前，在第一層間介電層204b之上形成蝕刻停止層206。在各種實施例中，可藉由沉積製程(例如，ALD製程、CVD製程、PE-CVD製程、或類似物)，以形成蝕刻停止層206及/或第二層間介電層204c。 As illustrated in cross-sectional view 800 of FIG. 8, a second interlayer dielectric layer 204c is formed over the first interlayer dielectric layer 204b. In some embodiments, an etch stop layer 206 may be formed over the first interlayer dielectric layer 204b prior to forming the second interlayer dielectric layer 204c. In various embodiments, the etch stop layer 206 and/or the second interlayer dielectric layer 204c may be formed by a deposition process (eg, an ALD process, a CVD process, a PE-CVD process, or the like).

在第二層間介電層204c之上形成第一遮罩結構 801。在一些實施例中，第一遮罩結構801可包括光敏感材料(例如，光阻劑)。在其他實施例中，第一遮罩結構801可包括介電遮罩層802及在介電遮罩層802之上之硬質遮罩804。在一些實施例中，介電遮蔽層802可包括氧化物(例如，矽、二氧化矽、或類似物)。在一些實施例中，硬質遮罩804可包括碳化物(例如，碳化矽、碳氧化矽、或類似物)、氮化物(例如，氮化矽、氮氧化矽、氮化鈦或類似物)、或類似物、氧化物(例如，氧化矽、氧化鈦、或類似物)、或類似物。 A first mask structure is formed over the second interlayer dielectric layer 204c 801. In some embodiments, the first mask structure 801 may include a light sensitive material (eg, photoresist). In other embodiments, the first mask structure 801 may include a dielectric mask layer 802 and a hard mask 804 on the dielectric mask layer 802 . In some embodiments, the dielectric shielding layer 802 may include an oxide (eg, silicon, silicon dioxide, or the like). In some embodiments, the hard mask 804 may include carbide (eg, silicon carbide, silicon oxycarbide, or the like), nitride (eg, silicon nitride, silicon oxynitride, titanium nitride, or the like), or the like, oxides (eg, silicon oxide, titanium oxide, or the like), or the like.

進行第一蝕刻製程以根據第一遮罩結構801選擇性地蝕刻第二層間介電層204c並界定中間互連接開口806。藉由第二層間介電層204c的側壁及水平延伸的表面界定中間互連接開口806。在一些實施例中，可藉由，在藉由第一遮罩結構801所暴露之區域中，將第二層間介電層204c暴露於第一蝕刻劑808，以選擇性地圖案化第二層間介電層204c。在一些實施例中，第一蝕刻劑808可包括乾式蝕刻劑(例如，具有氟化學物質、氯化學物質、或類似物)。在其他實施例中，第一蝕刻劑808可包括濕式蝕刻劑(例如，包括氫氟酸、氫氧化鉀、或類似物)。 A first etching process is performed to selectively etch the second interlayer dielectric layer 204c and define intermediate interconnection openings 806 according to the first mask structure 801 . The intermediate interconnection opening 806 is defined by the sidewalls and the horizontally extending surface of the second interlayer dielectric layer 204c. In some embodiments, the second interlayer may be selectively patterned by exposing the second interlayer dielectric layer 204c to the first etchant 808 in the regions exposed by the first mask structure 801 Dielectric layer 204c. In some embodiments, the first etchant 808 may comprise a dry etchant (eg, with fluorine chemistry, chlorine chemistry, or the like). In other embodiments, the first etchant 808 may include a wet etchant (eg, including hydrofluoric acid, potassium hydroxide, or the like).

如圖9的截面視圖900所圖示，去除一部分的第一遮罩結構801。在一些實施例中，可在將介電遮罩層802保持在第二層間介電層204c之上之適當位置的同時，去除硬質遮罩(圖8的804)。在各種實施例中，可藉由蝕刻製程、平坦化製程(例如，化學機械拋光(CMP)製程)、或 類似製程，以去除硬質遮罩(圖8的804)。 As illustrated in the cross-sectional view 900 of FIG. 9, a portion of the first mask structure 801 is removed. In some embodiments, the hard mask ( 804 of FIG. 8 ) may be removed while maintaining the dielectric mask layer 802 in place over the second interlayer dielectric layer 204c. In various embodiments, an etching process, a planarization process (eg, a chemical mechanical polishing (CMP) process), or A similar process is used to remove the hard mask (804 in FIG. 8).

如圖10的截面視圖1000所圖示，根據第二蝕刻製程進一步蝕刻第二層間介電層204c及蝕刻停止層206以形成第二互連接開口1002。在一些實施例中，第二互連接開口1002暴露第一互連接106的上表面。在一些實施例中，第二互連接開口1002進一步暴露第一層間介電層204b的上表面。在一些實施例中，第二蝕刻製程可根據介電遮罩層802將第二層間介電層204c及第一蝕刻停止層206a暴露於第二蝕刻劑1004。在一些實施例中，第二蝕刻製程可包括線性去除方法(linear removal method，LRM)。 As shown in the cross-sectional view 1000 of FIG. 10 , the second interlayer dielectric layer 204c and the etch stop layer 206 are further etched according to a second etch process to form the second interconnect opening 1002 . In some embodiments, the second interconnect opening 1002 exposes the upper surface of the first interconnect 106 . In some embodiments, the second interconnection opening 1002 further exposes the upper surface of the first interlayer dielectric layer 204b. In some embodiments, the second etch process may expose the second interlayer dielectric layer 204c and the first etch stop layer 206a to the second etchant 1004 according to the dielectric mask layer 802 . In some embodiments, the second etching process may include a linear removal method (LRM).

在一些替代實施例中(未圖示)，可根據單一蝕刻製程蝕刻第二層間介電層204c。在一些額外實施例中，可根據使用不同蝕刻劑之單獨的蝕刻製程，以蝕刻第二層間介電層204c及蝕刻停止層206。舉例而言，在一些實施例中，第一單一蝕刻製程可蝕刻通過第二層間介電層204c以暴露蝕刻停止層206，而第二單一蝕刻製程可蝕刻通過蝕刻停止層206以暴露第一互連接106的上表面。 In some alternative embodiments (not shown), the second interlayer dielectric layer 204c may be etched according to a single etch process. In some additional embodiments, the second interlayer dielectric layer 204c and the etch stop layer 206 may be etched according to separate etch processes using different etchants. For example, in some embodiments, the first single etch process may etch through the second interlayer dielectric layer 204c to expose the etch stop layer 206, and the second single etch process may etch through the etch stop layer 206 to expose the first interconnect Connection 106 to the upper surface.

如圖11的截面視圖1100所圖示，在第二互連接開口1002之中及第一互連接106的上表面上形成阻隔層1102。在一些實施例中，阻隔層1102可與蝕刻停止層206及/或第二層間介電層204c的側壁橫向地分離。在一些額外的實施例中，將阻隔層1102局限在第一互連接106的上表面之上，因而第一層間介電層204b的上表面暴露 在阻隔層1102的側壁與第二層間介電層204c的側壁間。 As illustrated in the cross-sectional view 1100 of FIG. 11 , a barrier layer 1102 is formed in the second interconnect opening 1002 and on the upper surface of the first interconnect 106 . In some embodiments, the barrier layer 1102 may be laterally separated from the sidewalls of the etch stop layer 206 and/or the second interlayer dielectric layer 204c. In some additional embodiments, the barrier layer 1102 is constrained over the upper surface of the first interconnect 106 so that the upper surface of the first interlayer dielectric layer 204b is exposed between the sidewalls of the blocking layer 1102 and the sidewalls of the second interlayer dielectric layer 204c.

在一些實施例中，阻隔層1102可包括自組裝單層(self-assembled monolayer，SAM)。在一些實施例中，自組裝單層可包括有機材料。舉例而言，阻隔層1102可包括矽烷(例如，氯矽烷、烷氧基矽烷、有機矽烷、或類似物)、硫醇鹽(例如，有機硫醇鹽)、或類似物。在一些實施例中，可藉由旋塗製程，以形成自組裝單層。在一些實施例中，阻隔層1102可形成為在大約10埃(Å)與大約30Å間的範圍中之厚度。在其他實施例中，阻隔層1102可形成為在大約15Å與大約25Å間、大約20Å與大約30Å間、或其他合適的值的範圍中之厚度。 In some embodiments, the barrier layer 1102 may comprise a self-assembled monolayer (SAM). In some embodiments, the self-assembled monolayer can include organic materials. For example, the barrier layer 1102 may include silanes (eg, chlorosilanes, alkoxysilanes, organosilanes, or the like), thiolates (eg, organic thiolates), or the like. In some embodiments, the self-assembled monolayer can be formed by a spin coating process. In some embodiments, the blocking layer 1102 may be formed with a thickness in the range between about 10 Angstroms (Å) and about 30 Å. In other embodiments, the barrier layer 1102 may be formed with a thickness in a range between about 15 Å and about 25 Å, between about 20 Å and about 30 Å, or other suitable values.

如圖12的橫截面視圖1200所圖示，在第二互連接開口1002之中選擇性地形成阻擋層1202。在一些實施例中，將阻隔層1102配置成充當防止將阻擋層1202形成至第一互連接106的上表面上之遮罩。阻擋層1202覆蓋一個或多個的第一層間介電層204b、第二層間介電層204c、及/或第一互連接106中的表面。並未將阻擋層1202形成至阻隔層1102的表面上，因而在阻擋層1202的形成之後，阻隔層1102具有一個或更多個暴露的表面。在一些實施例中，可將阻擋層1202形成為在大約10Å與大約20Å間的範圍中之厚度。在其他實施例中，阻擋層1202可形成為在大約10Å與大約15Å間、約15Å與約20Å間、或其他合適的值的範圍中之厚度。 As illustrated in the cross-sectional view 1200 of FIG. 12 , a barrier layer 1202 is selectively formed within the second interconnect opening 1002 . In some embodiments, the barrier layer 1102 is configured to act as a mask that prevents the formation of the barrier layer 1202 onto the upper surface of the first interconnect 106 . The barrier layer 1202 covers one or more of the first interlayer dielectric layer 204b , the second interlayer dielectric layer 204c , and/or surfaces in the first interconnect 106 . Barrier layer 1202 is not formed onto the surface of barrier layer 1102, so after formation of barrier layer 1202, barrier layer 1102 has one or more exposed surfaces. In some embodiments, barrier layer 1202 may be formed to a thickness in a range between about 10 Å and about 20 Å. In other embodiments, the barrier layer 1202 may be formed with a thickness in a range of between about 10 Å and about 15 Å, between about 15 Å and about 20 Å, or other suitable values.

在一些實施例中，可藉由原子層沉積製程，以選擇性地形成阻擋層1202。在此等實施例中，可藉由進行複數個原子層沉積循環，以進行原子層沉積製程。複數個原子層沉積循環分別將第一前驅物氣體引入至保持基材102的處理腔室中，淨化處理腔室以從處理腔室中排空第一前驅物氣體，將第二前驅物氣體引入處理腔室中，且隨後淨化處理腔室以從處理腔室中排空第二前驅物氣體。阻隔層1102對第一前驅物為惰性，因而第一前驅物並未黏附至阻隔層1102。而是，將第一前驅物氣體選擇性地形成至第一層間介電層204b、第二層間介電層204c、及/或蝕刻停止層206的一個或更多個表面上。第二前驅物氣體與第一前驅物氣體相互作用以在第一層間介電層204b、第二層間介電層204c、及/或蝕刻停止層206的一個或更多個表面上形成阻擋層1202的單層。由於並未在阻隔層1102上形成第一前驅物氣體，因而並未在阻隔層1102上形成單層。 In some embodiments, the barrier layer 1202 may be selectively formed by an atomic layer deposition process. In these embodiments, the atomic layer deposition process may be performed by performing a plurality of atomic layer deposition cycles. A plurality of atomic layer deposition cycles respectively introduce a first precursor gas into the processing chamber holding the substrate 102, purge the processing chamber to evacuate the first precursor gas from the processing chamber, introduce a second precursor gas into the processing chamber, and then purge the processing chamber to evacuate the second precursor gas from the processing chamber. The barrier layer 1102 is inert to the first precursor, so the first precursor does not adhere to the barrier layer 1102 . Rather, the first precursor gas is selectively formed onto one or more surfaces of the first interlayer dielectric layer 204b , the second interlayer dielectric layer 204c , and/or the etch stop layer 206 . The second precursor gas interacts with the first precursor gas to form a barrier layer on one or more surfaces of the first interlayer dielectric layer 204b, the second interlayer dielectric layer 204c, and/or the etch stop layer 206 1202 single layer. Since the first precursor gas is not formed on the barrier layer 1102, a monolayer is not formed on the barrier layer 1102.

如圖13的橫截面視圖1300所圖示，去除阻隔層(圖12的1102)。去除阻隔層(圖12的1102)會暴露第一互連接106的上表面，並留下開口1302，此開口延伸通過阻擋層1202延伸至第一互連接106。在一些實施例中，可藉由將阻隔層(圖12的1102)暴露於電漿，以去除阻隔層(圖12的1102)。舉例而言，在一些實施例中，可藉由將阻隔層暴露於氫基電漿(例如，H2電漿)，以去除阻隔層(圖12的1102)。在一些實施例中，由於阻擋層1202 的側壁是由阻隔層(圖12的1102)而非蝕刻製程所界定，界定開口1302的阻擋層1202的一個或更多個側壁可相對於第一層間介電層204b的上表面以通過阻隔層110所量測的角度成鈍角。在其他實施例中，界定開口1302之阻擋層1202的一個或更多個側壁可相對於第一層間介電層204b的上表面以通過阻擋層110所量測的角度成直角或成銳角。如圖14的橫截面視圖1400所圖示，在第二互連接開口1002之中形成第一襯裡層1402。在阻擋層1202之上形成第一襯裡層1402，且第一襯裡延伸通過阻擋層1202中之開口1302以接觸第一互連接106。在各種實施例中，第一襯裡層1402可包括釕、鎢、鈷、或類似物。在一些實施例中，可藉由沉積製程(例如，ALD製程、CVD製程、PE-CVD製程、或類似物)，以形成第一襯裡層1402。在一些實施例中，第一襯裡層1402可形成為在大約5Å與大約15Å間、大約10Å與大約15Å間、或其他合適的值的範圍中之厚度。 As illustrated in cross-sectional view 1300 of FIG. 13, the barrier layer (1102 of FIG. 12) is removed. Removing the barrier layer ( 1102 in FIG. 12 ) exposes the top surface of the first interconnect 106 and leaves an opening 1302 extending through the barrier layer 1202 to the first interconnect 106 . In some embodiments, the barrier layer ( 1102 of FIG. 12 ) may be removed by exposing the barrier layer ( 1102 of FIG. 12 ) to a plasma. For example, in some embodiments, the barrier layer may be removed by exposing the barrier layer to a hydrogen-based plasma (eg, H2 plasma) (1102 of Figure 12). In some embodiments, since the sidewalls of the barrier layer 1202 are defined by the barrier layer ( 1102 of FIG. 12 ) rather than the etch process, one or more sidewalls of the barrier layer 1202 defining the opening 1302 may be relative to the first interlayer The upper surface of the dielectric layer 204b forms an obtuse angle at the angle measured through the barrier layer 110 . In other embodiments, one or more sidewalls of barrier layer 1202 defining opening 1302 may be at right angles or acute angles relative to the upper surface of first interlayer dielectric layer 204b at the angle measured through barrier layer 110 . As illustrated in the cross-sectional view 1400 of FIG. 14 , a first liner layer 1402 is formed within the second interconnect opening 1002 . A first liner layer 1402 is formed over the barrier layer 1202 and the first liner extends through the opening 1302 in the barrier layer 1202 to contact the first interconnect 106 . In various embodiments, the first liner layer 1402 may include ruthenium, tungsten, cobalt, or the like. In some embodiments, the first liner layer 1402 may be formed by a deposition process (eg, ALD process, CVD process, PE-CVD process, or the like). In some embodiments, the first liner layer 1402 may be formed with a thickness in a range of between about 5 Å and about 15 Å, between about 10 Å and about 15 Å, or other suitable values.

如圖15的橫截面視圖1500所圖示，在第二互連接開口1002之中並在第一襯裡層1402之上形成第二襯裡層1502。在一些實施例中，第二襯裡層1502可包括鈷、鎢、釕、或類似物。在一些實施例中，第二襯裡層1502可包括與第一襯裡層1402不同的材料。在各種實施例中，可藉由沉積製程(例如，ALD製程、CVD製程、PE-CVD製程、或類似物)，以形成第二襯裡層1502。在一些實施例中，第二襯裡層1502可形成為在大約5Å與大約15Å 間、大約10Å與大約15Å間、或其他合適的值的範圍中之厚度。 As illustrated in the cross-sectional view 1500 of FIG. 15 , a second liner layer 1502 is formed within the second interconnect opening 1002 and over the first liner layer 1402 . In some embodiments, the second liner layer 1502 may include cobalt, tungsten, ruthenium, or the like. In some embodiments, the second backing layer 1502 may comprise a different material than the first backing layer 1402 . In various embodiments, the second liner layer 1502 may be formed by a deposition process (eg, ALD process, CVD process, PE-CVD process, or the like). In some embodiments, the second liner layer 1502 may be formed between about 5 Å and about 15 Å thickness in the range between about 10 Å and about 15 Å, or other suitable values.

如圖16的截面視圖1600所圖示，在第二互連接開口1002之中及第二襯裡層1502之上形成第三導電材料1602。在一些實施例中，可使用沉積製程及/或鍍覆製程(例如，電鍍、無電電鍍等)來形成第三導電材料1602。在各種實施例中，第三導電材料1602可包括銅、鋁、或類似物。 As illustrated in the cross-sectional view 1600 of FIG. 16 , a third conductive material 1602 is formed in the second interconnect opening 1002 and over the second liner layer 1502 . In some embodiments, the third conductive material 1602 may be formed using a deposition process and/or a plating process (eg, electroplating, electroless plating, etc.). In various embodiments, the third conductive material 1602 may include copper, aluminum, or the like.

如圖17的截面視圖1700所圖示，進行平坦化製程。沿著線1702進行平坦化製程，以從第二層間介電層204c之上去除部分的第三導電材料(圖16的1602)，並界定第二互連接108。在一些實施例中，平坦化製程亦去除部分的阻擋層(圖16的1202)、第一襯裡(圖16的1402)、及第二襯裡(圖16的1502)。第二互連接108包括接觸第一互連接106之第一襯裡208、藉由第一襯裡208所圍繞之第二襯裡210、藉由第二襯裡210所圍繞之導電填充212。在一些實施例中，平坦化製程可包括化學機械拋光製程。在一些實施例中，平坦化製程造成阻擋層110、第一襯裡208、第二襯裡210、及導電填充212的上表面與第二層間介電層204c的上表面大致共平面(例如，在化學機械拋光製程的公差之中共平面)。 As illustrated in cross-sectional view 1700 of FIG. 17, a planarization process is performed. A planarization process is performed along line 1702 to remove a portion of the third conductive material ( 1602 of FIG. 16 ) from above the second interlayer dielectric layer 204c and to define the second interconnect 108 . In some embodiments, the planarization process also removes portions of the barrier layer (1202 of FIG. 16), the first liner (1402 of FIG. 16), and the second liner (1502 of FIG. 16). The second interconnect 108 includes a first liner 208 contacting the first interconnect 106 , a second liner 210 surrounded by the first liner 208 , and conductive fill 212 surrounded by the second liner 210 . In some embodiments, the planarization process may include a chemical mechanical polishing process. In some embodiments, the planarization process causes the upper surfaces of barrier layer 110, first liner 208, second liner 210, and conductive fill 212 to be substantially coplanar with the upper surface of second interlayer dielectric layer 204c (eg, in chemical The tolerances of the mechanical polishing process are coplanar).

如圖18的橫截面視圖1800所圖示，在第二互連接108之上形成覆蓋層214。在一些實施例中，可藉由分別形成覆蓋層214的子層之複數個沉積循環，以形成覆蓋 層214。在一些實施例中，可藉由在第二互連接108之上沉積金屬，然後進行電漿處理，以分別進行複數個沉積循環。在一些實施例中，金屬可包括/或可為鈷、釕、鎢、或類似物。在一些實施例中，可藉由將沉積的金屬暴露於包括氮、氫、或類似物之電漿，以進行電漿處理。在一些實施例中，電漿可包括氨基(NH3)之電漿。在一些實施例中，覆蓋層214可形成為在大約20Å與大305Å間、大約20Å與大約25Å間、或其他合適的值的範圍中之厚度。 As illustrated in cross-sectional view 1800 of FIG. 18 , capping layer 214 is formed over second interconnect 108 . In some embodiments, capping layer 214 may be formed by a plurality of deposition cycles that separately form sublayers of capping layer 214 . In some embodiments, multiple deposition cycles may be performed separately by depositing metal over the second interconnect 108 followed by plasma processing. In some embodiments, the metal may include/or may be cobalt, ruthenium, tungsten, or the like. In some embodiments, plasma processing may be performed by exposing the deposited metal to a plasma including nitrogen, hydrogen, or the like. In some embodiments, the plasma may include a plasma of amino groups (NH 3 ). In some embodiments, the capping layer 214 may be formed with a thickness in a range between about 20 Å and greater than 305 Å, between about 20 Å and about 25 Å, or other suitable values.

在一些實施例中，可將覆蓋層214形成為完全地被局限在第二襯裡210與導電填充212之上。在一些此等實施例中，覆蓋層214的最大寬度大致上等於第二襯裡210的最大寬度。在其他實施例中，可將覆蓋層214形成為完全地被局限在第一襯裡208、第二襯裡210、與導電填充212之上。在一些此等實施例中，覆蓋層214的最大寬度大致上等於第一襯裡208的最大寬度。在又其他實施例中，覆蓋層214可形成為連續地延伸超過第一襯裡208的相對的最外側邊緣。 In some embodiments, capping layer 214 may be formed to be completely confined over second liner 210 and conductive fill 212 . In some such embodiments, the maximum width of the cover layer 214 is substantially equal to the maximum width of the second liner 210 . In other embodiments, capping layer 214 may be formed to be completely confined over first liner 208 , second liner 210 , and conductive fill 212 . In some such embodiments, the maximum width of the cover layer 214 is substantially equal to the maximum width of the first liner 208 . In yet other embodiments, the cover layer 214 may be formed to extend continuously beyond opposing outermost edges of the first liner 208 .

如圖19的截面視圖1900所圖示，在第二層間介電層204c之上形成上層間介電層204d。在各種實施例中，可藉由沉積製程(例如，ALD製程、CVD製程、PE-CVD製程、或類似物)，以形成上層間介電層204d。在一些實施例中，可在形成上層間介電層204d之前，將上蝕刻停止層502形成至第二層間介電層204c上。在一些此等實施例中，上蝕刻停止層502可包括具有第一材料502a之 多層蝕刻停止層、在第一材料502a之上之第二材料502b、及在第二材料502b之上之第三材料502c。在一些實施例中，第一材料502a、第二材料502b、及第三材料502c可包括一種或更多種的氧化物、氮化物、或碳化物。 As illustrated in the cross-sectional view 1900 of FIG. 19, an upper interlayer dielectric layer 204d is formed over the second interlayer dielectric layer 204c. In various embodiments, the upper interlayer dielectric layer 204d may be formed by a deposition process (eg, ALD process, CVD process, PE-CVD process, or the like). In some embodiments, the upper etch stop layer 502 may be formed on the second interlayer dielectric layer 204c before the upper interlayer dielectric layer 204d is formed. In some of these embodiments, the upper etch stop layer 502 may include a material having the first material 502a A multilayer etch stop layer, a second material 502b over the first material 502a, and a third material 502c over the second material 502b. In some embodiments, the first material 502a, the second material 502b, and the third material 502c may include one or more oxides, nitrides, or carbides.

如圖20的截面視圖2000所圖示，圖案化上層間介電層204d以界定上互連接開口2002。在一些實施例中，可根據第二遮罩結構2006藉由將上層間介電層204d選擇性地暴露於第三蝕刻劑2004，以圖案化上層間介電層204d。在一些實施例中，第二遮罩結構2006可包括光阻劑層、硬質遮罩層、或類似物。在各種實施例中，第三蝕刻劑2004可包括乾式蝕刻劑(例如，具有氯蝕刻化學物質、氟蝕刻化學物質、或類似物)、或濕式蝕刻劑(例如，包括氫氟酸、氫氧化鉀、或類似物)。 As illustrated in cross-sectional view 2000 of FIG. 20 , upper interlayer dielectric layer 204d is patterned to define upper interconnect openings 2002 . In some embodiments, the upper interlayer dielectric layer 204d may be patterned by selectively exposing the upper interlayer dielectric layer 204d to the third etchant 2004 according to the second mask structure 2006 . In some embodiments, the second mask structure 2006 may include a photoresist layer, a hard mask layer, or the like. In various embodiments, the third etchant 2004 may include a dry etchant (eg, with chlorine etch chemistry, fluorine etch chemistry, or the like), or a wet etchant (eg, including hydrofluoric acid, hydroxide potassium, or the like).

如圖21的橫截面視圖2100所圖示，在上互連接開口2002之中形成上互連接504。可將上互連接504形成為藉由上阻擋層506與上層間介電層204d分離。在一些實施例中，藉由在上互連接開口2002之中沉積上阻擋層，以形成上阻擋層506。隨後，藉由將第一上襯裡層形成至上阻擋層上及上互連接開口2002中、將第二上襯裡形成至第一上襯裡上及上互連接開口2002中、並將上導電材料形成至第二上襯裡上及上互連接開口2002中，以形成上互連接504。在上導電材料的形成之後，可進行平坦化製程(例如，化學機械拋光製程)以從上層間介電層204d之上去除多餘的上導電材料、第一上襯裡、第二上襯 裡、及/或上阻擋層。平坦化製程界定上互連接504以具有在上阻擋層506之上之第一上襯裡508、在第一上襯裡508之上之第二上襯裡510、及在第二上襯裡510之上的上導電填充512。 As illustrated in cross-sectional view 2100 of FIG. 21 , upper interconnection 504 is formed within upper interconnection opening 2002 . The upper interconnect 504 may be formed to be separated from the upper interlayer dielectric layer 204d by the upper barrier layer 506 . In some embodiments, the upper barrier layer 506 is formed by depositing an upper barrier layer in the upper interconnect opening 2002 . Subsequently, by forming a first upper liner layer onto the upper barrier layer and into the upper interconnect openings 2002, forming a second upper liner onto the first upper liner and into the upper interconnect openings 2002, and forming an upper conductive material to The upper interconnection opening 2002 is formed on the second upper liner to form the upper interconnection 504 . After the formation of the upper conductive material, a planarization process (eg, a chemical mechanical polishing process) may be performed to remove excess upper conductive material, the first upper liner, the second upper liner from above the upper interlayer dielectric layer 204d inner and/or upper barrier layers. The planarization process defines the upper interconnect 504 to have a first upper liner 508 over the upper barrier layer 506 , a second upper liner 510 over the first upper liner 508 , and an upper over the second upper liner 510 Conductive fill 512.

可藉由沉積製程(例如，CVD、PVD、PE-CVD、或類似物)形成上阻擋層、第一上襯裡、第二上襯裡、及上導電材料。在一些實施例中，上阻擋層可包括鉭、氮化鉭、氮化鈦、或類似物。在各種實施例中，第一上襯裡層可包括鎢、釕、鈷、或類似物。在一些實施例中，第二上襯裡層可包括與第一上襯裡層不同的材料。在各種實施例中，第二上襯裡層可包括鎢、釕、鈷、或類似物。在各種實施例中，上導電材料可包括銅、鋁、或類似物。 The upper barrier layer, the first upper liner, the second upper liner, and the upper conductive material may be formed by a deposition process (eg, CVD, PVD, PE-CVD, or the like). In some embodiments, the upper barrier layer may include tantalum, tantalum nitride, titanium nitride, or the like. In various embodiments, the first upper liner layer may include tungsten, ruthenium, cobalt, or the like. In some embodiments, the second upper liner layer may comprise a different material than the first upper liner layer. In various embodiments, the second upper liner layer may include tungsten, ruthenium, cobalt, or the like. In various embodiments, the upper conductive material may include copper, aluminum, or the like.

圖22例示形成具有在無阻擋界面處相遇之互連接之積體電路晶片的方法2200的一些實施例的流程圖。 22 illustrates a flowchart of some embodiments of a method 2200 of forming an integrated circuit die with interconnects that meet at an unobstructed interface.

儘管本文將所揭露的方法2200例示並描述成一系列動作或事件，但應當認知，此等動作或事件的圖示順序不應以限制性的意義解釋。舉例而言，除了本文中所例示及/或描述之該些動作或事件之外，一些動作能以不同的順序發生及/或與其他動作或事件同時發生。此外，實行本文中描述的一個或更多個態樣或實施例可能並不需要所有所例示的動作。此外，可在一個或更多個單獨的動作及/或階段中執行本文中所描繪之一個或更多個的動作。 Although the disclosed method 2200 is illustrated and described herein as a series of acts or events, it should be appreciated that the illustrated order of such acts or events should not be construed in a limiting sense. For example, some actions can occur in different orders and/or concurrently with other acts or events in addition to those illustrated and/or described herein. Furthermore, not all of the illustrated acts may be required to practice one or more aspects or embodiments described herein. Furthermore, one or more of the actions described herein may be performed in one or more separate actions and/or stages.

在動作2202處，在基材之上之第一層間介電層之中形成第一互連接。圖6至7例示對應至動作2202之一 些實施例的截面視圖600-700。 At act 2202, a first interconnect is formed in a first interlayer dielectric layer over the substrate. Figures 6-7 illustrate the correspondence to one of the actions 2202 Cross-sectional views 600-700 of some embodiments.

在動作2204處，在第一層間介電層之上形成第二層間介電層。圖8例示對應至動作2204之一些實施例800的截面視圖。 At act 2204, a second interlayer dielectric layer is formed over the first interlayer dielectric layer. FIG. 8 illustrates a cross-sectional view corresponding to some embodiments 800 of act 2204 .

在動作2206處，蝕刻第二層間介電層以形成界定互連接開口之內部表面，互連接開口暴露第一互連接的上表面。圖8至10例示對應至動作2206之一些實施例的截面視圖800-1000。 At act 2206, the second interlayer dielectric layer is etched to form interior surfaces defining interconnect openings that expose upper surfaces of the first interconnects. FIGS. 8-10 illustrate cross-sectional views 800 - 1000 corresponding to some embodiments of act 2206 .

在動作2208處，將阻隔層形成至第一互連接的上表面上。在一些實施例中，阻隔層可包括自組裝單層。圖11例示對應至動作2208之一些實施例1100的截面視圖。 At act 2208, a barrier layer is formed onto the upper surface of the first interconnect. In some embodiments, the barrier layer may comprise a self-assembled monolayer. FIG. 11 illustrates a cross-sectional view corresponding to some embodiments 1100 of act 2208 .

在動作2210處，在互連接開口之中選擇性地形成阻擋層。圖12例示對應至動作2210之一些實施例1200的截面視圖。 At act 2210, a barrier layer is selectively formed among the interconnect openings. FIG. 12 illustrates a cross-sectional view corresponding to some embodiments 1200 of act 2210 .

動作2212處，去除阻隔層以暴露第一互連接的上表面。圖13例示對應至動作2212之一些實施例1300的截面視圖。 At act 2212, the barrier layer is removed to expose the upper surface of the first interconnect. FIG. 13 illustrates a cross-sectional view corresponding to some embodiments 1300 of act 2212 .

在動作2214處，將第二互連接形成至阻擋層上及第一互連接的上表面上。在一些實施例中，可根據動作2216至2222形成第二互連接。 At act 2214, a second interconnect is formed on the barrier layer and on the upper surface of the first interconnect. In some embodiments, a second interconnect may be formed according to acts 2216-2222.

在動作2216處，將第一襯裡形成至阻擋層及第一互連接的上表面上。圖14例示對應至動作2216之一些實施例1400的截面視圖。 At act 2216, a first liner is formed onto the upper surface of the barrier layer and the first interconnect. FIG. 14 illustrates a cross-sectional view corresponding to some embodiments 1400 of act 2216 .

在動作2218處，將第二襯裡形成至第一襯裡上。圖15例示對應至動作2218之一些實施例1500的截面視圖。 At act 2218, a second liner is formed onto the first liner. 15 illustrates a cross-sectional view corresponding to some embodiments 1500 of act 2218.

在動作2220處，將導電材料形成至第二襯裡上。圖16例示對應至動作2220之一些實施例1600的截面視圖。 At act 2220, a conductive material is formed onto the second liner. 16 illustrates a cross-sectional view corresponding to some embodiments 1600 of act 2220.

在動作2222處，進行平坦化製程以從第二層間介電層之上去除多餘的導電材料並界定第二互連接。圖17例示對應至動作2222之一些實施例1700的截面視圖。 At act 2222, a planarization process is performed to remove excess conductive material from over the second interlayer dielectric layer and define a second interconnect. 17 illustrates a cross-sectional view corresponding to some embodiments 1700 of act 2222.

在動作2224處，將第二互連接形成至覆蓋層上。圖18例示對應至動作2224之一些實施例1800的截面視圖。 At act 2224, a second interconnect is formed onto the capping layer. 18 illustrates a cross-sectional view corresponding to some embodiments 1800 of act 2224.

在動作2226處，在第二層間介電層之上的上層間介電層之中形成上互連接。圖19至21例示對應至動作2226之一些實施例的截面視圖1900-2100。 At act 2226, an upper interconnect is formed in the upper interlayer dielectric layer over the second interlayer dielectric layer. 19-21 illustrate cross-sectional views 1900-2100 corresponding to some embodiments of act 2226.

據此，在一些實施例中，本揭露內容關於具有互連接結構之積體電路晶片，此互連接結構不具有將互連接與下層的互連接垂直分離之阻擋層。 Accordingly, in some embodiments, the present disclosure relates to integrated circuit chips having interconnect structures that do not have barrier layers that vertically separate the interconnects from underlying interconnects.

在一些實施例中，本揭露內容關於一種積體電路晶片。積體電路晶片包含設置在基材上之層間介電結構之中的第一互連接、沿著層間介電結構的側壁設置並具有在第一互連接之上界定開口之側壁阻擋層，及設置在阻擋層上的第二互連接，其中第二互連接延伸通過阻擋層中之開口延伸並到達第一互連接。在一些實施例中，將阻擋層設置 在層間介電結構的上表面上，上表面橫向地位於層間介電結構的側壁與第一互連接間。在一些實施例中，第二互連接包含佈置在阻擋層上並圍繞導電填充之第一襯裡。在一些實施例中，第一互連接及第一襯裡包含相同的材料；及導電填充及第一襯裡包含不同的材料。在一些實施例中，積體電路晶片進一步包含第二襯裡，第二襯裡皮設置在第一襯裡上並圍繞導電填充。在一些實施例中，積體電路晶片進一步包含覆蓋層，佈置在導電填充及第二襯裡上，覆蓋層及第二襯裡包含相同的材料。在一些實施例中，阻擋層在覆蓋層的橫向地外側。在一些實施例中，第一襯裡包含抵靠在阻擋層上之下表面及從下表面向外延伸並通過阻擋層之突起。 In some embodiments, the present disclosure relates to an integrated circuit chip. An integrated circuit chip includes a first interconnect disposed in an interlayer dielectric structure on a substrate, a sidewall barrier disposed along sidewalls of the interlayer dielectric structure and having sidewall barriers defining openings over the first interconnect, and disposed A second interconnect on the barrier layer, wherein the second interconnect extends through the opening in the barrier layer and reaches the first interconnect. In some embodiments, the barrier layer is provided On the upper surface of the interlayer dielectric structure, the upper surface is located laterally between the sidewalls of the interlayer dielectric structure and the first interconnection. In some embodiments, the second interconnect includes a first liner disposed on the barrier layer and surrounding the conductive fill. In some embodiments, the first interconnect and the first liner comprise the same material; and the conductive fill and the first liner comprise different materials. In some embodiments, the integrated circuit chip further includes a second liner skin disposed on the first liner and surrounding the conductive fill. In some embodiments, the integrated circuit chip further includes a capping layer disposed over the conductive fill and the second liner, the capping layer and the second liner comprising the same material. In some embodiments, the barrier layer is laterally outward of the cover layer. In some embodiments, the first liner includes protrusions that rest against the upper and lower surfaces of the barrier layer and extend outwardly from the lower surface and through the barrier layer.

在其他實施例中，本揭露內容關於一種積體電路晶片。積體電路晶片包含設置在基材上之第一層間介電層之中的第一互連接、設置在第一層間介電層之上的第二層間介電層、沿第二層間介電層的側壁及沿著第一層間介電層的上表面延伸之阻擋層，及設置在阻擋層上並圍繞導電填充的第一襯裡。第一襯裡延伸通過阻擋層到達第一互連接。在一些實施例中，阻擋層包含沿著第二層間介電層的側壁設置之垂直延伸區段及從垂直延伸區段朝向第一互連接向外突出之水平延伸區段。在一些實施例中，第一襯裡具有比阻擋層更低之電阻率。在一些實施例中，第一互連接及第一襯裡為相同的材料，此材料從第一互連接的底部連續地延伸至第二層間介電層的頂部。在一些實施例中，阻擋 層具有以一距離分離之側壁，此距離大致地等於第一互連接的頂部表面的寬度。在一些實施例中，導電填充的底部的中心比導電填充的底部外邊緣在垂直方向上更靠近第一互連接。在一些實施例中，導電填充包含在阻擋層之正上方之下表面及從下表面向外延伸之一突起，突起在第一互連接之正上方。在一些實施例中，從阻擋層的平面視圖觀看，阻擋層的底部表面界定圍繞第一襯裡之封閉環。 In other embodiments, the present disclosure relates to an integrated circuit chip. The integrated circuit chip includes a first interconnection disposed in the first interlayer dielectric layer on the substrate, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, along the second interlayer dielectric layer Sidewalls of the electrical layer and a barrier layer extending along the upper surface of the first interlayer dielectric layer, and a first liner disposed on the barrier layer and surrounding the conductive fill. The first liner extends through the barrier layer to the first interconnect. In some embodiments, the barrier layer includes vertically extending sections disposed along sidewalls of the second interlayer dielectric layer and horizontally extending sections projecting outwardly from the vertically extending sections toward the first interconnect. In some embodiments, the first liner has a lower resistivity than the barrier layer. In some embodiments, the first interconnect and the first liner are the same material that extends continuously from the bottom of the first interconnect to the top of the second interlayer dielectric layer. In some embodiments, blocking The layers have sidewalls separated by a distance approximately equal to the width of the top surface of the first interconnect. In some embodiments, the center of the bottom of the conductive fill is vertically closer to the first interconnect than the outer edge of the bottom of the conductive fill. In some embodiments, the conductive fill includes a lower surface directly above the barrier layer and a protrusion extending outwardly from the lower surface, the protrusion being directly above the first interconnect. In some embodiments, the bottom surface of the barrier layer defines a closed ring around the first liner when viewed from a plan view of the barrier layer.

在其他實施例中，本揭露內容關於形成積體電路晶片的方法。此方法包含：在基材之上之第一層間介電層之中形成第一互連接；在第一層間介電層之上形成第二層間介電層；圖案化第二層間介電層以形成界定互連接開口之側壁，互連接開口暴露第一互連接的上表面；將阻隔層在形成至第一互連接的上表面上，其中阻隔層與第二層間介電層的側壁橫向地分離；在互連接開口之中形成阻擋層；去除阻隔層以暴露第一互連接的上表面；及在互連接開口之中形成第二互連接。在一些實施例中，在互連接開口之中形成阻擋層之後，去除阻隔層。在一些實施例中，阻隔層包含自組裝單層。在一些實施例中，此方法進一步包含將第一襯裡形成至阻擋層上，且直接接觸第一互連接的上表面；將一導電材料形成至在第一襯裡上；及進行平坦化製程以從第二層間介電層之上去除部分的導電材料。 In other embodiments, the present disclosure relates to methods of forming integrated circuit chips. The method includes: forming a first interconnect in a first interlayer dielectric layer over a substrate; forming a second interlayer dielectric layer over the first interlayer dielectric layer; patterning the second interlayer dielectric layer to form sidewalls that define interconnection openings, the interconnection openings exposing the upper surface of the first interconnection; a barrier layer is formed on the upper surface of the first interconnection, wherein the barrier layer and the sidewalls of the second interlayer dielectric layer are lateral forming a barrier layer in the interconnect opening; removing the barrier layer to expose the upper surface of the first interconnect; and forming a second interconnect in the interconnect opening. In some embodiments, after the barrier layer is formed in the interconnect opening, the barrier layer is removed. In some embodiments, the barrier layer comprises a self-assembled monolayer. In some embodiments, the method further includes forming a first liner on the barrier layer in direct contact with the upper surface of the first interconnect; forming a conductive material on the first liner; and performing a planarization process to remove the A portion of the conductive material is removed from the second interlayer dielectric layer.

前文概述數種實施例的特徵，因而熟習此項技藝者可更理解本揭露內容的態樣。熟習此項技藝者應當認知，熟習此項技藝者可輕易地使用本揭露內容作為設計或修改 其他製程及結構之基礎，以實現本文介紹的實施例的相同目的及/或達成相同優點。熟習此項技藝者亦應當認識到，此等效構造不脫離本揭露內容的精神及範圍，且在不脫離本揭露內容之精神及範圍之情況下，熟習此項技藝者可在本文中進行各種改變、替換、及變更。 The foregoing has outlined features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should recognize that those skilled in the art can readily use the present disclosure for designing or modifying Other processes and structures to achieve the same objectives and/or achieve the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that those skilled in the art can make various modifications herein without departing from the spirit and scope of the present disclosure. Alterations, Substitutions, and Variations.

102:基材 102: Substrate

104:層間介電結構 104: Interlayer Dielectric Structure

105:下互連接 105: Down Interconnect

106:第一互連接 106: First Interconnect

108:第二互連接 108: Second Interconnect

110:阻擋層 110: Barrier

110h:水平延伸區段 110h: Horizontal extension section

110v:垂直延伸區段 110v: Vertical extension section

200:積體電路晶片 200: Integrated circuit chip

202:電晶體元件 202: Transistor Components

204a:下層間介電層 204a: lower interlayer dielectric layer

204b:第一層間介電層 204b: first interlayer dielectric layer

204c:第二層間介電層 204c: Second interlayer dielectric layer

206:蝕刻停止層 206: Etch Stop Layer

208:第一襯裡 208: First lining

210:第二襯裡 210: Second lining

212:導電填充 212: Conductive Fill

214:覆蓋層 214: Overlay

A-A’:橫截面線 A-A': cross section line

θ:角度 θ: angle

Claims (10)

一種積體電路晶片，包括：一第一互連接，設置在一基材上之一層間介電結構之中；一阻擋層，沿著該層間介電結構的多個側壁設置並具有在該第一互連接之上界定一開口之多個側壁，其中該阻擋層的該些側壁分離一距離，該距離大致地等於該第一互連接的頂部表面的寬度；及一第二互連接，設置在該阻擋層上，其中該第二互連接延伸通過該阻擋層中之該開口並到達該第一互連接。 An integrated circuit chip, comprising: a first interconnection disposed in an interlayer dielectric structure on a substrate; a barrier layer disposed along a plurality of sidewalls of the interlayer dielectric structure and having an interlayer dielectric structure in the first a plurality of sidewalls defining an opening over an interconnect, wherein the sidewalls of the barrier layer are separated by a distance substantially equal to the width of the top surface of the first interconnect; and a second interconnect disposed at on the barrier layer, wherein the second interconnect extends through the opening in the barrier layer and to the first interconnect. 如請求項1所述之積體電路晶片，其中該第二互連接包括被佈置在該阻擋層上並圍繞一導電填充之一第一襯裡。 The integrated circuit chip of claim 1, wherein the second interconnect includes a first liner disposed on the barrier layer and surrounding a conductive fill. 如請求項2所述之積體電路晶片，其中該第一互連接及該第一襯裡包括相同的材料；及該導電填充及該第一襯裡包括不同的材料。 The integrated circuit chip of claim 2, wherein the first interconnect and the first liner comprise the same material; and the conductive fill and the first liner comprise different materials. 如請求項2所述之積體電路晶片，進一步包括：一第二襯裡，設置在該第一襯裡上並圍繞該導電填充。 The integrated circuit chip of claim 2, further comprising: a second liner disposed on the first liner and surrounding the conductive filler. 如請求項4所述之積體電路晶片，進一步包括：一覆蓋層，佈置在該導電填充及該第二襯裡上，其中該覆蓋層及該第二襯裡包括相同的材料。 The integrated circuit chip of claim 4, further comprising: a cover layer disposed on the conductive filling and the second liner, wherein the cover layer and the second liner comprise the same material. 如請求項2所述之積體電路晶片，其中該第一襯裡包括抵靠在該阻擋層上之一下表面及從該下表面向外延伸並通過該阻擋層之一突起。 The integrated circuit chip of claim 2, wherein the first liner includes a lower surface abutting the barrier layer and a protrusion extending outwardly from the lower surface and through the barrier layer. 一種積體電路晶片，包括：一第一互連接，設置在一基材上之一第一層間介電層之中；一第二層間介電層，設置在該第一層間介電層之上；一阻擋層，沿該第二層間介電層的一側壁及沿著該第一層間介電層的一上表面延伸，其中在該第一層間介電層的該上表面上的該阻擋層的多個側壁分離一距離，該距離大致地等於該第一互連接的頂部表面的寬度；及一第一襯裡，設置在該阻擋層上並圍繞一導電填充，其中該第一襯裡延伸通過該阻擋層至該第一互連接。 An integrated circuit chip, comprising: a first interconnection disposed in a first interlayer dielectric layer on a substrate; a second interlayer dielectric layer disposed in the first interlayer dielectric layer above; a barrier layer extending along a sidewall of the second interlayer dielectric layer and along an upper surface of the first interlayer dielectric layer, wherein on the upper surface of the first interlayer dielectric layer the sidewalls of the barrier layer are separated by a distance approximately equal to the width of the top surface of the first interconnect; and a first liner disposed on the barrier layer and surrounding a conductive fill, wherein the first A liner extends through the barrier layer to the first interconnect. 如請求項7所述之積體電路晶片，其中該阻擋層包括沿著該第二層間介電層的該側壁設置之一垂直延伸區段及從該垂直延伸區段朝向該第一互連接向外突出之一水平延伸區段。 The integrated circuit chip of claim 7, wherein the barrier layer includes a vertically extending section disposed along the sidewall of the second interlayer dielectric layer and extending from the vertically extending section toward the first interconnection direction A horizontally extending section of the outer protrusion. 如請求項7所述之積體電路晶片，其中該導電填充的一底部的一中心比該導電填充的底部外邊緣在垂直方向上更靠近該第一互連接。 The integrated circuit chip of claim 7, wherein a center of a bottom of the conductive fill is vertically closer to the first interconnect than an outer edge of the bottom of the conductive fill. 一種形成積體電路晶片的方法，包括以下步驟：在一基材上之一第一層間介電層之中形成一第一互連接；在該第一層間介電層之上形成一第二層間介電層；圖案化該第二層間介電層以形成界定一互連接開口之多個側壁，該互連接開口暴露該第一互連接的一上表面；將一阻隔層形成至該第一互連接的該上表面上，其中該阻隔層與該第二層間介電層的該些側壁橫向地分離，該第一層間介電層的一上表面暴露在該阻隔層的側壁與該第二層間介電層的該些側壁間；在該互連接開口之中形成一阻擋層；去除該阻隔層以暴露該第一互連接的該上表面；及在該互連接開口之中形成一第二互連接。 A method of forming an integrated circuit chip, comprising the steps of: forming a first interconnection in a first interlayer dielectric layer on a substrate; forming a first interconnection on the first interlayer dielectric layer two interlayer dielectric layers; patterning the second interlayer dielectric layer to form a plurality of sidewalls defining an interconnection opening that exposes an upper surface of the first interconnection; forming a barrier layer to the first interconnection On the upper surface of an interconnection, wherein the barrier layer is laterally separated from the sidewalls of the second interlayer dielectric layer, an upper surface of the first interlayer dielectric layer is exposed on the sidewalls of the barrier layer and the between the sidewalls of the second interlayer dielectric layer; forming a barrier layer in the interconnection opening; removing the barrier layer to expose the upper surface of the first interconnection; and forming a barrier layer in the interconnection opening The second interconnection.
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