TWI762894B - Circuit device - Google Patents

Circuit device Download PDF

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TWI762894B
TWI762894B TW109110783A TW109110783A TWI762894B TW I762894 B TWI762894 B TW I762894B TW 109110783 A TW109110783 A TW 109110783A TW 109110783 A TW109110783 A TW 109110783A TW I762894 B TWI762894 B TW I762894B
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metal
transparent conductive
layer
pad
bonding area
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TW109110783A
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TW202119698A (en
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賴一丞
陳忠宏
王友志
郭世斌
鄭翔及
王信傑
陳國祥
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友達光電股份有限公司
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Abstract

A circuit device includes a substrate, a driving circuit, a first metal layer, a first insulating layer, a second insulating layer, second metal pads, and a transparent conductive layer. The first metal layer is located on the bonding region. The first insulating layer is located on the first metal layer. The second metal pads are located in first through holes of the first insulating layer. The transparent conductive layer is located in second through holes of the second insulating layer. The first metal layer includes a first metal pad directly connected to the second metal pads, and the first metal pad is electrically connected to transparent conductive pads in the transparent conductive layer; or the transparent conductive layer includes a transparent conductive pad directly connected to the second metal pads, and the transparent conductive pad is electrically connected to the first metal pads in the first metal layer.

Description

電路裝置circuit device

本發明是有關於一種電路裝置,且特別是有關於一種包括接合區的電路裝置。The present invention relates to a circuit arrangement, and in particular to a circuit arrangement including a land.

隨著時代的進展,為了使產品便於攜帶,輕、薄、短、小等特點逐漸變成消費者選擇產品的首要條件。除了縮小電子產品的尺寸外,許多廠商還致力於提升電子產品的可撓性,使產品更具競爭力。舉例來說,可撓式的天線可以設置於服裝、錶帶或摺疊式手機中。換句話說,相較於傳統不易彎折的天線,可撓式天線的可以應用的領域更加廣泛。With the development of the times, in order to make the product easy to carry, the characteristics of lightness, thinness, shortness and smallness have gradually become the primary conditions for consumers to choose products. In addition to reducing the size of electronic products, many manufacturers are also committed to improving the flexibility of electronic products to make products more competitive. For example, the flexible antenna can be installed in clothing, watch straps or foldable mobile phones. In other words, compared with the traditional antenna that is not easy to bend, the flexible antenna can be applied in a wider range.

然而,在一些可撓式電子裝置中,由於不同構件容易在接合過程中彎曲,可撓式電子裝置的製造難度較高。舉例來說,在將驅動晶片接合於可撓式基板的接合製程中,驅動晶片的接合墊容易因為彎曲而損壞,使驅動晶片不能正確的接合於可撓式基板。However, in some flexible electronic devices, the manufacturing of the flexible electronic devices is difficult because different components are easily bent during the bonding process. For example, in the bonding process of bonding the driving chip to the flexible substrate, the bonding pads of the driving chip are easily damaged due to bending, so that the driving chip cannot be properly bonded to the flexible substrate.

本發明提供一種電路裝置,可以提升接合製程的良率。The present invention provides a circuit device, which can improve the yield of the bonding process.

本發明的至少一實施例提供一種電路裝置,包括基板、驅動電路、第一金屬層、第一絕緣層、第二絕緣層、多個第二金屬接墊以及透明導電層。基板具有電路區以及第一接合區。驅動電路位於電路區上。第一金屬層位於第一接合區上,且電性連接至驅動電路。第一絕緣層位於第一金屬層上,且具有重疊於第一金屬層的多個第一通孔。第二金屬接墊位於第一通孔中,且第二金屬接墊凸出第一絕緣層的上表面。第二絕緣層位於第二金屬接墊上,且具有重疊於第二金屬接墊的多個第二通孔。透明導電層位於第二通孔中,且透明導電層凸出第二絕緣層的上表面。第一金屬層包括直接連接第二金屬接墊的第一金屬接墊,且第一金屬接墊透過第二金屬接墊而電性連接至透明導電層中的多個透明導電接墊;或透明導電層包括直接連接多個第二金屬接墊的一透明導電接墊,且透明導電接墊透過多個第二金屬接墊而電性連接至第一金屬層中的多個第一金屬接墊。At least one embodiment of the present invention provides a circuit device including a substrate, a driving circuit, a first metal layer, a first insulating layer, a second insulating layer, a plurality of second metal pads, and a transparent conductive layer. The substrate has a circuit area and a first bonding area. The driving circuit is located on the circuit area. The first metal layer is located on the first bonding area and is electrically connected to the driving circuit. The first insulating layer is located on the first metal layer and has a plurality of first through holes overlapping the first metal layer. The second metal pad is located in the first through hole, and the second metal pad protrudes from the upper surface of the first insulating layer. The second insulating layer is located on the second metal pad and has a plurality of second through holes overlapping the second metal pad. The transparent conductive layer is located in the second through hole, and the transparent conductive layer protrudes from the upper surface of the second insulating layer. The first metal layer includes a first metal pad directly connected to the second metal pad, and the first metal pad is electrically connected to a plurality of transparent conductive pads in the transparent conductive layer through the second metal pad; or transparent The conductive layer includes a transparent conductive pad directly connected to the plurality of second metal pads, and the transparent conductive pad is electrically connected to the plurality of first metal pads in the first metal layer through the plurality of second metal pads .

在整個說明書中,相同的附圖標記表示相同或類似的元件。在附圖中,為了清楚起見,放大了層、膜、面板、區域等的厚度。應當理解,當諸如層、膜、區域或基板的元件被稱為「在另一元件上」或「連接另一元件」時,其可以直接在另一元件上或與另一元件連接。二元件互相「電性連接」或「耦合」可為二元件間存在其它元件。Throughout the specification, the same reference numbers refer to the same or similar elements. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element. Two elements are "electrically connected" or "coupled" to each other by the existence of other elements between the two elements.

應當理解,儘管術語「第一」與「第二」等在本文中可以用於描述各種元件、部件、區域、層及/或部分,但是這些元件、部件、區域、及/或部分不應受這些術語的限制。這些術語僅用於將一個元件、部件、區域、層或部分與另一個元件、部件、區域、層或部分區分開。It will be understood that, although the terms "first" and "second" and the like may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or sections should not be limited by limitations of these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section.

圖1是依照本發明的一實施例的一種天線裝置的俯視示意圖。圖2是依照本發明的一實施例的一種電路裝置的仰視示意圖。圖2例如是圖1中之電路裝置20的放大示意圖。為了方便說明,圖1與圖2中之電路裝置20省略了部分構件。FIG. 1 is a schematic top view of an antenna device according to an embodiment of the present invention. FIG. 2 is a schematic bottom view of a circuit device according to an embodiment of the present invention. FIG. 2 is, for example, an enlarged schematic view of the circuit device 20 in FIG. 1 . For convenience of description, some components of the circuit device 20 in FIGS. 1 and 2 are omitted.

請參考圖1,天線裝置1包括天線基板10以及電路裝置20,其中電路裝置20接合至天線基板10。Please refer to FIG. 1 , the antenna device 1 includes an antenna substrate 10 and a circuit device 20 , wherein the circuit device 20 is bonded to the antenna substrate 10 .

天線基板10包括基板100、天線110、第一天線接墊120A以及第二天線接墊120B。基板100的材料可為玻璃、石英、有機聚合物或是金屬等等。在本實施例中,基板100為可撓式基板,且基板100包括透明、半透明或不透明的材料,但本發明不以此為限。天線110例如為螺旋狀或其他形狀,且天線110的兩端分別電性連接至第一天線接墊120A以及第二天線接墊120B。天線110、第一天線接墊120A以及第二天線接墊120B的材料包括導電材料,例如金、銀、銅、鋁、鉬、鈦或其他導電材料。The antenna substrate 10 includes a substrate 100 , an antenna 110 , a first antenna pad 120A and a second antenna pad 120B. The material of the substrate 100 can be glass, quartz, organic polymer or metal, and so on. In this embodiment, the substrate 100 is a flexible substrate, and the substrate 100 includes a transparent, translucent or opaque material, but the invention is not limited thereto. The antenna 110 is, for example, a spiral shape or other shapes, and both ends of the antenna 110 are electrically connected to the first antenna pad 120A and the second antenna pad 120B, respectively. The materials of the antenna 110 , the first antenna pad 120A and the second antenna pad 120B include conductive materials, such as gold, silver, copper, aluminum, molybdenum, titanium or other conductive materials.

請參考圖1與圖2,電路裝置20的基板200具有電路區202、第一接合區204A與第二接合區204B。第一接合區204A與第二接合區204B分別位於電路區202的相對兩側,其中第一接合區204A上的接墊(圖1與圖2省略繪出)與第二接合區204B上的接墊(圖1與圖2省略繪出)電性連接至電路區202上的元件,且第一接合區204A上的接墊與第二接合區204B上的接墊分別電性連接至第一天線接墊120A以及第二天線接墊120B。基板200的材料可為玻璃、石英、有機聚合物或是金屬等等。在本實施例中,基板200為可撓式基板,且基板200包括透明、半透明或不透明的材料。Referring to FIGS. 1 and 2 , the substrate 200 of the circuit device 20 has a circuit region 202 , a first bonding region 204A and a second bonding region 204B. The first bonding area 204A and the second bonding area 204B are respectively located on opposite sides of the circuit area 202 , wherein the pads on the first bonding area 204A (not shown in FIGS. 1 and 2 ) and the bonding pads on the second bonding area 204B The pads (not shown in FIG. 1 and FIG. 2 ) are electrically connected to the elements on the circuit area 202 , and the pads on the first bonding area 204A and the bonding pads on the second bonding area 204B are respectively electrically connected to the first The wire pads 120A and the second antenna pads 120B. The material of the substrate 200 can be glass, quartz, organic polymer or metal, and so on. In this embodiment, the substrate 200 is a flexible substrate, and the substrate 200 includes a transparent, translucent or opaque material.

在本實施例中,驅動電路210設置於電路區202上。電路區202部分重疊於天線110。在本實例中,驅動電路210部分重疊於天線110。在本實施例中,驅動電路210包括數位電路(Digital circuit)212、整流器(Rectifier)214以及分頻器(Divider)216,但本發明不以此為限。In this embodiment, the driving circuit 210 is disposed on the circuit area 202 . The circuit region 202 partially overlaps the antenna 110 . In this example, the driving circuit 210 partially overlaps the antenna 110 . In this embodiment, the driving circuit 210 includes a digital circuit (Digital circuit) 212 , a rectifier (Rectifier) 214 and a frequency divider (Divider) 216 , but the invention is not limited thereto.

圖3A是依照本發明的一實施例的一種天線裝置的剖面示意圖。為了方便說明,圖3A省略繪示了電路區上的部份元件。圖3B是圖3A的電路裝置的第一接合區的仰視示意圖。在此必須說明的是,圖3A和圖3B的實施例沿用圖1和圖2的實施例的元件標號與部分內容,其中採用相同或近似的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例,在此不贅述。3A is a schematic cross-sectional view of an antenna device according to an embodiment of the present invention. For convenience of description, FIG. 3A omits and illustrates some components on the circuit area. 3B is a schematic bottom view of the first bonding area of the circuit arrangement of FIG. 3A. It must be noted here that the embodiments of FIGS. 3A and 3B use the element numbers and part of the content of the embodiments of FIGS. 1 and 2 , wherein the same or similar reference numbers are used to represent the same or similar elements, and the same elements are omitted. Description of technical content. For the description of the omitted part, reference may be made to the foregoing embodiments, which will not be repeated here.

請參考圖3A與圖3B,天線裝置2包括天線基板10以及電路裝置20。為了使方便說明,圖3A繪示的是天線基板10以及電路裝置20還未互相接合的狀態,在天線裝置2中,天線基板10以及電路裝置20實際上互相接合。Referring to FIGS. 3A and 3B , the antenna device 2 includes an antenna substrate 10 and a circuit device 20 . For convenience of description, FIG. 3A shows a state in which the antenna substrate 10 and the circuit device 20 are not yet joined to each other. In the antenna device 2 , the antenna substrate 10 and the circuit device 20 are actually joined to each other.

天線基板10包括基板100、天線110、第一天線接墊120A以及第二天線接墊120B。在本實施例中,導電黏著層300A、300B分別形成於第一天線接墊120A以及第二天線接墊120B上。導電黏著層300A、300B例如為異方性導電膠(Anisotropic Conductive Paste,ACP)、異方性導電膜(Anisotropic Conductive Film,ACF)或其他導電黏著層。The antenna substrate 10 includes a substrate 100 , an antenna 110 , a first antenna pad 120A and a second antenna pad 120B. In this embodiment, the conductive adhesive layers 300A and 300B are respectively formed on the first antenna pad 120A and the second antenna pad 120B. The conductive adhesive layers 300A and 300B are, for example, anisotropic conductive paste (ACP), anisotropic conductive film (ACF) or other conductive adhesive layers.

電路裝置20包括基板200、驅動電路、第一金屬層220、第一絕緣層I1、第二絕緣層I2、多個第二金屬層230以及透明導電層240。The circuit device 20 includes a substrate 200 , a driving circuit, a first metal layer 220 , a first insulating layer I1 , a second insulating layer I2 , a plurality of second metal layers 230 and a transparent conductive layer 240 .

基板200具有電路區202、第一接合區204A與第二接合區204B,其中第一接合區204A與第二接合區204B分別位於電路區202的相對兩側。The substrate 200 has a circuit area 202 , a first bonding area 204A and a second bonding area 204B, wherein the first bonding area 204A and the second bonding area 204B are located on opposite sides of the circuit area 202 respectively.

驅動電路位於電路區220上。在本實施例中,驅動電路210包括多個主動元件T。舉例來說,驅動電路210中的整流器包括主動元件T。The driving circuit is located on the circuit region 220 . In this embodiment, the driving circuit 210 includes a plurality of active elements T. For example, the rectifier in the driving circuit 210 includes the active element T.

主動元件T位於基板200上,且包括閘極G、多晶矽層CH、源極S以及汲極D。多晶矽層CH位於基板200上,且包括源極區CH1、通道區CH2以及汲極區CH3,其中通道區CH2位於源極區CH1以及汲極區CH3之間。源極區CH1以及汲極區CH3例如為N型摻雜的多晶矽或P型摻雜的多晶矽。閘極絕緣層GI位於多晶矽層CH以及基板200上。閘極G位於閘極絕緣層GI上,且重疊於多晶矽層CH。第一絕緣層I1位於閘極G以及閘極絕緣層GI上。源極S以及汲極D位於第一絕緣層I1上,且分別透過開口O1、O2而電性連接至源極區CH1以及汲極區CH3,其中開口O1、O2貫穿第一絕緣層I1以及閘極絕緣層GI。The active element T is located on the substrate 200 and includes a gate electrode G, a polysilicon layer CH, a source electrode S and a drain electrode D. The polysilicon layer CH is located on the substrate 200 and includes a source region CH1 , a channel region CH2 and a drain region CH3 , wherein the channel region CH2 is located between the source region CH1 and the drain region CH3 . The source region CH1 and the drain region CH3 are, for example, N-type doped polysilicon or P-type doped polysilicon. The gate insulating layer GI is located on the polysilicon layer CH and the substrate 200 . The gate G is located on the gate insulating layer GI and overlaps the polysilicon layer CH. The first insulating layer I1 is located on the gate electrode G and the gate insulating layer GI. The source electrode S and the drain electrode D are located on the first insulating layer I1 and are electrically connected to the source region CH1 and the drain region CH3 through the openings O1 and O2 respectively, wherein the openings O1 and O2 penetrate the first insulating layer I1 and the gate electrode Extremely insulating layer GI.

在本實施例中,主動元件T為頂部閘極型的薄膜電晶體,但本發明不以此為限。在其他實施例中,主動元件T為底部閘極型的薄膜電晶體、雙閘極型的薄膜電晶體或其他形式的薄膜電晶體。在本實施例中,主動元件T為多晶矽薄膜電晶體,但本發明不以此為限。在其他實施例中,主動元件T為金屬氧化物薄膜電晶體、有機薄膜電晶體或其他形式的薄膜電晶體。In this embodiment, the active element T is a top gate type thin film transistor, but the invention is not limited to this. In other embodiments, the active element T is a bottom gate type thin film transistor, a double gate type thin film transistor or other forms of thin film transistor. In this embodiment, the active element T is a polysilicon thin film transistor, but the present invention is not limited to this. In other embodiments, the active element T is a metal oxide thin film transistor, an organic thin film transistor or other forms of thin film transistor.

第一金屬層220位於第一接合區204A上。在本實施例中,第一金屬層220包括位於第一接合區204A上的第一金屬接墊222以及位於第二接合區204B上的第一金屬接墊222,且兩個第一金屬接墊222彼此分離。在一些實施例中,第一金屬層220與閘極G屬於相同導電層。舉例來說,第一金屬接墊222與閘極G是於同一道圖案化製程(例如微影蝕刻製程)中形成,且第一金屬接墊222與閘極G皆位於閘極絕緣層GI上。在一些實施例中,第一金屬層220與閘極G的材料包括金、銀、銅、鋁、鉬、鈦或其他金屬或包含前述金屬的合金,第一金屬層220與閘極G的厚度T1例如為1800埃至2200埃。第一金屬層220與閘極G為單層或多層結構。The first metal layer 220 is located on the first bonding area 204A. In this embodiment, the first metal layer 220 includes a first metal pad 222 on the first bonding area 204A and a first metal pad 222 on the second bonding area 204B, and the two first metal pads 222 are separated from each other. In some embodiments, the first metal layer 220 and the gate G belong to the same conductive layer. For example, the first metal pad 222 and the gate G are formed in the same patterning process (such as a lithography etching process), and both the first metal pad 222 and the gate G are located on the gate insulating layer GI . In some embodiments, the materials of the first metal layer 220 and the gate electrode G include gold, silver, copper, aluminum, molybdenum, titanium or other metals or alloys including the aforementioned metals. The thicknesses of the first metal layer 220 and the gate electrode G include: T1 is, for example, 1800 angstroms to 2200 angstroms. The first metal layer 220 and the gate electrode G have a single-layer or multi-layer structure.

第一絕緣層I1位於第一金屬層220上,且具有重疊於第一金屬層220的多個第一通孔TH1。第一絕緣層I1例如為平坦層,且材料包括無機材料(例如:氧化矽、氮化矽、氮氧化矽、其它合適的材料、或上述至少二種材料的堆疊層)、有機材料(例如:聚酯類(PET)、聚烯類、聚丙醯類、聚碳酸酯類、聚環氧烷類、聚苯烯類、聚醚類、聚酮類、聚醇類、聚醛類或其它合適的材料或上述之組合)或其它合適的材料或上述之組合,第一絕緣層I1的厚度T2例如為6500埃至7900埃。第一絕緣層I1單層或多層結構。The first insulating layer I1 is located on the first metal layer 220 and has a plurality of first through holes TH1 overlapping the first metal layer 220 . The first insulating layer I1 is, for example, a flat layer, and the material includes inorganic materials (such as silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a stacked layer of at least two of the above materials), organic materials (such as: Polyesters (PET), polyolefins, polypropylenes, polycarbonates, polyalkylene oxides, polyphenylenes, polyethers, polyketones, polyalcohols, polyaldehydes or other suitable material or a combination of the above) or other suitable materials or a combination of the above, the thickness T2 of the first insulating layer I1 is, for example, 6500 angstroms to 7900 angstroms. The first insulating layer I1 has a single-layer or multi-layer structure.

第二金屬層230位於第一絕緣層I1上,且第二金屬層230包括彼此分離的多個第二金屬接墊232。第二金屬接墊232位於第一通孔TH1中,並直接連接第一金屬接墊222。在本實施例中,第二金屬接墊232排列成點狀分佈的陣列。第二金屬接墊230凸出第一絕緣層I1的上表面F1,其中第一絕緣層I1的上表面F1面對天線基板10。第二金屬層230的材料包括金、銀、銅、鋁、鉬、鈦或其他金屬,或包含前述金屬的合金,第二金屬接墊232凸出第一絕緣層I1的厚度T3例如為2900埃至3500埃,第二金屬層230為單層或多層結構。The second metal layer 230 is located on the first insulating layer I1, and the second metal layer 230 includes a plurality of second metal pads 232 separated from each other. The second metal pads 232 are located in the first through holes TH1 and are directly connected to the first metal pads 222 . In this embodiment, the second metal pads 232 are arranged in a dot-like array. The second metal pad 230 protrudes from the upper surface F1 of the first insulating layer I1 , wherein the upper surface F1 of the first insulating layer I1 faces the antenna substrate 10 . The material of the second metal layer 230 includes gold, silver, copper, aluminum, molybdenum, titanium or other metals, or alloys including the aforementioned metals, and the thickness T3 of the second metal pad 232 protruding from the first insulating layer I1 is, for example, 2900 angstroms To 3500 angstroms, the second metal layer 230 is a single-layer or multi-layer structure.

第一金屬層220或第二金屬層230電性連接至驅動電路210中的主動元件T。舉例來說,兩個主動元件T的汲極D分別透過兩個開口O3而直接連接至第一接合區204A上的第一金屬接墊222以及第二接合區204B上的第一金屬接墊222,其中開口O3貫穿第一絕緣層I1。The first metal layer 220 or the second metal layer 230 is electrically connected to the active element T in the driving circuit 210 . For example, the drains D of the two active elements T are directly connected to the first metal pads 222 on the first bonding area 204A and the first metal pads 222 on the second bonding area 204B through the two openings O3 respectively. , wherein the opening O3 penetrates through the first insulating layer I1.

在本實施例中,第一金屬接墊222各自直接連接至多個第二金屬接墊232。一個第一金屬接墊222重疊於多個第二金屬接墊232。In this embodiment, each of the first metal pads 222 is directly connected to the plurality of second metal pads 232 . A first metal pad 222 overlaps a plurality of second metal pads 232 .

在一些實施例中,第二金屬接墊232、源極S以及汲極D屬於相同導電層。舉例來說,第二金屬接墊232、源極S以及汲極D是於同一道圖案化製程(例如微影蝕刻製程)中形成,且第二金屬接墊232、源極S以及汲極D皆位於第一絕緣層I1上。In some embodiments, the second metal pad 232, the source electrode S and the drain electrode D belong to the same conductive layer. For example, the second metal pad 232 , the source S and the drain D are formed in the same patterning process (such as a lithography etching process), and the second metal pad 232 , the source S and the drain D All are located on the first insulating layer I1.

第二絕緣層I2位於第二金屬層230(第二金屬接墊232)、源極S以及汲極D上。第二絕緣層I2材料包括無機材料(例如:氧化矽、氮化矽、氮氧化矽、其它合適的材料、或上述至少二種材料的堆疊層)、有機材料(例如:聚酯類(PET)、聚烯類、聚丙醯類、聚碳酸酯類、聚環氧烷類、聚苯烯類、聚醚類、聚酮類、聚醇類、聚醛類或其它合適的材料或上述之組合)或其它合適的材料或上述之組合,第二絕緣層I2的厚度T4例如為1750埃至3300埃。第二絕緣層I2單層或多層結構。The second insulating layer I2 is located on the second metal layer 230 (the second metal pad 232 ), the source electrode S and the drain electrode D. The material of the second insulating layer I2 includes inorganic materials (such as silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a stacked layer of at least two of the above materials), organic materials (such as polyester (PET) , polyolefins, polypropylenes, polycarbonates, polyalkylene oxides, polystyrenes, polyethers, polyketones, polyalcohols, polyaldehydes or other suitable materials or a combination of the above) Or other suitable materials or a combination of the above, the thickness T4 of the second insulating layer I2 is, for example, 1750 angstroms to 3300 angstroms. The second insulating layer I2 has a single-layer or multi-layer structure.

在本實施例中,第二絕緣層I2共形於第二金屬層230、源極S以及汲極D。舉例來說,第二絕緣層I2從第一絕緣層I1的上表面F1沿著第二金屬接墊232的側面延伸至第二金屬接墊232的上表面F2。在本實施例中,於垂直基板200的方向E1上,第二絕緣層I2重疊於第二金屬接墊232的部分與不重疊於第二金屬接墊232的部分具有高度差。換句話說,在第一接合區204A與第二接合區204B上,第二絕緣層I2的上表面F3為高低起伏的表面,其中上表面F3朝向天線基板10。第二絕緣層I2具有重疊於第二金屬接墊232的上表面F2的多個第二通孔TH2。In this embodiment, the second insulating layer I2 is conformally formed on the second metal layer 230 , the source electrode S and the drain electrode D. For example, the second insulating layer I2 extends from the upper surface F1 of the first insulating layer I1 along the side surface of the second metal pad 232 to the upper surface F2 of the second metal pad 232 . In this embodiment, in the direction E1 perpendicular to the substrate 200 , the portion of the second insulating layer I2 overlapping the second metal pad 232 and the portion not overlapping the second metal pad 232 have a height difference. In other words, on the first bonding region 204A and the second bonding region 204B, the upper surface F3 of the second insulating layer I2 is a undulating surface, wherein the upper surface F3 faces the antenna substrate 10 . The second insulating layer I2 has a plurality of second through holes TH2 overlapping the upper surface F2 of the second metal pad 232 .

透明導電層240位於第二絕緣層I2的第二通孔TH2中,並直接連接第二金屬接墊232。透明導電層240的製造方法例如包括微影蝕刻製程。在本實施例中,透明導電層240包括多個透明導電接墊242,每個第二通孔TH2中設置有對應的一個透明導電接墊242,且每個透明導電接墊242直接連接對應的一個第二金屬接墊232。一個第一金屬接墊222透過多個第二金屬接墊232而電性連接至多個透明導電接墊242。The transparent conductive layer 240 is located in the second through hole TH2 of the second insulating layer I2 and directly connected to the second metal pad 232 . The manufacturing method of the transparent conductive layer 240 includes, for example, a lithography etching process. In this embodiment, the transparent conductive layer 240 includes a plurality of transparent conductive pads 242 , a corresponding transparent conductive pad 242 is disposed in each second through hole TH2 , and each transparent conductive pad 242 is directly connected to the corresponding one A second metal pad 232 . A first metal pad 222 is electrically connected to a plurality of transparent conductive pads 242 through a plurality of second metal pads 232 .

在本實施例中,第一接合區204A上之第一金屬層220(一個第一金屬接墊222)、第二金屬層230(多個第二金屬接墊232)以及透明導電層240(多個透明導電接墊242)構成第一接墊P1,第二接合區204B上之第一金屬層220(一個第一金屬接墊222)、第二金屬層230(多個第二金屬接墊232)以及透明導電層240(多個透明導電接墊242)構成第二接墊P2。第一接墊P1於基板200上的垂直投影面積大於或等於40000平方微米,且第二接墊P2於基板200上的垂直投影面積大於或等於40000平方微米。In this embodiment, the first metal layer 220 (a first metal pad 222 ), the second metal layer 230 (a plurality of second metal pads 232 ) and the transparent conductive layer 240 (a plurality of second metal pads 232 ) on the first bonding region 204A transparent conductive pads 242) constitute the first pad P1, the first metal layer 220 (one first metal pad 222) and the second metal layer 230 (a plurality of second metal pads 232) on the second bonding region 204B ) and the transparent conductive layer 240 (a plurality of transparent conductive pads 242 ) constitute the second pad P2 . The vertical projected area of the first pads P1 on the substrate 200 is greater than or equal to 40000 square micrometers, and the vertical projected area of the second pads P2 on the substrate 200 is greater than or equal to 40000 square micrometers.

透明導電層240凸出第二絕緣層I2的上表面F3。在本實施例中,在第一接合區204A與第二接合區204B上,透明導電層240的上表面F4共形於第二絕緣層I2之高低起伏的上表面F3。在本實施例中,在第一接合區204A與第二接合區204B上,透明導電層240的上表面F4最遠離基板200的部分與第二絕緣層I2的上表面F3最靠近基板200的部分具有高度差HD,其中高度差HD為3200埃至4200埃。The transparent conductive layer 240 protrudes from the upper surface F3 of the second insulating layer I2. In this embodiment, on the first bonding region 204A and the second bonding region 204B, the upper surface F4 of the transparent conductive layer 240 is conformal to the undulating upper surface F3 of the second insulating layer I2 . In this embodiment, on the first bonding area 204A and the second bonding area 204B, the part of the upper surface F4 of the transparent conductive layer 240 farthest from the substrate 200 and the part of the upper surface F3 of the second insulating layer I2 closest to the substrate 200 Has a height difference HD, wherein the height difference HD is 3200 angstroms to 4200 angstroms.

透明導電層240構成排成點狀分佈的陣列AR的多個凸起結構。在本實施例中,凸起結構彼此分離,且每個透明導電接墊242即為一個凸起結構。在其他實施例中,每個透明導電接墊242包括多個凸起結構。點狀分佈的凸起結構可以提升第一接墊P1與天線基板10之間的摩擦力以及第二接墊P2與天線基板10之間的摩擦力,藉此改善電路裝置20與天線基板10在加壓接合時發生滑動的問題。The transparent conductive layer 240 forms a plurality of protruding structures arranged in a dot-like array AR. In this embodiment, the protruding structures are separated from each other, and each transparent conductive pad 242 is a protruding structure. In other embodiments, each transparent conductive pad 242 includes a plurality of raised structures. The point-like distribution of the protruding structures can improve the friction between the first pad P1 and the antenna substrate 10 and the friction between the second pad P2 and the antenna substrate 10 , thereby improving the relationship between the circuit device 20 and the antenna substrate 10 . The problem of slippage occurs during pressurized engagement.

透明導電層240例如為銦錫氧化物、銦鋅氧化物、鋁錫氧化物、鋁鋅氧化物、銦鎵鋅氧化物、或是上述至少二者之堆疊層。The transparent conductive layer 240 is, for example, indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, or a stacked layer of at least two of the above.

各凸起結構(透明導電接墊242)朝外的表面F4與第二絕緣層I2的上表面F3之間的夾角θ為30度至60度。各凸起結構(透明導電接墊242)的頂面寬度W1大於或等於相鄰兩個凸起結構(透明導電接墊242)底部之間的距離W2。藉此能使電路裝置20與天線基板10之間具有較大的接合面積。在一些實施例中,各凸起結構(透明導電接墊242)的頂面寬度W1比上相鄰兩個凸起結構底部之間的距離W2為1:1至2:1。舉例來說,頂面寬度W1為20微米至60微米,距離W2為10微米至60微米。The included angle θ between the outward facing surface F4 of each protruding structure (transparent conductive pad 242 ) and the upper surface F3 of the second insulating layer I2 is 30 degrees to 60 degrees. The top surface width W1 of each protruding structure (transparent conductive pad 242 ) is greater than or equal to the distance W2 between the bottoms of two adjacent protruding structures (transparent conductive pad 242 ). Thereby, a larger bonding area can be provided between the circuit device 20 and the antenna substrate 10 . In some embodiments, the width W1 of the top surface of each raised structure (transparent conductive pad 242 ) is 1:1 to 2:1 to the distance W2 between the bottoms of two adjacent raised structures. For example, the top surface width W1 is 20 to 60 microns, and the distance W2 is 10 to 60 microns.

在本實施例中,凸起結構之間具有相連的網狀排膠溝槽MT,且網狀排膠溝槽MT於陣列AR的側面以及正面開放。在本實施例中,網狀排膠溝槽MT的寬度約等於相鄰兩個凸起結構底部之間的距離W2。在本實施例中,當天線基板10與電路裝置20接合時,網狀排膠溝槽MT可以作為導電黏著層300A、300B的溢流通道,使多餘的導電黏著層300A、300B可以沿著網狀排膠溝槽MT排除。In this embodiment, the protruding structures are connected with a mesh-shaped glue removal groove MT, and the mesh-shaped glue removal groove MT is open on the side and the front of the array AR. In this embodiment, the width of the mesh-shaped glue removal groove MT is approximately equal to the distance W2 between the bottoms of two adjacent raised structures. In this embodiment, when the antenna substrate 10 is joined to the circuit device 20 , the mesh-shaped glue removal groove MT can be used as an overflow channel for the conductive adhesive layers 300A and 300B, so that the redundant conductive adhesive layers 300A and 300B can pass along the mesh. Shaped degassing groove MT exclusion.

基於上述,第一金屬接墊222直接連接多個第二金屬接墊232,並透過多個第二金屬接墊232而電性連接至多個透明導電接墊242,因此,多個第二金屬接墊232之間的空隙以及多個透明導電接墊242之間的空隙可以避免接墊在接合區彎曲後出現破裂的問題,藉此提升接合製程的良率。Based on the above, the first metal pads 222 are directly connected to the plurality of second metal pads 232, and are electrically connected to the plurality of transparent conductive pads 242 through the plurality of second metal pads 232. Therefore, the plurality of second metal pads 242 The gaps between the pads 232 and the plurality of transparent conductive pads 242 can prevent the pads from cracking after the bonding area is bent, thereby improving the yield of the bonding process.

圖4A是依照本發明的一實施例的一種天線裝置的剖面示意圖。為了方便說明,圖4A省略繪示了電路區上的部份元件。圖4B是圖4A的電路裝置的第一接合區的仰視示意圖。在此必須說明的是,圖4A和圖4B的實施例沿用圖3A和圖3B的實施例的元件標號與部分內容,其中採用相同或近似的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例,在此不贅述。4A is a schematic cross-sectional view of an antenna device according to an embodiment of the present invention. For convenience of description, FIG. 4A omits and illustrates some components on the circuit area. FIG. 4B is a schematic bottom view of the first bonding area of the circuit arrangement of FIG. 4A . It must be noted here that the embodiments of FIGS. 4A and 4B use the element numbers and part of the content of the embodiments of FIGS. 3A and 3B , wherein the same or similar numbers are used to represent the same or similar elements, and the same elements are omitted. Description of technical content. For the description of the omitted part, reference may be made to the foregoing embodiments, which will not be repeated here.

圖4A的天線裝置3與圖3A的天線裝置2的主要差異在於:圖4A的電路裝置20a中,一個透明導電接墊242直接連接多個第二金屬接墊232,且透過多個第二金屬接墊232而電性連接至多個第一金屬接墊222。The main difference between the antenna device 3 of FIG. 4A and the antenna device 2 of FIG. 3A is that in the circuit device 20a of FIG. 4A , a transparent conductive pad 242 is directly connected to the plurality of second metal pads 232 and passes through the plurality of second metal pads The pads 232 are electrically connected to the plurality of first metal pads 222 .

請參考圖4A與圖4B,在本實施例中,第一接合區204A上之第一金屬層220包括彼此分離的多個第一金屬接墊222,且第一接合區204A上之透明導電層240包括一個透明導電接墊242;第二接合區204B上之第一金屬層220包括彼此分離的多個第一金屬接墊222,且第二接合區204B上之透明導電層240包括一個透明導電接墊242。Referring to FIGS. 4A and 4B , in this embodiment, the first metal layer 220 on the first bonding area 204A includes a plurality of first metal pads 222 separated from each other, and the transparent conductive layer on the first bonding area 204A 240 includes a transparent conductive pad 242; the first metal layer 220 on the second bonding area 204B includes a plurality of first metal pads 222 separated from each other, and the transparent conductive layer 240 on the second bonding area 204B includes a transparent conductive Pad 242 .

第一接合區204A上之第一金屬層220(多個第一金屬接墊222)、第二金屬層230(多個第二金屬接墊232)以及透明導電層240(一個透明導電接墊242)構成第一接墊P1,第二接合區204B上之第一金屬層220(多個第一金屬接墊222)、第二金屬層230(多個第二金屬接墊232)以及透明導電層240(一個透明導電接墊242)構成第二接墊P2。The first metal layer 220 (a plurality of first metal pads 222 ), the second metal layer 230 (a plurality of second metal pads 232 ), and the transparent conductive layer 240 (one transparent conductive pad 242 ) on the first bonding region 204A ) constitute the first pad P1, the first metal layer 220 (a plurality of first metal pads 222 ), the second metal layer 230 (a plurality of second metal pads 232 ) and the transparent conductive layer on the second bonding region 204B 240 (a transparent conductive pad 242) constitutes the second pad P2.

在本實施例中,透明導電層240構成排成點狀分佈的陣列AR的多個凸起結構242a。在本實施例中,第一接合區204A上之凸起結構242a彼此相連,且每個透明導電接墊242包括多個凸起結構242a。點狀分佈的凸起結構242a可以提升第一接墊P1與天線基板10之間的摩擦力以及第二接墊P2與天線基板10之間的摩擦力,藉此改善電路裝置20a與天線基板10在加壓接合時發生滑動錯位的問題。In this embodiment, the transparent conductive layer 240 forms a plurality of protruding structures 242a arranged in a dot-like array AR. In this embodiment, the protruding structures 242a on the first bonding area 204A are connected to each other, and each transparent conductive pad 242 includes a plurality of protruding structures 242a. The protruding structures 242a distributed in dots can enhance the friction force between the first pad P1 and the antenna substrate 10 and the friction force between the second pad P2 and the antenna substrate 10, thereby improving the circuit device 20a and the antenna substrate 10 The problem of sliding misalignment occurs during press engagement.

在本實施例中,在第一接合區204A與第二接合區204B上,於垂直基板200的方向E1上,第二金屬接墊232的上表面F2與第二絕緣層I2的上表面F3凸起之部分之間的厚度T5為1750埃至3300埃。在第一接合區204A與第二接合區204B上,凸起結構242a的表面F4最遠離基板200的部分與凸起結構242a的表面F4最靠近基板200的部分具有高度差HD,其中高度差HD為4700埃至5700埃。In this embodiment, on the first bonding region 204A and the second bonding region 204B, in the direction E1 perpendicular to the substrate 200 , the upper surface F2 of the second metal pad 232 and the upper surface F3 of the second insulating layer I2 are convex The thickness T5 between the rising portions is 1750 angstroms to 3300 angstroms. On the first bonding area 204A and the second bonding area 204B, a portion of the surface F4 of the raised structure 242a farthest from the substrate 200 and a portion of the surface F4 of the raised structure 242a closest to the substrate 200 have a height difference HD, wherein the height difference HD 4700 angstroms to 5700 angstroms.

各凸起結構242a朝外的表面F4與第二絕緣層I2的上表面F3之間的夾角θ為30度至60度。各凸起結構242a的頂面寬度W1大於或等於相鄰兩個凸起結構242A底部之間的距離W2。藉此能使電路裝置20A與天線基板10之間具有較大的接合面積。在一些實施例中,各凸起結構的頂面寬度比上相鄰兩個凸起結構底部之間的距離為1:1至2:1。舉例來說,頂面寬度W1為20微米至60微米,距離W2為10微米至60微米。The angle θ between the outward facing surface F4 of each protruding structure 242a and the upper surface F3 of the second insulating layer I2 is 30 degrees to 60 degrees. The width W1 of the top surface of each protruding structure 242a is greater than or equal to the distance W2 between the bottoms of two adjacent protruding structures 242A. Thereby, it is possible to have a large bonding area between the circuit device 20A and the antenna substrate 10 . In some embodiments, the ratio of the width of the top surface of each protruding structure to the distance between the bottoms of two adjacent protruding structures is 1:1 to 2:1. For example, the top surface width W1 is 20 to 60 microns, and the distance W2 is 10 to 60 microns.

在本實施例中,凸起結構之間具有相連的網狀排膠溝槽MT,且網狀排膠溝槽MT於陣列AR的側面以及正面開放。在本實施例中,網狀排膠溝槽MT的寬度約等於相鄰兩個凸起結構底部之間的距離W2。在本實施例中,當天線基板10與電路裝置20接合時,網狀排膠溝槽MT可以作為導電黏著層300A、300B的溢流通道,使多餘的導電黏著層300A、300B可以沿著網狀排膠溝槽MT排除。In this embodiment, the protruding structures are connected with a mesh-shaped glue removal groove MT, and the mesh-shaped glue removal groove MT is open on the side and the front of the array AR. In this embodiment, the width of the mesh-shaped glue removal groove MT is approximately equal to the distance W2 between the bottoms of two adjacent raised structures. In this embodiment, when the antenna substrate 10 is joined to the circuit device 20 , the mesh-shaped glue removal groove MT can be used as an overflow channel for the conductive adhesive layers 300A and 300B, so that the redundant conductive adhesive layers 300A and 300B can pass along the mesh. Shaped degassing groove MT exclusion.

在本實施例中,兩個主動元件T的汲極D分別直接連接至第一接合區204A上的第一金屬接墊222以及第二接合區204B上的第一金屬接墊222。In this embodiment, the drains D of the two active elements T are directly connected to the first metal pads 222 on the first bonding region 204A and the first metal pads 222 on the second bonding region 204B, respectively.

基於上述,透明導電接墊242直接連接多個第二金屬接墊232,並透過多個第二金屬接墊232而電性連接至多個第一金屬接墊222,因此,多個第二金屬接墊232之間的空隙以及多個第一金屬接墊222之間的空隙可以避免接墊在接合區彎曲後出現破裂的問題,藉此提升接合製程的良率。Based on the above, the transparent conductive pads 242 are directly connected to the plurality of second metal pads 232, and are electrically connected to the plurality of first metal pads 222 through the plurality of second metal pads 232. Therefore, the plurality of second metal pads 222 The gaps between the pads 232 and the gaps between the plurality of first metal pads 222 can avoid the problem of cracking of the pads after the bonding area is bent, thereby improving the yield of the bonding process.

圖5是依照本發明的一實施例的一種電路裝置的仰視示意圖。在此必須說明的是,圖5的實施例沿用圖2的實施例的元件標號與部分內容,其中採用相同或近似的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例,在此不贅述。5 is a schematic bottom view of a circuit device according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 5 uses the element numbers and part of the content of the embodiment of FIG. 2 , wherein the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, which will not be repeated here.

圖5的電路裝置20b與圖2的電路裝置20的主要差異在於:圖5的電路裝置20b中,基板200更包括第三接合區204C與第四接合區204D,第一接合區204A與第三接合區204C位於電路區202的同一側,且第二接合區204B與第四接合區204D位於電路區202的同一側。The main difference between the circuit device 20b in FIG. 5 and the circuit device 20 in FIG. 2 is that in the circuit device 20b in FIG. 5 , the substrate 200 further includes a third bonding area 204C and a fourth bonding area 204D, and the first bonding area 204A and the third bonding area 204A. The bonding pads 204C are located on the same side of the circuit region 202 , and the second bonding pads 204B and the fourth bonding pads 204D are positioned on the same side of the circuit region 202 .

在本實施例中,第一接合區204A、第二接合區204B、第三接合區204C與第四接合區204D上分別包括第一接墊(圖5省略繪出)、第二接墊(圖5省略繪出)、第三接墊(圖5省略繪出)與第四接墊(圖5省略繪出),其中第一接墊、第二接墊、第三接墊與第四接墊的結構類似於前述任一實施例中的第一接墊與第二接墊,於此不再贅述。In this embodiment, the first bonding area 204A, the second bonding area 204B, the third bonding area 204C and the fourth bonding area 204D respectively include a first pad (not shown in FIG. 5 ) and a second pad ( FIG. 5 ). 5 is omitted), the third pad (not shown in Figure 5) and the fourth pad (not shown in Figure 5), wherein the first pad, the second pad, the third pad and the fourth pad The structure is similar to the first pad and the second pad in any of the foregoing embodiments, and will not be repeated here.

綜上所述,第一金屬接墊直接連接多個第二金屬接墊,並透過多個第二金屬接墊而電性連接至多個透明導電接墊;或透明導電接墊直接連接多個第二金屬接墊,並透過多個第二金屬接墊而電性連接至多個第一金屬接墊。因此,金屬接墊之間的空隙及/或透明導電接墊之間的空隙可以避免接墊在接合區彎曲後出現破裂的問題,藉此提升接合製程的良率。另外,透明導電接墊構成之點狀分佈的凸起結構可以改善電路裝置與其他裝置在加壓接合時發生滑動錯位的問題,且透明導電接墊上的網狀排膠溝槽可以作為導電黏著層的溢流通道,使多餘的導電黏著層可以沿著網狀排膠溝槽排除。To sum up, the first metal pads are directly connected to the plurality of second metal pads, and are electrically connected to the plurality of transparent conductive pads through the plurality of second metal pads; or the transparent conductive pads are directly connected to the plurality of first metal pads. Two metal pads are electrically connected to the plurality of first metal pads through the plurality of second metal pads. Therefore, the gaps between the metal pads and/or the gaps between the transparent conductive pads can avoid the problem of cracking of the pads after the bonding area is bent, thereby improving the yield of the bonding process. In addition, the dot-shaped raised structures formed by the transparent conductive pads can improve the problem of sliding dislocation when the circuit device and other devices are press-bonded, and the mesh-shaped glue-removing grooves on the transparent conductive pads can be used as a conductive adhesive layer The overflow channel allows the excess conductive adhesive layer to be drained along the mesh-shaped glue removal groove.

1、2:天線裝置 10:天線基板 20、20a、20b:電路裝置 100、200:基板 110:天線 120A:第一天線接墊 120B:第二天線接墊 202:電路區 204A:第一接合區 204B:第二接合區 204C:第三接合區 204D:第四接合區 210:驅動電路 212:數位電路 214:整流器 216:分頻器 220:第一金屬層 222:第一金屬接墊 230:第二金屬層 232:第二金屬接墊 240:透明導電層 242:透明導電接墊 242a:凸起結構 300A、300B:導電黏著層 AR:陣列 CH:多晶矽層 CH1:源極區 CH2:通道區 CH3:汲極區 D:汲極 E1:方向 F1、F2、F3、F4:表面 I1:第一絕緣層 I2:第二絕緣層 G:閘極 GI:閘極絕緣層 HD:高度差 O1、O2、O3:開口 P1:第一接墊 P2:第二接墊 S:源極 T:主動元件 T1、T2、T3、T4、T5:厚度 TH1:第一通孔 TH2:第二通孔 MT:網狀排膠溝槽 W1:寬度 W2:距離 θ:夾角1, 2: Antenna device 10: Antenna substrate 20, 20a, 20b: circuit arrangement 100, 200: substrate 110: Antenna 120A: first antenna pad 120B: The second antenna pad 202: Circuit Area 204A: First bonding area 204B: Second junction area 204C: Third Junction Zone 204D: Fourth Junction Zone 210: Drive circuit 212: Digital Circuits 214: Rectifier 216: Divider 220: first metal layer 222: first metal pad 230: second metal layer 232: Second metal pad 240: transparent conductive layer 242: Transparent conductive pad 242a: Raised structure 300A, 300B: conductive adhesive layer AR: Array CH: polysilicon layer CH1: source region CH2: Channel area CH3: drain region D: drain E1: Direction F1, F2, F3, F4: Surface I1: first insulating layer I2: Second insulating layer G: gate GI: gate insulating layer HD: Height difference O1, O2, O3: Opening P1: first pad P2: Second pad S: source T: Active element T1, T2, T3, T4, T5: Thickness TH1: first through hole TH2: second through hole MT: mesh degumming groove W1: width W2: Distance θ: included angle

圖1是依照本發明的一實施例的一種天線裝置的俯視示意圖。 圖2是依照本發明的一實施例的一種電路裝置的仰視示意圖。 圖3A是依照本發明的一實施例的一種天線裝置的剖面示意圖。 圖3B是圖3A的電路裝置的第一接合區的仰視示意圖。 圖4A是依照本發明的一實施例的一種天線裝置的剖面示意圖。 圖4B是圖4A的電路裝置的第一接合區的仰視示意圖。 圖5是依照本發明的一實施例的一種電路裝置的仰視示意圖。FIG. 1 is a schematic top view of an antenna device according to an embodiment of the present invention. FIG. 2 is a schematic bottom view of a circuit device according to an embodiment of the present invention. 3A is a schematic cross-sectional view of an antenna device according to an embodiment of the present invention. 3B is a schematic bottom view of the first bonding area of the circuit arrangement of FIG. 3A. 4A is a schematic cross-sectional view of an antenna device according to an embodiment of the present invention. FIG. 4B is a schematic bottom view of the first bonding area of the circuit arrangement of FIG. 4A . 5 is a schematic bottom view of a circuit device according to an embodiment of the present invention.

2:天線裝置2: Antenna device

10:天線基板10: Antenna substrate

20:電路裝置20: Circuit device

100、200:基板100, 200: substrate

110:天線110: Antenna

120A:第一天線接墊120A: first antenna pad

120B:第二天線接墊120B: The second antenna pad

202:電路區202: Circuit Area

204A:第一接合區204A: First bonding area

204B:第二接合區204B: Second junction area

220:第一金屬層220: first metal layer

222:第一金屬接墊222: first metal pad

230:第二金屬層230: second metal layer

232:第二金屬接墊232: Second metal pad

240:透明導電層240: transparent conductive layer

242:透明導電接墊242: Transparent conductive pad

300A、300B:導電黏著層300A, 300B: conductive adhesive layer

AR:陣列AR: Array

CH:多晶矽層CH: polysilicon layer

CH1:源極區CH1: source region

CH2:通道區CH2: Channel area

CH3:汲極區CH3: drain region

D:汲極D: drain

E1:方向E1: Direction

F1、F2、F3、F4:表面F1, F2, F3, F4: Surface

I1:第一絕緣層I1: first insulating layer

I2:第二絕緣層I2: Second insulating layer

G:閘極G: gate

GI:閘極絕緣層GI: gate insulating layer

HD:高度差HD: Height difference

O1、O2、O3:開口O1, O2, O3: Opening

P1:第一接墊P1: first pad

P2:第二接墊P2: Second pad

S:源極S: source

T:主動元件T: Active element

T1、T2、T3、T4:厚度T1, T2, T3, T4: Thickness

TH1:第一通孔TH1: first through hole

TH2:第二通孔TH2: second through hole

W1:寬度W1: width

W2:距離W2: Distance

θ:夾角θ: included angle

Claims (11)

一種電路裝置,包括: 一基板,具有一電路區以及一第一接合區; 一驅動電路,位於該電路區上; 一第一金屬層,位於該第一接合區上,且電性連接至該驅動電路; 一第一絕緣層,位於該第一金屬層上,且具有重疊於該第一金屬層的多個第一通孔; 多個第二金屬接墊,位於該些第一通孔中,且該些第二金屬接墊凸出該第一絕緣層的上表面; 一第二絕緣層,位於該些第二金屬接墊上,且具有重疊於該些第二金屬接墊的多個第二通孔;以及 一透明導電層,位於該些第二通孔中,且該透明導電層凸出該第二絕緣層的上表面,其中: 該第一金屬層包括直接連接該些第二金屬接墊的一第一金屬接墊,且該第一金屬接墊透過該些第二金屬接墊而電性連接至該透明導電層中的多個透明導電接墊;或 該透明導電層包括直接連接該些第二金屬接墊的一透明導電接墊,且該透明導電接墊透過該些第二金屬接墊而電性連接至該第一金屬層中的多個第一金屬接墊。A circuit arrangement comprising: a substrate having a circuit area and a first bonding area; a drive circuit, located on the circuit area; a first metal layer located on the first bonding area and electrically connected to the driving circuit; a first insulating layer located on the first metal layer and having a plurality of first through holes overlapping the first metal layer; a plurality of second metal pads located in the first through holes, and the second metal pads protrude from the upper surface of the first insulating layer; a second insulating layer on the second metal pads and having a plurality of second through holes overlapping the second metal pads; and A transparent conductive layer located in the second through holes, and the transparent conductive layer protrudes from the upper surface of the second insulating layer, wherein: The first metal layer includes a first metal pad directly connected to the second metal pads, and the first metal pad is electrically connected to a plurality of the transparent conductive layer through the second metal pads transparent conductive pads; or The transparent conductive layer includes a transparent conductive pad directly connected to the second metal pads, and the transparent conductive pad is electrically connected to a plurality of first metal pads in the first metal layer through the second metal pads a metal pad. 如請求項1所述的電路裝置,其中該基板為可撓性基板。The circuit device of claim 1, wherein the substrate is a flexible substrate. 如請求項1所述的電路裝置,其中該驅動電路包括一整流器,且該整流器包括一主動元件,其中該第一金屬層或該第二金屬層電性連接該主動元件。The circuit device of claim 1, wherein the driving circuit includes a rectifier, and the rectifier includes an active element, wherein the first metal layer or the second metal layer is electrically connected to the active element. 如請求項1所述的電路裝置,其中該些第二金屬接墊排列成點狀分佈的陣列。The circuit device of claim 1, wherein the second metal pads are arranged in a dot-like array. 如請求項1所述的電路裝置,其中該透明導電層構成排成點狀分佈的陣列的多個凸起結構,且各該凸起結構朝外的表面與該第二絕緣層的該上表面之間的夾角為30度至60度。The circuit device according to claim 1, wherein the transparent conductive layer forms a plurality of protruding structures arranged in a dot-like array, and the outward facing surface of each protruding structure and the upper surface of the second insulating layer The angle between them is 30 degrees to 60 degrees. 如請求項1所述的電路裝置,其中該透明導電層構成排成點狀分佈的陣列的多個凸起結構,各該凸起結構的頂面寬度大於或等於相鄰兩個該些凸起結構底部之間的距離。The circuit device according to claim 1, wherein the transparent conductive layer forms a plurality of protruding structures arranged in a dot-like array, and the top surface width of each protruding structure is greater than or equal to two adjacent protruding structures The distance between the bottoms of the structures. 如請求項6所述的電路裝置,其中各該凸起結構的頂面寬度比上相鄰兩個該些凸起結構底部之間的距離為1:1至2:1。The circuit device of claim 6, wherein the width of the top surface of each protruding structure is 1:1 to 2:1 compared to the distance between the bottoms of two adjacent protruding structures. 如請求項1所述的電路裝置,其中該透明導電層構成排成點狀分佈的陣列的多個凸起結構,且該些凸起結構之間具有相連的網狀排膠溝槽,且該網狀排膠溝槽於該陣列的側面以及正面開放。The circuit device as claimed in claim 1, wherein the transparent conductive layer forms a plurality of protruding structures arranged in a dot-like array, and there are connected mesh-like degassing grooves between the protruding structures, and the Mesh degumming grooves are open on the sides and front of the array. 如請求項1所述的電路裝置,其中該第一接合區上之該第一金屬層、該透明導電層以及該第二金屬層構成一第一接墊,且該第一接墊於該基板上的垂直投影面積大於或等於40000平方微米。The circuit device of claim 1, wherein the first metal layer, the transparent conductive layer and the second metal layer on the first bonding area constitute a first pad, and the first pad is on the substrate The vertical projected area on is greater than or equal to 40,000 square microns. 如請求項1所述的電路裝置,其中該基板為長條狀,該基板更包括一第二接合區,且該第一接合區與該第二接合區分別位於該電路區的相對兩側。The circuit device according to claim 1, wherein the substrate is elongated, the substrate further includes a second bonding area, and the first bonding area and the second bonding area are respectively located on opposite sides of the circuit area. 如請求項10所述的電路裝置,其中該基板更包括一第三接合區與一第四接合區,該第一接合區與該第三接合區位於該電路區的同一側,且該第二接合區與該第四接合區位於該電路區的同一側。The circuit device of claim 10, wherein the substrate further comprises a third bonding area and a fourth bonding area, the first bonding area and the third bonding area are located on the same side of the circuit area, and the second bonding area The bonding area and the fourth bonding area are located on the same side of the circuit area.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120154690A1 (en) * 2010-12-16 2012-06-21 Qualcomm Mems Technologies, Inc. Flexible integrated circuit device layers and processes
US20170278782A1 (en) * 2010-06-29 2017-09-28 General Electric Company Electrical interconnect for an integrated circuit package and method of making same
US20190148213A1 (en) * 2017-11-13 2019-05-16 Au Optronics Corporation Transfer device
US20190221535A1 (en) * 2018-01-18 2019-07-18 Samsung Electronics Co., Ltd. Semiconductor device

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1723587A (en) * 2002-11-07 2006-01-18 碎云股份有限公司 Integrated circuit package including miniature antenna
KR100539229B1 (en) * 2003-01-30 2005-12-27 삼성전자주식회사 Semiconductor memory device including a dual port
WO2005076281A1 (en) * 2004-02-10 2005-08-18 Semiconductor Energy Laboratory Co., Ltd. Nonvolatile memory
CN100449734C (en) * 2004-03-16 2009-01-07 松下电器产业株式会社 Semiconductor device
JP4768379B2 (en) * 2005-09-28 2011-09-07 富士通株式会社 RFID tag
KR101195959B1 (en) * 2008-09-10 2012-11-05 가부시키가이샤 어드밴티스트 Memory device, method for manufacturing memory device, and method for writing data
KR101548674B1 (en) * 2009-08-26 2015-09-01 삼성전자주식회사 3 Three dimensional semiconductor memory device and method for fabricating the same
US9224084B2 (en) * 2009-04-01 2015-12-29 Vanguard Identification Systems, Inc. Smart device programmable electronic luggage tag
JP2011114633A (en) * 2009-11-27 2011-06-09 Fujitsu Ltd Antenna device and system including the same
KR101928897B1 (en) * 2010-08-27 2018-12-13 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Memory device and semiconductor device
TWI419094B (en) * 2010-09-10 2013-12-11 Au Optronics Corp Flexible display panel
US8618614B2 (en) * 2010-12-14 2013-12-31 Sandisk 3D Llc Continuous mesh three dimensional non-volatile storage with vertical select devices
US8723343B2 (en) * 2011-03-14 2014-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. Sensor with energy-harvesting device
JP2013017310A (en) * 2011-07-04 2013-01-24 Sumitomo Heavy Ind Ltd Electric power conversion system
JP5777096B2 (en) * 2011-07-21 2015-09-09 株式会社スマート Universal IC tag, its manufacturing method, and communication management system
JP5981711B2 (en) * 2011-12-16 2016-08-31 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method of semiconductor device
US9553476B2 (en) * 2012-03-23 2017-01-24 Lg Innotek Co., Ltd. Antenna assembly and method for manufacturing same
ITTO20120477A1 (en) * 2012-05-31 2013-12-01 St Microelectronics Srl NETWORK OF ELECTRONIC DEVICES FIXED TO A FLEXIBLE SUPPORT AND RELATIVE COMMUNICATION METHOD
US9601557B2 (en) * 2012-11-16 2017-03-21 Apple Inc. Flexible display
CN103927579B (en) * 2013-01-11 2017-10-17 深圳市金溢科技股份有限公司 A kind of ultra-thin bend resistance electronic tag
CN104267858B (en) * 2014-06-20 2017-07-14 敦泰电子有限公司 Sensing chip, manufacturing method thereof and electronic device provided with sensing chip
WO2016035771A1 (en) * 2014-09-01 2016-03-10 株式会社イーガルド Contactless information communication terminal unit, card-type device, portable telephone, and wearable device
US10902310B2 (en) * 2016-12-14 2021-01-26 Trackonomy Systems, Inc. Wireless communications and transducer based event detection platform
US10445634B2 (en) * 2016-12-14 2019-10-15 Trackonomy Systems, Inc. Fabricating multifunction adhesive product for ubiquitous realtime tracking
CN109638023A (en) * 2019-02-28 2019-04-16 昆山国显光电有限公司 A kind of array substrate, display panel and film layer crack detecting method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170278782A1 (en) * 2010-06-29 2017-09-28 General Electric Company Electrical interconnect for an integrated circuit package and method of making same
US20120154690A1 (en) * 2010-12-16 2012-06-21 Qualcomm Mems Technologies, Inc. Flexible integrated circuit device layers and processes
US20190148213A1 (en) * 2017-11-13 2019-05-16 Au Optronics Corporation Transfer device
US20190221535A1 (en) * 2018-01-18 2019-07-18 Samsung Electronics Co., Ltd. Semiconductor device

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