TWI758204B - Semiconductor package - Google Patents

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TWI758204B
TWI758204B TW110124366A TW110124366A TWI758204B TW I758204 B TWI758204 B TW I758204B TW 110124366 A TW110124366 A TW 110124366A TW 110124366 A TW110124366 A TW 110124366A TW I758204 B TWI758204 B TW I758204B
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substrate
semiconductor package
connection
adhesive layer
conductive adhesive
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TW110124366A
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Chinese (zh)
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TW202249198A (en
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張光漢
蕭宇良
楊智安
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聯發科技股份有限公司
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Priority claimed from US17/336,331 external-priority patent/US11694972B2/en
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Publication of TW202249198A publication Critical patent/TW202249198A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

A semiconductor package includes a substrate, a semiconductor die mounted on the substrate, and a heatsink over the semiconductor die. The heatsink includes a roof portion and at least one connecting portion extending between the roof portion and the substrate. The at least one connecting portion includes a connection lead mounted on a connection pad of the substrate. The connection pad includes a first portion and a second portion spaced apart from each other, which are configured to electrically couple to different voltage signals, respectively, for detecting heatsink floating.

Description

半導體封裝 Semiconductor packaging

本發明半導體技術領域，尤其涉及一種半導體封裝。 The present invention relates to the field of semiconductor technology, in particular to a semiconductor package.

具有高連接能力的VLSI(超大型積體電路，Very Large Scale Integration)積體電路封裝有引腳網格陣列(pin grid array，PGA)和球柵陣列(ball grid array，BGA)。一種這樣的封裝類型是塑料球柵陣列(PBGA)。與傳統封裝相比，PBGA具有許多優勢，例如焊球I/O和高速度。由於訊號轉換路徑較短，PBGA封裝具有較高的速度。焊球以矩陣陣列的形式設置在封裝表面，可以提供更多的訊號觸點或訊號接觸。 VLSI (Very Large Scale Integration) ICs with high connectivity are packaged in pin grid arrays (PGA) and ball grid arrays (BGA). One such package type is the Plastic Ball Grid Array (PBGA). PBGAs offer many advantages over traditional packaging, such as solder ball I/O and high speed. The PBGA package has higher speed due to the shorter signal conversion path. The solder balls are arranged on the surface of the package in the form of a matrix array, which can provide more signal contacts or signal contacts.

當PBGA產品工作時，積體電路晶片中會產生相當多的熱量。通常，安裝散熱器以有效地將熱量散發到外部。此外，散熱器表現出電磁(electromagnetic，EM)遮蔽的接地效應。然而，傳統上難以偵測的散熱器浮動可能會降低PBGA產品的散熱效率和EM遮蔽性能。因此，業界需要提供一種改進的具有散熱器的半導體封裝，能夠在最終測試期間偵測散熱器浮動。 When a PBGA product is in operation, a considerable amount of heat is generated in the integrated circuit die. Typically, heat sinks are installed to efficiently dissipate heat to the outside. In addition, the heat sink exhibits electromagnetic (EM) shielding grounding effects. However, the traditionally difficult to detect heat sink float may reduce the thermal efficiency and EM shielding performance of PBGA products. Therefore, there is a need in the industry to provide an improved semiconductor package with a heat sink capable of detecting heat sink float during final testing.

有鑑於此，本發明提供一種具有散熱器的改進的半導體封裝，以解決上述問題。 In view of this, the present invention provides an improved semiconductor package with a heat spreader to solve the above problems.

根據本發明的第一方面，公開一種半導體封裝，包括：基板；半導體晶粒，安裝在該基板上；和 散熱器，在該半導體晶粒上方，其中該散熱器包括頂部和在該頂部與該基板之間延伸的至少一個連接部分，其中該至少一個連接部分包括安裝在該基板的連接焊盤上的連接引線，其中該連接焊盤包括彼此間隔開的第一部分和第二部分，該第一部分和該第二部分配置為分別電耦合到不同的電壓訊號。 According to a first aspect of the present invention, a semiconductor package is disclosed, comprising: a substrate; a semiconductor die mounted on the substrate; and a heat spreader over the semiconductor die, wherein the heat spreader includes a top portion and at least one connection portion extending between the top portion and the substrate, wherein the at least one connection portion includes connections mounted on connection pads of the substrate A lead, wherein the connection pad includes a first portion and a second portion spaced apart from each other, the first portion and the second portion being configured to be electrically coupled to different voltage signals, respectively.

本發明的半導體封裝由於包括：基板；半導體晶粒，安裝在該基板上；以及散熱器，在該半導體晶粒上方，其中該散熱器包括頂部和在該頂部與該基板之間延伸的至少一個連接部分，其中該至少一個連接部分包括安裝在該基板的連接焊盤上的連接引線，其中該連接焊盤包括彼此間隔開的第一部分和第二部分，該第一部分和該第二部分配置為分別電耦合到不同的電壓訊號。透過測試第一部分和第二部分是否浮動，可以確定散熱器是否與基板連接良好。 The semiconductor package of the present invention comprises: a substrate; a semiconductor die mounted on the substrate; and a heat sink above the semiconductor die, wherein the heat sink includes a top portion and at least one extending between the top portion and the substrate a connecting portion, wherein the at least one connecting portion includes a connecting lead mounted on a connecting pad of the substrate, wherein the connecting pad includes a first portion and a second portion spaced apart from each other, the first portion and the second portion being configured to They are respectively electrically coupled to different voltage signals. By testing whether the first and second parts float, it can be determined whether the heat sink is well connected to the substrate.

1:半導體封裝 1: Semiconductor packaging

10:半導體晶粒 10: Semiconductor die

20:散熱器 20: Radiator

30:密封劑 30: Sealant

100:基板 100: Substrate

100a:晶片側 100a: Wafer side

100b:球柵陣列側 100b: Ball grid array side

110:連接焊盤 110: Connection pad

110a:第一部分 110a: Part 1

110b:第二部分 110b: Part II

120,120a:焊球焊盤 120, 120a: Solder ball pads

130:金屬互連結構 130: Metal Interconnect Structure

140:接地平面 140: Ground plane

160:阻焊層 160: Solder mask

160a:第一阻焊層開口 160a: first solder mask opening

160b:第二阻焊層開口 160b: Second solder mask opening

201:頂部 201: Top

201a:頂面 201a: Top Surface

203:連接部分 203: Connection part

205:連接引線 205: Connect the leads

301a:第一導電黏附層 301a: the first conductive adhesive layer

301b:第二導電黏附層 301b: second conductive adhesive layer

SB:焊球 SB: Solder Ball

透過閱讀後續的詳細描述和實施例可以更全面地理解本發明，本實施例參照附圖給出，其中：圖1為本發明一實施例的半導體封裝的剖面示意圖；圖2是圖1中半導體封裝的示意性透視圖。 The present invention can be more fully understood by reading the following detailed description and embodiments, and the present embodiment is given with reference to the accompanying drawings, wherein: FIG. 1 is a schematic cross-sectional view of a semiconductor package according to an embodiment of the present invention; Schematic perspective view of the package.

在下面對本發明的實施例的詳細描述中，參考了附圖，這些附圖構成了本發明的一部分，並且在附圖中透過圖示的方式示出了可以實踐本發明的特定的優選實施例。對這些實施例進行了足夠詳細的描述，以使所屬技術領域具有通常知識者能夠實踐它們，並且應當理解，在不脫離本發明的精神和範圍的情況下，可以利用其他實施例，並且可以進行機械，結構和程式上的改變。 本發明。因此，以下詳細描述不應被理解為限制性的，並且本發明的實施例的範圍僅由所附申請專利範圍限定。 In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof, and in which there are shown, by way of illustration, specific preferred embodiments in which the invention may be practiced . These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice them, and it should be understood that other embodiments may be utilized, and Mechanical, structural and procedural changes. this invention. Therefore, the following detailed description should not be construed as limiting, and the scope of embodiments of the present invention is limited only by the scope of the appended claims.

將理解的是，儘管術語“第一”、“第二”、“第三”、“主要”、“次要”等在本文中可用於描述各種元件、組件、區域、層和/或部分，但是這些元件、組件、區域、這些層和/或部分不應受到這些術語的限制。這些術語僅用於區分一個元素，組件，區域，層或部分與另一區域，層或部分。因此，在不脫離本發明構思的教導的情況下，下面討論的第一或主要元件、組件、區域、層或部分可以稱為第二或次要元件、組件、區域、層或部分。 It will be understood that, although the terms "first," "second," "third," "primary," "secondary," etc. may be used herein to describe various elements, components, regions, layers and/or sections, However, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first or major element, component, region, layer or section discussed below could be termed a second or secondary element, component, region, layer or section without departing from the teachings of the present inventive concept.

此外，為了便於描述，本文中可以使用諸如“在...下方”、“在...之下”、“在...下”、“在...上方”、“在...之上”之類的空間相對術語，以便於描述一個元件或特徵與之的關係。如圖所示的另一元件或特徵。除了在圖中描述的方位之外，空間相對術語還意圖涵蓋設備在使用或操作中的不同方位。該裝置可以以其他方式定向(旋轉90度或以其他定向)，並且在此使用的空間相對描述語可以同樣地被相應地解釋。另外，還將理解的是，當層被稱為在兩層“之間”時，它可以是兩層之間的唯一層，或者也可以存在一個或複數個中間層。 Also, for ease of description, such terms as "under", "under", "under", "above", "over" may be used herein. Spatially relative terms such as "on" are used to describe the relationship of an element or feature to it. another element or feature as shown. In addition to the orientation depicted in the figures, spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being 'between' two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

本文所使用的術語僅出於描述特定實施例的目的，並不旨在限制本發明構思。如本文所使用的，單數形式“一個”、“一種”和“該”也旨在包括複數形式，除非上下文另外明確指出。還將理解，術語“包括”和/或“包含”在本說明書中使用時，指定存在該特徵，整數，步驟，操作，元件和/或組件，但是不排除存在或添加一個或複數個其他特徵，整數，步驟，操作，元素，組件和/或其組。如本文所使用的，術語“和/或”包括一個或複數個相關聯的所列專案的任何和所有組合，並且可以縮寫為“/”。 The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the inventive concept. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the terms "comprising" and/or "comprising" when used in this specification designate the presence of that feature, integer, step, operation, element and/or component, but do not preclude the presence or addition of one or more other features , integers, steps, operations, elements, components and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items and may be abbreviated as "/".

將理解的是，當將元件或層稱為在另一元件或層“上”，“連接至”，“耦接至”或“鄰近”時，它可以直接在其他元素或層上，與其連接，耦接或相鄰，或 者可以存在中間元素或層。相反，當元件稱為“直接在”另一元件或層“上”，“直接連接至”，“直接耦接至”或“緊鄰”另一元件或層時，則不存在中間元件或層。 It will be understood that when an element or layer is referred to as being "on," "connected to," "coupled to," or "adjacent to" another element or layer, it can be directly on, connected to, the other element or layer , coupled or adjacent, or There may be intermediate elements or layers. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to," or "immediately adjacent" another element or layer, there are no intervening elements or layers present.

注意：(i)在整個附圖中相同的特徵將由相同的附圖標記表示，並且不一定在它們出現的每個附圖中都進行詳細描述，並且(ii)一系列附圖可能顯示單個專案的不同方面，每個方面都與各種參考標籤相關聯，這些參考標籤可能會出現在整個序列中，或者可能只出現在序列的選定圖中。 Note: (i) the same features will be represented by the same reference numerals throughout the drawings and are not necessarily described in detail in each drawing in which they appear, and (ii) a series of drawings may show a single item Different aspects of , each associated with various reference labels that may appear throughout the sequence, or may only appear in selected plots of the sequence.

本發明涉及具有散熱器的改進的半導體晶片封裝，例如塑料球柵陣列(plastic ball grid array，PBGA)封裝。散熱器的連接引線安裝在基板的連接焊盤上。連接焊盤分成兩個部分，包括第一部分和第二部分，第一部分和第二部分彼此間隔開並且彼此緊鄰佈置。第一部分和第二部分被配置為分別電耦合到不同的電壓訊號，使得可以在最終測試(final testing)期間偵測到散熱器浮動(heatsink floating)。 The present invention relates to improved semiconductor wafer packages, such as plastic ball grid array (PBGA) packages, with heat spreaders. The connection leads of the heat sink are mounted on the connection pads of the substrate. The connection pad is divided into two parts, including a first part and a second part, the first part and the second part being spaced apart from each other and arranged in close proximity to each other. The first portion and the second portion are configured to be electrically coupled to different voltage signals, respectively, such that heatsink floating can be detected during final testing.

請參考圖1及圖2，圖1為本發明一實施例的半導體封裝1的剖面示意圖。圖2為圖1中半導體封裝1的立體示意圖。如圖1及圖2所示，半導體封裝1包括基板100，例如封裝基板或印刷電路基板，但不限於此。根據實施例，基板100包括晶片側100a和球柵陣列(BGA)側100b。根據實施例，半導體晶粒10安裝在基板100的晶片側100a上。 Please refer to FIG. 1 and FIG. 2 . FIG. 1 is a schematic cross-sectional view of a semiconductor package 1 according to an embodiment of the present invention. FIG. 2 is a schematic perspective view of the semiconductor package 1 in FIG. 1 . As shown in FIG. 1 and FIG. 2 , the semiconductor package 1 includes a substrate 100 , such as a package substrate or a printed circuit substrate, but is not limited thereto. According to an embodiment, the substrate 100 includes a wafer side 100a and a ball grid array (BGA) side 100b. According to an embodiment, the semiconductor die 10 is mounted on the wafer side 100a of the substrate 100 .

根據一些實施例，半導體晶粒10可以透過引線接合(wire bonding)安裝在基板100上。根據另一實施例，半導體晶粒10可以透過具有導電凸塊或導電柱結構的倒裝晶片接合方式安裝在基板100上。 According to some embodiments, the semiconductor die 10 may be mounted on the substrate 100 through wire bonding. According to another embodiment, the semiconductor die 10 may be mounted on the substrate 100 by flip-chip bonding with conductive bump or conductive pillar structures.

根據實施例，焊球焊盤120的陣列設置在基板100的BGA側100b上。根據實施例，焊球SB分別安裝在焊球焊盤120上。 According to an embodiment, an array of solder ball pads 120 is provided on the BGA side 100b of the substrate 100 . According to the embodiment, the solder balls SB are mounted on the solder ball pads 120, respectively.

如圖1和圖2所示，根據實施例，散熱器20設置在半導體晶粒10上方。諸如模塑料的密封劑30可以設置在散熱器20周圍，並且可以密封 散熱器20和基板100之間的空間，以保護半導體晶粒10。 As shown in FIGS. 1 and 2 , according to an embodiment, a heat spreader 20 is disposed over the semiconductor die 10 . An encapsulant 30 such as molding compound can be provided around the heat sink 20 and can seal The space between the heat sink 20 and the substrate 100 to protect the semiconductor die 10 .

散熱器20包括頂部201和在頂部201與基板100之間延伸的至少一個連接部分203。根據一個實施例，頂部201可以是矩形頂部。根據實施例，頂部201具有平坦的頂面201a，其可以從密封劑30暴露(也即密封劑30未覆蓋頂面201a)，這樣可以增加散熱面積，以及減少覆蓋，以更快的散熱。 The heat sink 20 includes a top portion 201 and at least one connecting portion 203 extending between the top portion 201 and the substrate 100 . According to one embodiment, the top 201 may be a rectangular top. According to an embodiment, the top 201 has a flat top surface 201a that can be exposed from the encapsulant 30 (ie, the encapsulant 30 does not cover the top surface 201a), which can increase the heat dissipation area and reduce the coverage for faster heat dissipation.

根據實施例，四個示例性連接部分203分別從矩形屋頂部分或頂部201的四個角延伸。根據實施例，四個連接部分203中的每一個包括安裝在晶片側100a上的基板100的連接焊盤110上的連接引線(connection lead)205。連接焊盤110包括彼此間隔開的第一部分110a和第二部分110b。 According to an embodiment, four exemplary connecting portions 203 extend from the four corners of the rectangular roof portion or roof 201, respectively. According to an embodiment, each of the four connection portions 203 includes connection leads 205 mounted on connection pads 110 of the substrate 100 on the wafer side 100a. The connection pad 110 includes a first portion 110a and a second portion 110b spaced apart from each other.

根據一個實施例，第一部分110a和第二部分110b佈置成彼此緊鄰(相鄰)。根據實施例，第一部分110a和第二部分110b配置為分別電耦合到不同的電壓訊號。根據實施例，連接焊盤100的第一部分110a可以電耦合到預留的(reserved)VDD電壓並且連接焊盤110的第二部分110b可以電耦合到VSS電壓或地。 According to one embodiment, the first portion 110a and the second portion 110b are arranged in close proximity (adjacent) to each other. According to an embodiment, the first portion 110a and the second portion 110b are configured to be electrically coupled to different voltage signals, respectively. According to an embodiment, the first portion 110a of the connection pad 100 may be electrically coupled to a reserved VDD voltage and the second portion 110b of the connection pad 110 may be electrically coupled to the VSS voltage or ground.

根據實施例，連接引線205附接到連接焊盤100的第一部分110a和第二部分110b。根據實施例，連接引線205透過第一導電黏附層301a附接到第一部分110a並透過第二導電黏附層301b附接到第二部分110b。根據實施例，第一導電黏附層301a和第二導電黏附層301b可以包括導電環氧樹脂層。 According to an embodiment, the connection lead 205 is attached to the first portion 110a and the second portion 110b of the connection pad 100 . According to an embodiment, the connection lead 205 is attached to the first portion 110a through the first conductive adhesive layer 301a and to the second portion 110b through the second conductive adhesive layer 301b. According to an embodiment, the first conductive adhesive layer 301a and the second conductive adhesive layer 301b may include conductive epoxy layers.

根據實施例，半導體封裝1還包括位於連接引線202和連接焊盤110之間的阻焊層160。根據實施例，第一阻焊層開口160a設置在阻焊層160中以部分暴露連接焊盤110的第一部分110a的頂面。第一導電黏附層301a設置在第一阻焊開口160a中。 According to an embodiment, the semiconductor package 1 further includes a solder resist layer 160 between the connection leads 202 and the connection pads 110 . According to an embodiment, the first solder resist opening 160 a is disposed in the solder resist 160 to partially expose the top surface of the first portion 110 a of the connection pad 110 . The first conductive adhesive layer 301a is disposed in the first solder resist opening 160a.

根據實施例，第二阻焊層開口160b設置在阻焊層160中以部分地暴露連接焊盤110的第二部分110b的頂面。第二導電黏附層301b設置在第二阻焊層開 口160b。根據一個實施例，第一導電黏附層301a與第二導電黏附層301b不直接接觸，並且透過阻焊層160隔開。 According to an embodiment, the second solder resist opening 160b is disposed in the solder resist 160 to partially expose the top surface of the second portion 110b of the connection pad 110 . The second conductive adhesive layer 301b is disposed on the opening of the second solder resist layer. Port 160b. According to one embodiment, the first conductive adhesive layer 301 a and the second conductive adhesive layer 301 b are not in direct contact and are separated by the solder resist layer 160 .

根據實施例，連接焊盤110的第一部分110a透過基板100中的至少一個金屬互連結構130電連接到焊球焊盤120a。根據一個實施例，至少一個金屬互連結構130可以包括導電通孔。根據實施例，焊球焊盤120a直接設置在連接焊盤110下方。 According to an embodiment, the first portion 110a of the connection pad 110 is electrically connected to the solder ball pad 120a through at least one metal interconnect structure 130 in the substrate 100 . According to one embodiment, the at least one metal interconnect structure 130 may include conductive vias. According to an embodiment, the solder ball pads 120a are disposed directly under the connection pads 110 .

根據實施例，基板100包括接地平面140。根據實施例，連接焊盤110的第二部分110b電耦合到接地平面140。在最終測試過程中，如上所述，連接焊盤100的第一部分110a可以電耦合到預留的VDD(reserved VDD，RSVD)電壓並且連接焊盤110的第二部分110b可以電耦合到VSS電壓或地。如果發生任何散熱器浮動，則可以在最終測試期間偵測到顯著的電阻值。透過本發明的上述結構，透過測試第一部分110a和第二部分110b是否浮動，可以確定散熱器20是否與基板100連接良好。 According to an embodiment, the substrate 100 includes a ground plane 140 . According to an embodiment, the second portion 110b of the connection pad 110 is electrically coupled to the ground plane 140 . During final testing, as described above, the first portion 110a of the connection pad 100 may be electrically coupled to a reserved VDD (RSVD) voltage and the second portion 110b of the connection pad 110 may be electrically coupled to the VSS voltage or land. If any heat sink float occurs, significant resistance values can be detected during the final test. Through the above structure of the present invention, it can be determined whether the heat sink 20 is well connected to the substrate 100 by testing whether the first part 110a and the second part 110b are floating.

使用本發明是有利的，因為可以在晶片製造過程的最終測試階段期間偵測到散熱器浮動或脫離。當散熱器發生浮動時，可以透過焊球焊盤120a偵測到高阻抗訊號。若散熱器發生浮動，則連接引線205與第一部分110a和第二部分110b脫離接觸，這樣測到的阻抗就特別高(例如幾千歐姆或更大)或無窮大，因此判斷散熱器發生浮動。若測到的阻抗值在一定範圍內(例如幾十歐姆，幾百歐姆等等)，則說明連接引線205與一部分110a和第二部分110b保持接觸，沒有發生浮動。並且本發明透過提供這樣的配置，散熱器20可以透過最短路徑良好地連接到地並且可以保持良好的EMI遮蔽。 Use of the present invention is advantageous because heat spreader float or detachment can be detected during the final test phase of the wafer fabrication process. When the heat sink floats, a high impedance signal can be detected through the solder ball pads 120a. If the heat sink floats, the connecting lead 205 is out of contact with the first part 110a and the second part 110b, so the measured impedance is very high (eg, several thousand ohms or more) or infinite, so it is judged that the heat sink floats. If the measured impedance value is within a certain range (for example, several tens of ohms, several hundreds of ohms, etc.), it means that the connection lead 205 is in contact with the part 110a and the second part 110b and does not float. And by providing such a configuration, the present invention can be well connected to ground through the shortest path and can maintain good EMI shielding.

儘管已經對本發明實施例及其優點進行了詳細說明，但應當理解的是，在不脫離本發明的精神以及申請專利範圍所定義的範圍內，可以對本發明進行各種改變、替換和變更。所描述的實施例在所有方面僅用於說明的目的而 並非用於限制本發明。本發明的保護範圍當視所附的申請專利範圍所界定者為准。本領域技術人員皆在不脫離本發明之精神以及範圍內做些許更動與潤飾。 Although the embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made in the present invention without departing from the spirit of the invention and the scope defined by the scope of the claims. The described embodiments are in all respects for illustrative purposes only and It is not intended to limit the present invention. The protection scope of the present invention shall be determined according to the scope of the appended patent application. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention.

以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

1:半導體封裝 1: Semiconductor packaging

10:半導體晶粒 10: Semiconductor die

20:散熱器 20: Radiator

30:密封劑 30: Sealant

100:基板 100: Substrate

100a:晶片側 100a: Wafer side

100b:球柵陣列側 100b: Ball grid array side

110:連接焊盤 110: Connection pad

110a:第一部分 110a: Part 1

110b:第二部分 110b: Part II

120,120a:焊球焊盤 120, 120a: Solder ball pads

130:金屬互連結構 130: Metal Interconnect Structure

140:接地平面 140: Ground plane

160:阻焊層 160: Solder mask

160a:第一阻焊層開口 160a: first solder mask opening

160b:第二阻焊層開口 160b: Second solder mask opening

201:頂部 201: Top

201a:頂面 201a: Top Surface

203:連接部分 203: Connection part

205:連接引線 205: Connect the leads

301a:第一導電黏附層 301a: the first conductive adhesive layer

301b:第二導電黏附層 301b: second conductive adhesive layer

SB:焊球 SB: Solder Ball

Claims (11)

一種半導體封裝，包括：基板；半導體晶粒，安裝在該基板上；以及散熱器，在該半導體晶粒上方，其中該散熱器包括頂部和在該頂部與該基板之間延伸的至少一個連接部分，其中該至少一個連接部分包括安裝在該基板的連接焊盤上的連接引線，其中該連接焊盤包括彼此間隔開的第一部分和第二部分，該第一部分和該第二部分配置為分別電耦合到不同的電壓訊號；其中，該連接引線透過第一導電黏附層附接到該第一部分並且透過第二導電黏附層附接到該第二部分；該半導體封裝還包括：在該連接引線與該連接焊盤之間的阻焊層；第一阻焊層開口，位於該阻焊層中，以部分地暴露出該連接焊盤的該第一部分的頂面，其中該第一導電黏附層設置在該第一阻焊層開口中；以及第二阻焊層開口，位於該阻焊層中，以部分地暴露出該連接焊盤的該第二部分的頂面，其中該第二導電黏附層設置在該第二阻焊層開口中。 A semiconductor package comprising: a substrate; a semiconductor die mounted on the substrate; and a heat spreader over the semiconductor die, wherein the heat spreader includes a top portion and at least one connecting portion extending between the top portion and the substrate , wherein the at least one connection portion includes a connection lead mounted on a connection pad of the substrate, wherein the connection pad includes a first portion and a second portion spaced apart from each other, the first portion and the second portion being configured to electrically be coupled to different voltage signals; wherein the connection lead is attached to the first part through a first conductive adhesive layer and is attached to the second part through a second conductive adhesive layer; the semiconductor package further comprises: connecting the connection lead to the second part The solder mask between the connection pads; the first solder mask opening is located in the solder mask to partially expose the top surface of the first portion of the connection pad, wherein the first conductive adhesive layer is provided in the first solder mask opening; and a second solder mask opening in the solder mask to partially expose the top surface of the second portion of the connection pad, wherein the second conductive adhesive layer arranged in the opening of the second solder resist layer. 如請求項1之半導體封裝，其中該頂部為矩形頂部，且其中該至少一連接部分自該矩形頂部的一角延伸，或者/和，該頂部具有平坦的頂面。 The semiconductor package of claim 1, wherein the top is a rectangular top, and wherein the at least one connecting portion extends from a corner of the rectangular top, or/and, the top has a flat top surface. 如請求項1之半導體封裝，其中，該第一導電黏附層不與該第二導電黏附層直接相連，或者/和，該第一導電黏附層與該第二導電黏附層為導電環氧樹脂層。 The semiconductor package of claim 1, wherein the first conductive adhesive layer is not directly connected to the second conductive adhesive layer, or/and, the first conductive adhesive layer and the second conductive adhesive layer are conductive epoxy resin layers . 如請求項1之半導體封裝，其中該連接焊盤的該第一部分電耦合到預留的VDD電壓，並且該連接焊盤的該第二部分電耦合到VSS電壓或地。 The semiconductor package of claim 1, wherein the first portion of the connection pad is electrically coupled to the reserved VDD voltage, and the second portion of the connection pad is electrically coupled to the VSS voltage or ground. 如請求項1之半導體封裝，其中該基板包括封裝基板。 The semiconductor package of claim 1, wherein the substrate comprises a package substrate. 如請求項1之半導體封裝，其中該連接焊盤設置在該基板的晶片側上，並且其中該基板包括設置在球柵陣列側上的焊球焊盤。 The semiconductor package of claim 1, wherein the connection pads are disposed on the wafer side of the substrate, and wherein the substrate includes solder ball pads disposed on the ball grid array side. 如請求項6之半導體封裝，其中，焊球安裝在該焊球焊盤上，並且其中該連接焊盤透過該基板中的至少一個金屬互連結構電連接到該焊球焊盤。 The semiconductor package of claim 6, wherein a solder ball is mounted on the solder ball pad, and wherein the connection pad is electrically connected to the solder ball pad through at least one metal interconnect structure in the substrate. 如請求項7之半導體封裝，其中該至少一金屬互連結構為導電通孔，且其中該焊球焊盤直接設置於該連接焊盤下方。 The semiconductor package of claim 7, wherein the at least one metal interconnect structure is a conductive via, and wherein the solder ball pad is disposed directly below the connection pad. 如請求項4之半導體封裝，其中該基板包括接地平面。 The semiconductor package of claim 4, wherein the substrate includes a ground plane. 如請求項9之半導體封裝，其中該連接焊盤的該第二部分電耦合到該接地平面。 The semiconductor package of claim 9, wherein the second portion of the connection pad is electrically coupled to the ground plane. 如請求項1之半導體封裝，其中該半導體晶粒透過引線接合安裝在該基板上，或者，該半導體晶粒透過倒裝晶片接合安裝在該基板上。 The semiconductor package of claim 1, wherein the semiconductor die is mounted on the substrate by wire bonding, or the semiconductor die is mounted on the substrate by flip chip bonding.
TW110124366A 2021-06-02 2021-07-02 Semiconductor package TWI758204B (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6528876B2 (en) * 2000-06-26 2003-03-04 Siliconware Precision Industries Co., Ltd. Semiconductor package having heat sink attached to substrate
US20160300812A1 (en) * 2013-10-11 2016-10-13 Mediatek Inc. Semiconductor package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6528876B2 (en) * 2000-06-26 2003-03-04 Siliconware Precision Industries Co., Ltd. Semiconductor package having heat sink attached to substrate
US20160300812A1 (en) * 2013-10-11 2016-10-13 Mediatek Inc. Semiconductor package

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