TWI757243B - Graphene barrier for electrical interconnects and producing method thereof - Google Patents

Graphene barrier for electrical interconnects and producing method thereof Download PDF

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TWI757243B
TWI757243B TW105126626A TW105126626A TWI757243B TW I757243 B TWI757243 B TW I757243B TW 105126626 A TW105126626 A TW 105126626A TW 105126626 A TW105126626 A TW 105126626A TW I757243 B TWI757243 B TW I757243B
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barrier layer
precursor material
layer precursor
graphene
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TW201722852A (en
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羅曼 考迪洛
阿蘭薩蘇 梅斯特雷卡洛
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美商英特爾股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H01L23/53252—Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53276—Conductive materials containing carbon, e.g. fullerenes

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Abstract

Techniques are disclosed for producing graphitic barrier layers that encapsulate or otherwise isolate a metal interconnect feature from adjacent insulator or dielectric materials. The techniques can include an on-chip synthesis method in which barrier layer precursor materials, for example, hydrocarbon-based self-assembled monolayers, are positioned between a dielectric feature and an electrically conductive metal line. Through a treatment process, such as thermal annealing, the barrier layer precursor materials are converted into a graphitic barrier layer that comprises graphene and, in some cases, is a graphene monolayer. The disclosed graphitic barrier layers may be atomically thin, have a substantially uniform thickness and may optionally conduct charge, thereby allowing the barrier layer to serve as a current shunt, capable of supporting high current densities.

Description

用於電互連體的石墨烯障壁及其生產方法 Graphene barrier for electrical interconnect and method for producing the same

本發明係關於一種半導體裝置；特別關於一種用於電互連體的石墨烯障壁。 The present invention relates to a semiconductor device; in particular to a graphene barrier for electrical interconnects.

在積體電路的製造中，可以在半導體基板上使用銅鑲嵌工序形成互連體。這種工序通常開始於將溝槽及/或通孔蝕刻到絕緣體層中、將障壁材料沉積到溝槽中、及然後將銅金屬沉積在障壁材料上以形成互連體。隨著裝置尺寸繼續縮小，各種互連體部件變得更窄和更靠近在一起，從而產生許多複雜的問題。 In the manufacture of integrated circuits, interconnects may be formed on semiconductor substrates using a copper damascene process. Such a process typically begins with etching trenches and/or vias into the insulator layer, depositing barrier material into the trenches, and then depositing copper metal over the barrier material to form interconnects. As device dimensions continue to shrink, the various interconnect components become narrower and closer together, creating a number of complex issues.

100‧‧‧積體電路結構 100‧‧‧Integrated Circuit Structure

110‧‧‧層間介電質層 110‧‧‧Interlayer Dielectric Layer

210‧‧‧石墨障壁層 210‧‧‧Graphite barrier layer

310‧‧‧互連體 310‧‧‧Interconnect

200‧‧‧障壁層前驅物材料 200‧‧‧Precursor material for barrier layer

300‧‧‧金屬 300‧‧‧Metal

1000‧‧‧計算系統 1000‧‧‧Computing System

1002‧‧‧主機板 1002‧‧‧Motherboard

1004‧‧‧處理器 1004‧‧‧Processor

1006‧‧‧通訊晶片 1006‧‧‧Communication chip

400‧‧‧方法 400‧‧‧Method

圖1係說明實施例積體電路結構，其示出根據本揭露的實施方式的石墨障壁層。 1 illustrates an example integrated circuit structure showing a graphite barrier layer according to an embodiment of the present disclosure.

圖2說明根據本揭露的實施方式而產生包含石墨障壁層的積體電路的實施例技術。 2 illustrates an example technique for producing an integrated circuit including a graphite barrier layer according to an embodiment of the present disclosure.

圖3A至3F說明一系列積體電路結構的橫截 面側視圖，其示出了根據本揭露的實施方式的石墨障壁層之形成。 3A to 3F illustrate cross-sections of a series of integrated circuit structures A side view showing the formation of a graphite barrier layer in accordance with embodiments of the present disclosure.

圖4說明實施例計算系統，其係以包含根據本揭露的實施方式而配置的互連體結構的一個或多個積體電路來實現。 4 illustrates an example computing system implemented with one or more integrated circuits including interconnect structures configured in accordance with embodiments of the present disclosure.

如將領會的，圖式不一定按比例繪製或旨在將本揭露侷限於所示之特定配置。例如，雖然某些圖一般是以直線、直角及平滑表面來指示，而結構之實際實現可能具有非完美的直線、直角等，且某些特徵會具有表面拓撲或否則為不平滑，此係所使用的製程裝備和技術之現實世界限制。簡言之，所提供的圖式僅顯示實施例結構。 As will be appreciated, the drawings are not necessarily to scale or are intended to limit the disclosure to the particular configurations shown. For example, although some drawings are generally indicated with straight lines, right angles and smooth surfaces, the actual realization of the structure may have non-perfect lines, right angles, etc., and some features will have surface topology or otherwise be non-smooth. Real-world limitations of the process equipment and technology used. In short, the drawings provided show only embodiment structures.

【發明內容及實施方式】 [Content of the Invention and Embodiments]

本揭露的技術用於形成積體電路結構，其包括石墨障壁層，以將介電質部件從相鄰的導電部件分離。在某些實施方式中，石墨障壁層可，例如藉由使用自組裝材料和在某些實施方式中的自組裝單層(SAM)，在介電質和金屬互連體之間的位置中合成在晶片上。在此實施方式中，障壁層前驅物材料(例如，SAM)可以被放置在石墨障壁層的期望的最終位置中，並且在適當位置上可以被處理(例如，藉由熱退火處理)以產生石墨障壁層。所揭露的技術可以提供優於形成障壁層的傳統沉積技術的各種優點。例如，所揭露方法和材料可以允許產生石墨烯單層，其圍繞互連體結構的金屬並且基本上是共形的及/或 具有次奈米範圍內的厚度。所揭露的技術還可以增強互連體結構的機械性能(例如，藉由增加在障壁層和介電質及/或金屬互連體之間的斷裂能)。所揭露的石墨障壁層可以用於有效地防止導電互連體金屬有害地遷移到積體電路的介電質中。本文揭露的石墨障壁層可以具有在次奈米範圍內的厚度，並且在某些實施方式中也可以傳導電流。按照本揭露，將明瞭許多配置和變化。 The techniques of the present disclosure are used to form integrated circuit structures that include graphite barrier layers to separate dielectric features from adjacent conductive features. In certain embodiments, the graphitic barrier layer can be synthesized in place between the dielectric and the metal interconnect, for example by using self-assembled materials and in certain embodiments self-assembled monolayers (SAMs) on the wafer. In this embodiment, the barrier layer precursor material (eg, SAM) may be placed in the desired final location of the graphite barrier layer, and may be processed (eg, by thermal annealing) in place to produce graphite barrier layer. The disclosed techniques may provide various advantages over conventional deposition techniques for forming barrier layers. For example, the disclosed methods and materials can allow the creation of graphene monolayers that surround the metal of the interconnect structure and are substantially conformal and/or Has a thickness in the sub-nanometer range. The disclosed techniques can also enhance the mechanical properties of the interconnect structure (eg, by increasing the fracture energy between the barrier layer and the dielectric and/or metal interconnect). The disclosed graphite barrier layers can be used to effectively prevent detrimental migration of conductive interconnect metals into the dielectric of an integrated circuit. The graphitic barrier layers disclosed herein can have thicknesses in the sub-nanometer range, and in certain embodiments can also conduct electrical current. Numerous configurations and variations will be apparent in light of this disclosure.

總體概述 General overview

通常希望在積體電路的非導電(例如，介電質)和導電(例如，銅金屬)部件之間包括障壁材料。障壁材料可防止金屬互連體有害地遷移到介電質材料中，可以使金屬絕緣及/或增強介電質和金屬之間的黏附。然而，已知的傳統障壁材料不能縮小超越到幾奈米。因此，隨著互連體結構尺寸越來越小，常見的障壁材料佔據互連體線的橫截面面積的部分逐漸增大。如按照本揭露所理解的，用石墨障壁層，例如石墨烯單層，代替常見的障壁材料將藉由最大化由導電金屬芯所佔據的橫截面面積的比例來增加互連體線的有效導電率，同時還在介電質和互連體結構的金屬之間提供有效的擴散障壁。石墨烯是原子級薄度且導電的材料。儘管石墨烯可以用於一些應用中以提供有效的擴散障壁，但是存在與其相關的許多挑戰，特別是關於形成次奈米厚度的石墨烯障壁。例如，將在單獨的基板上生長的石墨烯或石墨材料轉移到具有一些拓撲(例 如，溝槽)的積體電路晶片係非簡單的或易於以其它方式實現的。 It is often desirable to include barrier material between the non-conductive (eg, dielectric) and conductive (eg, copper metal) components of the integrated circuit. The barrier material can prevent detrimental migration of the metal interconnect into the dielectric material, can insulate the metal and/or enhance adhesion between the dielectric and the metal. However, known conventional barrier materials cannot shrink beyond a few nanometers. Therefore, as the interconnect structure size becomes smaller, the portion of the cross-sectional area of the interconnect line that is occupied by the common barrier material gradually increases. As understood in light of this disclosure, replacing the common barrier material with a graphitic barrier layer, such as a graphene monolayer, will increase the effective conduction of the interconnect lines by maximizing the proportion of the cross-sectional area occupied by the conductive metal core rate, while also providing an effective diffusion barrier between the dielectric and the metal of the interconnect structure. Graphene is an atomically thin and conductive material. Although graphene can be used in some applications to provide an effective diffusion barrier, there are many challenges associated with it, especially with regard to forming graphene barriers of sub-nanometer thickness. For example, transfer graphene or graphitic materials grown on separate substrates to have some topology (e.g. Such as trenches) integrated circuit wafers are not simple or easy to implement in other ways.

因此，及根據本揭露的實施方式，提供了形成用於金屬互連體結構的石墨障壁層的技術。在一個具體實施方式中，可以使用自組裝材料，例如自組裝單層(SAM)，以產生石墨障壁層。例如，烴基SAM可位於積體電路的介電質和導電金屬之間，然後對其進行處理工序(例如，熱退火工序)。憑藉該工序，烴基SAM可以在位於介電質和互連體之間時被轉化為石墨障壁層。 Accordingly, and in accordance with embodiments of the present disclosure, techniques for forming graphite barrier layers for metal interconnect structures are provided. In a specific embodiment, self-assembled materials, such as self-assembled monolayers (SAMs), can be used to create graphitic barrier layers. For example, a hydrocarbon-based SAM can be located between the dielectric and conductive metal of an integrated circuit, which is then subjected to a processing process (eg, a thermal annealing process). With this procedure, the hydrocarbon-based SAM can be converted into a graphitic barrier layer when located between the dielectric and the interconnect.

所揭露的形成石墨障壁層的技術可以提供優於在溝槽或通孔中沉積或生長石墨烯的已知方法的各種優點。例如，所揭露的技術能夠產生石墨障壁層，其具有小於2nm的最大厚度或在次奈米範圍內的最大厚度(例如，小於1、小於.75、或小於.5奈米的厚度)。在一個具體實施例中，石墨障壁層是石墨烯單層。另外，石墨障壁層可以是基本上共形的，意味著該層是連續的並且沿著金屬互連體及/或介電質膜的界面具有基本上均勻的厚度。然而，應注意，其他實施方式不需要具有均勻的厚度。石墨障壁層可或不可傳導電荷，並且在石墨障壁層傳導電荷的實施方式中，該層可用作能夠承受高電流密度的電流分流器。按照本揭露，將明瞭許多變化和配置。 The disclosed techniques for forming graphitic barrier layers may provide various advantages over known methods of depositing or growing graphene in trenches or vias. For example, the disclosed techniques can produce graphitic barrier layers that have a maximum thickness of less than 2 nm or a maximum thickness in the sub-nanometer range (eg, less than 1, less than .75, or less than .5 nanometers thick). In a specific embodiment, the graphitic barrier layer is a graphene monolayer. Additionally, the graphitic barrier layer may be substantially conformal, meaning that the layer is continuous and of substantially uniform thickness along the interface of the metal interconnect and/or the dielectric film. However, it should be noted that other embodiments need not have a uniform thickness. The graphitic barrier layer may or may not conduct charge, and in embodiments in which the graphitic barrier layer conducts charge, the layer may function as a current shunt capable of withstanding high current densities. Numerous variations and configurations will become apparent in light of this disclosure.

石墨障壁層 Graphite barrier layer

圖1說明積體電路結構100的橫截面側視 圖，其示出了根據本揭露的實施方式所配置的石墨障壁層210。具體地，圖1示出了基部層間介電質(ILD)層110，其具有金屬互連體310或形成在其中的其它導電線。金屬互連體310被石墨障壁層210包圍。如本文所定義的，名詞石墨障壁層是指，所界定的層包含石墨烯的至少一部分。例如，在某些實施方式中，石墨障壁層包含基於石墨障壁層的總重量的至少5%、至少10%、至少25%、至少30%、至少40%、至少50%、至少60%、至少75%、至少80%、至少85%、至少90%、至少95%、或至少99%重量的石墨烯。在某些實施方式中，石墨障壁層210包含一個或多個石墨烯單層。在某些這樣的實施方式中，石墨障壁層由單個石墨烯單層組成或基本上由單個石墨烯單層組成。在這些和其它各種實施方式中，石墨烯單層至少部分地圍繞金屬互連體310。如果存在，則額外的石墨烯單層可至少部分地圍繞最內部的石墨烯單層。除石墨烯之外，石墨障壁層可以包含其它材料，例如聚合物、一個或多個官能基(例如，排列石墨烯結構的周邊邊緣的官能基)、鉭(Ta)、氮化鉭(TaN)、鉭鈷(TaCo)、氮化鈦(TiN)、鎢(W)、氮化鎢(WN)、鈷鎢(CoW)、氮化鉬(MoN)、釕/鉭合金(Ru/Ta)和已知的填充材料。仍在其他實施方式中，石墨障壁層可僅包含石墨烯(純石墨烯層、>99%石墨烯)。 FIG. 1 illustrates a cross-sectional side view of an integrated circuit structure 100 Figure, showing a graphite barrier layer 210 configured in accordance with embodiments of the present disclosure. Specifically, FIG. 1 shows a base interlayer dielectric (ILD) layer 110 having metal interconnects 310 or other conductive lines formed therein. The metal interconnect 310 is surrounded by the graphite barrier layer 210 . As defined herein, the term graphitic barrier layer means that the defined layer comprises at least a portion of graphene. For example, in certain embodiments, the graphite barrier layer comprises at least 5%, at least 10%, at least 25%, at least 30%, at least 40%, at least 50%, at least 60%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, or at least 99% by weight graphene. In certain embodiments, the graphitic barrier layer 210 comprises one or more graphene monolayers. In certain such embodiments, the graphitic barrier layer consists or consists essentially of a single graphene monolayer. In these and various other embodiments, the graphene monolayer at least partially surrounds the metal interconnect 310 . If present, additional graphene monolayers may at least partially surround the innermost graphene monolayer. In addition to graphene, the graphitic barrier layer may contain other materials such as polymers, one or more functional groups (eg, functional groups that line the perimeter edges of the graphene structure), tantalum (Ta), tantalum nitride (TaN) , tantalum cobalt (TaCo), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), cobalt tungsten (CoW), molybdenum nitride (MoN), ruthenium/tantalum alloy (Ru/Ta) and known filling material. In still other embodiments, the graphitic barrier layer may comprise only graphene (pure graphene layer, >99% graphene).

所揭露的石墨障壁層可以是將ILD從金屬互連體分離的唯一材料。例如，所揭露的石墨障壁層可以黏 附到介電質和金屬互連體這兩者，並且在這樣做時，可以消除對任何額外的常見障壁層及/或襯墊的需要，以將金屬從介電質分離。石墨障壁層210可具有在次奈米範圍內的最大厚度。例如，石墨障壁層可具有小於2、小於1.8、小於1.75、小於1.6、小於1.5、小於1.35、小於1.2、小於1、小於.8、小於.75、小於.6、小於.5或小於.35nm的最大厚度。在某些實施方式中，石墨障壁層的厚度近似等於單一石墨烯單層的厚度。石墨障壁層的厚度可在任何時候被定義為ILD 110和金屬互連體310之間的距離。 The disclosed graphite barrier layer may be the only material separating the ILD from the metal interconnect. For example, the disclosed graphite barrier layer can be adhered to Attached to both the dielectric and metal interconnects, and in doing so, can eliminate the need for any additional common barrier layers and/or liners to separate the metal from the dielectric. The graphite barrier layer 210 may have a maximum thickness in the sub-nanometer range. For example, the graphite barrier layer can have less than 2, less than 1.8, less than 1.75, less than 1.6, less than 1.5, less than 1.35, less than 1.2, less than 1, less than .8, less than .75, less than .6, less than .5, or less than .35 nm maximum thickness. In certain embodiments, the thickness of the graphite barrier layer is approximately equal to the thickness of a single graphene monolayer. The thickness of the graphite barrier layer can be defined as the distance between the ILD 110 and the metal interconnect 310 at any time.

石墨障壁層可以共形下伏ILD 110的拓撲，並且在某些這樣的實施方式中，石墨障壁層可為基本上共形的。在這些和其它實施方式中，石墨障壁層的厚度可以被定義為基本上均勻的，意味著該層的最薄部分在該層的最厚部分的40%內、在35%內、在30%內、在25%內、在20%內、在15%內、在10%內、在5%內、或在2%內。石墨障壁層210的其它構造將取決於給定的應用並且按照本揭露將明瞭。還應注意，石墨障壁層可以是連續的，以便不備有斷裂；透過該斷裂，金屬可能潛在地擴散到相鄰介電質或絕緣體材料中。如按照本揭露將領會，石墨障壁層的一致性和連續性質可從一個實施方式到下一個實施方式而有所不同。 The graphitic barrier layer may conformally underlying the topology of the ILD 110, and in certain such embodiments, the graphitic barrier layer may be substantially conformal. In these and other embodiments, the thickness of the graphite barrier layer can be defined as being substantially uniform, meaning that the thinnest portion of the layer is within 40%, within 35%, within 30% of the thickest portion of the layer within 25%, within 20%, within 15%, within 10%, within 5%, or within 2%. Other configurations of the graphite barrier layer 210 will depend on the given application and will be apparent in light of this disclosure. It should also be noted that the graphitic barrier layer may be continuous so as not to provide for fractures through which the metal may potentially diffuse into adjacent dielectric or insulator materials. As will be appreciated in light of this disclosure, the uniformity and continuous nature of the graphitic barrier layer may vary from one embodiment to the next.

ILD 110可以包含範圍廣泛的介電質材料中的任何一種，包括但不必限於：(1)氧化物，例如二氧化 矽(SiO2)，氧化鋁(Al2O3)等；(2)氮化物，例如氮化矽(Si3N4)；(3)碳化物，例如碳化矽(SiC)；(4)碳氮化物，例如碳氮化矽(SiCN)；(5)氮氧化物，例如氮氧化矽(SiOxNy)；及/或(6)任何上述的組合(例如，SiCN/SiN等)。在某些實施方式中，根據需要，至少ILD 110的表面可以被官能化，例如包括親水或疏水取代基。在某些實施方式中，ILD 110的表面包括羥基，並且ILD 110的表面因此是親水性的。仍在其他實施方式中，ILD 110可以包含低k介電質材料或高k介電質材料，這取決於裝置的應用和期望的性能。用於ILD 110的其它合適的材料及/或配置將取決於給定的應用並且按照本揭露將可被明瞭。 ILD 110 may comprise any of a wide range of dielectric materials including, but not necessarily limited to: (1) oxides such as silicon dioxide ( SiO2 ), aluminum oxide ( Al2O3 ), etc.; ( 2 ) nitrogen ( 3 ) carbides, such as silicon carbide (SiC); ( 4 ) carbonitrides, such as silicon carbonitride (SiCN); (5) oxynitrides, such as Silicon oxynitride ( SiOxNy ); and/or (6) any combination of the above (eg, SiCN/SiN, etc.). In certain embodiments, at least the surface of ILD 110 can be functionalized, eg, including hydrophilic or hydrophobic substituents, as desired. In certain embodiments, the surface of ILD 110 includes hydroxyl groups, and the surface of ILD 110 is thus hydrophilic. In still other embodiments, the ILD 110 may comprise a low-k dielectric material or a high-k dielectric material, depending on the application and desired performance of the device. Other suitable materials and/or configurations for ILD 110 will depend on the given application and will be apparent in light of this disclosure.

金屬互連體310可包含範圍廣泛的導電金屬中的任何一種，例如但不必限於：銅(Cu)；鋁(Al)；銀(Ag)；鎳(Ni)；金(Au)；鈦(Ti)；鎢(W)；釕(Ru)；鈷(Co)；鉻(Cr)；鐵(Fe)；鉿(Hf)；鉭(Ta)；釩(V)；鉬(Mo)；鈀(Pd)；鉑(Pt)；及/或上述任何的合金或組合。雖然在本揭露中被稱為“金屬”，但是在某些情況中，互連體材料可以是金屬的或非金屬的，並且可以包括聚合物材料。為此，具有適當程度的導電性的任何材料可用於IC 100的一個或多個金屬互連體310。用於給定互連體310的其它合適的金屬/材料將取決於給定的應用並且按照本揭露將可被明瞭。 Metal interconnect 310 may comprise any of a wide range of conductive metals such as, but not necessarily limited to: copper (Cu); aluminum (Al); silver (Ag); nickel (Ni); gold (Au); titanium (Ti) ); tungsten (W); ruthenium (Ru); cobalt (Co); chromium (Cr); iron (Fe); hafnium (Hf); tantalum (Ta); vanadium (V); molybdenum (Mo); palladium (Pd) ); platinum (Pt); and/or any alloy or combination of the foregoing. Although referred to in this disclosure as "metals," in some cases, the interconnect material may be metallic or non-metallic, and may include polymeric materials. To this end, any material having an appropriate degree of conductivity may be used for one or more metal interconnects 310 of IC 100 . Other suitable metals/materials for a given interconnect 310 will depend on the given application and will be apparent in light of this disclosure.

製造的實施例方法 Example Method of Manufacture

可藉由各種技術產生如本文揭露的石墨障壁層。圖2說明根據本揭露的一個或多個實施方式來形成包括石墨障壁層的積體電路裝置的方法400。圖3A至3F說明了，根據各種實施方式，當執行圖2的方法400時所形成的實施例結構。注意，本文所述的技術可以用於任何合適的結構或裝置，其將獲得使用一個或多個石墨障壁層之益處，來防止例如導電金屬遷移到相鄰的非導電絕緣部件中。 Graphite barrier layers as disclosed herein can be produced by various techniques. 2 illustrates a method 400 of forming an integrated circuit device including a graphite barrier layer in accordance with one or more embodiments of the present disclosure. 3A-3F illustrate example structures formed when the method 400 of FIG. 2 is performed, according to various implementations. Note that the techniques described herein can be used in any suitable structure or device that would benefit from the use of one or more graphitic barrier layers to prevent, for example, conductive metal from migrating into adjacent non-conductive insulating features.

如圖2所示，根據實施方式，方法400包括，形成(402)介電質層，例如圖3A所示的ILD 110。在某些情況下，可根據需要在基板、晶圓或其它合適的表面上形成或沉積ILD 110。按照本揭露將領會到，可以利用範圍廣泛的合適沉積技術中的任何一種來形成ILD 110，例如但不必限於：物理氣相沉積(PVD)；化學氣相沉積(CVD)；旋轉塗佈/旋塗沉積(SOD)；及/或任何上述的組合。用於ILD 110的其它合適的配置、材料、沉積技術、及/或厚度將取決於給定的應用並且按照本揭露將可被明瞭。圖3A示出ILD 110的一個實施例結構；然而，ILD 110可以根據任何期望的結構形成，並且可以藉由任何數量的已知技術蝕刻或以其它方式操作以形成溝槽及/或通孔。 As shown in FIG. 2, according to an embodiment, the method 400 includes forming (402) a dielectric layer, such as the ILD 110 shown in FIG. 3A. In some cases, ILD 110 may be formed or deposited on a substrate, wafer, or other suitable surface as desired. It will be appreciated in light of this disclosure that ILD 110 may be formed using any of a wide variety of suitable deposition techniques, such as, but not necessarily limited to: physical vapor deposition (PVD); chemical vapor deposition (CVD); spin coating/spin coating overcoat deposition (SOD); and/or a combination of any of the foregoing. Other suitable configurations, materials, deposition techniques, and/or thicknesses for ILD 110 will depend on the given application and will be apparent in light of this disclosure. 3A illustrates one embodiment structure of ILD 110; however, ILD 110 may be formed according to any desired structure and may be etched or otherwise manipulated by any number of known techniques to form trenches and/or vias.

方法400繼續，選用地處理(404)介電質層 的表面，例如圖3A中所示的ILD 110的表面。可選用地處理ILD 110的表面，例如，使ILD 110的所暴露表面親水(例如，藉由增加在ILD 110的表面上的羥基的濃度)。按照本揭露，將明瞭任何數量的合適的處理技術。 Method 400 continues by optionally processing (404) the dielectric layer surface, such as the surface of ILD 110 shown in FIG. 3A. The surface of ILD 110 can optionally be treated, eg, by making the exposed surface of ILD 110 hydrophilic (eg, by increasing the concentration of hydroxyl groups on the surface of ILD 110). Any number of suitable processing techniques will be apparent in light of this disclosure.

根據實施例實施方式，在形成ILD 110並且處理(如果需要)ILD 110之後，方法400繼續，施加(406)障壁層前驅物材料200到介電質層，以形成圖3B所示的實施例結構。障壁層前驅物材料200可以在液相或氣相中施加到ILD 110。例如，障壁層前驅物材料可在溶劑中稀釋並在液相中施加到ILD。或者，障壁層前驅物材料可以在類似於原子層沉積(ALD)的工序中被蒸發並在氣相中沉積在ILD 110上。在施加之後，障壁層前驅物材料可以具有小於2奈米、小於1奈米的厚度、如上所述的石墨障壁層的任何厚度、或取決於給定的目標應用或最終用途的某些其它合適的厚度。 After forming the ILD 110 and processing (if necessary) the ILD 110, method 400 continues by applying ( 406 ) the barrier layer precursor material 200 to the dielectric layer to form the example structure shown in FIG. 3B in accordance with example embodiments . The barrier layer precursor material 200 may be applied to the ILD 110 in the liquid or gas phase. For example, the barrier layer precursor material can be diluted in a solvent and applied to the ILD in the liquid phase. Alternatively, the barrier layer precursor material may be evaporated in a process similar to atomic layer deposition (ALD) and deposited on the ILD 110 in the vapor phase. After application, the barrier layer precursor material may have a thickness of less than 2 nanometers, less than 1 nanometer, any thickness of the graphitic barrier layer as described above, or some other suitable depending on the given target application or end use thickness of.

障壁層前驅物材料200可包含自組裝材料，並且在某些實施方式中，障壁層前驅物材料可以包含一個或多個自組裝單層(SAM)。在障壁層前驅物材料包含SAM的某些實施方式中，SAM分子可包括具有一個或多個連接的官能基的基部結構。合適的基部結構的實施例包括脂族和芳族基兩者，例如環狀芳族化合物。合適的官能基的實施例包括但不限於硫醇、羧酸、羧酸鹽、胺(例如單胺或聚胺化的伯胺、仲胺和叔胺)、苯胺基、吡啶基和金屬原子(例如，任何可催化無電反應的金屬)。實施例 SAM包括但不限於矽烷(例如，脂族和芳族氯矽烷、甲氧基矽烷和乙氧基矽烷)、膦酸、鍺烷(例如氯鍺烷)和乙烯封端的化合物。在某些實施方式中，障壁層前驅物材料可包含一種或多種下列化合物：三氯(苯基)矽烷、二苯基二氯鍺烷、4-聯苯基二甲基氯矽烷、對氨基苯基三甲氧基矽烷、4-(2-(三乙氧基甲矽烷基)乙基)吡啶和(9)-蒽基三甲氧基矽烷。 The barrier layer precursor material 200 may comprise a self-assembled material, and in certain embodiments, the barrier layer precursor material may comprise one or more self-assembled monolayers (SAMs). In certain embodiments in which the barrier layer precursor material comprises a SAM, the SAM molecule may comprise a base structure with one or more attached functional groups. Examples of suitable base structures include both aliphatic and aromatic groups, such as cyclic aromatic compounds. Examples of suitable functional groups include, but are not limited to, thiols, carboxylic acids, carboxylates, amines (such as mono- or polyaminated primary, secondary, and tertiary amines), anilino groups, pyridyl groups, and metal atoms ( For example, any metal that can catalyze an electroless reaction). Example SAMs include, but are not limited to, silanes (eg, aliphatic and aromatic chlorosilanes, methoxysilanes, and ethoxysilanes), phosphonic acids, germanes (eg, chlorogermanes), and vinyl terminated compounds. In certain embodiments, the barrier layer precursor material may comprise one or more of the following compounds: trichloro(phenyl)silane, diphenyldichlorogermane, 4-biphenyldimethylchlorosilane, p-aminobenzene trimethoxysilane, 4-(2-(triethoxysilyl)ethyl)pyridine and (9)-anthryltrimethoxysilane.

在障壁層前驅物材料包括SAM的某些實施方式中，障壁層前驅物材料可限於單一種的SAM分子或可包括多種的SAM分子。在這些和其他實施方式中，障壁層前驅物材料包含具有次奈米尺寸的化合物。例如，障壁層前驅物材料的直徑可不大於2、不大於1.75、不大於1.5、不大於1.25、不大於1、不大於.8、不大於.75、不大於.6、不大於.5、不大於.4、不大於.3、不大於.2、或不大於.1nm。 In certain embodiments where the barrier layer precursor material includes a SAM, the barrier layer precursor material may be limited to a single SAM molecule or may include multiple SAM molecules. In these and other embodiments, the barrier layer precursor material comprises a compound having sub-nanometer dimensions. For example, the diameter of the barrier layer precursor material may be no greater than 2, no greater than 1.75, no greater than 1.5, no greater than 1.25, no greater than 1, no greater than .8, no greater than .75, no greater than .6, no greater than .5, no greater than . Greater than .4, not greater than .3, not greater than .2, or not greater than .1 nm.

如方法400所示，可選用地用一種或多種催化劑活化(407)障壁層前驅物材料。合適的催化劑包括例如金屬催化劑，例如鈀、鎳、鈷、釕、鉑、金、銀、或能夠催化無電反應的任何其它金屬。可以藉由任何合適的方法施加催化劑到障壁層前驅物材料，包括但不必限於PVD、CVD和ALD。 As shown in method 400, the barrier layer precursor material is optionally activated (407) with one or more catalysts. Suitable catalysts include, for example, metal catalysts such as palladium, nickel, cobalt, ruthenium, platinum, gold, silver, or any other metal capable of catalyzing electroless reactions. The catalyst can be applied to the barrier layer precursor material by any suitable method, including but not necessarily limited to PVD, CVD, and ALD.

根據實施例實施方式，方法400繼續，選用地沉積(408)金屬300到障壁層前驅物材料200上，以形成如圖3C所示的結構。金屬300可以是上面關於金屬 互連體310所描述的任何材料，或者可以選用地為不同類型的材料。在某些實施方式中，金屬300可以與金屬互連體310相同，然而，在其他實施方式中，金屬300可以不同於金屬互連體310。例如，在某些實施方式中，金屬300可以是沉積到障壁層前驅物材料上的初始金屬，並且隨後被不同的金屬替代以形成金屬互連體310。用於形成金屬300的合適技術包括例如PVD、CVD、ALD和電鍍工序。在用無電催化劑活化(407)障壁層前驅物材料的某些實施方式中，可藉由無電鍍工序形成金屬300。在一個具體實施方式中，障壁層前驅物材料被催化活化(例如藉由暴露於氯化鈀(II)或鈀、鈷、鎳、銀、金或釕基催化劑)，並且藉由無電電鍍施加金屬300。 Method 400 continues by optionally depositing ( 408 ) metal 300 onto barrier layer precursor material 200 to form the structure shown in FIG. 3C in accordance with an example embodiment. Metal 300 can be above on metal Any of the materials described for interconnect 310, or alternatively different types of materials. In some embodiments, metal 300 may be the same as metal interconnect 310 , however, in other embodiments, metal 300 may be different from metal interconnect 310 . For example, in certain embodiments, the metal 300 may be the initial metal deposited onto the barrier layer precursor material, and then replaced by a different metal to form the metal interconnect 310 . Suitable techniques for forming metal 300 include, for example, PVD, CVD, ALD, and electroplating processes. In certain embodiments where an electroless catalyst is used to activate (407) the barrier layer precursor material, the metal 300 may be formed by an electroless plating process. In one embodiment, the barrier layer precursor material is catalytically activated (eg, by exposure to palladium(II) chloride or a palladium, cobalt, nickel, silver, gold or ruthenium based catalyst) and the metal is applied by electroless plating 300.

如圖3D所示，根據實施例實施方式，方法400繼續，處理(412)障壁層前驅物材料200，以轉化障壁層前驅物材料200為石墨障壁層210。在某些實施方式中，障壁層前驅物材料200的處理涉及熱處理，例如在高溫下。在某些實施方式中，障壁層前驅物材料的處理涉及加熱到至少400、至少500、至少600、至少700、至少800、或至少900℃的溫度。在某些實施方式中，障壁層前驅物材料被加熱到400至900℃之間、400至600℃之間、或500至800℃之間。暴露於高溫同時，障壁層前驅物材料也可以經受已增加的壓力，包括大於1atm的壓力，例如至少5、至少10、至少15、至少20、至少25、或至少30atm的壓力。如按照本揭露將領會的，在某些 實施方式中，當施加較高的處理壓力時，可以使用較低的處理溫度。儘管不希望受理論束縛，與障壁層前驅物材料中存在的SAM接觸的金屬可以用作催化劑，以促使烴材料轉化為石墨烯。 As shown in FIG. 3D , the method 400 continues by processing ( 412 ) the barrier layer precursor material 200 to convert the barrier layer precursor material 200 into a graphite barrier layer 210 , according to an example embodiment. In certain embodiments, processing of the barrier layer precursor material 200 involves thermal processing, such as at elevated temperatures. In certain embodiments, the processing of the barrier layer precursor material involves heating to a temperature of at least 400, at least 500, at least 600, at least 700, at least 800, or at least 900°C. In certain embodiments, the barrier layer precursor material is heated to between 400 and 900°C, between 400 and 600°C, or between 500 and 800°C. The barrier layer precursor material may also be subjected to increased pressures, including pressures greater than 1 atm, such as pressures of at least 5, at least 10, at least 15, at least 20, at least 25, or at least 30 atm, while being exposed to high temperatures. As will be understood in accordance with this disclosure, in certain In embodiments, lower processing temperatures may be used when higher processing pressures are applied. While not wishing to be bound by theory, the metal in contact with the SAM present in the barrier layer precursor material may act as a catalyst to facilitate the conversion of the hydrocarbon material to graphene.

如方法400所示，可選用地在處理之前用覆蓋材料(410)覆蓋障壁層前驅物材料200。任何合適的覆蓋材料，例如氣密材料，包括例如氮化矽，可以用於覆蓋前驅物材料。按照本揭露，其它適合於覆蓋的材料將可被明瞭。覆蓋材料可以例如允許前驅物材料經受比沒有覆蓋所可行的溫度更高的溫度。例如，具有被覆蓋的前驅物材料的互連體結構可能夠承受溫度或600℃或更高的。 As shown in method 400, the barrier layer precursor material 200 is optionally covered with a capping material (410) prior to processing. Any suitable capping material, such as a hermetic material, including, for example, silicon nitride, can be used to cap the precursor material. Other suitable materials for covering will become apparent in light of this disclosure. The cover material may, for example, allow the precursor material to withstand higher temperatures than would be possible without the cover. For example, an interconnect structure with a covered precursor material may be able to withstand temperatures or 600°C or higher.

根據實施例實施方式，如方法400所示，在某些實施方式中，可選用地去除(413)金屬300，以形成如圖3E所示的結構。可以藉由任何合適的工序，例如藉由濕蝕刻工序，或藉由不損害石墨障壁層210的任何其它工序來去除金屬300。在這些和其他實施方式中，根據實施例實施方式，在去除金屬300以形成如圖3F所示的結構之後，可以沉積(415)金屬互連體310。可使用任何合適的技術來沉積金屬互連體310，諸如上面關於沉積金屬300所討論的任何技術，或任何其它合適的技術。 According to example implementations, as shown in method 400, in some implementations, metal 300 is optionally removed (413) to form the structure shown in Figure 3E. The metal 300 may be removed by any suitable process, such as by a wet etching process, or by any other process that does not damage the graphite barrier layer 210 . In these and other embodiments, after removal of metal 300 to form the structure shown in FIG. 3F, metal interconnects 310 may be deposited (415) in accordance with example embodiments. Metal interconnect 310 may be deposited using any suitable technique, such as any of the techniques discussed above with respect to depositing metal 300, or any other suitable technique.

方法400示出了選用地，可平面化及/或拋光(414)積體電路的各種部件。例如，本文所述的任何層可以根據需要進行化學機械平坦化(CMP)工序或其它適當的拋光/平坦化工序，例如以允許後續處理。平坦化及/ 或拋光可以在前驅物障壁材料的處理之前或之後進行。在某些實施方式中，ILD 110、障壁層前驅物材料200、石墨障壁層210、一個或多個互連體310及/或覆蓋層(如果存在)可以經歷CMP工序以去除不需要的餘物。 Method 400 illustrates that, optionally, various components of an integrated circuit may be planarized and/or polished (414). For example, any of the layers described herein may be subjected to a chemical mechanical planarization (CMP) process or other suitable polishing/planarization process as desired, eg, to allow for subsequent processing. flattening and/ Or polishing can be performed before or after processing of the precursor barrier material. In certain embodiments, ILD 110, barrier layer precursor material 200, graphite barrier layer 210, one or more interconnects 310, and/or capping layer (if present) may undergo a CMP process to remove unwanted residues .

如方法400所示，石墨障壁層和周圍的介電質和金屬互連體可被進一步處理，以形成(416)積體電路(IC)100，如圖1所示。在某些情況中，IC 100可以是例如具有一個或多個裝置及/或金屬層的部分處理的IC。按照本揭露，將明瞭許多適當的配置。IC 100可以在處理障壁層前驅物材料之前或之後形成，以轉化障壁層前驅物材料為石墨障壁層。 As shown in method 400 , the graphitic barrier layer and surrounding dielectric and metal interconnects may be further processed to form ( 416 ) an integrated circuit (IC) 100 , as shown in FIG. 1 . In some cases, IC 100 may be, for example, a partially processed IC with one or more device and/or metal layers. In light of this disclosure, many suitable configurations will become apparent. IC 100 may be formed before or after processing the barrier layer precursor material to convert the barrier layer precursor material into a graphitic barrier layer.

在某些情況中，所揭露的技術可以與多種互連體環境和結構中的任意種兼容。某些實施例結構可包括但不必限於：單鑲嵌結構；雙鑲嵌結構(例如，具有下伏通孔的線)；異向性結構；同向性結構；及/或任何其它所需的IC結構、互連體、或其它導電結構。此外，根據實施方式，給定互連體的尺寸可以針對給定目標應用或最終用途的需要來定制。用於給定互連體的其它合適的配置將取決於給定的應用並且根據本揭露將可被明瞭。 In some cases, the disclosed techniques may be compatible with any of a variety of interconnect environments and structures. Certain example structures may include, but are not necessarily limited to: single damascene structures; dual damascene structures (eg, lines with underlying vias); anisotropic structures; isotropic structures; and/or any other desired IC structures , interconnects, or other conductive structures. Furthermore, depending on the embodiment, the dimensions of a given interconnect may be tailored to the needs of a given target application or end use. Other suitable configurations for a given interconnect will depend on the given application and will be apparent from this disclosure.

額外的技術和注意事項 Additional Techniques and Considerations

應當理解，在障壁層前驅物材料包含烴基SAM的某些實施方式中，障壁層前驅物材料的處理(例如，藉由如本文所述的熱退火工序)可以將SAM轉化為 石墨障壁層，包含，例如，石墨烯單層。以這種方式，根據實施方式，所揭露的技術允許石墨烯的晶片上合成。所揭露的技術可以提供優於形成障壁層的傳統技術，例如藉由沉積，的許多優點。例如，所揭露方法和材料可以允許產生石墨烯單層，其圍繞互連體結構的金屬，基本上是共形的及/或具有次奈米範圍內的厚度。此外，所揭露的技術可以幫助避免常在沉積障壁層材料時發生的不均勻側壁沉積的問題。例如，根據某些實施方式，所揭露的技術可用於最小化或避免為確保所有區域被充分覆蓋而沉積過量障壁層材料的需要。以此方式，根據某些實施方式，所揭露的技術可用於保護障壁層材料，並最小化使用於過量障壁層材料的互連體結構的橫截面表面積。根據一些實施方式，自組裝障壁層前驅物材料的使用亦可以最小化或消除由於非共形應用而在傳統沉積方法中常見的結構缺陷。在金屬芯的存在下對障壁層前驅物材料的熱處理也可以正面地影響所得互連體結構的機械特性。例如，可藉由本文所述的熱處理工序增加金屬互連體和介電質之間的斷裂能。 It will be appreciated that in certain embodiments in which the barrier layer precursor material comprises a hydrocarbon-based SAM, processing of the barrier layer precursor material (eg, by a thermal annealing procedure as described herein) can convert the SAM into a Graphite barrier layers, including, for example, graphene monolayers. In this manner, according to embodiments, the disclosed techniques allow for on-wafer synthesis of graphene. The disclosed techniques may provide many advantages over conventional techniques for forming barrier layers, such as by deposition. For example, the disclosed methods and materials may allow the creation of graphene monolayers that surround the metal of the interconnect structure, are substantially conformal and/or have thicknesses in the sub-nanometer range. In addition, the disclosed techniques can help avoid the problem of uneven sidewall deposition that often occurs when depositing barrier layer materials. For example, according to certain embodiments, the disclosed techniques can be used to minimize or avoid the need to deposit excess barrier layer material to ensure that all areas are adequately covered. In this way, according to certain embodiments, the disclosed techniques can be used to protect the barrier layer material and minimize the cross-sectional surface area of the interconnect structure for excess barrier layer material. According to some embodiments, the use of self-assembled barrier layer precursor materials can also minimize or eliminate structural defects that are common in conventional deposition methods due to non-conformal applications. Thermal treatment of the barrier layer precursor material in the presence of the metal core can also positively affect the mechanical properties of the resulting interconnect structure. For example, the fracture energy between the metal interconnect and the dielectric can be increased by the thermal treatment procedures described herein.

可以使用各種方法來確定是否使用所揭露的技術來生產裝置。例如，拉曼光譜可以檢測石墨烯的存在，即便在非常低的重量百分比下。另外，可以使用結構分析(例如，掃描/透射電子顯微鏡(SEM/TEM)、組成映射、及/或原子探針成像/3D斷層攝影)的已知方法來確定給定積體電路的障壁層的尺寸。 Various methods can be used to determine whether to produce a device using the disclosed techniques. For example, Raman spectroscopy can detect the presence of graphene even at very low weight percentages. Additionally, known methods of structural analysis (eg, scanning/transmission electron microscopy (SEM/TEM), composition mapping, and/or atom probe imaging/3D tomography) can be used to determine the thickness of the barrier layer of a given integrated circuit. size.

實施例系統 Example system

圖4示出了計算系統1000，係以根據本揭露的實施例實施方式的配置及/或以其它方式所製造的一個或多個積體電路結構來實現。如可所見，計算系統1000容納主機板1002。主機板1002包括多個組件，該等多個組件包括但不限於處理器1004及至少一通訊晶片1006，其每一個可以實體和電耦接到主機板1002，或以其他方式整合在其中。應當領會，主機板1002可以是例如任何印刷電路板，無論是主機板還是安裝在主機板上的子板或計算系統1000的唯一的板等。取決於其應用，計算系統1000包括可以或不可以實體及電耦接至主機板1002的一或多個其它組件。這些其它組件可包括但不限於依電性記憶體(例如，DRAM)、非依電性記憶體(例如，ROM)、圖形處理器、數位訊號處理器、密碼處理器、晶片組、天線、顯示器、觸控幕顯示器、觸控幕控制器、電池、音頻編解碼、視頻編解碼、功率放大器、全球定位系統(GPS)裝置、羅盤、加速計、陀螺儀、揚聲器、相機、及大量儲存裝置(例如硬碟機、光碟(CD)、數位多樣式光碟(DVD)、等等)。如本文中各種描述的，包括在計算系統1000中的任何組件可以包括一個或多個積體電路結構，其配置有具有石墨障壁層的一個或多個導電互連體部件。這些積體電路結構可用於，例如實現板載處理器快取或記憶體陣列或包括互連體的其它電路部件。在某些實施方式中，可以將多個部件整合到一個或多個晶片 中(例如，注意通訊晶片1006可以是處理器1004的一部分或者整合到處理器1004中)。 4 illustrates a computing system 1000 implemented in one or more integrated circuit structures configured and/or otherwise fabricated in accordance with example implementations of the present disclosure. As can be seen, computing system 1000 houses motherboard 1002 . The motherboard 1002 includes a plurality of components including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which may be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein. It should be appreciated that the host board 1002 may be, for example, any printed circuit board, whether a host board or a daughter board mounted on the host board or the only board of the computing system 1000, or the like. Depending on its application, computing system 1000 includes one or more other components that may or may not be physically and electrically coupled to motherboard 1002 . These other components may include, but are not limited to, electrical memory (eg, DRAM), non-electrical memory (eg, ROM), graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays , touchscreen monitors, touchscreen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices ( such as hard drives, compact discs (CDs), digital versatile discs (DVDs), etc.). As variously described herein, any of the components included in computing system 1000 may include one or more integrated circuit structures configured with one or more conductive interconnect components having graphite barrier layers. These integrated circuit structures may be used, for example, to implement on-board processor caches or memory arrays or other circuit components including interconnects. In certain embodiments, multiple components may be integrated into one or more wafers (eg, note that the communication chip 1006 may be part of the processor 1004 or integrated into the processor 1004).

通訊晶片1006能夠無線通訊以用於自計算系統1000傳輸資料及對計算系統1000傳輸資料。「無線」一詞及其衍生詞用以說明經由使用藉由非固體介質之調變的電磁輻射來傳輸資料的電路、裝置、系統、方法、技術、通訊通道、等等。此詞並非意指相關連裝置未含有任何接線，但是在某些實施方式中它們可能未含任何接線。通訊晶片1006可以實施數種無線標準或是通信協定之任意者，包括但不限於Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE 802.16系列)、IEEE 802.20、長期進化(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍牙、其衍生、以及以3G、4G、5G、及更新的世代來標示的任何其它無線通信協定。計算系統1000包括複數通訊晶片1006。舉例而言，第一通訊晶片1006可以專用於較短範圍的無線通訊，例如Wi-Fi及藍牙，而第二通訊晶片1006可以專用於較長範圍的無線通訊，例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO、等等。 The communication chip 1006 is capable of wireless communication for transferring data to and from the computing system 1000 . The term "wireless" and its derivatives are used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that transmit data through the use of electromagnetic radiation modulated by non-solid media. This term does not mean that the associated devices do not contain any wiring, although in some embodiments they may not contain any wiring. The communication chip 1006 can implement any of several wireless standards or communication protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless communication protocol denoted by 3G, 4G, 5G, and later generations. Computing system 1000 includes a plurality of communication chips 1006 . For example, the first communication chip 1006 can be dedicated to short-range wireless communication, such as Wi-Fi and Bluetooth, and the second communication chip 1006 can be dedicated to longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA , WiMAX, LTE, Ev-DO, etc.

計算系統1000的處理器1004包括封裝在處理器1004之內的積體電路晶粒。如本文中各種描述，在本揭露的某些實施方式中，處理器的積體電路晶粒包括板載記憶體電路，其係由配置有石墨障壁層的一個或多個積體電路結構來實現。「處理器」一詞意指處理來自暫存器 及/或記憶體的電子資料以將電子資料轉換成儲存在暫存器及/或記憶體中的其它電子資料之任何裝置或裝置的一部份。 The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004 . As variously described herein, in certain embodiments of the present disclosure, an IC die of a processor includes on-board memory circuitry implemented by one or more IC structures configured with a graphite barrier layer . The term "processor" means processing from a register and/or memory to convert electronic data into other electronic data stored in registers and/or memory, any device or part of a device.

通訊晶片1006也可包括封裝於通訊晶片1006之內的積體電路晶粒。根據某些這樣的實施例實施方式，通訊晶片的積體電路晶粒包括用如本文中各種描述形成的一個或多個積體電路結構實現的一個或多個裝置(例如，在給定互連體層內的鑲嵌和雙鑲嵌石墨障壁層，或可由薄石墨障壁層受益的其它半導體結構)。注意，根據本揭露將領會，多標準無線能力可以直接整合到處理器1004中(例如，其中任何通訊晶片1006的功能被整合到處理器1004中，而不是具有分開的通訊晶片)。還要注意，處理器1004可以是具有這種無線能力的晶片組。簡言之，可以使用任何數量的處理器1004及/或通訊晶片1006。同樣，任何一個晶片或晶片組可以具有整合其中的多個功能。 The communication chip 1006 may also include an integrated circuit die packaged within the communication chip 1006 . According to certain such example implementations, an integrated circuit die of a communication die includes one or more devices (eg, at a given interconnect) implemented with one or more integrated circuit structures formed as variously described herein. damascene and dual damascene graphite barrier layers within bulk layers, or other semiconductor structures that could benefit from thin graphite barrier layers). Note that, as will be appreciated from this disclosure, multi-standard wireless capabilities may be integrated directly into the processor 1004 (eg, where the functionality of any communication chip 1006 is integrated into the processor 1004, rather than having a separate communication chip). Note also that the processor 1004 may be a chipset with such wireless capabilities. In short, any number of processors 1004 and/or communication chips 1006 may be used. Likewise, any one chip or chip set may have multiple functions integrated therein.

在各種的實施中，計算系統1000可以是膝上型電腦、筆記型電腦、超薄筆記型電腦、智慧型電話、平板電腦、個人數位助理(PDA)、及超薄行動PC、行動電話、桌上型電腦、伺服器、印表機、掃描器、監視器、機上盒、娛樂控制單元、數位相機、可攜式音樂播放器、或是數位攝影機。在進一步的實現中，如本文中各種描述，計算系統1000可以是處理資料或採用被配置有具有石墨障壁層的一個或多個導電互連體部件的積體電路部件 的任何其他電子裝置。 In various implementations, computing system 1000 may be a laptop, notebook, ultra-thin notebook, smart phone, tablet, personal digital assistant (PDA), and ultra-thin mobile PC, mobile phone, desk PCs, servers, printers, scanners, monitors, set-top boxes, entertainment control units, digital cameras, portable music players, or digital video cameras. In further implementations, as variously described herein, computing system 1000 may be an integrated circuit component that processes data or employs one or more conductive interconnect components having a graphite barrier layer. any other electronic device.

進一步的實施例實施方式 Further Example Implementation

將明瞭許多實施方式，並且本文描述的部件可以組合在任何數量的配置中。以下實施例屬於另外的實施例實施方式，從其中可明瞭許多排列和構造。 Numerous embodiments will be apparent, and the components described herein may be combined in any number of configurations. The following examples pertain to additional example embodiments from which many arrangements and configurations will be apparent.

實施例1為一種積體電路裝置，包括：層間介電質(ILD)部件；導電互連體部件；以及石墨障壁層，位於該介電質部件和該導電互連體部件之間，該石墨障壁層具有小於2奈米的最大厚度。 Embodiment 1 is an integrated circuit device comprising: an interlayer dielectric (ILD) feature; a conductive interconnect feature; and a graphite barrier layer between the dielectric feature and the conductive interconnect feature, the graphite The barrier layer has a maximum thickness of less than 2 nanometers.

實施例2包括實施例1的標的，其中該石墨障壁層具有小於1.5奈米的最大厚度。 Embodiment 2 includes the subject matter of Embodiment 1, wherein the graphitic barrier layer has a maximum thickness of less than 1.5 nanometers.

實施例3包括實施例1至2中之任一者的標的，其中該石墨障壁層具有小於1奈米的最大厚度。 Embodiment 3 includes the subject matter of any one of Embodiments 1-2, wherein the graphitic barrier layer has a maximum thickness of less than 1 nanometer.

實施例4包括實施例1至3中之任一者的標的，其中該石墨障壁層具有小於0.5奈米的最大厚度。 Embodiment 4 includes the subject matter of any one of Embodiments 1-3, wherein the graphitic barrier layer has a maximum thickness of less than 0.5 nanometers.

實施例5包括實施例1至4中之任一者的標的，其中該石墨障壁層包括基於該石墨障壁層的重量的至少5%重量的石墨烯。 Embodiment 5 includes the subject matter of any one of Embodiments 1-4, wherein the graphitic barrier layer includes at least 5% by weight graphene based on the weight of the graphitic barrier layer.

實施例6包括實施例1至5中之任一者的標的，其中該石墨障壁層包括基於該石墨障壁層的重量的至少25%重量的石墨烯。 Embodiment 6 includes the subject matter of any one of Embodiments 1-5, wherein the graphitic barrier layer includes at least 25% by weight graphene based on the weight of the graphitic barrier layer.

實施例7包括實施例1至6中之任一者的標的，其中該石墨障壁層包括基於該石墨障壁層的重量的至 少30%重量的石墨烯。 Embodiment 7 includes the subject matter of any one of embodiments 1-6, wherein the graphite barrier layer comprises to 30% less graphene by weight.

實施例8包括實施例1至7中之任一者的標的，其中該石墨障壁層的該厚度基本上是均勻的，使得該層的最薄部分係在該層的最厚部分的35%內。 Embodiment 8 includes the subject matter of any one of embodiments 1-7, wherein the thickness of the graphite barrier layer is substantially uniform such that the thinnest portion of the layer is tied within 35% of the thickest portion of the layer .

實施例9包括實施例1至8中之任一者的標的，其中該石墨障壁層的該厚度基本上是均勻的，使得該層的最薄部分係在該層的最厚部分的20%內。 Embodiment 9 includes the subject matter of any of embodiments 1-8, wherein the thickness of the graphite barrier layer is substantially uniform such that the thinnest portion of the layer is tied within 20% of the thickest portion of the layer .

實施例10包括實施例1至9中之任一者的標的，其中該石墨障壁層包括至少一石墨烯單層。 Embodiment 10 includes the subject matter of any one of embodiments 1-9, wherein the graphite barrier layer includes at least one graphene monolayer.

實施例11包括實施例1至10中之任一者的標的，其中該石墨障壁基本上由石墨烯單層組成。 Embodiment 11 includes the subject matter of any of embodiments 1-10, wherein the graphite barrier consists essentially of a graphene monolayer.

實施例12包括實施例1至11中之任一者的標的，其中每個導電互連體部件和石墨障壁層具有雙鑲嵌橫截面輪廓。 Embodiment 12 includes the subject matter of any one of Embodiments 1-11, wherein each conductive interconnect member and graphite barrier layer has a dual damascene cross-sectional profile.

實施例13為一種積體電路裝置，包括：層間介電質(ILD)部件；導電互連體部件；以及石墨障壁層，位於該介電質部件和該導電互連體部件之間，其中該石墨障壁層具有基本上是均勻的厚度，使得該層的最薄部分係在該層的最厚部分的35%內。 Embodiment 13 is an integrated circuit device comprising: an interlayer dielectric (ILD) feature; a conductive interconnect feature; and a graphite barrier layer between the dielectric feature and the conductive interconnect feature, wherein the The graphite barrier layer has a substantially uniform thickness such that the thinnest portion of the layer is tied within 35% of the thickest portion of the layer.

實施例14包括實施例13的標的，其中該石墨障壁層的最薄部分係在該石墨障壁層的最厚部分的20%內。 Embodiment 14 includes the subject matter of embodiment 13, wherein the thinnest portion of the graphitic barrier layer is within 20% of the thickest portion of the graphitic barrier layer.

實施例15包括實施例13至14中之任一者的標的，其中該石墨障壁層具有小於2奈米的最大厚度。 Embodiment 15 includes the subject matter of any one of Embodiments 13-14, wherein the graphitic barrier layer has a maximum thickness of less than 2 nanometers.

實施例16包括實施例13至15中之任一者的標的，其中該石墨障壁層具有小於1.5奈米的最大厚度。 Embodiment 16 includes the subject matter of any one of Embodiments 13-15, wherein the graphitic barrier layer has a maximum thickness of less than 1.5 nanometers.

實施例17包括實施例13至16中之任一者的標的，其中該石墨障壁層具有小於1奈米的最大厚度。 Embodiment 17 includes the subject matter of any one of Embodiments 13-16, wherein the graphitic barrier layer has a maximum thickness of less than 1 nanometer.

實施例18包括實施例13至17中之任一者的標的，其中該石墨障壁層具有小於0.5奈米的最大厚度。 Embodiment 18 includes the subject matter of any one of Embodiments 13-17, wherein the graphitic barrier layer has a maximum thickness of less than 0.5 nanometers.

實施例19包括實施例13至18中之任一者的標的，其中該石墨障壁層包括基於該石墨障壁層的重量的至少5%重量的石墨烯。 Embodiment 19 includes the subject matter of any one of Embodiments 13-18, wherein the graphitic barrier layer includes at least 5% by weight graphene based on the weight of the graphitic barrier layer.

實施例20包括實施例13至19中之任一者的標的，其中該石墨障壁層包括基於該石墨障壁層的重量的至少25%重量的石墨烯。 Embodiment 20 includes the subject matter of any one of Embodiments 13-19, wherein the graphitic barrier layer includes at least 25% by weight graphene based on the weight of the graphitic barrier layer.

實施例21包括實施例13至20中之任一者的標的，其中該石墨障壁層包括基於該石墨障壁層的重量的至少30%重量的石墨烯。 Embodiment 21 includes the subject matter of any one of Embodiments 13-20, wherein the graphitic barrier layer includes at least 30% by weight graphene based on the weight of the graphitic barrier layer.

實施例22包括實施例13至21中之任一者的標的，其中該石墨障壁層包括至少一石墨烯單層。 Embodiment 22 includes the subject matter of any one of Embodiments 13-21, wherein the graphite barrier layer includes at least one graphene monolayer.

實施例23包括實施例13至22中之任一者的標的，其中該石墨障壁層基本上由石墨烯單層組成。 Embodiment 23 includes the subject matter of any of embodiments 13-22, wherein the graphite barrier layer consists essentially of a graphene monolayer.

實施例24包括實施例13至23中之任一者的標的，其中每個導電互連體部件和石墨障壁層具有雙鑲嵌橫截面輪廓。 Embodiment 24 includes the subject matter of any one of Embodiments 13-23, wherein each conductive interconnect feature and graphite barrier layer has a dual damascene cross-sectional profile.

實施例25為一種行動計算裝置，包括實施例1至24中任一者的標的。 Embodiment 25 is a mobile computing device including the subject matter of any one of Embodiments 1 to 24.

實施例26為一種產生石墨障壁層之方法，該方法包括：形成介電質部件；施加障壁層前驅物材料到該介電質部件；沉積導電部件在該障壁層前驅物材料上；以及轉化該障壁層前驅物材料為石墨障壁層。 Embodiment 26 is a method of producing a graphitic barrier layer, the method comprising: forming a dielectric feature; applying a barrier layer precursor material to the dielectric feature; depositing a conductive feature on the barrier layer precursor material; and converting the barrier layer precursor material The barrier layer precursor material is a graphite barrier layer.

實施例27包括實施例26的標的，其中該障壁層前驅物材料包含自組裝化合物。 Embodiment 27 includes the subject matter of embodiment 26, wherein the barrier layer precursor material comprises a self-assembling compound.

實施例28包括實施例26至27的標的，其中該障壁層前驅物材料限於單一種的自組裝化合物。 Embodiment 28 includes the subject matter of Embodiments 26-27, wherein the barrier layer precursor material is limited to a single self-assembling compound.

實施例29包括實施例26至27的標的，其中該障壁層前驅物材料包括多於一種的自組裝化合物。 Embodiment 29 includes the subject matter of embodiments 26-27, wherein the barrier layer precursor material includes more than one self-assembling compound.

實施例30包括實施例26至29的標的，其中該障壁層前驅物材料包括自組裝單層。 Embodiment 30 includes the subject matter of Embodiments 26-29, wherein the barrier layer precursor material comprises a self-assembled monolayer.

實施例31包括實施例26至30的標的，其中該障壁層前驅物材料包括烴基自組裝單層。 Embodiment 31 includes the subject matter of embodiments 26-30, wherein the barrier layer precursor material comprises a hydrocarbon-based self-assembled monolayer.

實施例32包括實施例26至31的標的，其中該障壁層前驅物材料包括一或多個芳族化合物。 Embodiment 32 includes the subject matter of Embodiments 26-31, wherein the barrier layer precursor material includes one or more aromatic compounds.

實施例33包括實施例26至32的標的，其中障壁層前驅物材料可包括至少一種下列化合物：三氯(苯基)矽烷、二苯基二氯鍺烷、4-聯苯基二甲基氯矽烷、對氨基苯基三甲氧基矽烷、4-(2-(三乙氧基甲矽烷基)乙基)吡啶和(9)-蒽基三甲氧基矽烷。 Embodiment 33 includes the subject matter of embodiments 26-32, wherein the barrier layer precursor material can include at least one of the following compounds: trichloro(phenyl)silane, diphenyldichlorogermane, 4-biphenyldimethyl chloride Silane, p-aminophenyltrimethoxysilane, 4-(2-(triethoxysilyl)ethyl)pyridine and (9)-anthryltrimethoxysilane.

實施例34包括實施例26至33的標的，其中轉化該障壁層前驅物材料為石墨障壁層係藉由對該障壁層前驅物材料進行熱處理來完成。 Embodiment 34 includes the subject matter of embodiments 26-33, wherein converting the barrier layer precursor material to a graphite barrier layer is accomplished by thermally treating the barrier layer precursor material.

實施例35包括實施例34的標的，其中熱處理包含加熱障壁層前驅物材料到至少600℃。 Embodiment 35 includes the subject matter of Embodiment 34, wherein the thermal treatment comprises heating the barrier layer precursor material to at least 600°C.

實施例36包括實施例34至35的標的，其中熱處理包含加熱障壁層前驅物材料到至少900℃。 Embodiment 36 includes the subject matter of Embodiments 34-35, wherein the thermal treatment comprises heating the barrier layer precursor material to at least 900°C.

實施例37包括實施例26至36的標的，其中轉化該障壁層前驅物材料為石墨障壁層發生在大於1atm的壓力下。 Embodiment 37 includes the subject matter of embodiments 26-36, wherein converting the barrier layer precursor material to a graphite barrier layer occurs at a pressure greater than 1 atm.

實施例38包括實施例26至37的標的，其中轉化該障壁層前驅物材料為石墨障壁層發生在至少400℃的溫度和大於1atm的壓力下。 Embodiment 38 includes the subject matter of Embodiments 26-37, wherein converting the barrier layer precursor material to a graphite barrier layer occurs at a temperature of at least 400° C. and a pressure greater than 1 atm.

實施例39包括實施例26至38的標的，其中施加該障壁層前驅物材料發生在該液相中。 Embodiment 39 includes the subject matter of Embodiments 26-38, wherein applying the barrier layer precursor material occurs in the liquid phase.

實施例40包括實施例26至38的標的，其中施加該障壁層前驅物材料發生在該氣相中。 Embodiment 40 includes the subject matter of Embodiments 26-38, wherein applying the barrier layer precursor material occurs in the gas phase.

實施例41包括實施例26至40的標的，且進一步包括在轉化障壁層前驅物材料為石墨障壁層之前覆蓋障壁層前驅物材料。 Embodiment 41 includes the subject matter of Embodiments 26-40, and further includes covering the barrier layer precursor material prior to converting the barrier layer precursor material to a graphite barrier layer.

實施例42包括實施例41的標的，其中藉由在該障壁層前驅物材料上沉積氣密層來完成覆蓋該障壁層前驅物材料。 Embodiment 42 includes the subject matter of embodiment 41, wherein covering the barrier layer precursor material is accomplished by depositing an air barrier layer over the barrier layer precursor material.

實施例43包括實施例42的標的，其中該氣密層包括氮化矽。 Embodiment 43 includes the subject matter of embodiment 42, wherein the hermetic layer includes silicon nitride.

實施例44包括實施例26至43的標的，且進一步包括在施加該障壁層前驅物材料之前處理該介電質部 件的表面。 Embodiment 44 includes the subject matter of Embodiments 26-43, and further includes treating the dielectric portion prior to applying the barrier layer precursor material surface of the piece.

實施例45包括實施例44的標的，其中處理該介電質部件的表面使該介電質部件的表面親水。 Embodiment 45 includes the subject matter of embodiment 44, wherein treating the surface of the dielectric feature renders the surface of the dielectric feature hydrophilic.

實施例46包括實施例26至45的標的，且進一步包括用一種或多種催化劑活化障壁層前驅物材料。 Embodiment 46 includes the subject matter of Embodiments 26-45, and further includes activating the barrier layer precursor material with one or more catalysts.

實施例47包括實施例46的標的，其中該一種或多種催化劑包括以下金屬中的至少一種：鈀、鎳、鈷、釕、鉑、金和銀。 Embodiment 47 includes the subject matter of embodiment 46, wherein the one or more catalysts include at least one of the following metals: palladium, nickel, cobalt, ruthenium, platinum, gold, and silver.

實施例48包括實施例26至47的標的，其中在轉化該障壁層前驅物材料為石墨障壁層之後，去除導電部件，並將個別的導電部件施加到該石墨障壁層。 Embodiment 48 includes the subject matter of Embodiments 26-47, wherein after converting the barrier layer precursor material to a graphite barrier layer, conductive features are removed and individual conductive features are applied to the graphite barrier layer.

實施例49包括實施例26至48的標的，且進一步包括將該石墨障壁層合併到積體電路裝置中。 Embodiment 49 includes the subject matter of Embodiments 26-48, and further includes incorporating the graphite barrier layer into an integrated circuit device.

實施例50是被配置為執行實施例26至49中的一個或多個標的之裝置。 Embodiment 50 is an apparatus configured to perform one or more of the subject matter of Embodiments 26-49.

實施例51是由實施例26至49中任一個的標的所形成的積體電路裝置。 Embodiment 51 is an integrated circuit device formed from the subject matter of any of Embodiments 26-49.

針對說明與描述之目的，已顯示了前文對本揭示之實施例實施方式之描述。其不旨在窮舉或將本揭露限制在所揭露絲毫不差的形式中。按照本揭露，許多修改與變化是可行的。本揭露之範圍並無意受此詳細描述所限制，而是受所附申請專利範圍的限制。 The foregoing descriptions of embodiments of the present disclosure have been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the exact form disclosed. Many modifications and variations are possible in light of the present disclosure. The scope of the present disclosure is not intended to be limited by this detailed description, but rather by the scope of the appended claims.

100‧‧‧積體電路結構 100‧‧‧Integrated Circuit Structure

110‧‧‧層間介電質層 110‧‧‧Interlayer Dielectric Layer

210‧‧‧石墨障壁層 210‧‧‧Graphite barrier layer

310‧‧‧互連體 310‧‧‧Interconnect

Claims (10)

一種產生石墨烯障壁層之方法，該方法包含：形成介電質部件；處理該介電質部件的表面使該介電質部件的表面親水；施加障壁層前驅物材料到該介電質部件；沉積導電部件在該障壁層前驅物材料上；以包括氮化矽的氣密材料覆蓋該障壁層前驅物材料；以及轉化該障壁層前驅物材料為石墨烯障壁層，其中，該導電部件和該石墨烯障壁層具有雙鑲嵌橫截面輪廓。 A method of producing a graphene barrier layer, the method comprising: forming a dielectric feature; treating a surface of the dielectric feature to make the surface of the dielectric feature hydrophilic; applying a barrier layer precursor material to the dielectric feature; depositing a conductive member on the barrier layer precursor material; covering the barrier layer precursor material with a hermetic material comprising silicon nitride; and converting the barrier layer precursor material into a graphene barrier layer, wherein the conductive member and the The graphene barrier layer has a dual damascene cross-sectional profile. 如申請專利範圍第1項之方法，其中該障壁層前驅物材料包含自組裝化合物。 The method of claim 1, wherein the barrier layer precursor material comprises a self-assembling compound. 如申請專利範圍第1項之方法，其中該障壁層前驅物材料包含自組裝單層。 The method of claim 1, wherein the barrier layer precursor material comprises a self-assembled monolayer. 如申請專利範圍第1項之方法，其中該障壁層前驅物材料包含烴基自組裝單層。 The method of claim 1, wherein the barrier layer precursor material comprises a hydrocarbon-based self-assembled monolayer. 如申請專利範圍第1項之方法，其中轉化該障壁層前驅物材料為石墨烯障壁層係藉由對該障壁層前驅物材料進行熱處理來完成。 The method of claim 1, wherein converting the barrier layer precursor material into a graphene barrier layer is accomplished by thermally treating the barrier layer precursor material. 如申請專利範圍第1項之方法，其中轉化該障壁層前驅物材料為石墨烯障壁層發生在大於1atm的壓力下。 The method of claim 1, wherein converting the barrier layer precursor material to a graphene barrier layer occurs at a pressure greater than 1 atm. 如申請專利範圍第1項之方法，其中施加該障壁層前驅物材料發生在該液相中。 The method of claim 1, wherein applying the barrier layer precursor material occurs in the liquid phase. 如申請專利範圍第1項之方法，其中施加該障壁層前驅物材料發生在該氣相中。 The method of claim 1, wherein applying the barrier layer precursor material occurs in the gas phase. 如申請專利範圍第1項之方法，進一步包含用一或多種催化劑活化該障壁層前驅物材料。 The method of claim 1 of the claimed scope, further comprising activating the barrier layer precursor material with one or more catalysts. 一種積體電路裝置，係藉由申請專利範圍第1至9項中任一項之方法所產生。 An integrated circuit device is produced by the method of any one of items 1 to 9 of the claimed scope.
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