TWI756657B - Improving metal contacts to group iv semiconductors by inserting interfacial atomic monolayers - Google Patents
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本發明有關於藉由在金屬與半導體之間的界面處***第V族或第III族原子單層，或***由一第V族原子單層與一第III族原子單層所製成的雙層，或***多個此種雙層而降低金屬–半導體(第IV族)接面之比接觸電阻的技術。The present invention relates to bilayers made by intercalating a monolayer of Group V or Group III atoms, or of a monolayer of Group V atoms and a monolayer of Group III atoms, at the interface between metal and semiconductor A technique for reducing the specific contact resistance of the metal-semiconductor (Group IV) junction, or inserting multiple such bilayers.
當電晶體的尺寸縮減至奈米級尺寸，例如成為超薄主體(UTB)絕緣層上覆矽(SOI)場效電晶體(FET)、鰭式場效電晶體(FinFET)及奈米線場效電晶體(nanowire FET)的形式，但與電晶體源極和汲極卻帶來不受歡迎的電阻而對這些元件及使用這些電晶體所製成之積體電路產品的效能造成越來越重的負擔。此外，當電晶體源極區和汲極區的尺寸縮小至低於約10奈米(nm)時，理論上預期且實驗上亦證明會降低摻雜劑活化作用(dopant activation)。摻雜劑活化作用意味著藉由刻意在宿主半導體(semiconductor host)中引入雜質物種以貢獻出所欲的自由載子(電子或電洞)。此種奈米級摻雜劑活化作用降低進一步造成在奈米級金屬接觸的摻雜源/汲極(S/D)區處及在奈米級摻雜區的主體部分內產生不受歡迎的高電阻。若半導體中的有效摻雜降低，金屬接觸對半導體的電阻則會增加，此電阻增加主要是由於在金屬-半導體接觸處出現蕭特基能障(Schottky barrier)所致。When the size of transistors is reduced to nanoscale, such as ultra-thin bulk (UTB) silicon-on-insulator (SOI) field effect transistors (FETs), fin field effect transistors (FinFETs) and nanowire field effect transistors In the form of transistors (nanowire FETs), but with the undesired resistance of the source and drain of the transistors, the performance of these components and the integrated circuit products made with these transistors is becoming more and more important. burden. In addition, as the dimensions of transistor source and drain regions shrink below about 10 nanometers (nm), it is theoretically expected and experimentally demonstrated to reduce dopant activation. Dopant activation means donating desired free carriers (electrons or holes) by deliberately introducing impurity species into the semiconductor host. This reduction in nanoscale dopant activation further contributes to undesired generation at the doped source/drain (S/D) regions of the nanoscale metal contacts and within the bulk portion of the nanoscale doped regions. high resistance. If the effective doping in the semiconductor decreases, the resistance of the metal contact to the semiconductor increases, which is mainly due to the appearance of the Schottky barrier at the metal-semiconductor contact.
眾人皆知在靠近金屬-半導體界面的半導體淺區域中進行高濃度摻雜，可藉由減小蕭特基能障的寬度而降低金屬-半導體接觸的電阻。儘管從電性反應的觀點(例如，由電流-電壓測量)來看是能障寬度減小，但蕭特基高度似乎是降低了。J. M. Shannon在1976年的《固態電子學(Solid-State Electronics)》期刊第19期537～543頁發表標題為「利用高摻雜表面層控制蕭特基能障高度(Control of Schottky barrier height using highly doped surface layers)」的早期文獻中描述可利用表面摻雜來達到此「有效的能障高度」降低。亦知可利用所謂使金屬矽化物產生摻雜劑偏析現象(dopant segregation)而將高濃度的摻雜原子引入靠近金屬接觸的半導體淺區域中。A. Kikuchi與S. Sugaki在1982年5月的《應用物理(J. Appl. Phys)》期刊第53期第5卷中報告在PtSi形成期間，所佈植的磷原子會累積在靠近PtSi-Si界面處並降低n型矽的蕭特基能障測量高度。蕭特基二極體的測量(有效)能障高度下降是由於累積在矽中的磷原子導致該能障更為陡峭所造成。也就是Shannon在1976年所描述的效應造成該種結果。It is known that high concentration doping in the shallow regions of the semiconductor near the metal-semiconductor interface reduces the resistance of the metal-semiconductor contact by reducing the width of the Schottky barrier. Although the energy barrier width decreases from an electrical response point of view (eg, as measured by current-voltage), the Schottky height appears to decrease. JM Shannon published the title "Control of Schottky barrier height using highly doped surface layer" in "Solid-State Electronics", No. 19, pp. 537-543 in 1976. This "effective energy barrier height" reduction can be achieved using surface doping as described in earlier literature on doped surface layers. It is also known to utilize a phenomenon called dopant segregation in metal silicides to introduce high concentrations of dopant atoms into shallow regions of the semiconductor near the metal contacts. A. Kikuchi and S. Sugaki reported in the May 1982 issue of J. Appl. Phys, No. 53, Vol. 5 that during the formation of PtSi, implanted phosphorus atoms accumulate near PtSi- The measured height of the Schottky barrier at the Si interface and lowering the n-type silicon. The drop in the measured (effective) energy barrier height for Schottky diodes is due to the steeper energy barrier caused by the accumulation of phosphorus atoms in the silicon. It is the effect described by Shannon in 1976 that causes this result.
過去數個十年來，矽微電子工業仰賴使靠近金屬-矽接觸的矽中具有高摻雜濃度以作為使電晶體源極和汲極獲得可接受之低接觸電阻的手段。接觸金屬多半是金屬矽化物，且近來多為矽化鎳或矽化鎳鉑。在未來，當電晶體尺寸持續縮減且該接觸電阻變成在源極與汲極間之總電阻中占較大部分(從而成為重要的效能限制因子時)，可預期到此減小接觸電阻的方法將不敷使用。於2011年公開的最新國際半導體技術藍圖(ITRS)報告指出，預期在2014年，電晶體閘極長度規格會達到18奈米，且規定比接觸電阻(specific contact resistance)不超過1.0x10-8 歐姆.平方公分(Ohm.cm2 )，但尚未有已知的解決方案能解決塊體MOS電晶體(bulk MOS transistor)中的接觸電阻問題。日益顯示必需降低在金屬-半導體接觸處的蕭特基能障，以使接觸電阻降低至可接受的程度，以MOS電晶體的摻雜源/汲極接觸為例，需使接觸電阻遠低於1.0x10-8 歐姆.平方公分。能夠降低蕭特基能障且從而降低與摻雜半導體區域接觸之電阻的技術亦可應用在所謂的「金屬源/汲極電晶體」上，金屬源/汲極電晶體不具有經摻雜的源極和汲極，而是利用金屬與電晶體通道之間直接接觸(電晶體通道是含有自由載子的區域，能藉由閘極上的電壓來調控自由載子並在源極與汲極之間傳遞電流)。For the past several decades, the silicon microelectronics industry has relied on high doping concentrations in the silicon near the metal-silicon contacts as a means of achieving acceptably low contact resistances at the source and drain of transistors. The contact metal is mostly metal silicide, and more recently nickel silicide or nickel-platinum silicide. In the future, as transistor sizes continue to shrink and the contact resistance becomes a larger portion of the total resistance between source and drain (and thus becomes an important performance limiting factor), this approach to reducing contact resistance is expected will not be sufficient. The latest International Technology Roadmap for Semiconductors (ITRS) report published in 2011 pointed out that it is expected that in 2014, the transistor gate length specification will reach 18 nm, and the specific contact resistance (specific contact resistance) should not exceed 1.0x10 -8 ohm .square centimeters (Ohm.cm 2 ), but there is no known solution to the contact resistance problem in bulk MOS transistors. It is increasingly apparent that the Schottky barrier at the metal-semiconductor contact must be lowered to reduce the contact resistance to an acceptable level. Taking the doped source/drain contact of a MOS transistor as an example, the contact resistance needs to be much lower than 1.0x10 -8 ohm. cm². Techniques capable of lowering the Schottky barrier and thus the resistance in contact with doped semiconductor regions can also be applied to so-called "metal source/drain transistors", which do not have doped The source and drain electrodes use the direct contact between the metal and the transistor channel (the transistor channel is a region containing free carriers, which can be regulated by the voltage on the gate and between the source and drain electrodes. transfer current).
在1991至1992年間所公開的文獻中報導出Baroni、Resta、Baldereschi及其他學者對理論預測做出的實驗證明，實驗證明由兩個不同元素所形成的雙內層(double intralayer)可建立界面偶極，不僅能夠修改異質接面能帶的不連續性(heterojunction band discontinuities)，還能在同質接面中產生能帶不連續性。McKinley等人在1991年《真空科技(J. Vac. Sci. Technol)》期刊五月/六月號第A9(3)期且標題為「藉由超薄Ga-As偶極層控制Ge同質接面能帶偏移(Control of Ge homojunction band offsets via ultrathin Ga-As dipole layers)」的文章中以及在1992年《應用表面科學》期刊56～58期第762～765頁且標題為「藉由超薄Ga-As偶極層控制Ge同質接面能帶偏移(Control of Ge homojunction band offsets via ultrathin Ga-As dipole layers)」的文章中率先報導可在{111}-晶向的Ge同質接面處獲得035～0.45電子伏特(eV)。In the literature published between 1991 and 1992, Baroni, Resta, Baldereschi and others reported experimental proof of theoretical predictions that a double intralayer formed by two different elements could create an interface couple It can not only modify the heterojunction band discontinuities (heterojunction band discontinuities), but also create band discontinuities in the homojunction. McKinley et al. in J. Vac. Sci. Technol 1991 May/June No. A9(3) titled "Controlling Ge Homogeneous Junctions by Ultrathin Ga-As Dipole Layers" In the article "Control of Ge homojunction band offsets via ultrathin Ga-As dipole layers" and in the 1992 Journal of Applied Surface Science 56-58 pp. 762-765 with the title "Ultrathin Ga-As dipole layers" The article "Control of Ge homojunction band offsets via ultrathin Ga-As dipole layers by thin Ga-As dipole layers" was the first to report that Ge homojunctions in {111}-orientation Obtained at 035 ~ 0.45 electron volts (eV).
於室溫下在p-型Ge(111)基板上進行砷、鎵和鍺沉積。利用原位內核軌域X射線光致發光法(in situ core level x-ray photoluminescence)測量價電能帶偏移。藉由鍺(Ge)的3d內核軌域***成兩部分可證實所沉積的Ge區域(覆蓋層)對於Ge基板具有電價能帶偏移；其中一部份是由Ge基板所造成，另一部分則是由Ge覆蓋層所造成。可利用「鎵(Ga)優先」或「砷(As)優先」的生長順序引入Ga-As偶極內層(Ga-As dipole intralayers)而在Ge同質接面中獲得正電價能帶偏移或負電價能帶偏移。在較低能量(即，較受束縛)時，發現能帶偏移為0.35～0.45eV，且Ge價電能帶邊緣在該接面的砷(As)側上。可根據W. A. Harrison等人在1978年《物理評論》期刊(Phys. Rev. B 18, 4402, 1978)標題為「極性異質接合界面(Polar Heterojunction Interfaces)」之文章中所述的哈里森「理論鍊金術」模型來解釋偶極內層。因此，使用內層(intralayer)來控制能帶的不連續性可應用在同質接面上，以擴大其能帶偏移工程的潛在領域而超越半導體異質接面。Arsenic, gallium and germanium depositions were performed on p-type Ge(111) substrates at room temperature. Valence band shifts were measured using in situ core level x-ray photoluminescence. By splitting the 3d core orbital of germanium (Ge) into two parts, it can be confirmed that the deposited Ge region (cap layer) has a valence band offset to the Ge substrate; one part is caused by the Ge substrate, and the other part is caused by the Ge substrate. is caused by the Ge overlay. Ga-As dipole intralayers can be introduced into Ga-As dipole intralayers using the growth sequence of "gallium (Ga) first" or "arsenic (As) first" to obtain a positive valence band offset or Negative electricity price band offset. At lower energies (ie, more bound), the band shift was found to be 0.35-0.45 eV, and the Ge valence band edge was on the arsenic (As) side of the junction. According to Harrison's "theoretical chain" described by WA Harrison et al. Alchemy" model to explain the inner dipole layer. Therefore, the use of intralayers to control band discontinuities can be applied to homojunctions to expand the potential field of band-shift engineering beyond semiconductor heterojunctions.
在1992年，繼McKinley等人的報告之後，Marsi等人在1992年2月15日的《應用物理(J. Appl. Phys )》期刊第71期第4卷中發表標題為「同質接面能帶排列的顯微操作(Microscopic manipulation of homojunction band lineups)」之文章、1992年2月15日的《真空科技(J. Vac. Sci. Technol.)》期刊七月/八月號第A10(4)期中發表標題為「利用偶極內層：鎵內的鋁-砷層誘發同質接面能帶不連續性(Homojunction band discontinuities induced by dipolar intralayers: Al-As in Ge)」之文章以及1992年8月15日的《應用物理》期刊第72期第4卷中發表標題為「人造同質接面能帶不連續性的局部性質(Local nature of artificial homojunction band discontinuities)」之文章。在該第一篇文章中，Marsi等人報告當在界面處***原子級厚度的III-V族雙內層時，在Si-Si及Ge-Ge同質接面處可產生價電-能帶不連續性。同樣利用原位內核軌域X射線光致發光法測量價電能帶不連續性。在鍺(Ge)樣本中，藉由鍺(Ge)的3d內核軌域***成兩部分可證實所沉積的Ge區域(覆蓋層)對於Ge基板具有電價能帶偏移；且藉由矽(Si)的2p內核軌域的***可證實所沉積的Si區域對於Si基板具有電價能帶偏移。所觀察到不連續性的程度介在0.4至0.5eV的範圍間(例如Si-P-Ga-Si的不連續性為0.5eV，及Si-P-Al-Si的不連續性為0.4eV)，並且儘管大多數的理論預期偶極效應會造成較大的價電能帶不連續性，但此結果在定性方面上符合理論預測值。若先沉積陰離子，位於第IV族同質接面處的III-V族內層會系統性地誘發人造價電能帶不連續性。亦有報導指出，以在Si-Si同質接面使用鋁-磷(Al-P)或鎵-磷(Ga-P)內層為例，正如預期般，使界面沉積順序顛倒會導致價電能帶不連續性逆轉。In 1992, following the report of McKinley et al., Marsi et al. published in the February 15, 1992, J. Appl. Microscopic manipulation of homojunction band lineups" article, J. Vac. Sci. Technol., July/August 1992, Issue A10(4) ) published an article entitled "Homojunction band discontinuities induced by dipolar intralayers: Al-As in Ge" titled "Homojunction band discontinuities induced by dipolar intralayers: Al-As in Ge" and August 1992 An article titled "Local nature of artificial homojunction band discontinuities" was published in the "Applied Physics" journal, No. 72,
在第二篇文章中，同樣使用X射線光致發光法，並顯示在兩個{111}-晶向的鍺區域之間使用鋁-砷(Al-As)作為「偶極內層」能誘發類似的能帶偏移效應。特別是，採用「陰離子優先」的Ge(基板)-As-Al-Ge(覆蓋層)順序會得到0.4eV的偏移，此結果與McLinley所報導的「陰離子優先」As-Ga順序的結果一致，且相較於基板部分而言，該覆蓋層部分展現較低的鍵結能。第三篇文章研究III-V族雙層(內層)的多重堆疊。針對單個雙層、堆疊的兩個雙層以及堆疊的三個雙層所測得的價電能帶偏移值維持相等，為0.5eV。在2(Ga-P)及2(P-Ga)上進行的實驗與在2(Al-P)及2(P-Al)上進行的實驗完全一致；從單個雙層改成兩個雙層或甚至改成三個雙層都未觀察到價電能帶偏移值實質提高。因此結論是，在界面堆疊多個III-V族雙層不會提高單一個雙層的作用，這與依據多個連續偶極所作的基本預期相反。In the second article, X-ray photoluminescence was also used, and it was shown that the use of aluminum-arsenic (Al-As) as a "dipole inner layer" between two {111}-oriented germanium regions can induce Similar band-shift effects. In particular, a shift of 0.4 eV was obtained using the "anion-preferred" Ge (substrate)-As-Al-Ge (cap layer) sequence, a result consistent with the "anion-preferred" As-Ga sequence reported by McLinley , and the capping layer portion exhibits lower bonding energy than the substrate portion. The third article investigates multiple stacking of III-V bilayers (inner layers). The measured valence band offset values remain equal at 0.5 eV for a single bilayer, stacked two bilayers, and stacked three bilayers. Experiments performed on 2(Ga-P) and 2(P-Ga) were identical to those performed on 2(Al-P) and 2(P-Al); changed from a single bilayer to two bilayers No substantial increase in valence band offset was observed, or even changing to three bilayers. It is therefore concluded that stacking multiple III-V bilayers at the interface does not enhance the effect of a single bilayer, contrary to the basic expectation based on multiple consecutive dipoles.
Grupp與Connelly兩人在美國專利第7,084,423、7,176,483、7,462,860和7,884,003號及在審查中的美國專利申請案第2011/0169124號中描述一種金屬-半導體接觸，該等金屬-半導體接觸在金屬與第IV族半導體的界面處具有一界面層，藉以達到降低在該接觸處的蕭特基能障，且從而降低該接觸的比電阻(specific resistivity)。該界面層的可行實施例或實施方案中可包括單層(monolayer)的砷或氮。Both Grupp and Connelly, in US Patent Nos. 7,084,423, 7,176,483, 7,462,860 and 7,884,003 and co-pending US Patent Application No. 2011/0169124, describe a metal-semiconductor contact that An interface layer is provided at the interface of the group semiconductor, thereby reducing the Schottky energy barrier at the contact and thereby reducing the specific resistivity of the contact. Possible examples or embodiments of the interfacial layer may include a monolayer of arsenic or nitrogen.
本發明的顯著特徵是在單個秩序排列(例如，磊晶定向)的界面單層中組織刻意引入的第V族或第III族原子(或第II族或第VI族原子)。此外，本發明提供一種製程和結構，在該製程與結構中可藉由沉積且無需利用矽化反應(silicidation)而形成金屬接觸，其特徵在於允許使用更廣範圍的金屬來形成金屬-半導體接觸，尤其是在特殊應用上具有比金屬矽化物更加優良性質的金屬，例如具有更高的導電性、透光性或鐵磁性的金屬。當此等元件的尺寸縮小而具有20奈米或更小的臨界尺寸(例如，源極的寬度和高度)時，期望金屬源/汲極場效電晶體中具有最大限度的金屬導電性。例如所謂自旋電子學(spintronics)應用領域中的自旋效應電晶體的元件就需要從半導體到鐵磁金屬(例如釓)的有效自旋注入作用。具有鐵磁金屬源極和汲極與第IV族半導體通道的自旋-金屬-氧化物-半導體場效電晶體(spin-MOSFET)就是自旋效應電晶體的一個範例。在發光顯示器中，經常期望使金屬接觸能讓發射光良好地穿透(高透明度)且同時對於主動材料(active material)可形成低電阻接觸。反之，在光電元件(例如，半導體雷射或半導體模組)中，則可能希望金屬接觸電阻是不透明的，而使因光吸收作用所造成的損失降至最低。金屬矽化物具有些許透明度這個不希望具有的特性，造成光能量可能進入位在光電元件之光場中的矽化物區域，繼而使得光線在矽化物中被吸收。A distinguishing feature of the present invention is the organization of deliberately introduced Group V or Group III atoms (or Group II or Group VI atoms) in a single ordered (eg, epitaxially oriented) interfacial monolayer. Furthermore, the present invention provides a process and structure in which metal contacts can be formed by deposition without the use of silicidation, which is characterized by allowing the use of a wider range of metals to form metal-semiconductor contacts, Especially metals with better properties than metal silicides for special applications, such as metals with higher electrical conductivity, light transmission or ferromagnetic properties. As such components shrink in size to have critical dimensions (eg, source width and height) of 20 nanometers or less, maximum metal conductivity in metal source/drain field effect transistors is desired. Components such as spin-effect transistors in the field of so-called spintronics applications require efficient spin injection from semiconductors into ferromagnetic metals such as gadolinium. A spin-metal-oxide-semiconductor field-effect transistor (spin-MOSFET) with a ferromagnetic metal source and drain and a Group IV semiconductor channel is an example of a spin-effect transistor. In light emitting displays, it is often desirable to have metal contacts that allow good penetration of the emitted light (high transparency) and at the same time allow low resistance contacts to be formed for the active material. Conversely, in optoelectronic components (eg, semiconductor lasers or semiconductor modules), it may be desirable for the metal contact resistance to be opaque to minimize losses due to light absorption. Metal silicides have the undesirable property of being somewhat transparent, allowing light energy to enter the silicide regions in the light field of the photovoltaic element, which in turn allows light to be absorbed in the silicide.
本發明無需對位在金屬接觸附近的半導體進行摻雜，但本發明也可能與半導體摻雜步驟一同實施。本發明亦無需金屬矽化步驟。根據本發明實施例所構築的元件在半導體與金屬接觸之間的界面處含有至少一個秩序排列的第V族元素單層及/或一秩序排列的第III族元素單層。在形成至少一個秩序排列的界面原子單層之後沉積該金屬。The invention does not require doping of the semiconductor located near the metal contact, but the invention may also be practiced with a semiconductor doping step. The present invention also does not require a silicidation step. Devices constructed in accordance with embodiments of the present invention contain at least one ordered monolayer of Group V elements and/or an ordered monolayer of Group III elements at the interface between the semiconductor and the metal contact. The metal is deposited after forming at least one ordered monolayer of interfacial atoms.
本發明實施例提供在第IV族半導體與金屬之間設置有一或多個單層的電接觸，該半導體的特徵在於其結晶晶格結構及由一或多種第V族材料原子所形成之單原子層或由一或多種第III族材料原子所形成之單原子層所構成的單層，每個單原子層彼此磊晶對齊且磊晶對齊該半導體晶格；以及本發明實施例提供形成此種電接觸的方法。Embodiments of the present invention provide electrical contacts that provide one or more monolayers between a Group IV semiconductor and a metal, the semiconductor being characterized by its crystalline lattice structure and single atoms formed from one or more Group V material atoms layer or a monolayer consisting of monoatomic layers formed of one or more Group III material atoms, each monoatomic layer being epitaxially aligned with each other and in epitaxial alignment with the semiconductor lattice; and embodiments of the present invention provide for the formation of such method of electrical contact.
本發明之進一步實施例提供一種包含金屬和第IV族半導體的電接觸，並且在該金屬與該半導體之間的界面處藉由第V族原子單層及選用性的第III族原子單層隔開該金屬與該半導體。該金屬可用與該第III族金屬原子單層相同的金屬元素原子所製成，或是該金屬可用與該第III族金屬原子單層不同的金屬元素原子所製成。在某些實例中，該第III族原子可為下述任意一者或多者：鋁、鎵、銦或硼，或鋁、鎵、硼及/或銦的混合物。該第IV族半導體可為：鍺、矽、鍺與矽之合金、鍺與錫之合金、含碳之矽及/或鍺的合金或化合物。該第V族原子包括下述任意一者或多者：氮、磷、砷及銻。在某些實例中，一第III族原子單層將緊鄰該第IV族半導體的表面。在其他實例中，第V族原子單層將緊鄰該第IV族半導體的表面。第IV族半導體的該表面可為{111}-晶向表面或{100}-晶向表面。A further embodiment of the present invention provides an electrical contact comprising a metal and a Group IV semiconductor and separated by a monolayer of Group V atoms and optionally a monolayer of Group III atoms at the interface between the metal and the semiconductor open the metal and the semiconductor. The metal may be made of the same metal element atoms as the monolayer of Group III metal atoms, or the metal may be made of a different metal element atom than the monolayer of Group III metal atoms. In certain examples, the Group III atom can be any one or more of the following: aluminum, gallium, indium, or boron, or a mixture of aluminum, gallium, boron, and/or indium. The Group IV semiconductor may be: germanium, silicon, alloys of germanium and silicon, alloys of germanium and tin, alloys or compounds of silicon and/or germanium containing carbon. The Group V atoms include any one or more of the following: nitrogen, phosphorus, arsenic, and antimony. In some instances, a monolayer of Group III atoms will be immediately adjacent to the surface of the Group IV semiconductor. In other examples, a monolayer of Group V atoms will be immediately adjacent to the surface of the Group IV semiconductor. The surface of the Group IV semiconductor may be a {111}-oriented surface or a {100}-oriented surface.
本發明亦包括形成電接觸(例如以上所述者)的方法。在某些實例中，此方法涉及利用結晶選擇性蝕刻法(crystallographically selective etch)蝕刻該第IV族半導體的{100}-晶向表面以揭露並暴露出一個或多個{111}-晶向的半導體晶面；在該{111}晶面上形成第V族原子單層；及隨後在該第V族原子單層上沉積第III族原子單層。可利用個別氣相沉積製程或個別化學反應的方式製造該第V族及/或第III族原子單層。例如，在超高真空(UHV)條件下進行的製程中，在沉積該第V族原子或第III族原子之前，視情況需要，可在原位清潔該半導體的{111}-晶向晶面，並將該半導體加熱到足夠高的溫度以獲得重組結構，以{111}矽表面為例可獲得7x7重組結構，或以{111}矽鍺表面為例可獲得5x5重組結構，或以{111}鍺表面為例可獲得2x8重組結構，在此之後，於沉積第V族原子及/或第III族原子的期間內，可將該半導體加熱至一升高溫度。在形成第一種第V族原子單層與第一種第III族金屬原子單層之後，可在該第一個雙層(兩個單層)上直接沉積金屬原子，或在沉積金屬原子以形成接觸之前，可添加額外的第V族原子單層及/或第III族原子單層以建立出由超過單一雙層以上的多個單層所形成的堆疊。The present invention also includes methods of forming electrical contacts such as those described above. In certain examples, the method involves etching the {100}-oriented surface of the Group IV semiconductor using a crystallographically selective etch to expose and expose one or more {111}-oriented semiconductor crystal planes; forming a monolayer of Group V atoms on the {111} planes; and subsequently depositing a monolayer of Group III atoms on the Group V atomic monolayer. The Group V and/or Group III atomic monolayers may be fabricated using individual vapor deposition processes or individual chemical reactions. For example, in a process performed under ultra-high vacuum (UHV) conditions, the {111}-oriented crystal plane of the semiconductor may be cleaned in situ, as appropriate, prior to depositing the Group V or Group III atoms , and heat the semiconductor to a high enough temperature to obtain a reconstituted structure, taking the {111} silicon surface as an example to obtain a 7x7 reconstituted structure, or taking the {111} silicon germanium surface as an example to obtain a 5x5 recombination structure, or using the {111 } A 2x8 reconstituted structure can be obtained on a germanium surface as an example, after which the semiconductor can be heated to an elevated temperature during the deposition of the group V and/or group III atoms. After the formation of the first monolayer of Group V atoms and the first monolayer of Group III metal atoms, metal atoms can be deposited directly on the first bilayer (two monolayers), or after the metal atoms are deposited to Additional monolayers of Group V atoms and/or monolayers of Group III atoms may be added to create a stack of more than a single bilayer of monolayers prior to contact formation.
以下進一步詳細描述本發明的上述及進一步實施例。The above and further embodiments of the present invention are described in further detail below.
鑒於上述挑戰，本案發明人意識到需要一種能夠降低金屬接觸對於摻雜S/D區之阻力的金屬接觸技術，或需要一種能盡可能消除金屬與半導體間之蕭特基能障的金屬-半導體技術。低電阻式金屬-半導體接觸技術將可用於任何需要低電阻的應用上，例如可用於太陽能電池應用中及用於金屬S/D場效電晶體(FET)中。本發明係關於藉由在金屬與半導體之間的界面處***第V族或第III族原子單層，或***由一第V族原子單層與一第III族原子單層所形成的雙層，或***多個此種雙層而降低金屬-(第IV族)半導體接面之比接觸電阻的技術。本發明包括藉由在金屬與半導體之間的界面處提供至少一個單一秩序排列原子層以形成此種具有極低能障高度(接近零)及極低比接觸電阻之金屬-半導體接觸的方法。所形成的低比電阻金屬-第IV族半導體接面可應用在半導體元件(包括電子元件，例如電晶體、二極體，等等)及光電元件(例如，雷射、太陽能電池、光偵測器)中以作為低電阻電極，及/或可應用在場效電晶體(FET)中以作為金屬源極及/或汲極區(或源極/汲極區的一部分)。與半導體表面相鄰的第V族或第III族原子單層主要是形成在第IV族半導體表面上並與該第IV族半導體表面原子化學鍵結的秩序排列原子層。In view of the above challenges, the inventors of the present application realized that there is a need for a metal contact technology that can reduce the resistance of the metal contact to the doped S/D region, or a metal-semiconductor that can eliminate the Schottky energy barrier between the metal and the semiconductor as much as possible. Technology. Low resistance metal-semiconductor contact technology will be useful in any application requiring low resistance, such as in solar cell applications and in metal S/D field effect transistors (FETs). The present invention relates to a bilayer formed by intercalating a monolayer of Group V or Group III atoms, or a monolayer of Group V atoms and a monolayer of Group III atoms, at the interface between metal and semiconductor , or a technique to reduce the ratio contact resistance of the metal-(group IV) semiconductor junction by inserting multiple such bilayers. The present invention includes methods for forming such metal-semiconductor contacts with extremely low energy barrier heights (near zero) and extremely low specific contact resistances by providing at least one single ordered atomic layer at the interface between the metal and the semiconductor. The formed low resistivity metal-group IV semiconductor junction can be used in semiconductor devices (including electronic devices such as transistors, diodes, etc.) and optoelectronic devices (eg, lasers, solar cells, photodetectors, etc.) devices) as low resistance electrodes, and/or may be applied in field effect transistors (FETs) as metal source and/or drain regions (or part of source/drain regions). A monolayer of Group V or Group III atoms adjacent to a semiconductor surface is primarily an ordered layer of atoms formed on and chemically bonded to the Group IV semiconductor surface atoms.
本發明與Grupp和Connelly兩人早期研究工作(上述引用文獻)的區別在於，本發明的重點在秩序排列的單層，以及含有第V族元素(例如，磷或銻)和第III族元素(例如，鋁、硼、鎵或銦)。此外，在以上所引用之Marsi等人和McKinley等人的研究工作中說明意欲在半導體的兩個區域之間建立出能帶偏移，並未提及修改金屬與半導體之間的蕭特基能障或甚至未提到這麼做的可能性。The present invention differs from the earlier work of Grupp and Connelly (cited above) in that the present invention focuses on ordered monolayers, and the presence of group V elements (eg, phosphorus or antimony) and group III elements ( For example, aluminum, boron, gallium or indium). Furthermore, in the research work of Marsi et al. and McKinley et al. cited above, it is stated that an energy band offset is intended to be established between two regions of the semiconductor, and there is no mention of modifying the Schottky energy between the metal and the semiconductor. obstacles or even the possibility of doing so is not mentioned.
如下述，若第III族原子與第V族原子兩者皆存在時，所形成的雙層在半導體與主體金屬之間提供電偶極。當僅有單一個第V族原子層時，由於在該主體金屬內形成鏡像電荷(image charge)，因此也會出現類似的偶極。此外，在某些實例中，在半導體與主體金屬之間可使用多個雙層(例如，兩個或三個此種雙層)。的確，可增加偶極層，直到隨著場(field)增加所產生的過多能量造成原子本身重新排列。As described below, if both Group III and Group V atoms are present, the bilayer formed provides an electric dipole between the semiconductor and the host metal. A similar dipole also occurs when there is only a single group V atomic layer due to the formation of image charges within the host metal. Furthermore, in some examples, multiple bilayers (eg, two or three such bilayers) may be used between the semiconductor and the host metal. Indeed, the dipole layer can be added until the excess energy generated as the field increases causes the atoms to rearrange themselves.
再者，儘管本文中描述由第V族或第III族純物質形成的單層，本發明的某些實施例可能使用含有一種以上之第V族原子(例如，在一單層內含有砷和磷原子的混合物)或一種以上之第III族原子的單層(monolayer)。因此，在以下內容及請求項中提到單層(不論是否是一雙層的一部分或其他情況)時，該用語應視為涵蓋由單一種第V族或第III族原子所形成的單層以及由一種以上之第V族或第III族元素原子所形成的單層。Furthermore, although monolayers formed from pure Group V or Group III species are described herein, certain embodiments of the present invention may use materials containing more than one Group V atom (eg, arsenic and arsenic in a monolayer). A mixture of phosphorus atoms) or a monolayer of one or more Group III atoms. Accordingly, where reference is made to a monolayer (whether part of a bilayer or otherwise) in the following and in the claims, the term shall be deemed to encompass monolayers formed from a single type of Group V or Group III atom and monolayers formed by more than one group V or group III element atoms.
在本文所述的實例中，該半導體為第IV族半導體，例如，鍺、矽、矽與鍺之合金，或含有矽、鍺、碳及錫其中之兩種或多種元素的合金。由化合物半導體所製成的場效電晶體(FET)或其他電子元件亦可藉由使用根據本發明所提供的低電阻接面而受益。又於下述實例中，描述與半導體(及由秩序排列之第V族原子所形成的界面層)形成接面的金屬是第III族金屬。然而，此點並非必然的情況。該金屬不一定必為第III族金屬。亦可使用其他金屬，例如低功函數金屬，例如鎂、鑭、鐿(ytterbium)或釓(gadolinium)，藉以在金屬與半導體之間獲得低電位(低電能)能障或高電洞位能能障。或可選用高功函數金屬，例如鎳、鉑、銥(iridium)或釕，藉以在金屬與半導體之間獲得低電洞能障或高電子能障。然而，這並不排除使用更高功函數金屬(例如，鉑或釕)來製造具有低電子能障的接觸。儘管該金屬具有高功函數，借助於使半導體界面處出現秩序排列的第V元素單層而建立出大的偶極，而使得該金屬費米能階(Fermi level)與半導體傳導帶(conduction band)之間的能障可能很低。In the examples described herein, the semiconductor is a Group IV semiconductor, eg, germanium, silicon, an alloy of silicon and germanium, or an alloy containing two or more of the elements silicon, germanium, carbon, and tin. Field effect transistors (FETs) or other electronic components fabricated from compound semiconductors may also benefit from the use of low resistance junctions provided in accordance with the present invention. Also in the following examples, the metals described to form junctions with semiconductors (and interfacial layers formed from ordered group V atoms) are Group III metals. However, this is not necessarily the case. The metal does not necessarily have to be a Group III metal. Other metals, such as low work function metals such as magnesium, lanthanum, ytterbium or gadolinium, can also be used to obtain a low potential (low electrical energy) barrier or high hole energy between the metal and the semiconductor barrier. Alternatively, a high work function metal such as nickel, platinum, iridium or ruthenium can be selected to obtain a low hole energy barrier or a high electron energy barrier between the metal and the semiconductor. However, this does not preclude the use of higher work function metals (eg, platinum or ruthenium) to fabricate contacts with low electronic energy barriers. Although the metal has a high work function, a large dipole is established by causing an ordered V-th element monolayer at the semiconductor interface, so that the Fermi level of the metal is related to the conduction band of the semiconductor. ) may be low.
在許多應用中，使用相同的金屬製造與p-型及n-型摻雜半導體區域兩者的接觸，例如形成p-通道場效電晶體及n-通道場效電晶體中的源極接觸和汲極接觸，可能是有利的。此外，上述作法對於將作為阻障金屬(例如，氮化鉭(TaN)或氮化鈦(TiN)或釕(Ru))以及將用來製造與p-型及n-型摻雜半導體區域兩者之接觸的金屬而言亦可能極為有利。在使用相同金屬形成p-型及n-型摻雜半導體區域兩者之低能障接觸的例子中，與半導體表面化學鍵結的界面單層將會是位在n-型接觸處之秩序排列的第V族原子界面層，以及將會是位在p-型接觸處之秩序排列的第III族原子界面層。同樣地，當使用相同金屬形成n-通道及p-通道金屬源/汲極MOSFET兩者的金屬源極及/或汲極時，與該半導體表面化學鍵結的該界面單層將會是位在n-通道MOSFET之源/汲極接面處之秩序排列的第V族原子界面層，以及將會是位在p-通道MOSFET之源/汲極接面處之秩序排列的第III族原子界面層。In many applications, the same metal is used to make contacts to both p-type and n-type doped semiconductor regions, such as forming source contacts in p-channel field effect transistors and n-channel field effect transistors and Drain contacts may be advantageous. In addition, the above approach is useful for applications that will act as barrier metals (eg, tantalum nitride (TaN) or titanium nitride (TiN) or ruthenium (Ru)) and will be used to fabricate both p-type and n-type doped semiconductor regions. It can also be extremely beneficial for the metals that they come into contact with. In the case of using the same metal to form low energy barrier contacts for both p-type and n-type doped semiconductor regions, the interfacial monolayer chemically bonded to the semiconductor surface will be the first in order at the n-type contact. The interfacial layer of group V atoms, and the interfacial layer of group III atoms that will be ordered at p-type contacts. Likewise, when the same metal is used to form the metal source and/or drain of both n-channel and p-channel metal source/drain MOSFETs, the interfacial monolayer chemically bonded to the semiconductor surface will be located at An ordered group V atomic interface layer at the source/drain junction of an n-channel MOSFET, and would be an ordered group III atomic interface at the source/drain junction of a p-channel MOSFET Floor.
可使用鐵磁金屬(例如釓、鐵、鎳或鈷或這些元素的合金)或錳的鐵磁合金來獲得具有高自旋注入效率的金屬-半導體接觸。在期望具有高電子自旋注入效率的特殊應用中，與半導體表面化學鍵結的界面層較佳是秩序排列的第V族原子界面層。鐵磁金屬可直接沉積在該第V族單層上，或可使第III族金屬單原子層與該第V族原子化學鍵結，並在該第III族單層上沉積鐵磁金屬。Metal-semiconductor contacts with high spin injection efficiency can be obtained using ferromagnetic metals such as gadolinium, iron, nickel or cobalt or alloys of these elements, or ferromagnetic alloys of manganese. In special applications where high electron spin injection efficiency is desired, the interface layer chemically bonded to the semiconductor surface is preferably an ordered group V atomic interface layer. The ferromagnetic metal can be deposited directly on the Group V monolayer, or a Group III metal monolayer can be chemically bonded to the Group V atom and the ferromagnetic metal deposited on the Group III monolayer.
亦可使用其他金屬材料，包括純金屬的合金、金屬矽化物(例如，成份為Ni2 Si、NiSi或NiSi2 的矽化鎳或矽化鉑或矽化鈷)或甚至是半金屬，其中該金屬材料直接鄰接該第V族或第III族單層。在製造上，n-型及p-型半導體接觸兩者皆採用相同金屬材料，或使用相同金屬材料作為n-通道型及p-通道型兩種MOSFET的的金屬源極及/或汲極是可行且可能是最為方便的。Other metal materials can also be used, including alloys of pure metals, metal silicides ( eg, nickel silicide or platinum silicide or cobalt Adjacent to the Group V or Group III monolayer. In manufacturing, the same metal material is used for both the n-type and p-type semiconductor contacts, or the same metal material is used as the metal source and/or drain for both n-channel and p-channel MOSFETs. feasible and probably the most convenient.
為了獲得期望中在整個接觸內對於電子具有極低能障高度且對於電子導電作用具有極低電阻的金屬-半導體接觸，該秩序排列的原子單層可為秩序排列的第V族原子單層。該第V族原子可為氮原子、磷原子、砷原子或銻原子或這些第V族原子的混合物。在本發明的一實施例中，該第V族原子單層是砷原子層，且該砷原子層磊晶(或實質磊晶)排列並與該鍺或矽或第IV半導體合金結晶晶格對齊。此種對電子傳導具有極低電阻的接觸可用來與n-型摻雜半導體(例如，n-通道FET的n-型摻雜源極區和汲極區)進行電接觸，或用於製成金屬源/汲極區(該等金屬源/汲極區與n-通道FET中的電子通道直接接觸)。To obtain the desired metal-semiconductor contact with very low energy barrier height for electrons and very low resistance to electron conduction throughout the contact, the ordered monolayer of atoms may be an ordered monolayer of Group V atoms. The group V atom may be a nitrogen atom, a phosphorus atom, an arsenic atom or an antimony atom or a mixture of these group V atoms. In one embodiment of the invention, the group V atomic monolayer is an arsenic atomic layer, and the arsenic atomic layer is epitaxially (or substantially epitaxially) aligned and aligned with the germanium or silicon or IV semiconductor alloy crystal lattice . Such contacts with very low resistance to electron conduction can be used to make electrical contacts to n-type doped semiconductors (eg, n-type doped source and drain regions of n-channel FETs), or to make Metal source/drain regions (these metal source/drain regions are in direct contact with the electron channels in the n-channel FET).
在許多實例中，在第IV族半導體的表面上形成該金屬接觸且該第IV族半導體的表面將是{111}-晶向表面，以及在最大的可能範圍內，在該單一個秩序排列之原子層中的每一個第V族原子以三價配位(three-way coordination)的方式與該半導體之{111}晶向表面中的原子形成化學鍵結。然而，在其他實例中，該第IV族半導體的接觸表面將為{100}或{110}表面。在某些實例中可能以{100}表面為佳。In many instances, the metal contact is formed on the surface of the Group IV semiconductor and the surface of the Group IV semiconductor will be a {111}-oriented surface, and to the greatest extent possible, within the single ordering Each group V atom in the atomic layer forms a chemical bond with an atom in the {111} oriented surface of the semiconductor in a three-way coordination manner. However, in other examples, the contact surface of the Group IV semiconductor will be a {100} or {110} surface. A {100} surface may be preferred in some instances.
在詳細討論本發明實施例之前，回顧一下某些基礎理論將有所幫助。在金屬與半導體之間的接觸界面處，可觀察到金屬中的費米能量將「釘扎(pinned)」在半導體能隙中的一特定能量處而使每種半導體造成在金屬費米能階與該半導體中的傳導能帶或價電能帶之間造成一個能障。儘管半導體能進行傳導(例如，含有摻雜劑時)，如第(1a)圖所示，該費米能量EF 固定在接近體結晶中的半導體能帶邊緣EC (當未施加電壓時，該系統各處中的EF 是均勻一致的)，EC 維持遠高於該界面處的EF 。因此，該半導體靠近界面處的區域不能成為良好導體。該金屬與半導體的強導電區之間僅能傳輸微弱電流。藉由熱離子發射作用(藉由激發而跨越該能障)或藉由隧穿該能障而可傳導電子流進入該傳導帶中，且當該能障的寬度可能僅為數十埃(Angstrom)時，隧穿機率往往更小。更廣範而言，可藉由所謂的「熱離子場發射作用」，也就是熱離子發射作用結合電子穿過該能障的隧穿作用，而使該金屬與半導體之間可傳導電流。Before discussing embodiments of the invention in detail, it will be helpful to review some of the underlying theory. At the contact interface between the metal and the semiconductor, it is observed that the Fermi energy in the metal will be "pinned" at a specific energy in the semiconductor energy gap such that each semiconductor causes the Fermi energy in the metal to be at the Fermi level. An energy barrier is created between the conduction band or the valence band in the semiconductor. Although the semiconductor is capable of conducting (for example, with dopants), as shown in (1a), the Fermi energy EF is fixed close to the semiconductor band edge EC in the bulk crystal (when no voltage is applied, The EF is uniform throughout the system), the EC remains much higher than the EF at the interface. Therefore, the region of the semiconductor near the interface cannot be a good conductor. Only weak currents can be transferred between the metal and the strongly conductive regions of the semiconductor. Electron flow can be conducted into the conduction band by thermionic emission (crossing the energy barrier by excitation) or by tunneling through the energy barrier, and when the energy barrier may be only a few tens of angstroms wide (Angstrom et al. ), the tunneling probability tends to be smaller. More broadly, electrical current can be conducted between the metal and the semiconductor by so-called "thermionic field emission," ie, thermionic emission combined with the tunneling of electrons through the energy barrier.
本發明旨在藉由在金屬與半導體之間***電偶極層，使該界面處之能帶邊緣和費米能量的相對位置偏移，而消除或至少大幅降低此能障。第1(b)圖中圖示最終能量。該淨結果是去除了幾乎所有的能障區域，僅留下該偶極層之間的能障區。The present invention aims to eliminate or at least greatly reduce this energy barrier by interposing an electric dipole layer between the metal and the semiconductor to shift the relative positions of the band edge and the Fermi energy at the interface. The final energy is shown in Figure 1(b). The net result is that almost all of the energy barrier region is removed, leaving only the energy barrier region between the dipole layers.
用世界科學出版社(新加坡，1999年)之W. A. Harrison所著《基本電子結構(Elementary Electronic Structure)》修訂版(2004)以及W. A. Harrison等人在1978年《物理評論》期刊(Phys. Rev. B 18, 4402)標題為「極性異質接合界面(Polar Heterojunction Interfaces)」之文章中所描述的「理論鍊金術」可以最能簡單理解如何完成矽-金屬界面。想像將位在最靠近金屬之平面中的每個矽原子核中移除一個質子，可將矽核轉換成鋁核(元素週期表中左側的其中一個元素)，並將該質子***該矽晶格的倒數第二個平面中的矽核中，而使該矽核變成磷核。此方法能有效地在最靠近金屬的原子平面中製造出一片的負電荷及在倒數第二個平面中製造出一片正電荷，並且在該兩個原子平面之間形成偶極而具有一個大電場。實際上此電場會使此層中的鍵極化，而使此層中的鍵縮小為介電常數的倒數倍(對於矽而言是1/12 = 0.083)，但結果如第5(a)圖所示仍具有大的電場和大的電位偏移。實際上，不僅只該偶極層中的鍵被極化，相鄰層中的鍵也會被極化，而改變該區域中所有原子的有效電荷，並使該電場變成如第5(b)圖中所示般。然而造成極類似的電位淨偏移(以矽中的(100)平面為例，該電位淨偏移估計約1.39eV，且鍵長d = 2.35 Å)，足以去除主要的能障。Using the revised edition of "Elementary Electronic Structure" (2004) by WA Harrison, World Science Press (Singapore, 1999) and the 1978 "Phys. Rev. B" by WA Harrison et al. 18, 4402) titled "Polar Heterojunction Interfaces" The "theoretical alchemy" described in the article titled "Polar Heterojunction Interfaces" provides the easiest understanding of how to accomplish the silicon-metal interface. Imagine removing a proton from each silicon nucleus in the plane closest to the metal, converting the silicon nucleus into an aluminum nucleus (one of the elements on the left side of the periodic table), and inserting that proton into the silicon lattice in the silicon nucleus in the penultimate plane, and the silicon nucleus becomes a phosphorus nucleus. This method effectively creates a sheet of negative charge in the atomic plane closest to the metal and a sheet of positive charge in the penultimate plane, and forms a dipole with a large electric field between the two atomic planes . In fact this electric field polarizes the bonds in this layer and shrinks the bonds in this layer to the inverse of the dielectric constant (1/12 = 0.083 for silicon), but the result is as in 5(a) The figure still shows a large electric field and a large potential shift. In fact, not only bonds in this dipole layer are polarized, but bonds in adjacent layers are also polarized, changing the effective charge of all atoms in the region and causing the electric field to become as in 5(b) As shown in the picture. However, resulting in a very similar net potential shift (in the case of the (100) plane in silicon, estimated to be about 1.39 eV with bond length d = 2.35 Å), it is sufficient to remove the main energy barrier.
吾等可重複該理論鍊金術的製程，從鋁核中移除另一個質子，而使該鋁核變成鎂核，並將該質子***該磷核中而使該磷核成為硫核。套用同樣的概念，此種做法會使每個平面上的電荷加倍，並使偶極偏移加倍。此做法相當於***元素週期表第II欄中之原子的平面及***第VI欄中之原子的平面，而不是第III和第V欄。甚至該方法可套用第三次而***NaCl層，但在本發明中，多數情況下，此種沉積作用可能使矽結構無法維持繼續保持磊晶，而即有可能形成中性的NaCl岩鹽平面，而非偶極層。另一方面，某些貴金屬鹵化物的確會形成矽的四面體結構，並可預期這些貴金屬鹵化物可磊晶地成長，而相當於第VII欄元素的單層及第IB欄(貴金屬)元素的單層，且預估其偶極偏移將會是鋁-磷(Al-P)雙層之偶極偏移的三倍。因此，本發明還包括由第VI、VII、II和IB欄以及第V和III欄之磊晶層所造成的偶極偏移。We can repeat the process of the theoretical alchemy, removing another proton from the aluminum nucleus, making the aluminum nucleus become a magnesium nucleus, and inserting the proton into the phosphorus nucleus, making the phosphorus nucleus become a sulfur nucleus. Applying the same concept, this approach doubles the charge on each plane and doubles the dipole shift. This is equivalent to inserting the plane of the atom in column II of the periodic table and inserting the plane of the atom in column VI, not columns III and V. Even this method can be applied for the third time to insert the NaCl layer, but in the present invention, in most cases, this deposition may make the silicon structure unable to maintain and continue to maintain epitaxial, that is, it is possible to form a neutral NaCl rock salt plane, rather than a dipole layer. On the other hand, some noble metal halides do form the tetrahedral structure of silicon, and these noble metal halides can be expected to grow epitaxially, with monolayers equivalent to Column VII elements and Column IB (noble metal) elements monolayer, and its dipole shift is predicted to be three times that of an aluminum-phosphorus (Al-P) bilayer. Therefore, the present invention also includes the dipole shifts caused by the epitaxial layers of columns VI, VII, II and IB and columns V and III.
若取代理論性地將最後兩個平面的矽原子轉換成磷和鋁的方式，而改在矽和金屬之間***實際的磷或任何其他第V欄元素的單一個原子層以及插鋁或其他第III欄元素的單一原子層，結果不會改變。任何可適當對應的第V族-第III族材料雙層皆可用於達到消除(或至少大幅降低)蕭特基能障的目的，並可根據便利性或其他考量來選擇該等材料雙層，且同樣地，第IB、II、VI及VII欄中的任何元素可如上述段落中所提到的元素般達到同樣效果。更明確言之，可沉積第VI族元素～硫及/或硒及/或碲的秩序排列單層並聯合第II族元素～鋅及/或鎘的秩序排列單層而形成秩序排列的第II-VI族雙層。If instead of theoretically converting the last two planes of silicon atoms into phosphorus and aluminum, intercalating between the silicon and the metal is an actual single atomic layer of phosphorus or any other column V element and intercalating aluminum or other A single atomic layer of the elements in column III, the results do not change. Any suitable bilayers of Group V-Group III materials can be used for the purpose of eliminating (or at least substantially reducing) the Schottky energy barrier, and such bilayers may be selected for convenience or other considerations, And likewise, any of the elements in columns IB, II, VI and VII can achieve the same effect as the elements mentioned in the preceding paragraphs. More specifically, ordered monolayers of group VI elements—sulfur and/or selenium and/or tellurium can be deposited and combined with ordered monolayers of group II elements—zinc and/or cadmium to form ordered II - Group VI bilayer.
現回到第2圖，第2圖圖示用於形成對半導體表面具有極低電阻之金屬接觸的製程實例10。在此製程中，使用第IV族半導體(或第IV族半導體及/或碳之化合物或合金)的{100}-晶向表面(步驟12)，且利用結晶選擇性蝕刻法蝕刻該{100}-晶向表面以揭露和暴露出一或多個{111}-半導體晶面(步驟14)。隨後，在該{111}-晶面上形成第V族原子單層(步驟16)，接著沉積適當的第III族金屬(步驟18)以形成該接觸。需注意，第V族原子單層並不一定是完美的秩序排列單層。也就是說，該第V族原子單層在覆蓋方面可能具有某些間隙或些許過量的原子。換言之，在沉積該秩序排列的單層之後，可能留下一些未填滿(unsatisfied)的第IV族半導體的懸鍵，或第V族原子的數目超過早先該第IV族半導體的懸鍵數目，或在表面上有一部分的半導體或第V族原子變得紊亂且無法對齊該半導體晶格。然而，任一種上述情況仍然視為是可用於本發明目的第V族原子單層。Returning now to Figure 2, Figure 2 illustrates an example 10 of a process for forming metal contacts with very low resistance to semiconductor surfaces. In this process, the {100}-oriented surface of a Group IV semiconductor (or a compound or alloy of a Group IV semiconductor and/or carbon) is used (step 12), and the {100} is etched using a crystal selective etching method - Orienting the surface to expose and expose one or more {111}-semiconductor crystal planes (step 14). Subsequently, a monolayer of Group V atoms is formed on the {111}-plane (step 16), followed by deposition of an appropriate Group III metal (step 18) to form the contact. Note that the group V atomic monolayer is not necessarily a perfectly ordered monolayer. That is, the monolayer of Group V atoms may have some gaps or a slight excess of atoms in coverage. In other words, after deposition of the ordered monolayer, some unsatisfied Group IV semiconductor dangling bonds may be left, or the number of Group V atoms exceeds the number of dangling bonds of the Group IV semiconductor earlier, Or a portion of the semiconductor or group V atoms on the surface becomes disordered and fails to align the semiconductor lattice. However, any of the above is still considered to be a Group V atomic monolayer useful for the purposes of the present invention.
在第2圖所述之製程的另一替代製程中，步驟18中的金屬原子可為第III族金屬原子以外的金屬原子。例如，該金屬可為純金屬的合金、金屬矽化物或金屬化合物。In another alternative to the process described in Figure 2, the metal atoms in
可利用氣相沉積製程或化學反應的方式製造第V族原子單層。在氣相沉積製程的例子中，此製程包括在升高的溫度下使該半導體暴露於該第V族原子蒸汽流或該第V族元素的分子流。可利用熱使該第V族元素來源蒸發而產生該第V族原子/分子氣流。在本發明一實施例中，該氣流是成份為As4 的砷分子流，且可如實施分子束磊晶法所知的方式般，在努特生坩堝(Knudsen cell，k-cell)中利用熱使元素砷源蒸發而生成該As4 分子流。The group V atomic monolayer can be fabricated using a vapor deposition process or chemical reaction. In the example of a vapor deposition process, the process includes exposing the semiconductor to the vapor stream of the Group V atom or the molecular stream of the Group V element at an elevated temperature. The Group V atomic/molecular gas stream may be generated by thermally evaporating the Group V element source. In one embodiment of the present invention, the gas stream is a molecular stream of arsenic with a composition of As 4 , and can be utilized in a Knudsen cell (k-cell) in a manner known from the implementation of molecular beam epitaxy Heat vaporizes the source of elemental arsenic to generate this As 4 molecular stream.
可用於沉積第V族及/或第III族單層的各種製造手段包括分子束磊晶法(MBE)、氣態源分子束磊晶法(GSMBE)、有機金屬分子束磊晶法(MOMBE)、有機金屬化學氣相沉積法(MOCVD)、有機金屬氣相磊晶法(MOVPE)、原子層沉積法(ALD)、原子層磊晶法(ALE)及化學氣相沉積法(CVD)，包括電晶增強化學氣相沉積法(PECVD)或光子或雷射-誘發式化學氣相沉積法(photon or laser-induced CVD)。Various fabrication means that can be used to deposit Group V and/or Group III monolayers include molecular beam epitaxy (MBE), gaseous source molecular beam epitaxy (GSMBE), metal-organic molecular beam epitaxy (MOMBE), Metal-organic chemical vapor deposition (MOCVD), metal-organic vapor phase epitaxy (MOVPE), atomic layer deposition (ALD), atomic layer epitaxy (ALE), and chemical vapor deposition (CVD), including electro- Crystal-enhanced chemical vapor deposition (PECVD) or photon or laser-induced chemical vapor deposition (photon or laser-induced CVD).
可依據本發明實施例而使用的其他氣相沉積製程涉及使該第V族元素的氣相化合物(例如，第V族元素的氫化物)解離而在該半導體表面上沉積該第V族元素原子。合適的第V族氫化物氣體包括用於沉積氨原子的氨(NH3 )、用於沉積磷的磷化氫(PH3 )、用於沉積砷的砷化氫(AsH3 )及用於沉積銻原子層的銻化氫(SbH3 )。或者，所欲的第V族元素之氣相化合物可為有機金屬化合物，此種化合物的實例為用於沉積砷單層的烷基胂(alkyl arsine)，例如叔丁基胂(tertiary butyl arsine)，或用於沉積銻單層的烷基銻化氫，例如三乙基銻(triethylstibine)。Other vapor deposition processes that may be used in accordance with embodiments of the present invention involve dissociating a vapor phase compound of the Group V element (eg, a hydride of a Group V element) to deposit the Group V element atoms on the semiconductor surface . Suitable Group V hydride gases include ammonia ( NH3 ) for depositing ammonia atoms, phosphine (PH3 ) for depositing phosphorus, arsine (AsH3 ) for depositing arsenic, and Antimony atomic layer of antimony hydrogen (SbH 3 ). Alternatively, the desired gas phase compound of the Group V element may be an organometallic compound, examples of such compounds are alkyl arsines such as tertiary butyl arsine for depositing arsenic monolayers , or alkyl antimonides such as triethylstibine for depositing antimony monolayers.
在超高真空(UHV)條件下進行的製程中，使矽暴露於該第V族原子或化合物的蒸汽流之前，可在原位清潔該具有{111}-晶向晶面的矽，並將該矽加熱到足夠高的溫度以獲得 {111}矽表面的7x7重組結構。第3(a)圖(透視圖)、第3(b)圖(原始單位晶胞的平面圖)及第3(c)圖(原始單位晶胞的側視圖)提供此種7x7表面20的視圖。原子22代表下方(1x1)主體矽材料中的原子。原子24代表所謂的休憩原子(rest atom，位在附著原子(adatom)下方的一層原子)。原子26代表二聚體(dimer，成對的表面矽原子)。原子28代表附著原子(置於該結晶表面上的矽原子)。元件符號30則表示該結構中的角落孔洞。In a process performed under ultra-high vacuum (UHV) conditions, the silicon with {111}-oriented planes can be cleaned in situ before exposing the silicon to the vapor stream of the group V atom or compound, and the The silicon is heated to a high enough temperature to obtain a 7x7 reconstituted structure on the {111} silicon surface. Figures 3(a) (perspective view), Figure 3(b) (plan view of the original unit cell) and Figure 3(c) (side view of the original unit cell) provide views of such a
之後，使該矽暴露於該第V族原子蒸汽或該第V族化合物分子蒸汽的期間內，該矽保持在介於約20℃至750℃(包括兩端值)範圍間的一溫度。該矽表面可暴露在第V族原子或化合物分子蒸汽流下持續一秒或數秒或甚至持續數分鐘。使該矽保持在適當溫度下，形成秩序排列的第V族原子單層，並在形成之後，該單層可制止沉積額外的第V族原子或沉積其他原子(例如氫或氧或碳原子)。或可在使該半導體暴露於第V族原子蒸汽或第V族分子化合物蒸汽的期間內改變該半導體溫度，使該半導體溫度從介於600℃至800℃範圍內的高溫開始下降至介於500℃至20℃範圍內的較低溫度。Thereafter, the silicon is maintained at a temperature in the range of about 20°C to 750°C (both inclusive) during the exposure of the silicon to the Group V atomic vapor or the Group V compound molecular vapor. The silicon surface may be exposed to a stream of Group V atom or compound molecular vapor for a second or a few seconds or even for a few minutes. Keeping the silicon at a suitable temperature forms an ordered monolayer of group V atoms, and after formation, the monolayer prevents the deposition of additional group V atoms or the deposition of other atoms (such as hydrogen or oxygen or carbon atoms) . Alternatively, the temperature of the semiconductor may be varied during exposure of the semiconductor to the vapor of a group V atom or a vapor of a molecular compound of the group V, such that the temperature of the semiconductor decreases from a high temperature in the range of 600°C to 800°C to between 500°C and 500°C. Lower temperatures in the range of °C to 20 °C.
如第4圖所示，第V族原子32(例如，As、Sb或P)直接與露出的矽表面原子34鍵結以形成完全配位的晶格終端，並且在最大可能程度上不具有懸鍵，第4圖為所產生之結構的側視圖。每個第V族原子之5個價電子的其中三個價電子與第IV族半導體表面處的矽原子形成鍵結，且剩下的兩個價電子則如圖中所示般形成「孤電子對(lone-pair)」軌域。As shown in Figure 4, group V atoms 32 (eg, As, Sb, or P) bond directly to exposed
可在除了{111}晶向以外的矽表面上，例如在{100}晶向的矽表面上應用類似製程以獲得第V族原子單層。亦可在除了矽以外的第IV族半導體表面上，例如在包括鍺、矽鍺、矽碳、鍺錫或矽鍺碳的半導體上應用類似製程以獲得第V族原子單層。此外，也可在第IV族半導體表面上應用類似製程以獲得第VI族原子單層。A similar process can be applied on silicon surfaces other than {111} oriented, eg, {100} oriented silicon surfaces, to obtain a monolayer of group V atoms. Similar processes can also be applied on surfaces of Group IV semiconductors other than silicon, for example, on semiconductors including germanium, silicon germanium, silicon carbon, germanium tin or silicon germanium carbon to obtain a monolayer of Group V atoms. In addition, similar processes can also be applied on the surface of Group IV semiconductors to obtain a monolayer of Group VI atoms.
可在超高真空(UHV)腔室中、在真空腔室中或在減壓腔室中使已加熱的半導體表面暴露於第V族原子流或化合物分子流下。若進行該製程的腔室並非UHV腔室，在該暴露過程中可能存在背景氣體或載氣。在一實施例中，以主要由氫氣(H2 )或氮氣(N2 )所組成的氣體混合物以稀釋的形成來輸送砷化氫(AsH3 )。在半導體製造過程中，一般將砷化氫稀釋到數個百分比或甚至低達100ppm的濃度，或將砷化氫在超純的氫氣或氮氣中稀釋至數個百分比或甚至低達100ppm的濃度濃度。不論是純的砷化氫或在氫氣或氮氣中含有1%或數個百分比之砷化氫的稀釋混合物，砷化氫會在已加熱的半導體表面處解離而釋出自由的砷原子，自由的砷原子與露出的矽表面直接鍵結以形成完全配位的晶格終端且不含或僅有極少的懸鍵。The heated semiconductor surface may be exposed to a stream of Group V atoms or compound molecules in an ultra-high vacuum (UHV) chamber, in a vacuum chamber, or in a reduced pressure chamber. If the chamber in which the process is performed is not a UHV chamber, a background or carrier gas may be present during the exposure. In one embodiment, arsine (AsH 3 ) is delivered in a diluted form with a gas mixture consisting primarily of hydrogen (H 2 ) or nitrogen (N 2 ). In semiconductor manufacturing processes, arsine is typically diluted to concentrations of several percent or even as low as 100 ppm, or in ultrapure hydrogen or nitrogen to concentrations of several percent or even as low as 100 ppm . Whether pure arsine or a diluted mixture containing 1% or several percent arsine in hydrogen or nitrogen, arsine dissociates at the heated semiconductor surface to liberate free arsenic atoms, free arsenic. Arsenic atoms bond directly to the exposed silicon surface to form fully coordinated lattice terminations with no or very few dangling bonds.
以氫化物前驅物氣體(AsH4 )在矽上沉積砷原子單層的較佳製程始於在氫氣氛圍中將該矽表面加熱至一溫度，該溫度足以減少任何表面氧化物，隨後將該矽表面加熱至介於650℃至750℃(最佳介於675℃至725℃)範圍間的溫度且同時將該表面暴露於AsH4 蒸汽下持續一段介於10秒至30分鐘之間(最佳介於20秒至2分鐘之間)的時間。可在CVD系統或ALD系統中進行此製程，並形成秩序排列(ordered)的砷原子單層。在此形成步驟之後，該單層制止(resist)沉積額外的第V族原子或沉積其他原子(例如氫或氧或碳原子)。或可在使該半導體暴露於AsH4 蒸汽的期間內改變該半導體溫度，使該半導體溫度從介於650℃至750℃範圍內的高溫開始下降至介於500℃至20℃範圍內的較低溫度。A preferred process for depositing a monolayer of arsenic atoms on silicon with a hydride precursor gas (AsH 4 ) begins with heating the silicon surface to a temperature sufficient to reduce any surface oxides in a hydrogen atmosphere, followed by the silicon The surface is heated to a temperature ranging from 650°C to 750°C (optimally 675°C to 725°C) while exposing the surface to AsH4 vapor for a period between 10 seconds and 30 minutes (optimally 675°C to 725°C). between 20 seconds and 2 minutes). This process can be performed in a CVD system or an ALD system and forms an ordered monolayer of arsenic atoms. After this formation step, the monolayer resists the deposition of additional Group V atoms or the deposition of other atoms such as hydrogen or oxygen or carbon atoms. Alternatively, the semiconductor temperature can be varied during exposure of the semiconductor to AsH4 vapor, starting from a high temperature in the range of 650°C to 750°C to a lower temperature in the range of 500°C to 20°C temperature.
如上述，並不嚴格要求該第V族原子形成完美的單層。可在此第V族單層上沉積金屬，或沉積更多的矽且隨後沉積金屬。因此，在界面層處(如上述者)可能存在著電荷單層，或者 若在第V族單層之後並在該金屬之前分別沉積一個、兩個或三個矽原子層，則在從該半導體-金屬界面起算的第二、第三或第四個平面處可能存在著電荷單層。在帶電的第V族原子(離子)單層與該金屬原子之間具有一或多個矽原子層且從而隔開該第V族原子(離子)單層與該金屬原子的優點是，可增加該等層之間所建立的電偶極大小，且從而對於該金屬-半導體接面處的電子而言可較大幅地降低蕭特基能障。另一方面，使用一或多個矽原子層隔開該帶電第V族原子(離子)單層與該金屬原子的缺點是該偶極區的空間範圍較大而不利於傳導電荷通過該能障。在第V族原子與金屬原子之間具有矽原子層所能思及的僅有優勢就是可用在對p-型半導體具有大的蕭特基能障的應用中。As above, it is not strictly required that the group V atoms form a perfect monolayer. Metal can be deposited on this Group V monolayer, or more silicon can be deposited and then metal deposited. Thus, there may be a charge monolayer at the interface layer (such as those described above), or if one, two or three atomic layers of silicon are deposited after the group V monolayer and before the metal, respectively, the - A charge monolayer may exist at the second, third or fourth plane from the metal interface. The advantage of having one or more layers of silicon atoms between a charged monolayer of group V atoms (ions) and the metal atoms, and thereby separating the monolayer of group V atoms (ions) from the metal atoms, is that increased The galvanic couple established between the layers is small and thus the Schottky barrier for electrons at the metal-semiconductor junction can be reduced considerably. On the other hand, the use of one or more layers of silicon atoms to separate the charged group V atomic (ion) monolayer from the metal atoms has the disadvantage that the spatial extent of the dipole region is too large to conduct charge across the energy barrier . The only conceivable advantage of having a layer of silicon atoms between the group V atoms and the metal atoms is in applications with a large Schottky barrier to p-type semiconductors.
於第5圖所示的實施例中，在{111}-晶向之第IV族半導體36的表面上形成配位的第V族原子單層38之後，沉積第III族原子單層40，隨後沉積該金屬接觸(主體金屬原子42)，而提供低能障且低電阻的金屬接觸。在本發明的此實施例中，該金屬原子單層40是第III族金屬原子層，其可包括鋁、鎵或銦或這些第III族金屬原子的混合物。在本發明的其他實施例中，可使用除了第III族金屬以外的其他金屬或金屬合金，或除了第III族金屬以外的其他金屬或金屬合金可與第III族金屬併用。此第III族金屬原子單層是選用性的，並且此第III族金屬原子單層不一定必需存在於根據本發明所形成的所有接面中，在該主體金屬中形成的鏡像電荷(image charge)將會是平衡負電荷(以下將做進一步說明)。In the embodiment shown in FIG. 5, after a coordinated group V
若存在有第III族金屬原子單層，該金屬原子單層中的金屬原子較佳與半導體表面中已存在的第V族原子單層形成配位，從而形成秩序排列的金屬原子層。然而，該第一層的金屬原子非藉由化學鍵結與下方第Ｖ族原子秩序排列層形成強配位鍵結的實施例也是可行的。接著，該製程繼續進行以沉積額外的金屬原子42，該額外的原子可與該第一層金屬原子為相同的金屬元素，或是與該第一層金屬原子為不同的金屬元素。第5圖圖示若原子40與原子42為相同元素時所獲得的結構。If there is a monolayer of Group III metal atoms, the metal atoms in the monolayer of metal atoms preferably form coordination with the existing monolayer of Group V atoms on the semiconductor surface, thereby forming an ordered layer of metal atoms. However, an embodiment in which the metal atoms of the first layer form strong coordination bonds with the underlying group V atomic arrangement layer without chemical bonding is also feasible. Then, the process continues to deposit
第5圖中示出在該半導體原子36與主體金屬42之間設置一個包含第V族原子單層38和第III族原子單層40的雙層。圖中的曲線圖(a)和(b)兩圖代表在跨越該接面的不同位置處的位能，曲線圖(a)顯示該理論鍊金術中未使鄰鍵極化的第一步驟，及曲線圖(b)則是考慮到鬆弛作用(relaxation)所繪製而成的曲線。曲線(b)有些許誇大以強調橫跨該接面的電位性質。Figure 5 shows a bilayer comprising a
可利用氣相沉積製程或利用化學反應製造該第III族金屬原子單層。例如，在氣相沉積製程的實例中，可藉著使半導體表面暴露於第III族金屬元素的原子蒸汽流或暴露於該金屬元素化合物的蒸汽流下而在該半導體表面上形成該金屬原子單層。該暴露步驟可持續進行少於一秒的時間或持續進行長達數秒或甚至數分鐘。The monolayer of Group III metal atoms can be fabricated using a vapor deposition process or using chemical reactions. For example, in the example of a vapor deposition process, the metal atomic monolayer may be formed on the semiconductor surface by exposing the semiconductor surface to a stream of atomic vapors of a Group III metal element or to a stream of vapors of a compound of the metal element. . This exposure step may be performed for a period of less than a second or for up to several seconds or even minutes.
該氣相沉積製程可能涉及使具有第V族原子單層的半導體暴露於金屬原子蒸汽流或金屬元素分子流下。可利用熱使該金屬源蒸發而產生該金屬原子/分子流。在本發明一實施例中，該氣流是藉著如實施分子束磊晶法所知的方式般在努特生坩堝(k-cell)中利用熱使元素鋁源蒸發或使用電子束加熱元素鋁源使其蒸發而生成的鋁原子流。在沉積該金屬原子期間可加熱該半導體。在替代的氣相沉積製程中，可使該金屬的氣相化合物(例如，有機金屬化合物)解離而在該半導體表面上沉積該金屬原子。此種製程最常歸類於化學氣相沉積製程。鋁的適當有機金屬化合物包括三甲基鋁。更明確而言，藉由使化學蒸汽來源解離來沉積金屬原子單層時，若該些金屬原子進行磊晶排列且對齊該半導體晶格，該方式被稱為原子層磊晶法，或者若該些金屬原子為進行磊晶排列，則該方式則為原子層沉積法。在另一種替代的氣相沉積製程中，可能藉著從固體來源濺射出該金屬原子而沉積該些金屬原子，此方式為已知的物理氣相(PVD)製程。The vapor deposition process may involve exposing a semiconductor having a monolayer of Group V atoms to a stream of vapors of metal atoms or a stream of metal element molecules. The metal atom/molecular flow can be produced by evaporating the metal source with heat. In one embodiment of the invention, the gas flow is by thermally evaporating a source of elemental aluminum in a K-cell in a K-cell or using an electron beam to heat elemental aluminum, as is known from the practice of molecular beam epitaxy. A stream of aluminum atoms generated by the source to vaporize it. The semiconductor may be heated during deposition of the metal atoms. In an alternative vapor deposition process, a vapor phase compound of the metal (eg, an organometallic compound) may be dissociated to deposit the metal atoms on the semiconductor surface. This process is most often classified as a chemical vapor deposition process. Suitable organometallic compounds of aluminum include trimethylaluminum. More specifically, when a monolayer of metal atoms is deposited by dissociating a chemical vapor source, if the metal atoms are epitaxially aligned and aligned with the semiconductor lattice, the method is called atomic layer epitaxy, or if the Some metal atoms are epitaxially arranged, and the method is atomic layer deposition. In an alternative vapor deposition process, the metal atoms may be deposited by sputtering the metal atoms from a solid source, known as a physical vapor phase (PVD) process.
沉積該金屬原子單層之後，該製程可持續進行以沉積附加的金屬原子層(該金屬原子與第III族原子單層可為相同金屬或不同金屬)。該額外附加之金屬原子層的元素組成和厚度可按照所製成金屬-半導體接觸之特殊用途的要求而定。例如作為奈米級FET的接觸時，該等附加的金屬原子層可為阻障金屬層，例如氮化鉭、氮化鈦或釕。在本文及微電子工業的常用術語中，阻障金屬(barrier metal)是通常利用共形沉積技術(例如，原子層沉積(ALD)、電漿增強ALD或化學氣相沉積(CVD))所沉積而成的薄金屬層，該薄金屬層可提供阻止銅金屬層擴散進入半導體中的屏障。或者，可利用電化學沉積製程或利用反應性物理氣相沉積法(PVD)沉積該阻障金屬，物理氣相沉積法是從固體來源或靶材濺射出該金屬。在替代實施例中，該附加的金屬原子層可由金屬矽化物所構成，例如由成份為Ni2 Si、NiSi或NiSi2 的矽化鎳、矽化鉑、矽化鎳鉑或矽化鈷所構成，其中該金屬矽化物與該第V族單層或第V族-第III族雙層直接相鄰。After depositing the metal atomic monolayer, the process may continue to deposit additional metal atomic layers (the metal atomic and Group III atomic monolayers may be the same metal or different metals). The elemental composition and thickness of the additional metal atomic layer can be determined according to the requirements of the particular application for which the metal-semiconductor contact is made. Such additional metal atomic layers may be barrier metal layers such as tantalum nitride, titanium nitride or ruthenium, for example as contacts for nanoscale FETs. In common terminology herein and in the microelectronics industry, barrier metals are typically deposited using conformal deposition techniques such as atomic layer deposition (ALD), plasma enhanced ALD, or chemical vapor deposition (CVD) A thin metal layer is formed that provides a barrier to prevent the copper metal layer from diffusing into the semiconductor. Alternatively, the barrier metal can be deposited using an electrochemical deposition process or using reactive physical vapor deposition (PVD), which sputters the metal from a solid source or target. In alternative embodiments, the additional metal atomic layer may be composed of metal silicides, such as nickel silicide, platinum silicide, nickel platinum silicide, or cobalt silicide of composition Ni 2 Si, NiSi or NiSi 2 , wherein the metal The silicide is directly adjacent to the Group V monolayer or Group V-Group III bilayer.
除了如先前所述般在矽表面上沉積第V族材料(例如，砷、磷，等等)的單層之外，在足夠高的溫度下沉積一部分的第V族材料是有利的，在足夠高溫下，有一些第V族原子會進入矽本身中。或者，可採用其他已知方式製備該矽表面，使得該第V族出現在靠近該矽表面之處。在此步驟之後，以適當的方式沉積該第V族材料以在該矽表面上形成單層。此種作法的目的是有利於矽中的額外第V族原子形成額外的偶極並且在沉積於第V族材料單層上的金屬內具有鏡像電荷，而有利於提高總體偶極效應。In addition to depositing a monolayer of a Group V material (eg, arsenic, phosphorous, etc.) on the silicon surface as previously described, it is advantageous to deposit a portion of the Group V material at a sufficiently high temperature, At high temperatures, some of the group V atoms get into the silicon itself. Alternatively, the silicon surface can be prepared in other known ways such that the Group V occurs near the silicon surface. Following this step, the Group V material is deposited in a suitable manner to form a monolayer on the silicon surface. The purpose of this is to facilitate the additional group V atoms in the silicon to form additional dipoles and have image charges in the metal deposited on the monolayer of the group V material, thereby helping to increase the overall dipole effect.
第6(a)和6(b)圖是根據本發明實施例所構築之金屬-半導體接觸的進一步實例。在第6(a)圖中，接觸44類似於第5圖中所示之接觸，但該接觸44包含由第V族元素和第III族金屬所形成的額外雙層。產生橫跨該長層間間距(即，介在組成該雙層的單層38與單層40之間的相對較長距離)的電偶極。在第6(b)圖中，接觸44’具有橫跨該短層間間距(即，介在組成該雙層的單層38與單層40之間的相對較短距離)的電偶極。Figures 6(a) and 6(b) are further examples of metal-semiconductor contacts constructed in accordance with embodiments of the present invention. In Figure 6(a), the
如第7圖所示，為了獲得對電洞具有極低能障高度且對於傳導電洞通過該接觸而言具有極低電阻的金屬-半導體接觸，該秩序排列的原子單層是秩序排列的金屬原子單層40且包含第V族原子所形成的單原子層38，該單原子層38與該金屬原子單層化學鍵結並且就由該金屬原子單層40而與半導體36的表面原子隔開。在某些實施例中，該金屬原子所形成之單原子層是第III族金屬原子單層，且該第III族原子可為鋁原子、鎵原子或銦原子或這些第III族金屬原子的混合物。在某些實例中，該第III族金屬原子單層為銦原子層，且該銦原子層磊晶(或實質磊晶)排列並與鍺或矽或第IV半導體合金結晶晶格對齊，並且相鄰的第V族原子單層與該金屬原子單層化學鍵結。第V族原子可為氮原子、磷原子、砷原子或銻原子或這些第V族原子的混合物。在某些實例中，該第V族金屬原子單層為砷原子層，且該砷原子層呈秩序排列並且與該第III族金屬原子對齊並形成化學鍵結，而該第III族金屬原子形成單原子層並與該鍺或矽或第IV半導體合金結晶晶格的表面原子形成結晶對齊及化學鍵結。圖中示出介在半導體與主體金屬之間的兩個雙層，但在本發明範圍內亦可思及包含單一個雙層的實施例。As shown in Figure 7, in order to obtain a metal-semiconductor contact with a very low barrier height for holes and a very low resistance for conducting holes through the contact, the ordered atomic monolayer is an ordered metal The
在某些實施例中，要求形成對p-型半導體具有極低電阻的接觸或要求提供用於p-通道場效電晶體中之具有極高導電性的源極及/或汲極，該接觸表面是{111}-晶向的半導體表面。在其他實施例中，該半導體的接觸表面為{100}晶向表面。In certain embodiments, it is required to form very low resistance contacts to p-type semiconductors or to provide very high conductivity source and/or drain electrodes for use in p-channel field effect transistors, the contacts The surface is a {111}-oriented semiconductor surface. In other embodiments, the contact surface of the semiconductor is a {100} oriented surface.
第8圖圖示用於建立第7圖中所示之接觸的製程45。以使用{100}-晶向的半導體表面作為開始(步驟46)，使用結晶選擇性蝕刻法蝕刻該{100}表面以揭露並暴露出一個或多個{111}-晶向的半導體晶面(步驟48)。在該{111}晶面上形成第III族金屬原子單層(步驟50)，隨後沉積第V族原子單層(步驟52)。顯然，基於不同元件幾何結構或其他考量，可直接由已有的{111}表面作為該製程的開始。FIG. 8 illustrates the
在沉積第V族原子單層之後，該製程繼續進行以沉積額外的多個金屬層(步驟54)。該額外附加之金屬原子層的元素組成和厚度可按照所製成金屬-半導體接觸之特殊用途的要求而定，可如前述般形成用於對電子傳導具有極低電阻之n-型半導體的接觸。After depositing the group V atomic monolayer, the process continues to deposit additional metal layers (step 54). The elemental composition and thickness of the additional metal atomic layer can be determined according to the requirements of the particular application for which the metal-semiconductor contact is to be made, and can be formed as previously described for n-type semiconductor contacts with very low resistance to electron conduction .
可利用氣相沉積製程或化學反應製造第III族原子單層。在氣相沉積製程的例子中，使該半導體暴露於該第III族金屬原子蒸汽流或該第III族金屬元素的化合物分子流。可利用熱使第III族元素來源蒸發而產生該第III族原子/分子氣流。在本發明一實施例中，該氣流是藉著如實施分子束磊晶法所知的方式般在努特生坩堝(k-cell)中利用熱使元素銦源蒸發所生成的銦原子流。在替代的氣相沉積製程中，可使第III族元素的氣相化合物(例如，第III族元素的有機金屬化合物)解離而在該半導體表面上沉積第III族元素原子。藉由加熱該半導體表面可達到使第III族金屬之氣相前驅化合物解離。若不宜將該半導體表面加熱至太高的溫度，可利用電漿增強化學氣相沉積(PECVD)或電漿增強原子層沉積(PEALD)型的工具和製程來達到解離作用。或者，可利用光子誘發式製程來達到使金屬前驅物解離。Group III atomic monolayers can be fabricated using vapor deposition processes or chemical reactions. In an example of a vapor deposition process, the semiconductor is exposed to a stream of a vapor of the Group III metal atoms or a molecular stream of a compound of the Group III metal element. The Group III atomic/molecular gas stream can be produced by evaporating the source of the Group III element using heat. In one embodiment of the invention, the gas stream is a stream of indium atoms generated by thermally evaporating a source of elemental indium in a K-cell in a K-cell, as is known from the practice of molecular beam epitaxy. In an alternative vapor deposition process, a vapor phase compound of a Group III element (eg, an organometallic compound of a Group III element) may be dissociated to deposit Group III element atoms on the semiconductor surface. Dissociation of the gas phase precursor compound of the Group III metal can be achieved by heating the semiconductor surface. If it is not appropriate to heat the semiconductor surface to too high a temperature, plasma enhanced chemical vapor deposition (PECVD) or plasma enhanced atomic layer deposition (PEALD) type tools and processes can be used to achieve dissociation. Alternatively, photon-induced processes can be used to achieve dissociation of the metal precursor.
在將具有{111}-晶向表面的半導體暴露在第III族原子或第III族分子化合物的蒸汽流下之前，可於原位清潔該具有{111}-晶向表面的半導體，例如以矽為例，可在超高真空條件下將該半導體加熱至足夠高的溫度以獲得該{111}矽表面的7x7重組結構。隨後，在將該半導體暴露在該第III族原子蒸汽或第III族分子化合物蒸汽下的期間內，使該半導體保持在介於約20℃至750℃(包括兩端值)範圍內的溫度。或者，在該半導體暴露於該第III族原子蒸汽或第III族分子化合物蒸汽的期間內可改變該半導體溫度，使該半導體溫度從介於600℃至800℃範圍內的高溫開始下降至介於500℃至20℃範圍內的較低溫度。Semiconductors with {111}-oriented surfaces can be cleaned in situ, such as silicon For example, the semiconductor can be heated to a sufficiently high temperature under ultra-high vacuum conditions to obtain a 7x7 reconstituted structure of the {111} silicon surface. Subsequently, the semiconductor is maintained at a temperature in the range of about 20°C to 750°C, inclusive, during exposure of the semiconductor to the Group III atomic vapor or Group III molecular compound vapor. Alternatively, the semiconductor temperature may be varied during exposure of the semiconductor to the Group III atomic vapor or Group III molecular compound vapor such that the semiconductor temperature begins to decrease from a high temperature in the range of 600°C to 800°C to between Lower temperatures in the range of 500°C to 20°C.
可該半導體在第III族原子或化合物蒸汽流下暴露短於一秒或長達數秒或甚至數分鐘的時間。該第III族原子與露出的第IV族半導體表面直接鍵結而形成第III原子單層，該第III族原子的晶體盡最大可能程度地對齊該半導體晶格。The semiconductor may be exposed to a stream of Group III atom or compound vapor for a time shorter than a second or as long as several seconds or even minutes. The group III atoms are directly bonded to the exposed group IV semiconductor surface to form a monolayer of group III atoms, and the crystals of the group III atoms are aligned to the greatest possible extent in the semiconductor lattice.
可在UHV腔室中、在真空腔室中或在減壓腔室中使半導體的表面暴露於第III族原子流或分子化合物蒸汽流。若進行該製程的腔室並非UHV腔室，在該暴露過程中可能存在背景氣體或載氣。在一實施例中，以主要由載氣(例如，氫氣或氮氣)所組成的氣體混合物以稀釋的形成來輸送有機金屬化合物前驅物(例如三甲基銦)，並且該有機金屬化合物前驅物在該已加熱的半導體表面處解離而釋出自由的銦原子，自由的銦原子與露出的矽直接鍵結。在另一實施例中，該有機金屬化合物為三甲基鋁或三甲基鎵，三甲基鋁或三甲基鎵在已加熱的半導體表面處進行反應以分別形成鋁原子單層或鎵原子單層。The surface of the semiconductor may be exposed to a stream of Group III atomic or molecular compound vapors in a UHV chamber, in a vacuum chamber, or in a reduced pressure chamber. If the chamber in which the process is performed is not a UHV chamber, a background or carrier gas may be present during the exposure. In one embodiment, the organometallic compound precursor (eg, trimethylindium) is delivered in a diluted form with a gas mixture consisting essentially of a carrier gas (eg, hydrogen or nitrogen), and the organometallic compound precursor is The heated semiconductor surface dissociates to release free indium atoms, which bond directly to the exposed silicon. In another embodiment, the organometallic compound is trimethylaluminum or trimethylgallium which reacts at the heated semiconductor surface to form a monolayer of aluminum atoms or gallium atoms, respectively single layer.
在{111}-晶向之第IV族半導體的表面上形成配位的第III族金屬原子單層之後，沉積第III族原子單層40，接著沉積一層第V族原子以形成低能障、低電阻的金屬接觸。該第V族原子層中的第V族原子較佳已位在該半導體表面上的第III族金屬原子單層進行配位，從而形成秩序排列的第V族原子層。隨後，該製程繼續進行以沉積額外的金屬原子，該額外的原子可與該第一層金屬原子為相同的金屬元素，或是與該第一層金屬原子為不同的金屬元素。After a monolayer of coordinated Group III metal atoms is formed on the surface of the {111}-oriented Group IV semiconductor, a monolayer of
在本發明的另一實施例中，在{100}或{111}-晶向的第IV族半導體的表面上形成配位的第III族金屬原子單層之後，可接著在該單層上沉積金屬以形成低能障、低電阻的金屬接觸。該金屬不一定是第V族金屬。該金屬可能是具有所欲性質的金屬，例如具有結構或化學安定性以確保所形成之電接觸或電子元件的可靠性。用於形成接觸的安定金屬實例包括鉑(Pt)、鎢(W)及前述的「阻障金屬」：TaN、TiN和Ru。可直接在第III族單層上沉積金屬，使得該第III族單層恰好位在該金屬與該半導體之間的界面處，或者可利用一個或兩個第IV族半導體單層隔開該第III族單層與該金屬。因此，若有一個或兩個第IV族半導體原子層分別介在該第III族單層與金屬之間，則在該界面層處或在從該半導體-金屬界面算起第三個平面處可存在有第III單層所帶來的單層電荷。在帶電的第III原子(離子)單層與金屬原子之間具有一個或數個矽原子層且從而將該帶電第III原子(離子)單層與該金屬原子隔開的優點是可增加該等層之間所建立的電偶極大小，且從而較大幅地降低在p-型半導體接面或MOSFET之金屬與p-型通道源/汲極接面處的蕭特基能障。In another embodiment of the present invention, after forming a monolayer of coordinated Group III metal atoms on the surface of a {100} or {111}-oriented Group IV semiconductor, deposition on the monolayer may follow metal to form low energy barrier, low resistance metal contacts. The metal need not be a Group V metal. The metal may be a metal having desired properties, such as structural or chemical stability to ensure the reliability of electrical contacts or electronic components formed. Examples of stabilizer metals used to form contacts include platinum (Pt), tungsten (W), and the aforementioned "barrier metals": TaN, TiN, and Ru. The metal can be deposited directly on the Group III monolayer such that the Group III monolayer is just at the interface between the metal and the semiconductor, or one or two Group IV semiconductor monolayers can be used to separate the Group III monolayer. Group III monolayer with this metal. Thus, if one or two atomic layers of group IV semiconductor are interposed between the group III monolayer and the metal, respectively, there may be present at the interface layer or at the third plane from the semiconductor-metal interface There is a monolayer charge brought by the III monolayer. The advantage of having one or several layers of silicon atoms between the charged III atomic (ion) monolayer and the metal atoms and thus separating the charged III atomic (ion) monolayer from the metal atom is that these The galvanic pair created between the layers is small and thereby considerably reduces the Schottky barrier at the p-type semiconductor junction or the metal of the MOSFET and the p-type channel source/drain junction.
本發明的另一實施例形成一種金屬半導體接觸，該金屬半導體接觸在該金屬-半導體界面處具有第V族或第III族原子單層，並在該金屬-半導體界面處，是藉由從與該半導體表面接觸的材料層中偏析出第V族或第III族原子而形成該第V族(例如，砷)單層或第III族(例如，硼)單層。可例如使用CVD或PVD在該半導體表面上沉積該材料層。藉著使CVD或PVD沉積製程中納入第V族原子以作為摻雜劑或利用離子佈植將該第V族原子引入該材料層中。或可藉由使另一種元素或多種元素與半導體表面發生反應而形成該材料層，在此情況下，可在藉由化學反應形成該材料之前或之後，佈植該第V族或第III族原子。例如，該層可能是藉著使矽表面進行熱氧化反應所形成的氧化矽或氮化矽層，且可利用離子佈植將第V族或第III族原子引入該氧化矽或氮化矽層內。在另一實施例中，該層可能是由摻雜有高濃度第Ｖ族元素(例如，磷)或第III族元素(例如，硼)之氧化矽所形成的沉積薄膜。前者通常認為是「磷矽玻璃(PSG)」且後者通常是「硼矽玻璃(BSG)」，及用來沉積此等經摻雜之矽酸鹽玻璃的方法(例如，CVD)已廣為人知並廣泛用於微電子工業中。或者，該材料層可能是使金屬與矽表面反應所形成的金屬矽化物，並可利用離子佈植將第V族或第III族原子引入該金屬矽化物層中。Another embodiment of the present invention forms a metal-semiconductor contact having a monolayer of Group V or Group III atoms at the metal-semiconductor interface, and at the metal-semiconductor interface by The group V or group III atoms are segregated in the material layer in contact with the semiconductor surface to form the group V (eg, arsenic) monolayer or the group III (eg, boron) monolayer. The layer of material can be deposited on the semiconductor surface, eg, using CVD or PVD. The Group V atoms are introduced into the material layer by incorporating them as dopants in a CVD or PVD deposition process or by ion implantation. Alternatively, the layer of material may be formed by reacting another element or elements with the semiconductor surface, in which case the Group V or Group III implantation may be performed either before or after the formation of the material by chemical reaction atom. For example, the layer may be a silicon oxide or silicon nitride layer formed by thermally oxidizing the silicon surface, and ion implantation may be used to introduce group V or group III atoms into the silicon oxide or silicon nitride layer Inside. In another embodiment, the layer may be a deposited film of silicon oxide doped with a high concentration of a Group V element (eg, phosphorus) or a Group III element (eg, boron). The former is commonly referred to as "phosphosilicate glass (PSG)" and the latter is usually "borosilicate glass (BSG)", and the methods used to deposit these doped silicate glasses (eg, CVD) are well known and widely used Used in the microelectronics industry. Alternatively, the material layer may be a metal silicide formed by reacting a metal with a silicon surface, and ion implantation may be used to introduce Group V or Group III atoms into the metal silicide layer.
在與半導體表面接觸的材料層中引入一濃度的第V族或第III族原子之後，使整個層結構在足夠高的溫度下進行退火(annealed)以造成該第V族或第III族原子偏析(segregate)至該界面，而在該界面處形成秩序排列的第V族或第III族單層，並且該第V族或第III族原子以磊晶配位與半導體原子的頂層鍵結。在該材料層是經摻雜之氧化矽(例如，PSG或BSG)或氮化矽且該半導體為矽的例子中，在該退火循環造成一部分的第V族或第III族元素偏析至該矽-氧化矽(或氮化矽)的界面處之後，隨後可利用選擇性濕式化學蝕刻法去除該氧化矽(氮化矽)，而留下位於該半導體表面處之已配位的第V族或第III族原子單層，及沉積金屬以形成該半導體的金屬接觸。在該材料層是金屬矽化物且該半導體是矽的例子中，在該退火循環造成第V族或第III族元素的界面偏析作用而形成秩序排列的界面單層之後，可去除該金屬矽化物，或使該金屬矽化物留在原地，以該金屬矽化物本身作為金屬接觸。After introducing a concentration of Group V or Group III atoms into a layer of material in contact with the semiconductor surface, the entire layer structure is annealed at a temperature high enough to cause segregation of the Group V or Group III atoms (segregate) to the interface, where an ordered group V or group III monolayer is formed, and the group V or group III atoms are bonded to the top layer of semiconductor atoms in epitaxial coordination. In instances where the material layer is doped silicon oxide (eg, PSG or BSG) or silicon nitride and the semiconductor is silicon, the annealing cycle causes a portion of the Group V or Group III elements to segregate into the silicon - After the silicon oxide (or silicon nitride) interface, the silicon oxide (silicon nitride) can then be removed by selective wet chemical etching, leaving the coordinated group V at the semiconductor surface or a monolayer of Group III atoms, and depositing metal to form the metal contacts of the semiconductor. In instances where the material layer is a metal silicide and the semiconductor is silicon, the metal silicide may be removed after the annealing cycle causes interfacial segregation of Group V or Group III elements to form an ordered interfacial monolayer , or leave the metal silicide in place, using the metal silicide itself as a metal contact.
本發明的又另一些實施例涉及使用{100}-晶向的半導體表面。第9圖圖示一個包含此種表面的接觸，此接觸包含一第V族原子單層，並且可使用上述技術中的任一技術在第IV半導體{100}表面上沉積該第V族原子單層。隨後在該第V族原子上沉積第III族金屬原子單層，接著沉積額外的金屬層。這些額外的金屬原子與第一層金屬原子可能為相同的金屬元素，或這些額外的金屬原子與第一層金屬原子可能為不同的金屬元素。第9圖所示的金屬-半導體接觸可為電子提供極低的能障高度並為電子通過該接觸的電性傳導作用提供極低的電阻。若欲使該接觸為電子提供極低的能障高度且為電洞通過該接觸的電性傳導作用提供極低電阻，可使該雙層中之第V族原子與第III族原子的位置彼此對調。Still other embodiments of the present invention relate to the use of {100}-oriented semiconductor surfaces. Figure 9 illustrates a contact comprising such a surface, which contact comprises a monolayer of Group V atoms, and which can be deposited on a {100} surface of a IV semiconductor using any of the techniques described above Floor. A monolayer of Group III metal atoms is then deposited on the Group V atoms, followed by additional metal layers. The additional metal atoms and the first-layer metal atoms may be the same metal element, or the additional metal atoms and the first-layer metal atoms may be different metal elements. The metal-semiconductor contact shown in Figure 9 can provide a very low energy barrier height for electrons and a very low resistance to the electrical conduction of electrons through the contact. If the contact is to provide a very low energy barrier height for electrons and a very low resistance for the electrical conduction of holes through the contact, the positions of the Group V and Group III atoms in the double layer can be placed relative to each other. Swap.
製造實驗用的蕭特基偶極，藉以說明砷界面單層對於示範用之鋁-矽蕭特基能障的影響。該些示範實驗並非代表是典型製程條件，也未必就代表是最佳製程條件。在{111}-晶向且具約1x1017
原子/立方公分之硼濃度的p-型摻雜矽晶圓上完成該些示例性實驗。在超高真空條件下製造第一組實驗用的蕭特基偶極，以及在氫氣氛圍中於低壓化學氣相沉積條件下製造第二組實驗用的蕭特基偶極。An experimental Schottky dipole was fabricated to illustrate the effect of the arsenic interfacial monolayer on the demonstration Al-Si Schottky barrier. These demonstration experiments do not represent typical process conditions, nor do they necessarily represent optimal process conditions. These exemplary experiments were performed on p-type doped silicon wafers with {111}-crystalline orientation and a boron concentration of about 1×10 17 atoms/
以下述方式處理該第一組偶極：在超高真空中加熱該矽達800℃以清潔該{111}Si表面並使該{111}Si表面重組成為7x7重組結構之後，使溫度從800℃降至700℃且隨後使該矽表面暴露於As2
砷分子流中持續10分鐘，之後終止As2
氣流。使用拉塞福背散射分析法(Rutherford back scattering analysis)確認此暴露步驟所得到的砷原子之面密度等於7.30x1014
原子/平方公分，此數值接近已知在1x1重組{111}矽表面上之表面原子的面密度7.83x1014
原子/平方公分。如此，可合理得出已大約沉積了單層的砷原子。待冷卻至室溫後，在相同的超高真空系統中沉積一層純鋁，且隨後將該層純鋁圖案化以提供簡單的偶極結構可供進行電性測量。為了做比較，可利用類似的步驟順序處理一個類似的晶圓，只除了不會將該矽表面刻意暴露於任何砷原子下。第10圖圖示從每個晶圓(含砷及不含砷)上取相同大小的偶極進行測量後，所測得這些實驗性偶極的電流-電壓特性。如第10圖之測量曲線72所示，在晶圓上於界面處不含砷的偶極一致表現出對於p-型矽具有相對小的蕭特基能障高度。由曲線72，利用標準偶極方程式(熱離子發射模型)擬合該測量數據可得到能障高度。所得到未經砷暴露處理之偶極的能障高度為0.40eV(實驗誤差約為0.03eV)，此能障高度值與已公開的p-型矽上之緊密鋁接觸的能障高度值一致。如第10圖之數據曲線70所示，在晶圓上曾使該矽界面暴露在砷下而形成砷單層的偶極一致表現出對p-型矽具有較大的蕭特基能障高度。根據n-型與p-型能障高度的總合大小非常接近該矽能帶隙的通則，對p-型矽具有較大能障高度就代表對n-型矽具有較小的能障高度。因此，實驗證明在鋁與{111}-晶向矽表面之間的界面處引入砷原子單層，對於p-型矽而言，確實可提供較大的蕭特基能障，這和在鋁費米能階與矽傳導帶之間降低的電子能障結果一致(即，對n-型矽具有降低的蕭特基能障高度的結果一致)。The first set of dipoles were treated in the following manner: After heating the silicon up to 800°C in ultra-high vacuum to clean the {111}Si surface and reorganize the {111}Si surface into a 7x7 reconstituted structure, the temperature was increased from 800°C to It was lowered to 700°C and then the silicon surface was exposed to As 2 arsenic molecular flow for 10 minutes before As 2 gas flow was terminated. Rutherford back scattering analysis was used to confirm that the areal density of arsenic atoms obtained from this exposure step was equal to 7.30x10 14 atoms/
以下述方式處理該第二組偶極：在流動的氫氣中加熱該矽達900℃以清潔該{111}Si表面之後，使溫度從900℃降至700℃且隨後使該矽表面暴露於砷化氫(AsH3
)分子流中持續10分鐘，並且在AsH3
氣流結束之前使溫度保持在700℃。以大量的氫氣(H2
)將砷化氫稀釋至約2ppm的濃度且總氣流量為每分鐘20.4公升。使用拉塞福背散射分析法確認此暴露步驟所得到的砷原子之面密度等於7.8x1014
原子/平方公分，此數值接近已知在1x1重組{111}矽表面上之表面原子的面密度7.83x1014
原子/平方公分。如此，可合理得出已大約沉積了單層的砷原子。待冷卻至室溫後，在獨立的超高真空系統中利用電子束蒸鍍法(electron beam evaporation)沉積一層純鋁，且隨後將該層純鋁圖案化以提供簡單的偶極結構而可供進行電性測量。為了做比較，可利用類似的步驟順序處理一個類似的晶圓，只除了不會將矽表面刻意暴露於任何砷原子下。第11圖圖示所測得之這些實驗性偶極(含砷及不含砷)的電流-電壓特性。如第11圖之測量曲線82所示般，在晶圓上於界面處不含砷的偶極一致表現出對於p-型矽而言具有相對小的蕭特基能障高度。由曲線82，利用標準偶極方程式(熱離子發射模型)擬合測量數據可得到能障高度。所得到未經砷暴露處理之偶極的能障高度為0.42eV(實驗誤差約為0.03eV)，此能障高度值與p-型矽上已公開之緊密鋁接觸的能障高度值相符。如第11圖之數據曲線80所示，在晶圓上曾使該矽界面暴露在砷下而形成砷單層的偶極一致表現出對於p-型矽而言具有較大的蕭特基能障高度。根據n-型與p-型能障高度的總合大小非常接近該矽能帶隙的通則，對p-型矽具有較大能障高度代表對於n-型矽具有較小的能障高度。因此，實驗證明在鋁與{111}-晶向矽表面之間的界面處引進砷原子單層，對於p-型矽而言，確實可提供較大的蕭特基能障，這和在鋁費米能階與矽傳導帶之間降低的電子能障結果一致(即，對n-型矽具有降低的蕭特基能障高度的結果一致)。The second set of dipoles were treated by heating the silicon to 900°C in flowing hydrogen to clean the {111}Si surface, reducing the temperature from 900°C to 700°C and then exposing the silicon surface to arsenic Hydrogen hydride (AsH3 ) molecular flow was continued for 10 minutes and the temperature was maintained at 700°C until the AsH3 flow was terminated. Arsine was diluted with a large amount of hydrogen ( H2 ) to a concentration of about 2 ppm and the total gas flow was 20.4 liters per minute. Rutherford backscattering analysis was used to confirm that the areal density of arsenic atoms obtained from this exposure step was equal to 7.8x10 14 atoms/
因此，現已說明數種藉由在金屬與半導體之間的界面處***一個第V族或第III族原子單層或多個第V族及第III族原子單層以降低金屬-半導體接面之比接觸電阻的技術。Accordingly, several methods have been described to reduce the metal-semiconductor junction by inserting a monolayer of Group V or Group III atoms or a plurality of monolayers of Group V and Group III atoms at the interface between the metal and the semiconductor than the contact resistance technology.
10:製程
12、14、16、18:步驟
20:表面
22、24、26、28:原子
30:角落孔洞
32:第V族原子
34:矽表面原子
36:第IV族半導體
38:第V族原子單層
40:第III族原子單層
42:金屬原子
44:接觸
45:製程
46、48、50、52、54:步驟
70:曲線
72:曲線
80:曲線
82:曲線10:
附圖的圖式係以舉例方式圖示說明本發明，而非作為限制之用，該等圖式如下：The drawings of the accompanying drawings illustrate the invention by way of example and not by way of limitation, and are as follows:
第1(a)和1(b)圖圖示在金屬-半導體接面處的位能能障；明確言之，第1(a)圖圖示在半導體(左側)-金屬(右側)界面處具有會阻礙電流的固定厚實能障；及第1(b)圖圖示插在金屬與半導體之間的偶極層如何消除除了位在一對原子平面之間以外的能障。Figures 1(a) and 1(b) illustrate the potential energy barrier at the metal-semiconductor junction; specifically, Figure 1(a) illustrates the potential energy barrier at the semiconductor (left)-metal (right) interface have a fixed thick energy barrier that blocks current flow; and Figure 1(b) illustrates how a dipole layer interposed between the metal and the semiconductor eliminates energy barriers other than between a pair of atomic planes.
第2圖圖示根據本發明實施例形成對半導體表面具有極低電阻之金屬接觸的製程實例。Figure 2 illustrates an example of a process for forming a metal contact with very low resistance to a semiconductor surface in accordance with an embodiment of the present invention.
第3(a)、3(b)和3(c)圖提供7x7已重組之{111}-晶向矽表面的視圖。Figures 3(a), 3(b) and 3(c) provide views of the 7x7 reconstituted {111}-oriented silicon surface.
第4圖圖示第V族原子與暴露的矽表面原子直接鍵結以形成完全配位之晶格終端而不具有懸鍵的實例。Figure 4 illustrates an example where Group V atoms are directly bonded to exposed silicon surface atoms to form fully coordinated lattice terminations without dangling bonds.
第5圖圖示根據本發明實施例利用第2圖中所示之製程在n型半導體的(111)表面上***一雙層(兩個單層)而製造出接觸。Figure 5 illustrates the fabrication of contacts by inserting a bilayer (two monolayers) on the (111) surface of an n-type semiconductor using the process shown in Figure 2 in accordance with an embodiment of the present invention.
第6(a)和6(b)圖分別圖示在具有跨越長晶面間距或短晶面間距之場區的n-型半導體中，位於(111)界面上的兩個雙層。Figures 6(a) and 6(b) illustrate two bilayers at the (111) interface, respectively, in an n-type semiconductor with a field region spanning the long interplanar spacing or the short interplanar spacing.
第7圖係根據本發明之進一步實施例，圖示如第6圖所示但卻用於p-型半導體的兩個雙層，該等雙層可為整個接觸中的電洞傳導作用提供極低的電阻。Figure 7 illustrates two bilayers as shown in Figure 6, but for p-type semiconductors, which can provide extremes for hole conduction throughout the contact, according to a further embodiment of the present invention. low resistance.
第8圖係根據本發明實施例圖示一種用於建立第7圖中所示之接觸的製程。FIG. 8 illustrates a process for establishing the contacts shown in FIG. 7 in accordance with an embodiment of the present invention.
第9圖圖示如第5圖所示但並非用於{111}表面，而是用於{100}半導體表面的單個雙層(兩個單層)。Figure 9 illustrates a single bilayer (two monolayers) as shown in Figure 5 but not for {111} surfaces, but for {100} semiconductor surfaces.
第10和11圖圖示藉由實驗從鋁-{111}晶向p-型矽接觸所獲得的蕭特基偶極電流-電壓特性，並與在界面處具有砷原子單層之接觸的測量數據以及不具有砷界面層之接觸的數據做比較。Figures 10 and 11 illustrate the Schottky dipole current-voltage characteristics obtained experimentally from Al-{111} oriented p-type silicon contacts, and measurements with contacts with a monolayer of arsenic atoms at the interface Data are compared with data for contacts without an arsenic interface layer.
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| US20050104137A1 (en) * | 2002-08-12 | 2005-05-19 | Carl Faulkner | Insulated gate field-effect transistor having III-VI source/drain layer(s) |
| US20050247956A1 (en) * | 2002-08-12 | 2005-11-10 | Grupp Daniel E | Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
| TW200703647A (en) * | 2005-07-01 | 2007-01-16 | Ibm | Ultrathin-body schottky contact MOSFET |
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| US20050104137A1 (en) * | 2002-08-12 | 2005-05-19 | Carl Faulkner | Insulated gate field-effect transistor having III-VI source/drain layer(s) |
| US20050247956A1 (en) * | 2002-08-12 | 2005-11-10 | Grupp Daniel E | Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
| TW200703647A (en) * | 2005-07-01 | 2007-01-16 | Ibm | Ultrathin-body schottky contact MOSFET |
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