TWI756103B

TWI756103B - Pixel array substrate

Info

Publication number: TWI756103B
Application number: TW110113064A
Authority: TW
Inventors: 余悌魁; 徐雅玲
Original assignee: 友達光電股份有限公司
Priority date: 2021-04-12
Filing date: 2021-04-12
Publication date: 2022-02-21
Also published as: TW202240565A

Abstract

A pixel array substrate including pixels, scan lines and data lines is provided. The pixels are arranged in pixel rows and pixel columns.　Pixels of each of the pixel rows are arranged along a first direction. Pixels of each of the pixel columns are arranged along a second direction. Each of the pixels includes a first pixel structure and a second pixel structure, wherein the first pixel structure includes a first active device and a first pixel electrode electrically connected to the first active device, the second pixel structure includes a second active device and a second pixel electrode electrically connected to the second active device, and the first pixel electrode and the second pixel electrode are sequentially arranged along the second direction. First active devices and second active devices of pixels of the same pixel row are electrically connected to the same scan line. First active devices and second active devices of pixels of the same pixel column are electrically connected to two adjacent data lines. The first active device and the second active device of each of pixels of each of the pixel columns are electrically connected to the two adjacent data lines, respectively. Multiple pixels are arranged in multiple pixel columns and multiple pixel rows 多个像素排列在多个像素列和多个像素行中 A plurality of pixels arranged in a plurality of pixel columns and a plurality of pixel rows 布置在多个像素列和多个像素行中的多个像素無法載入全部結果再試一次正在重試... 正在重試...

Description

畫素陣列基板pixel array substrate

本發明是有關於一種畫素陣列基板。 The present invention relates to a pixel array substrate.

為解決顯示裝置側視角偏白(color washout)的問題，一般會將單一畫素劃分為兩個畫素結構，稱為主畫素結構和次畫素結構，並搭配適當之電路驅動架構，以使主畫素結構和次畫素結構的畫素電壓不同。藉此，改善側視角偏白的問題。然而，在解決側視角偏白問題的同時，於現行之顯示裝置的畫素陣列基板的佈局下，卻易出現閃爍(flick)及亮/暗線的問題。 In order to solve the problem of color washout from the side view angle of the display device, a single pixel is generally divided into two pixel structures, called the main pixel structure and the sub-pixel structure, and an appropriate circuit driving structure is used to Make the pixel voltages of the primary pixel structure and the secondary pixel structure different. Thereby, the problem of whitening in side viewing angle is improved. However, while solving the whitening problem of the side viewing angle, the current layout of the pixel array substrate of the display device is prone to the problems of flicker and bright/dark lines.

本發明提供一種畫素陣列基板，性能佳。 The present invention provides a pixel array substrate with good performance.

本發明的畫素陣列基板包括多個畫素、多條掃描線以及多條資料線。多個畫素排成多個畫素列及多個畫素行，其中每一畫素列的多個畫素沿第一方向排列，每一畫素行的多個畫素沿第二方向排列，且第一方向與第二方向交錯。每一畫素包括第一畫素結構及第二畫素結構，第一畫素結構包括第一主動元件及電性連接至第一主動元件的第一畫素電極，第二畫素結構包括第二主動元件及電性連接至第二主動元件的第二畫素電極，其中第一畫素電極與第二畫素電極沿第二方向依序排列。多條掃描線在第一方向上延伸，其中同一畫素列的多個畫素的多個第一主動元件及多個第二主動元件電性連接至同一掃描線。多條資料線在第二方向上延伸，其中每一畫素行之多個畫素的多個第一主動元件及多個第二主動元件電性連接至相鄰兩資料線，且每一畫素行之多個畫素的每一者的第一主動元件及第二主動元件分別電性連接至相鄰兩資料線。多個畫素行包括沿第一方向依序排列的第n個畫素行、第n+1個畫素行及第n+2個畫素行，其中n為大於或等於1的正整數。多個畫素列包括沿第二方向依序排列的第m個畫素列及第m+1個畫素列，其中m為大於或等於1的正整數。多條資料線包括沿第一方向依序排列的第一資料線、第二資料線、第三資料線、第四資料線、第五資料線及第六資料線。每一畫素具有相對的第一側及第二側。第n個畫素行及第m個畫素列的畫素的第一主動元件電性連接至位於畫素之第二側的第二資料線，且第n個畫素行及第m個畫素列的畫素的第二主動元件電性連接至位於畫素之第一側的第一資料線。第n個畫素行及第m+1個畫素列的畫素的第一主動元件電性連接至位於畫素之第二側的第二資料線，且第n個畫素行及第m+1個畫素列的畫素的第二主動元件電性連接至位於畫素之第一側的第一資料線。第n+1個畫素行及第m個畫素列的畫素的第一主動元件電性連接至位於畫素之第一側的第三資料線，且第n+1個畫素行及第m個畫素列的畫素的第二主動元件電性連接至位於畫素之第二側的第四資料線。第n+1個畫素行及第m+1個畫素列的畫素的第一主動元件電性連接至位於畫素之第二側的第四資料線，且第n+1個畫素行及第m+1個畫素列的畫素的第二主動元件電性連接至位於畫素之第一側的第三資料線。第n+2個畫素行及第m個畫素列的畫素的第一主動元件電性連接至位於畫素之第二側的第六資料線，且第n+2個畫素行及第m個畫素列的畫素的第二主動元件電性連接至位於畫素之第一側的第五資料線。第n+2個畫素行及第m+1個畫素列的畫素的第一主動元件電性連接至位於畫素之第二側的第六資料線，且第n+2個畫素行及第m+1個畫素列的畫素的第二主動元件電性連接至位於畫素之第一側的第五資料線。在同一圖框時間內，第一資料線的一資料訊號的極性、第二資料線的一資料訊號的極性、第三資料線的一資料訊號的極性、第四資料線的一資料訊號的極性、第五資料線的一資料訊號的極性及第六資料線的一資料訊號的極性分別為正、負、正、負、正及負。 The pixel array substrate of the present invention includes a plurality of pixels, a plurality of scan lines and a plurality of data lines. The plurality of pixels are arranged in a plurality of pixel rows and a plurality of pixel rows, wherein the plurality of pixels in each pixel row are arranged in a first direction, and the plurality of pixels in each pixel row are arranged in a second direction, and The first direction is interleaved with the second direction. Each pixel includes a first pixel structure and a second pixel structure, and the first pixel structure includes a first active element and an electrical The first pixel electrode connected to the first active element, the second pixel structure includes a second active element and a second pixel electrode electrically connected to the second active element, wherein the first pixel electrode and the second pixel electrode The electrodes are sequentially arranged along the second direction. The plurality of scan lines extend in the first direction, wherein the plurality of first active elements and the plurality of second active elements of the plurality of pixels in the same pixel row are electrically connected to the same scan line. A plurality of data lines extend in the second direction, wherein a plurality of first active elements and a plurality of second active elements of a plurality of pixels in each pixel row are electrically connected to two adjacent data lines, and each pixel row The first active element and the second active element of each of the plurality of pixels are respectively electrically connected to two adjacent data lines. The plurality of pixel rows include an n-th pixel row, an n+1-th pixel row, and an n+2-th pixel row arranged in sequence along the first direction, where n is a positive integer greater than or equal to 1. The plurality of pixel rows include an m-th pixel row and an m+1-th pixel row arranged in sequence along the second direction, where m is a positive integer greater than or equal to 1. The plurality of data lines include a first data line, a second data line, a third data line, a fourth data line, a fifth data line and a sixth data line arranged in sequence along the first direction. Each pixel has opposing first and second sides. The first active elements of the pixels of the nth pixel row and the mth pixel row are electrically connected to the second data line on the second side of the pixel, and the nth pixel row and the mth pixel row are electrically connected to the second data line on the second side of the pixel. The second active element of the pixel is electrically connected to the first data line on the first side of the pixel. The first active elements of the pixels of the nth pixel row and the m+1th pixel row are electrically connected to the second data line on the second side of the pixel, and the nth pixel row and the m+1th pixel row are electrically connected to the second data line on the second side of the pixel. The second active elements of the pixels of each pixel row are electrically connected to the first data lines located on the first side of the pixels. The first active elements of the pixels of the n+1th pixel row and the mth pixel column are electrically connected to the first active element located on the first side of the pixel. There are three data lines, and the second active elements of the pixels of the n+1th pixel row and the mth pixel column are electrically connected to the fourth data line located on the second side of the pixel. The first active elements of the pixels in the n+1 th pixel row and the m+1 th pixel row are electrically connected to the fourth data line on the second side of the pixel, and the n+1 th pixel row and The second active element of the pixel of the m+1th pixel row is electrically connected to the third data line located on the first side of the pixel. The first active elements of the pixels of the n+2th pixel row and the mth pixel row are electrically connected to the sixth data line located on the second side of the pixel, and the n+2th pixel row and the mth pixel row are electrically connected to the sixth data line on the second side of the pixel. The second active elements of the pixels of each pixel row are electrically connected to the fifth data line located on the first side of the pixels. The first active elements of the pixels in the n+2 th pixel row and the m+1 th pixel row are electrically connected to the sixth data line on the second side of the pixel, and the n+2 th pixel row and The second active element of the pixel of the m+1th pixel row is electrically connected to the fifth data line located on the first side of the pixel. In the same frame time, the polarity of a data signal of the first data line, the polarity of a data signal of the second data line, the polarity of a data signal of the third data line, the polarity of a data signal of the fourth data line , the polarity of a data signal of the fifth data line and the polarity of a data signal of the sixth data line are respectively positive, negative, positive, negative, positive and negative.

100:畫素陣列基板 100: pixel array substrate

A1、A2:區域 A1, A2: Area

C:畫素行 C: pixel row

CE1:第一共用電極 CE1: first common electrode

CE2:第二共用電極 CE2: second common electrode

CL:共用線 CL: common line

Cn:第n個畫素行 Cn: the nth pixel row

Cn+1:第n+1個畫素行 Cn+1: the n+1th pixel row

Cn+2:第n+2個畫素行 Cn+2: n+2 pixel row

Cn+3:第n+3畫素行 Cn+3: n+3 pixel row

Cn+4:第n+4個畫素行 Cn+4: the n+4th pixel row

Cn+5:第n+5畫素行 Cn+5: pixel row n+5

DL:資料線 DL: data line

DL1:第一資料線 DL1: The first data line

DL2:第二資料線 DL2: Second data line

DL3:第三資料線 DL3: The third data line

DL4:第四資料線 DL4: Fourth data line

DL5:第五資料線 DL5: Fifth Data Line

DL6:第六資料線 DL6: The sixth data line

DL7:第七資料線 DL7: Seventh Data Line

DL8:第八資料線 DL8: The eighth data line

DL9:第九資料線 DL9: ninth data line

DL10:第十資料線 DL10: Tenth Data Line

DL11:第十一資料線 DL11: The eleventh data line

DL12:第十二資料線 DL12: Twelfth Data Line

HG、HG1、HG2、HG3、HG4:掃描線 HG, HG1, HG2, HG3, HG4: scan lines

PE1:第一畫素電極 PE1: first pixel electrode

PE2:第二畫素電極 PE2: Second pixel electrode

PX:畫素 PX: pixel

PXa:主畫素 PXa: Main Pixel

PXb:次畫素 PXb: Subpixel

PX1:第一畫素結構 PX1: First pixel structure

PX2:第二畫素結構 PX2: Second pixel structure

R:畫素列 R: pixel row

Rm:第m個畫素列 Rm: the mth pixel column

Rm+1:第m+1個畫素行 Rm+1: m+1 pixel row

Rm+2:第m+2個畫素行 Rm+2: m+2 pixel row

Rm+3:第m+3個畫素行 Rm+3: m+3 pixel row

VG:轉接線 VG: transfer cable

T1:第一主動元件 T1: The first active element

T1a、T2a:第一端 T1a, T2a: first end

T1b、T2b:第二端 T1b, T2b: the second end

T1c、T2c:控制端 T1c, T2c: control terminal

T1d、T2d:半導體圖案 T1d, T2d: semiconductor pattern

T2:第二主動元件 T2: The second active element

x:第一方向 x: first direction

y:第二方向 y: the second direction

圖1為本發明一實施例之畫素陣列基板100的示意圖。 FIG. 1 is a schematic diagram of a pixel array substrate 100 according to an embodiment of the present invention.

圖2為本發明一實施例之畫素陣列基板100之佈局(layout)的俯視示意圖。 FIG. 2 is a schematic top view of a layout of a pixel array substrate 100 according to an embodiment of the present invention.

圖3為本發明一實施例之畫素陣列基板100之佈局(layout)的俯視示意圖。 FIG. 3 is a schematic top view of a layout of a pixel array substrate 100 according to an embodiment of the present invention.

現將詳細地參考本發明的示範性實施例，示範性實施例的實例說明於附圖中。只要有可能，相同元件符號在圖式和描述中用來表示相同或相似部分。 Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and description to refer to the same or like parts.

應當理解，當諸如層、膜、區域或基板的元件被稱為在另一元件“上”或“連接到”另一元件時，其可以直接在另一元件上或與另一元件連接，或者中間元件可以也存在。相反，當元件被稱為“直接在另一元件上”或“直接連接到”另一元件時，不存在中間元件。如本文所使用的，“連接”可以指物理及/或電性連接。再者，“電性連接”或“耦合”可以是二元件間存在其它元件。 It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may refer to the existence of other elements between the two elements.

本文使用的“約”、“近似”、或“實質上”包括所述值和在本領域普通技術人員確定的特定值的可接受的偏差範圍內的平均值，考慮到所討論的測量和與測量相關的誤差的特定數量(即，測量系統的限制)。例如，“約”可以表示在所述值的一個或多個標準偏差內，或±30%、±20%、±10%、±5%內。再者，本文使用的“約”、“近似”或“實質上”可依光學性質、蝕刻性質或其它性質，來選擇較可接受的偏差範圍或標準偏差，而可不用一個標準偏差適用全部性質。 As used herein, "about," "approximately," or "substantially" includes the stated value and the average within an acceptable deviation from the particular value as determined by one of ordinary skill in the art, given the measurement in question and the A specified amount of measurement-related error (ie, a limitation of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, "about", "approximately" or "substantially" may be used to select a more acceptable range of deviation or standard deviation depending on optical properties, etching properties or other properties, and not one standard deviation may apply to all properties. .

除非另有定義，本文使用的所有術語(包括技術和科學術語)具有與本發明所屬領域的普通技術人員通常理解的相同的含義。將進一步理解的是，諸如在通常使用的字典中定義的那些術語應當被解釋為具有與它們在相關技術和本發明的上下文中的含義一致的含義，並且將不被解釋為理想化的或過度正式的意義，除非本文中明確地這樣定義。 Unless otherwise defined, all terms (including technical and scientific The term ) has the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed as having meanings consistent with their meanings in the context of the related art and the present invention, and are not to be construed as idealized or excessive Formal meaning, unless expressly defined as such herein.

圖2為本發明一實施例之畫素陣列基板100之佈局(layout)的俯視示意圖。圖2對應圖1的區域A1。 FIG. 2 is a schematic top view of a layout of a pixel array substrate 100 according to an embodiment of the present invention. FIG. 2 corresponds to the area A1 of FIG. 1 .

圖3為本發明一實施例之畫素陣列基板100之佈局(layout)的俯視示意圖。圖3對應圖1的區域A2。 FIG. 3 is a schematic top view of a layout of a pixel array substrate 100 according to an embodiment of the present invention. FIG. 3 corresponds to area A2 of FIG. 1 .

圖1省略圖2及圖3的第一共用電極CE1、第二共用電極CE2、共用線CL及轉接線VG。 FIG. 1 omits the first common electrode CE1 , the second common electrode CE2 , the common line CL, and the transition line VG of FIGS. 2 and 3 .

請參照圖1、圖2及圖3，畫素陣列基板100包括多個畫素PX。多個畫素PX排成多個畫素列R及多個畫素行C，其中每一畫素列R的多個畫素PX沿著第一方向x排列，每一畫素行C的多個畫素PX沿第二方向y排列，且第一方向x與第二方向y交錯。舉例而言，在本實施例中，第一方向x與第二方向y可垂直，但本發明不以此為限。 Please refer to FIG. 1 , FIG. 2 and FIG. 3 , the pixel array substrate 100 includes a plurality of pixels PX. A plurality of pixels PX are arranged into a plurality of pixel rows R and a plurality of pixel rows C, wherein the plurality of pixels PX of each pixel row R are arranged along the first direction x, and the plurality of pixels of each pixel row C are arranged. The pixels PX are arranged along the second direction y, and the first direction x and the second direction y are staggered. For example, in this embodiment, the first direction x and the second direction y may be perpendicular, but the invention is not limited to this.

請參照圖1及圖2，每一畫素PX包括第一畫素結構PX1及第二畫素結構PX2。第一畫素結構PX1包括第一主動元件T1(繪於圖2)及電性連接至第一主動元件T1的第一畫素電極PE1(繪於圖2)。請參照圖2，詳細而言，第一主動元件T1包括第一薄膜電晶體，第一薄膜電晶體具有一控制端T1c、一半導體圖案T1d及電性連接至半導體圖案T1d之不同兩區的第一端T1a和第二端T1b，其中第一畫素電極PE1電性連接至第一薄膜電晶體的第二端T1b。請參照圖1及圖2，第二畫素結構PX2包括第二主動元件T2及電性連接至第二主動元件T2的第二畫素電極PE2。請參照圖2，詳細而言，第二主動元件T2包括第二薄膜電晶體，第二薄膜電晶體具有一控制端T2c、一半導體圖案T2d及電性連接至半導體圖案T2d之不同兩區的第一端T2a與第二端T2b，其中第二畫素電極PE2電性連接至第二薄膜電晶體的第二端T2b。 Please refer to FIG. 1 and FIG. 2 , each pixel PX includes a first pixel structure PX1 and a second pixel structure PX2 . The first pixel structure PX1 includes a first active element T1 (as shown in FIG. 2 ) and a first pixel electrode PE1 (as shown in FIG. 2 ) electrically connected to the first active element T1 . Please refer to FIG. 2 , in detail, the first active element T1 includes a first film A transistor, the first thin film transistor has a control terminal T1c, a semiconductor pattern T1d, and a first terminal T1a and a second terminal T1b electrically connected to two different regions of the semiconductor pattern T1d, wherein the first pixel electrode PE1 is electrically connected to the second terminal T1b of the first thin film transistor. Referring to FIG. 1 and FIG. 2 , the second pixel structure PX2 includes a second active element T2 and a second pixel electrode PE2 electrically connected to the second active element T2 . Referring to FIG. 2 , in detail, the second active element T2 includes a second thin film transistor, and the second thin film transistor has a control terminal T2c, a semiconductor pattern T2d, and a second thin film transistor electrically connected to two different regions of the semiconductor pattern T2d. One end T2a and the second end T2b, wherein the second pixel electrode PE2 is electrically connected to the second end T2b of the second thin film transistor.

請參照圖1及圖2，每一畫素PX的第一畫素電極PE1與第二畫素電極PE2沿第二方向y依序排列。在本實施例中，第一畫素電極PE1的面積小於第二畫素電極PE2的面積，第一畫素結構PX1可為主畫素(main pixel)結構，而第二畫素結構PX2可為次畫素(sub pixel)結構。圖2及圖3以近似於矩形的兩圖案示意性地代表第一畫素電極PE1及第二畫素電極PE2。然而，本發明不限於此，本領域具有通常知識者可依實際需求設計第一畫素電極PE1及第二畫素電極PE2的圖案。舉例而言，於一實施例中，第一畫素電極PE1(或第二畫素電極PE2)可具有交叉設置的二主幹部以及與二主幹部連接的多組分支，所述二主幹部定義出四個象限，且多組分支可分別設置於所述四個象限。 Referring to FIG. 1 and FIG. 2 , the first pixel electrode PE1 and the second pixel electrode PE2 of each pixel PX are sequentially arranged along the second direction y. In this embodiment, the area of the first pixel electrode PE1 is smaller than that of the second pixel electrode PE2, the first pixel structure PX1 may be a main pixel structure, and the second pixel structure PX2 may be Sub pixel (sub pixel) structure. FIG. 2 and FIG. 3 schematically represent the first pixel electrode PE1 and the second pixel electrode PE2 with two patterns that are approximately rectangular. However, the present invention is not limited to this, and those skilled in the art can design the patterns of the first pixel electrode PE1 and the second pixel electrode PE2 according to actual needs. For example, in one embodiment, the first pixel electrode PE1 (or the second pixel electrode PE2 ) may have two trunks disposed intersectingly and multiple sets of branches connected to the two trunks, the two trunks define There are four quadrants, and multiple groups of branches can be respectively arranged in the four quadrants.

請參照圖2，在本實施例中，每一畫素PX的第一畫素結構PX1還可包括第一共用電極CE1，其中第一共用電極CE1與第一畫素電極PE1部分重疊，以形成第一畫素結構PX1的儲存電容；每一畫素PX的第二畫素結構PX2還可包括第二共用電極CE2，其中第二共用電極CE2與第二畫素電極PE2部分重疊，以形成第二畫素結構PX2的儲存電容。 Referring to FIG. 2, in this embodiment, the first pixel structure PX1 of each pixel PX may further include a first common electrode CE1, wherein the first common electrode CE1 and the first common electrode CE1 A pixel electrode PE1 partially overlaps to form the storage capacitor of the first pixel structure PX1; the second pixel structure PX2 of each pixel PX may further include a second common electrode CE2, wherein the second common electrode CE2 and the second pixel structure PX1 The pixel electrodes PE2 are partially overlapped to form the storage capacitor of the second pixel structure PX2.

請參照圖1、圖2及圖3，畫素陣列基板100包括在第一方向x上延伸的多條掃描線HG以及在第二方向y上延伸的多條資料線DL。同一畫素列R的多個畫素PX的多個第一主動元件T1及多個第二主動元件T2電性連接至同一條掃描線HG。每一畫素行C之多個畫素PX的多個第一主動元件T1及多個第二主動元件T2電性連接至相鄰兩資料線DL，其中每一畫素PX的第一主動元件T1及第二主動元件T2分別電性連接至相鄰兩資料線DL。總言之，每一畫素PX的第一主動元件T1與第二主動元件T2是共用同一條掃描線HG，並分別利用左右兩條不同的資料線DL分別加以驅動第一主動元件T1與第二主動元件T2；即，畫素陣列基板100可利用2D1G的方式驅動。 1 , 2 and 3 , the pixel array substrate 100 includes a plurality of scan lines HG extending in a first direction x and a plurality of data lines DL extending in a second direction y. The plurality of first active elements T1 and the plurality of second active elements T2 of the plurality of pixels PX in the same pixel row R are electrically connected to the same scan line HG. A plurality of first active elements T1 and a plurality of second active elements T2 of the plurality of pixels PX in each pixel row C are electrically connected to two adjacent data lines DL, wherein the first active element T1 of each pixel PX and the second active element T2 are respectively electrically connected to two adjacent data lines DL. In a word, the first active element T1 and the second active element T2 of each pixel PX share the same scan line HG, and use two different left and right data lines DL to drive the first active element T1 and the second active element T2 respectively. Two active elements T2; that is, the pixel array substrate 100 can be driven in a 2D1G manner.

請參照圖1及圖2，在本實施例中，為實現超窄邊框，畫素陣列基板100還可包括穿插在多個畫素行C之間的轉接線VG。轉接線VG在第二方向y上延伸，且電性連接至對應的掃描線HG。在畫素陣列基板100的俯視圖中，每一轉接線VG可位於相鄰兩畫素行C之間。在本實施例中，畫素陣列基板100還可包括在第二方向y上延伸的共用線CL。在畫素陣列基板100的俯視圖中，每一共用線CL位於相鄰的兩畫素行C之間。總言之，在本實施例中，多個畫素行C之間的面積可用以設置轉接線VG及共用線CL，但本發明不以此為限。 Referring to FIG. 1 and FIG. 2 , in this embodiment, in order to realize an ultra-narrow frame, the pixel array substrate 100 may further include a transition line VG interspersed between a plurality of pixel rows C. The transition line VG extends in the second direction y and is electrically connected to the corresponding scan line HG. In the top view of the pixel array substrate 100 , each wiring VG may be located between two adjacent pixel rows C. In this embodiment, the pixel array substrate 100 may further include a common line CL extending in the second direction y. In the top view of the pixel array substrate 100 , each common line CL is located between two adjacent pixel rows C. In summary, in this implementation In an example, the area between a plurality of pixel rows C can be used for setting the transition line VG and the common line CL, but the invention is not limited to this.

請參照圖1、圖2及圖3，多個畫素行C包括沿第一方向x依序排列的第n個畫素行Cn、第n+1個畫素行Cn+1、第n+2個畫素行Cn+2、第n+3畫素行Cn+3、第n+4個畫素行Cn+4及第n+5畫素行Cn+5，其中n為大於或等於1的正整數。 Referring to FIG. 1 , FIG. 2 and FIG. 3 , the plurality of pixel rows C include the n-th pixel row Cn, the n+1-th pixel row Cn+1, and the n+2-th pixel row Cn+1, which are sequentially arranged along the first direction x. The pixel row Cn+2, the n+3th pixel row Cn+3, the n+4th pixel row Cn+4, and the n+5th pixel row Cn+5, where n is a positive integer greater than or equal to 1.

多個畫素列R包括沿第二方向y依序排列的第m個畫素列Rm、第m+1個畫素列Rm+1、第m+2個畫素列Rm+2及第m+3個畫素列Rm+3，其中m為大於或等於1的正整數。 The plurality of pixel rows R include the m-th pixel row Rm, the m+1-th pixel row Rm+1, the m+2-th pixel row Rm+2, and the m-th pixel row Rm+2 sequentially arranged along the second direction y +3 pixel columns Rm+3, where m is a positive integer greater than or equal to 1.

多條資料線DL包括沿第一方向x依序排列的第一資料線DL1、第二資料線DL2、第三資料線DL3、第四資料線DL4、第五資料線DL5、第六資料線DL6、第七資料線DL7、第八資料線DL8、第九資料線DL9、第十資料線DL10、第十一資料線DL11及第十二資料線DL12。 The plurality of data lines DL include a first data line DL1, a second data line DL2, a third data line DL3, a fourth data line DL4, a fifth data line DL5, and a sixth data line DL6 arranged in sequence along the first direction x , the seventh data line DL7, the eighth data line DL8, the ninth data line DL9, the tenth data line DL10, the eleventh data line DL11 and the twelfth data line DL12.

每一畫素PX具有相對的第一側及第二側。在本實施例中，第一側例如是每一畫素PX的右邊，且第二側例如是每一畫素PX的左邊，但本發明不以此為限。 Each pixel PX has opposite first and second sides. In this embodiment, the first side is, for example, the right side of each pixel PX, and the second side is, for example, the left side of each pixel PX, but the invention is not limited thereto.

請參照圖1及圖2，第n個畫素行Cn及第m個畫素列Rm的一畫素PX的第一主動元件T1電性連接至位於畫素PX之第二側(例如：左邊)的第二資料線DL2，且第n個畫素行Cn及第m個畫素列Rm的畫素PX的第二主動元件T2電性連接至位於畫素PX之第一側(例如：右邊)的第一資料線DL1。 Please refer to FIG. 1 and FIG. 2 , the first active element T1 of a pixel PX of the nth pixel row Cn and the mth pixel row Rm is electrically connected to the second side (eg, the left side) of the pixel PX. the second data line DL2, and the second active element T2 of the pixel PX of the nth pixel row Cn and the mth pixel row Rm is electrically connected to the first side (for example: the right side) of the pixel PX. The first data line DL1.

第n個畫素行Cn及第m+1個畫素列Rm+1的一畫素PX的第一主動元件T1電性連接至位於畫素PX之第二側(例如：左邊)的第二資料線DL2，且第n個畫素行Cn及第m+1個畫素列Rm+1的畫素PX的第二主動元件T2電性連接至位於畫素PX之第一側(例如：右邊)的第一資料線DL1。 The first active element T1 of a pixel PX in the n-th pixel row Cn and the m+1-th pixel row Rm+1 is electrically connected to the second data on the second side (eg, left) of the pixel PX Line DL2, and the second active element T2 of the pixel PX of the nth pixel row Cn and the m+1th pixel row Rm+1 is electrically connected to the first side (eg, the right side) of the pixel PX. The first data line DL1.

第n個畫素行Cn及第m+2個畫素列Rm+2的一畫素PX的第一主動元件T1電性連接至位於畫素PX之第一側(例如：右邊)的第一資料線DL1，且第n個畫素行Cn及第m+2個畫素列Rm+2的畫素PX的第二主動元件T2電性連接至位於畫素PX之第二側(例如：左邊)的第二資料線DL2。 The first active element T1 of a pixel PX in the n-th pixel row Cn and the m+2-th pixel row Rm+2 is electrically connected to the first data on the first side (eg, the right side) of the pixel PX Line DL1, and the second active element T2 of the pixel PX of the nth pixel row Cn and the m+2th pixel row Rm+2 is electrically connected to the second active element T2 located on the second side (eg: left) of the pixel PX The second data line DL2.

第n個畫素行Cn及第m+3個畫素列Rm+3的一畫素PX的第一主動元件T1電性連接至位於畫素PX之第一側(例如：右邊)的第一資料線DL1，且第n個畫素行Cn及第m+3個畫素列Rm+3的畫素PX的第二主動元件T2電性連接至位於畫素PX之第二側(例如：左邊)的第二資料線DL2。 The first active element T1 of a pixel PX in the n-th pixel row Cn and the m+3-th pixel row Rm+3 is electrically connected to the first data on the first side (eg, the right side) of the pixel PX Line DL1, and the second active element T2 of the pixel PX of the nth pixel row Cn and the m+3th pixel row Rm+3 is electrically connected to the second active element T2 located on the second side (eg: left) of the pixel PX The second data line DL2.

第n+1個畫素行Cn+1及第m個畫素列Rm的一畫素PX的第一主動元件T1電性連接至位於畫素PX之第一側(例如：右邊)的第三資料線DL3，且第n+1個畫素行Cn+1及第m個畫素列Rm的畫素PX的第二主動元件T2電性連接至位於畫素PX之第二側(例如：左邊)的第四資料線DL4。 The first active element T1 of a pixel PX in the n+1 th pixel row Cn+1 and the m th pixel row Rm is electrically connected to the third data located on the first side (eg, the right side) of the pixel PX Line DL3, and the second active element T2 of the pixel PX of the n+1th pixel row Cn+1 and the mth pixel row Rm is electrically connected to the second active element T2 located on the second side (eg: left) of the pixel PX The fourth data line DL4.

第n+1個畫素行Cn+1及第m+1個畫素列Rm+1的一畫素PX的第一主動元件T1電性連接至位於畫素PX之第二側(例如：左邊)的第四資料線DL4，且第n+1個畫素行Cn+1及第m+1個畫素列Rm+1的畫素PX的第二主動元件T2電性連接至位於畫素PX之第一側的第三資料線DL3。 The first active element T1 of a pixel PX in the n+1 pixel row Cn+1 and the m+1 pixel row Rm+1 is electrically connected to the second side of the pixel PX (eg For example: the fourth data line DL4 on the left), and the second active element T2 of the pixel PX in the n+1 th pixel row Cn+1 and the m+1 th pixel row Rm+1 is electrically connected to the The third data line DL3 on the first side of the pixel PX.

第n+1個畫素行Cn+1及第m+2個畫素列Rm+2的一畫素PX的第一主動元件T1電性連接至位於畫素PX之第二側(例如：左邊)的第四資料線DL4，且第n+1個畫素行Cn+1及第m+2個畫素列Rm+2的畫素PX的第二主動元件T2電性連接至位於畫素PX之第一側(例如：右邊)的第三資料線DL3。 The first active element T1 of a pixel PX in the n+1 th pixel row Cn+1 and the m+2 th pixel row Rm+2 is electrically connected to the second side (eg, the left side) of the pixel PX. the fourth data line DL4, and the second active element T2 of the pixel PX of the n+1th pixel row Cn+1 and the m+2th pixel row Rm+2 is electrically connected to the The third data line DL3 on one side (eg, the right side).

第n+1個畫素行Cn+1及第m+3個畫素列Rm+3的一畫素PX的第一主動元件T1電性連接至位於畫素PX之第一側(例如：右邊)的第三資料線DL3，且第n+1個畫素行Cn+1及第m+3個畫素列Rm+3的畫素PX的第二主動元件T2電性連接至位於畫素PX之第二側(例如：左邊)的第四資料線DL4。 The first active element T1 of a pixel PX in the n+1 th pixel row Cn+1 and the m+3 th pixel row Rm+3 is electrically connected to the first side (eg, the right side) of the pixel PX. the third data line DL3, and the second active element T2 of the pixel PX of the n+1th pixel row Cn+1 and the m+3th pixel row Rm+3 is electrically connected to the second active element T2 of the pixel PX located at the The fourth data line DL4 on the two sides (eg, left).

第n+2個畫素行Cn+2及第m個畫素列Rm的一畫素PX的第一主動元件T1電性連接至位於畫素PX之第二側(例如：左邊)的第六資料線DL6，且第n+2個畫素行Cn+2及第m個畫素列Rm的畫素PX的第二主動元件T2電性連接至位於畫素PX之第一側(例如：右邊)的第五資料線DL5。 The first active element T1 of a pixel PX in the n+2th pixel row Cn+2 and the mth pixel row Rm is electrically connected to the sixth data on the second side (for example: the left side) of the pixel PX Line DL6, and the second active element T2 of the pixel PX in the n+2th pixel row Cn+2 and the mth pixel row Rm is electrically connected to the first side (for example: the right side) of the pixel PX The fifth data line DL5.

第n+2個畫素行Cn+2及第m+1個畫素列Rm+1的一畫素PX的第一主動元件T1電性連接至位於畫素PX之第二側(例如：左邊)的第六資料線DL6，且第n+2個畫素行Cn+2及第m+1個畫素列Rm+1的畫素PX的第二主動元件T2電性連接至位於畫素PX之第一側(例如：右邊)的第五資料線DL5。 The first active element T1 of a pixel PX in the n+2 th pixel row Cn+2 and the m+1 th pixel row Rm+1 is electrically connected to the second side (eg, the left side) of the pixel PX. the sixth data line DL6, and the second active element T2 of the pixel PX in the n+2 pixel row Cn+2 and the m+1 pixel row Rm+1 is electrically connected to the bit The fifth data line DL5 on the first side (eg, the right side) of the pixel PX.

第n+2個畫素行Cn+2及第m+2個畫素列Rm+2的一畫素PX的第一主動元件T1電性連接至位於畫素PX之第一側(例如：右邊)的第五資料線DL5，且第n+2個畫素行Cn+2及第m+2個畫素列Rm+2的畫素PX的第二主動元件T2電性連接至位於畫素PX之第二側(例如：左邊)的第六資料線DL6。 The first active element T1 of a pixel PX in the n+2 th pixel row Cn+2 and the m+2 th pixel row Rm+2 is electrically connected to the first side (eg, the right side) of the pixel PX. the fifth data line DL5, and the second active element T2 of the pixel PX in the n+2 pixel row Cn+2 and the m+2 pixel row Rm+2 is electrically connected to the The sixth data line DL6 on the two sides (eg, left).

第n+2個畫素行Cn+2及第m+3個畫素列Rm+3的一畫素PX的第一主動元件T1電性連接至位於畫素PX之第一側(例如：右邊)的第五資料線DL5，且第n+2個畫素行Cn+2及第m+3個畫素列Rm+3的畫素PX的第二主動元件T2電性連接至位於畫素PX之第二側(例如：左邊)的第六資料線DL6。 The first active element T1 of a pixel PX in the n+2 th pixel row Cn+2 and the m+3 th pixel row Rm+3 is electrically connected to the first side (eg, the right side) of the pixel PX. the fifth data line DL5, and the second active element T2 of the pixel PX in the n+2 pixel row Cn+2 and the m+3 pixel row Rm+3 is electrically connected to the The sixth data line DL6 on the two sides (eg, left).

請參照圖1及圖3，第n+3個畫素行Cn+3及第m個畫素列Rm的一畫素PX的第一主動元件T1電性連接至位於畫素PX之第二側(例如：左邊)的第八資料線DL8，且第n+3個畫素行Cn+3及第m個畫素列Rm的畫素PX的第二主動元件T2電性連接至位於畫素PX之第一側(例如：右邊)的第七資料線DL7。 Referring to FIG. 1 and FIG. 3 , the first active element T1 of a pixel PX in the n+3 pixel row Cn+3 and the mth pixel row Rm is electrically connected to the second side ( For example: the eighth data line DL8 on the left), and the second active element T2 of the pixel PX of the n+3 pixel row Cn+3 and the mth pixel row Rm is electrically connected to the second active element T2 of the pixel PX located at the The seventh data line DL7 on one side (eg, right side).

第n+3個畫素行Cn+3及第m+1個畫素列Rm+1的一畫素PX的第一主動元件T1電性連接至位於畫素PX之第一側(例如：右邊)的第七資料線DL7，且第n+3個畫素行Cn+3及第m+1個畫素列Rm+1的畫素PX的第二主動元件T2電性連接至位於畫素PX之第二側(例如：左邊)的第八資料線DL8。 The first active element T1 of a pixel PX in the n+3 pixel row Cn+3 and the m+1 pixel row Rm+1 is electrically connected to the first side (eg, the right side) of the pixel PX. the seventh data line DL7, and the second active element T2 of the pixel PX in the n+3 pixel row Cn+3 and the m+1 pixel row Rm+1 is electrically connected to the The eighth data line DL8 on the two sides (eg, left).

第n+3個畫素行Cn+3及第m+2個畫素列Rm+2的一畫素PX的第一主動元件T1電性連接至位於畫素PX之第一側(例如：右邊)的第七資料線DL7，且第n+3個畫素行Cn+3及第m+2個畫素列Rm+2的畫素PX的第二主動元件T2電性連接至位於畫素PX之第二側(例如：左邊)的第八資料線DL8。 One of the n+3 pixel row Cn+3 and the m+2 pixel row Rm+2 The first active element T1 of the pixel PX is electrically connected to the seventh data line DL7 located on the first side (eg, the right side) of the pixel PX, and the n+3th pixel row Cn+3 and the m+2th pixel row Cn+3 The second active element T2 of the pixel PX in the pixel row Rm+2 is electrically connected to the eighth data line DL8 located on the second side (eg, the left side) of the pixel PX.

第n+3個畫素行Cn+3及第m+3個畫素列Rm+3的一畫素PX的第一主動元件T1電性連接至位於畫素PX之第二側(例如：左邊)的第八資料線DL8，且第n+3個畫素行Cn+3及第m+3個畫素列Rm+3的畫素PX的第二主動元件T2電性連接至位於畫素PX之第一側(例如：右邊)的第七資料線DL7。 The first active element T1 of a pixel PX in the n+3 pixel row Cn+3 and the m+3 pixel row Rm+3 is electrically connected to the second side (eg, the left side) of the pixel PX. The eighth data line DL8, and the second active element T2 of the pixel PX in the n+3 pixel row Cn+3 and the m+3 pixel row Rm+3 is electrically connected to the The seventh data line DL7 on one side (eg, right side).

第n+4個畫素行Cn+4及第m個畫素列Rm的一畫素PX的第一主動元件T1電性連接至位於畫素PX之第一側(例如：右邊)的第九資料線DL9，且第n+4個畫素行Cn+4及第m個畫素列Rm的畫素PX的第二主動元件T2電性連接至位於畫素PX之第二側(例如：左邊)的第十資料線DL10。 The first active element T1 of a pixel PX in the n+4th pixel row Cn+4 and the mth pixel row Rm is electrically connected to the ninth data located on the first side (eg, the right side) of the pixel PX Line DL9, and the second active element T2 of the pixel PX of the n+4th pixel row Cn+4 and the mth pixel row Rm is electrically connected to the second active element T2 located on the second side (eg: left) of the pixel PX Tenth data line DL10.

第n+4個畫素行Cn+4及第m+1個畫素列Rm+1的一畫素PX的第一主動元件T1電性連接至位於畫素PX之第一側(例如：右邊)的第九資料線DL9，且第n+4個畫素行Cn+4及第m+1個畫素列Rm+1的畫素PX的第二主動元件T2電性連接至位於畫素PX之第二側(例如：左邊)的第十資料線DL10。 The first active element T1 of a pixel PX in the n+4th pixel row Cn+4 and the m+1th pixel row Rm+1 is electrically connected to the first side (eg, the right side) of the pixel PX. The ninth data line DL9, and the second active element T2 of the pixel PX in the n+4th pixel row Cn+4 and the m+1th pixel row Rm+1 is electrically connected to the The tenth data line DL10 on the second side (eg, left side).

第n+4個畫素行Cn+4及第m+2個畫素列Rm+2的一畫素PX的第一主動元件T1電性連接至位於畫素PX之第二側(例如：左邊)的第十資料線DL10，且第n+4個畫素行Cn+4及第m +2個畫素列Rm+2的畫素PX的第二主動元件T2電性連接至位於畫素PX之第一側(例如：右邊)的第九資料線DL9。 The first active element T1 of a pixel PX in the n+4th pixel row Cn+4 and the m+2th pixel row Rm+2 is electrically connected to the second side (eg, the left side) of the pixel PX. The tenth data line DL10 of , and the n+4th pixel row Cn+4 and the mth pixel row Cn+4 The second active elements T2 of the pixels PX in the +2 pixel rows Rm+2 are electrically connected to the ninth data line DL9 located on the first side (eg, the right side) of the pixels PX.

第n+4個畫素行Cn+4及第m+3個畫素列Rm+3的一畫素PX的第一主動元件T1電性連接至位於畫素PX之第二側(例如：左邊)的第十資料線DL10，且第n+4個畫素行Cn+4及第m+3個畫素列Rm+3的畫素PX的第二主動元件T2電性連接至位於畫素PX之第一側(例如：右邊)的第九資料線DL9。 The first active element T1 of a pixel PX in the n+4th pixel row Cn+4 and the m+3th pixel row Rm+3 is electrically connected to the second side (eg, the left side) of the pixel PX. The tenth data line DL10, and the second active element T2 of the pixel PX in the n+4th pixel row Cn+4 and the m+3th pixel row Rm+3 is electrically connected to the The ninth data line DL9 on one side (eg, right side).

第n+5個畫素行Cn+5及第m個畫素列Rm的一畫素PX的第一主動元件T1電性連接至位於畫素PX之第二側(例如：左邊)的第十二資料線DL12，且第n+5個畫素行Cn+5及第m個畫素列Rm的畫素PX的第二主動元件T2電性連接至位於畫素PX之第一側(例如：右邊)的第十一資料線DL11。 The first active element T1 of a pixel PX in the n+5th pixel row Cn+5 and the mth pixel row Rm is electrically connected to the twelfth side located on the second side (eg, left) of the pixel PX The data line DL12, and the second active element T2 of the pixel PX of the n+5th pixel row Cn+5 and the mth pixel row Rm is electrically connected to the first side (eg, the right side) of the pixel PX The eleventh data line DL11.

第n+5個畫素行Cn+5及第m+1個畫素列Rm+1的一畫素PX的第一主動元件T1電性連接至位於畫素PX之第一側(例如：右邊)的第十一資料線DL11，且第n+5個畫素行Cn+5及第m+1個畫素列Rm+1的畫素PX的第二主動元件T2電性連接至位於畫素PX之第二側(例如：左邊)的第十二資料線DL12。 The first active element T1 of a pixel PX in the n+5th pixel row Cn+5 and the m+1th pixel row Rm+1 is electrically connected to the first side (eg, the right side) of the pixel PX. The eleventh data line DL11, and the second active element T2 of the pixel PX of the n+5th pixel row Cn+5 and the m+1th pixel row Rm+1 is electrically connected to the pixel PX located between the The twelfth data line DL12 on the second side (eg, left side).

第n+5個畫素行Cn+5及第m+2個畫素列Rm+2的一畫素PX的第一主動元件T1電性連接至位於畫素PX之第一側(例如：右邊)的第十一資料線DL11，且第n+5個畫素行Cn+5及第m+2個畫素列Rm+2的畫素PX的第二主動元件T2電性連接至位於畫素PX之第二側(例如：左邊)的第十二資料線DL12。 The first active element T1 of a pixel PX in the n+5th pixel row Cn+5 and the m+2th pixel row Rm+2 is electrically connected to the first side (eg, the right side) of the pixel PX. The eleventh data line DL11, and the second active element T2 of the pixel PX of the n+5th pixel row Cn+5 and the m+2th pixel row Rm+2 is electrically connected to the pixel PX located between the The twelfth data line DL12 on the second side (eg, left side).

第n+5個畫素行Cn+5及第m+3個畫素列Rm+3的一畫素PX的第一主動元件T1電性連接至位於畫素PX之第二側(例如：左邊)的第十二資料線DL12，且第n+5個畫素行Cn+5及第m+3個畫素列Rm+3的畫素PX的第二主動元件T2電性連接至位於畫素PX之第一側(例如：右邊)的第十一資料線DL11。 The first active element T1 of a pixel PX in the n+5th pixel row Cn+5 and the m+3th pixel row Rm+3 is electrically connected to the second side (eg, the left side) of the pixel PX. The twelfth data line DL12, and the second active element T2 of the pixel PX of the n+5th pixel row Cn+5 and the m+3th pixel row Rm+3 is electrically connected to the pixel PX located between the The eleventh data line DL11 on the first side (eg, the right side).

圖1示出在同一圖框時間下，輸入至每一畫素PX之第一畫素結構PX1及第二畫素結構PX2之訊號的極性。請參照圖1，在同一圖框時間內，分別與多個畫素列Rn、Rm+1、Rm+2、Rm+3電性連接的多條掃描線HG1、HG2、HG3、HG4以一時間延遲依時序被輸入閘極開啟訊號。在同一圖框時間內，第一資料線DL1的資料訊號的極性、第二資料線DL2的資料訊號的極性、第三資料線DL3的資料訊號的極性、第四資料線DL4的資料訊號的極性、第五資料線DL5的資料訊號的極性、第六資料線DL6的資料訊號的極性、第七資料線DL7的資料訊號的極性、第八資料線DL8的資料訊號的極性、第九資料線DL9的資料訊號的極性、第十資料線DL10的資料訊號的極性、第十一資料線DL11的資料訊號的極性及第十二資料線DL12的資料訊號的極性分別為正、負、正、負、正、負、負、正、負、正、負及正。 1 shows the polarities of the signals input to the first pixel structure PX1 and the second pixel structure PX2 of each pixel PX at the same frame time. Referring to FIG. 1 , within the same frame time, a plurality of scan lines HG1 , HG2 , HG3 , and HG4 electrically connected to a plurality of pixel rows Rn, Rm+1, Rm+2, and Rm+3 are respectively connected for a period of time. The delay is input to the gate turn-on signal in sequence. During the same frame time, the polarity of the data signal of the first data line DL1, the polarity of the data signal of the second data line DL2, the polarity of the data signal of the third data line DL3, the polarity of the data signal of the fourth data line DL4 , the polarity of the data signal of the fifth data line DL5, the polarity of the data signal of the sixth data line DL6, the polarity of the data signal of the seventh data line DL7, the polarity of the data signal of the eighth data line DL8, the polarity of the data signal of the ninth data line DL9 The polarity of the data signal, the polarity of the data signal of the tenth data line DL10, the polarity of the data signal of the eleventh data line DL11 and the polarity of the data signal of the twelfth data line DL12 are respectively positive, negative, positive, negative, Positive, Negative, Negative, Positive, Negative, Positive, Negative, and Positive.

在上述之至少部分的畫素陣列基板100的佈局及其驅動下，於同一圖框時間內，具有相同極性之第一畫素結構PX1電性連接至位於第一側的資料線DL，具有相同極性之第二畫素結構PX2電性連接至位於第二側的資料線DL。亦即，於同一圖框時間內，具有相同極性之第一畫素結構PX1及第二畫素結構PX2不會都是電性連接至位於同一側的資料線DL。藉此，無論進階低色偏技術(Advanced Low color washout；ALCW)的功能是否開啟，閃爍(flick)的問題可獲得改善。 Under the above-mentioned layout and driving of at least part of the pixel array substrate 100, the first pixel structures PX1 with the same polarity are electrically connected to the data lines DL on the first side within the same frame time, and have the same polarity. The polar second pixel structure PX2 is electrically connected to the data line DL on the second side. That is, at the same frame time Inside, the first pixel structure PX1 and the second pixel structure PX2 with the same polarity are not both electrically connected to the data line DL on the same side. Thereby, the problem of flicker can be improved regardless of whether the advanced low color washout (ALCW) function is enabled or not.

請參照圖1，在本實施例中，ALCW的功能是指，除了每一畫素PX的主畫素結構及次畫素結構具有不同的電壓，以改善顯示裝置側視角偏白(color washout)問題外，多個畫素PX也有主畫素PXa(以具有點狀的圖案表示)與次畫素PXb(以具有空白的圖案表示)之分。舉例而言，在本實施例中，多個主畫素PXa及多個次畫素PXb是在第一方向x及第二方向y上以最小的間距交替排列，但本發明不以此為限。 Referring to FIG. 1 , in this embodiment, the function of ALCW means that the main pixel structure and the sub-pixel structure of each pixel PX have different voltages to improve the color washout of the display device. In addition to the problem, the plurality of pixels PX are also divided into a main pixel PXa (represented by a pattern with dots) and a sub-pixel PXb (represented by a pattern with blanks). For example, in this embodiment, the plurality of main pixels PXa and the plurality of sub-pixels PXb are alternately arranged in the first direction x and the second direction y with the smallest spacing, but the present invention is not limited to this .

請參照圖1，舉例而言，第n個畫素行Cn及第m個畫素列Rm的第二畫素結構PX2、第n個畫素行Cn及第m+1個畫素列Rm+1的第二畫素結構PX2、第n+1個畫素行Cn+1及第m個畫素列Rm的第一畫素結構PX1、第n+1個畫素行Cn+1及第m+1個畫素列Rm+1的第二畫素結構PX2、第n+2畫素行Cn+2及第m個畫素列Rm的第二畫素結構PX2、第n+2畫素行Cn+2及第m+1個畫素列Rm+1的第二畫素結構PX2、第n+3個畫素行Cn+1及第m個畫素列Rm的第一畫素結構PX1、第n+3個畫素行Cn+3及第m+1個畫素列Rm+1的第二畫素結構PX2、第n+4個畫素行Cn+4及第m個畫素列Rm的第二畫素結構PX2、第n+4個畫素行Cn+4及第m+1個畫素列Rm+1的第二畫素結構PX2、第n+5個畫素行Cn+5及第m個畫素列Rm的第一畫素結構PX1和第n+5個畫素行Cn+5及第m+1個畫素列Rm+1的第二畫素結構PX2具有相同的正極性，但第n個畫素行Cn及第m個畫素列Rm的第二畫素結構PX2、第n個畫素行Cn及第m+1個畫素列Rm+1的第二畫素結構PX2、第n+1個畫素行Cn+1及第m個畫素列Rm的第一畫素結構PX1、第n+1個畫素行Cn+1及第m+1個畫素列Rm+1的第二畫素結構PX2、第n+2畫素行Cn+2及第m個畫素列Rm的第二畫素結構PX2、第n+2畫素行Cn+2及第m+1個畫素列Rm+1的第二畫素結構PX2、第n+3個畫素行Cn+1及第m個畫素列Rm的第一畫素結構PX1、第n+3個畫素行Cn+3及第m+1個畫素列Rm+1的第二畫素結構PX2、第n+4個畫素行Cn+4及第m個畫素列Rm的第二畫素結構PX2、第n+4個畫素行Cn+4及第m+1個畫素列Rm+1的第二畫素結構PX2、第n+5個畫素行Cn+5及第m個畫素列Rm的第一畫素結構PX1和第n+5個畫素行Cn+5及第m+1個畫素列Rm+1的第二畫素結構PX2是分別電性連接位於其第一側、第一側、第一側、第一側、第一側、第一側、第二側、第二側、第二側、第二側、第二側及第二側的資料線DL。藉此，無論進階低色偏技術(Advanced Low color washout；ALCW)的功能是否開啟，閃爍(flick)的問題可獲得改善。 Referring to FIG. 1 , for example, the second pixel structure PX2 of the n-th pixel row Cn and the m-th pixel row Rm, the n-th pixel row Cn and the m+1-th pixel row Rm+1 The second pixel structure PX2, the n+1th pixel row Cn+1 and the first pixel structure PX1 of the mth pixel row Rm, the n+1th pixel row Cn+1 and the m+1th pixel row Cn+1 The second pixel structure PX2 of the pixel row Rm+1, the n+2th pixel row Cn+2 and the second pixel structure PX2 of the mth pixel row Rm, the n+2th pixel row Cn+2 and the mth pixel row Cn+2 The second pixel structure PX2 of +1 pixel row Rm+1, the n+3th pixel row Cn+1, and the first pixel structure PX1 of the mth pixel row Rm, and the n+3th pixel row The second pixel structure PX2 of Cn+3 and the m+1th pixel row Rm+1, the second pixel structure PX2 of the n+4th pixel row Cn+4 and the mth pixel row Rm, the The second pixel structure PX2 of the n+4 pixel rows Cn+4 and the m+1 pixel row Rm+1, the n+5th pixel structure The first pixel structure PX1 of the pixel row Cn+5 and the mth pixel row Rm and the second pixel structure PX2 of the n+5th pixel row Cn+5 and the m+1th pixel row Rm+1 have the same positive polarity, but the second pixel structure PX2 of the nth pixel row Cn and the mth pixel row Rm, the second pixel structure of the nth pixel row Cn and the m+1th pixel row Rm+1 The first pixel structure PX1, the n+1th pixel row Cn+1 and the m+1th pixel row of the pixel structure PX2, the n+1th pixel row Cn+1 and the mth pixel row Rm The second pixel structure PX2 of Rm+1, the second pixel structure PX2 of the n+2th pixel row Cn+2 and the mth pixel row Rm, the n+2th pixel row Cn+2 and the m+1th pixel row The second pixel structure PX2 of the pixel row Rm+1, the n+3 pixel row Cn+1 and the first pixel structure PX1 of the mth pixel row Rm, the n+3 pixel row Cn+ 3 and the second pixel structure PX2 of the m+1th pixel row Rm+1, the n+4th pixel row Cn+4 and the second pixel structure PX2 of the mth pixel row Rm, and the n+th pixel row Cn+4 The second pixel structure PX2 of the 4 pixel rows Cn+4 and the m+1 th pixel row Rm+1, the n+5 th pixel row Cn+5 and the first pixel of the m th pixel row Rm The structure PX1 and the second pixel structure PX2 of the n+5th pixel row Cn+5 and the m+1th pixel column Rm+1 are electrically connected to the first side, the first side, and the first side respectively. , the first side, the first side, the first side, the second side, the second side, the second side, the second side, the second side and the data line DL of the second side. Thereby, the problem of flicker can be improved regardless of whether the advanced low color washout (ALCW) function is enabled or not.

此外，與一畫素列R的多個畫素PX的多個第一畫素結構PX1共用多條資料線DL且位於前一畫素列R的多個畫素結構不會都是第一畫素結構PX1(即，主畫素結構)或都是第二畫素結構PX2(即，次畫素結構)或。因此，在進階低色偏技術(Advanced Low color washout；ALCW)的功能關閉的情況下，在同一畫素列R上不易出現暗線(或亮線)，進而使得暗線/亮線的問題獲得改善。 In addition, a plurality of first pixel structures PX1 of a plurality of pixels PX of a pixel row R share a plurality of data lines DL and are located in a plurality of pixel structures of a previous pixel row R Not all of the first pixel structure PX1 (ie, the primary pixel structure) or all of the second pixel structure PX2 (ie, the secondary pixel structure) or. Therefore, when the advanced low color washout (ALCW) function is turned off, dark lines (or bright lines) are less likely to appear on the same pixel row R, thereby improving the problem of dark lines/bright lines .

請參照圖1，舉例而言，與第m+1個畫素列Rm+1的多個畫素PX的多個第一畫素結構PX1共用多條資料線DL且位於前一畫素列R(即，第m個畫素列Rm)的多個畫素結構由右到左分別是第一畫素結構PX1、第二畫素結構PX2、第一畫素結構PX1、第二畫素結構PX2、第一畫素結構PX1及第二畫素結構PX2。因此，在進階低色偏技術(Advanced Low color washout；ALCW)的功能關閉的情況下，在第m+1個畫素列Rm+1上不易出現暗線(或亮線)。 Referring to FIG. 1 , for example, a plurality of first pixel structures PX1 of a plurality of pixels PX in the m+1 th pixel row Rm+1 share a plurality of data lines DL and are located in the previous pixel row R (That is, the pixel structures of the m-th pixel row Rm) are, from right to left, the first pixel structure PX1, the second pixel structure PX2, the first pixel structure PX1, and the second pixel structure PX2, respectively. , a first pixel structure PX1 and a second pixel structure PX2. Therefore, when the advanced low color washout (ALCW) function is disabled, dark lines (or bright lines) are less likely to appear on the m+1 th pixel row Rm+1.

100:畫素陣列基板 100: pixel array substrate

A1、A2:區域 A1, A2: Area

C:畫素行 C: pixel row

Cn:第n個畫素行 Cn: the nth pixel row

Cn+1:第n+1個畫素行 Cn+1: the n+1th pixel row

Cn+2:第n+2個畫素行 Cn+2: n+2 pixel row

Cn+3:第n+3畫素行 Cn+3: n+3 pixel row

Cn+4:第n+4個畫素行 Cn+4: the n+4th pixel row

Cn+5:第n+5畫素行 Cn+5: pixel row n+5

DL:資料線 DL: data line

DL1:第一資料線 DL1: The first data line

DL2:第二資料線 DL2: Second data line

DL3:第三資料線 DL3: The third data line

DL4:第四資料線 DL4: Fourth data line

DL5:第五資料線 DL5: Fifth Data Line

DL6:第六資料線 DL6: The sixth data line

DL7:第七資料線 DL7: Seventh Data Line

DL8:第八資料線 DL8: The eighth data line

DL9:第九資料線 DL9: ninth data line

DL10:第十資料線 DL10: Tenth Data Line

DL11:第十一資料線 DL11: The eleventh data line

DL12:第十二資料線 DL12: Twelfth Data Line

HG、HG1、HG2、HG3、HG4:掃描線 HG, HG1, HG2, HG3, HG4: scan lines

PX:畫素 PX: pixel

PXa:主畫素 PXa: Main Pixel

PXb:次畫素 PXb: Subpixel

PX1:第一畫素結構 PX1: First pixel structure

PX2:第二畫素結構 PX2: Second pixel structure

R:畫素列 R: pixel row

Rm:第m個畫素列 Rm: the mth pixel column

Rm+1:第m+1個畫素行 Rm+1: m+1 pixel row

Rm+2:第m+2個畫素行 Rm+2: m+2 pixel row

Rm+3:第m+3個畫素行 Rm+3: m+3 pixel row

x:第一方向 x: first direction

y:第二方向 y: the second direction

Claims

一種畫素陣列基板，包括：多個畫素，排成多個畫素列及多個畫素行，其中每一畫素列的多個畫素沿一第一方向排列，每一畫素行的多個畫素沿一第二方向排列，該第一方向與該第二方向交錯，且每一畫素包括：一第一畫素結構，包括一第一主動元件及電性連接至該第一主動元件的一第一畫素電極；以及一第二畫素結構，包括一第二主動元件及電性連接至該第二主動元件的一第二畫素電極，其中該第一畫素電極與該第二畫素電極沿該第二方向依序排列；多條掃描線，在該第一方向上延伸，其中同一畫素列的多個畫素的多個第一主動元件及多個第二主動元件電性連接至同一掃描線；以及多條資料線，在該第二方向上延伸，其中每一該畫素行之多個畫素的多個第一主動元件及多個第二主動元件電性連接至相鄰兩資料線，且每一該畫素行之該些畫素的每一者的該第一主動元件及該第二主動元件分別電性連接至該相鄰兩資料線；該些畫素行包括沿該第一方向依序排列的一第n個畫素行、一第n+1個畫素行及一第n+2個畫素行，其中n為大於或等於1的正整數；該些畫素列包括沿該第二方向依序排列的一第m個畫素列及一第m+1個畫素列，其中m為大於或等於1的正整數；該些資料線包括沿該第一方向依序排列的一第一資料線、一第二資料線、一第三資料線、一第四資料線、一第五資料線及一第六資料線；每一畫素具有相對的一第一側及一第二側；該第n個畫素行及該第m個畫素列的一畫素的該第一主動元件電性連接至位於該畫素之該第二側的該第二資料線，且該第n個畫素行及該第m個畫素列的該畫素的該第二主動元件電性連接至位於該畫素之該第一側的該第一資料線；該第n個畫素行及該第m＋1個畫素列的一畫素的該第一主動元件電性連接至位於該畫素之該第二側的該第二資料線，且該第n個畫素行及該第m＋1個畫素列的該畫素的該第二主動元件電性連接至位於該畫素之該第一側的該第一資料線；該第n＋1個畫素行及該第m個畫素列的一畫素的該第一主動元件電性連接至位於該畫素之該第一側的該第三資料線，且該第n＋1個畫素行及該第m個畫素列的該畫素的該第二主動元件電性連接至位於該畫素之該第二側的該第四資料線；該第n＋1個畫素行及該第m＋1個畫素列的一畫素的該第一主動元件電性連接至位於該畫素之該第二側的該第四資料線，且該第n＋1個畫素行及該第m＋1個畫素列的該畫素的該第二主動元件電性連接至位於該畫素之該第一側的該第三資料線；該第n＋2個畫素行及該第m個畫素列的一畫素的該第一主動元件電性連接至位於該畫素之該第二側的該第六資料線，且該第n＋2個畫素行及該第m個畫素列的該畫素的該第二主動元件電性連接至位於該畫素之該第一側的該第五資料線；該第n＋2個畫素行及該第m＋1個畫素列的一畫素的該第一主動元件電性連接至位於該畫素之該第二側的該第六資料線，且該第n＋2個畫素行及該第m＋1個畫素列的該畫素的該第二主動元件電性連接至位於該畫素之該第一側的該第五資料線；在同一圖框時間內，該第一資料線的一資料訊號的極性、該第二資料線的一資料訊號的極性、該第三資料線的一資料訊號的極性、該第四資料線的一資料訊號的極性、該第五資料線的一資料訊號的極性及該第六資料線的一資料訊號的極性分別為正、負、正、負、正及負。 A pixel array substrate, comprising: A plurality of pixels are arranged into a plurality of pixel rows and a plurality of pixel rows, wherein the plurality of pixels of each pixel row are arranged along a first direction, and the plurality of pixels of each pixel row are arranged along a second direction Arranged, the first direction and the second direction are staggered, and each pixel includes: a first pixel structure including a first active element and a first pixel electrode electrically connected to the first active element; and A second pixel structure includes a second active element and a second pixel electrode electrically connected to the second active element, wherein the first pixel electrode and the second pixel electrode are along the second direction arranged in order; a plurality of scan lines extending in the first direction, wherein a plurality of first active elements and a plurality of second active elements of a plurality of pixels in the same pixel row are electrically connected to the same scan line; and A plurality of data lines extending in the second direction, wherein a plurality of first active elements and a plurality of second active elements of a plurality of pixels in each pixel row are electrically connected to two adjacent data lines, and each The first active element and the second active element of each of the pixels of the pixel row are respectively electrically connected to the two adjacent data lines; The pixel rows include an n-th pixel row, an n+1-th pixel row, and an n+2-th pixel row arranged in sequence along the first direction, where n is a positive integer greater than or equal to 1; The pixel rows include an m-th pixel row and an m+1-th pixel row sequentially arranged along the second direction, wherein m is a positive integer greater than or equal to 1; The data lines include a first data line, a second data line, a third data line, a fourth data line, a fifth data line and a sixth data line arranged in sequence along the first direction; each pixel has a first side and a second side opposite; The first active element of a pixel of the nth pixel row and the mth pixel row is electrically connected to the second data line on the second side of the pixel, and the nth pixel the second active element of the pixel of the pixel row and the mth pixel row is electrically connected to the first data line located on the first side of the pixel; The first active element of a pixel of the nth pixel row and the m+1th pixel row is electrically connected to the second data line on the second side of the pixel, and the nth pixel the second active element of the pixel of the pixel row and the m+1th pixel row is electrically connected to the first data line located on the first side of the pixel; The first active element of a pixel of the n+1 th pixel row and the m th pixel row is electrically connected to the third data line located on the first side of the pixel, and the n+1 th pixel row the second active element of the pixel of the pixel row and the mth pixel row is electrically connected to the fourth data line located on the second side of the pixel; The first active element of a pixel of the n+1th pixel row and the m+1th pixel row is electrically connected to the fourth data line on the second side of the pixel, and the n+1th pixel row is electrically connected to the fourth data line on the second side of the pixel. the second active element of the pixel of the pixel row and the m+1th pixel row is electrically connected to the third data line located on the first side of the pixel; The first active element of a pixel of the n+2th pixel row and the mth pixel row is electrically connected to the sixth data line on the second side of the pixel, and the n+2th pixel the second active element of the pixel of the pixel row and the mth pixel row is electrically connected to the fifth data line located on the first side of the pixel; The first active element of a pixel of the n+2th pixel row and the m+1th pixel row is electrically connected to the sixth data line on the second side of the pixel, and the n+2th pixel the second active element of the pixel of the pixel row and the m+1th pixel row is electrically connected to the fifth data line located on the first side of the pixel; During the same frame time, the polarity of a data signal of the first data line, the polarity of a data signal of the second data line, the polarity of a data signal of the third data line, the polarity of a data signal of the third data line, the polarity of a data signal of the fourth data line The polarity of the data signal, the polarity of a data signal of the fifth data line and the polarity of a data signal of the sixth data line are respectively positive, negative, positive, negative, positive and negative.

如請求項1所述的畫素陣列基板，其中該些資料線更包括一第七資料線、一第八資料線、一第九資料線、一第十資料線、一第十一資料線及一第十二資料線，該第一資料線、該第二資料線、該第三資料線、該第四資料線、該第五資料線、該第六資料線、該第七資料線、該第八資料線、該第九資料線、該第十資料線、該第十一資料線及該第十二資料線沿該第一方向依序排列；該第n＋3個畫素行及該第m個畫素列的一畫素的該第一主動元件電性連接至位於該畫素之該第二側的該第八資料線，且該第n＋3個畫素行及該第m個畫素列的該畫素的該第二主動元件電性連接至位於該畫素之該第一側的該第七資料線；該第n＋3個畫素行及該第m＋1個畫素列的一畫素的該第一主動元件電性連接至位於該畫素之該第一側的該第七資料線，且該第n＋3個畫素行及該第m＋1個畫素列的該畫素的該第二主動元件電性連接至位於該畫素之該第二側的該第八資料線；該第n＋4個畫素行及該第m個畫素列的一畫素的該第一主動元件電性連接至位於該畫素之該第一側的該第九資料線，且該第n＋4個畫素行及該第m個畫素列的該畫素的該第二主動元件電性連接至位於該畫素之該第二側的該第十資料線；該第n＋4個畫素行及該第m＋1個畫素列的一畫素的該第一主動元件電性連接至位於該畫素之該第一側的該第九資料線，且該第n＋4個畫素行及該第m＋1個畫素列的該畫素的該第二主動元件電性連接至位於該畫素之該第二側的該第十資料線；該第n＋5個畫素行及該第m個畫素列的一畫素的該第一主動元件電性連接至位於該畫素之該第二側的該第十二資料線，且該第n＋5個畫素行及該第m個畫素列的該畫素的該第二主動元件電性連接至位於該畫素之該第一側的該第十一資料線；該第n＋5個畫素行及該第m＋1個畫素列的一畫素的該第一主動元件電性連接至位於該畫素之該第一側的該第十一資料線，且該第n＋5個畫素行及該第m＋1個畫素列的該畫素的該第二主動元件電性連接至位於該畫素之該第二側的該第十二資料線；在同一該圖框時間內，該第七資料線的一資料訊號的極性、該第八資料線的一資料訊號的極性、該第九資料線的一資料訊號的極性、該第十資料線的一資料訊號的極性、該第十一資料線的一資料訊號的極性及該第十二資料線的一資料訊號的極性分別為負、正、負、正、負及正。 The pixel array substrate of claim 1, wherein the data lines further comprise a seventh data line, an eighth data line, a ninth data line, a tenth data line, an eleventh data line and a twelfth data line, the first data line, the second data line, the third data line, the fourth data line, the fifth data line, the sixth data line, the seventh data line, the The eighth data line, the ninth data line, the tenth data line, the eleventh data line and the twelfth data line are arranged in sequence along the first direction; The first active element of a pixel in the n+3 th pixel row and the m th pixel row is electrically connected to the eighth data line on the second side of the pixel, and the n+3 th pixel row the second active element of the pixel of the pixel row and the mth pixel row is electrically connected to the seventh data line located on the first side of the pixel; The first active element of a pixel of the n+3th pixel row and the m+1th pixel row is electrically connected to the seventh data line on the first side of the pixel, and the n+3th pixel the second active element of the pixel of the pixel row and the m+1th pixel row is electrically connected to the eighth data line located on the second side of the pixel; The first active element of a pixel of the n+4th pixel row and the mth pixel row is electrically connected to the ninth data line on the first side of the pixel, and the n+4th pixel the second active element of the pixel of the pixel row and the m-th pixel row is electrically connected to the tenth data line located on the second side of the pixel; The first active element of a pixel in the n+4th pixel row and the m+1th pixel row is electrically connected to the ninth data line on the first side of the pixel, and the n+4th pixel the second active element of the pixel of the pixel row and the m+1th pixel row is electrically connected to the tenth data line located on the second side of the pixel; The first active element of a pixel in the n+5th pixel row and the mth pixel row is electrically connected to the twelfth data line on the second side of the pixel, and the n+5th pixel the second active element of the pixel of the pixel row and the mth pixel row is electrically connected to the eleventh data line located on the first side of the pixel; The first active element of a pixel of the n+5th pixel row and the m+1th pixel row is electrically connected to the eleventh data line on the first side of the pixel, and the n+5th pixel the second active element of the pixel in the pixel row and the m+1th pixel row is electrically connected to the twelfth data line on the second side of the pixel; During the same frame time, the polarity of a data signal of the seventh data line, the polarity of a data signal of the eighth data line, the polarity of a data signal of the ninth data line, the polarity of the tenth data line The polarity of a data signal, the polarity of a data signal of the eleventh data line and the polarity of a data signal of the twelfth data line are negative, positive, negative, positive, negative and positive, respectively.

如請求項2所述的畫素陣列基板，其中該第n個畫素行及該第m＋2個畫素列的一畫素的該第一主動元件電性連接至位於該畫素之該第一側的該第一資料線，且該第n個畫素行及該第m＋2個畫素列的該畫素的該第二主動元件電性連接至位於該畫素之該第二側的該第二資料線；該第n個畫素行及該第m＋3個畫素列的一畫素的該第一主動元件電性連接至位於該畫素之該第一側的該第一資料線，且該第n個畫素行及該第m＋3個畫素列的該畫素的該第二主動元件電性連接至位於該畫素之該第二側的該第二資料線；該第n＋1個畫素行及該第m＋2個畫素列的一畫素的該第一主動元件電性連接至位於該畫素之該第二側的該第四資料線，且該第n＋1個畫素行及該第m＋2個畫素列的該畫素的該第二主動元件電性連接至位於該畫素之該第一側的該第三資料線；該第n＋1個畫素行及該第m＋3個畫素列的一畫素的該第一主動元件電性連接至位於該畫素之該第一側的該第三資料線，且該第n＋1個畫素行及該第m＋3個畫素列的該畫素的該第二主動元件電性連接至位於該畫素之該第二側的該第四資料線；該第n＋2個畫素行及該第m＋2個畫素列的一畫素的該第一主動元件電性連接至位於該畫素之該第一側的該第五資料線，且該第n＋2個畫素行及該第m＋2個畫素列的該畫素的該第二主動元件電性連接至位於該畫素之該第二側的該第六資料線；該第n＋2個畫素行及該第m＋3個畫素列的一畫素的該第一主動元件電性連接至位於該畫素之該第一側的該第五資料線，且該第n＋2個畫素行及該第m＋3個畫素列的該畫素的該第二主動元件電性連接至位於該畫素之該第二側的該第六資料線。 The pixel array substrate of claim 2, wherein the first active element of a pixel of the nth pixel row and the m+2th pixel row is electrically connected to the first side of the pixel the first data line, and the second active element of the pixel of the nth pixel row and the m+2th pixel row is electrically connected to the second data on the second side of the pixel String; The first active element of a pixel of the nth pixel row and the m+3th pixel row is electrically connected to the first data line on the first side of the pixel, and the nth pixel the second active element of the pixel of the pixel row and the m+3th pixel row is electrically connected to the second data line located on the second side of the pixel; The first active element of a pixel of the n+1th pixel row and the m+2th pixel row is electrically connected to the fourth data line located on the second side of the pixel, and the n+1th pixel the second active element of the pixel of the pixel row and the m+2th pixel row is electrically connected to the third data line located on the first side of the pixel; The first active element of a pixel in the n+1th pixel row and the m+3th pixel row is electrically connected to the third data line on the first side of the pixel, and the n+1th pixel the second active element of the pixel of the pixel row and the m+3th pixel row is electrically connected to the fourth data line located on the second side of the pixel; The first active element of a pixel of the n+2th pixel row and the m+2th pixel row is electrically connected to the fifth data line on the first side of the pixel, and the n+2th pixel the second active element of the pixel of the pixel row and the m+2th pixel row is electrically connected to the sixth data line located on the second side of the pixel; The first active element of a pixel of the n+2th pixel row and the m+3th pixel row is electrically connected to the fifth data line located on the first side of the pixel, and the n+2th pixel The second active element of the pixel of the pixel row and the m+3th pixel row is electrically connected to the sixth data line located on the second side of the pixel.

如請求項3所述的畫素陣列基板，其中該第n＋3個畫素行及該第m＋2個畫素列的一畫素的該第一主動元件電性連接至位於該畫素之該第一側的該第七資料線，且該第n＋3個畫素行及該第m＋2個畫素列的該畫素的該第二主動元件電性連接至位於該畫素之該第二側的該第八資料線；該第n＋3個畫素行及該第m＋3個畫素列的一畫素的該第一主動元件電性連接至位於該畫素之該第二側的該第八資料線，且該第n＋3個畫素行及該第m＋3個畫素列的該畫素的該第二主動元件電性連接至位於該畫素之該第一側的該第七資料線；該第n＋4個畫素行及該第m＋2個畫素列的一畫素的該第一主動元件電性連接至位於該畫素之該第二側的該第十資料線，且該第n＋4個畫素行及該第m＋2個畫素列的該畫素的該第二主動元件電性連接至位於該畫素之該第一側的該第九資料線；該第n＋4個畫素行及該第m＋3個畫素列的一畫素的該第一主動元件電性連接至位於該畫素之該第二側的該第十資料線，且該第n＋4個畫素行及該第m＋3個畫素列的該畫素的該第二主動元件電性連接至位於該畫素之該第一側的該第九資料線；該第n＋5個畫素行及該第m＋2個畫素列的一畫素的該第一主動元件電性連接至位於該畫素之該第一側的該第十一資料線，且該第n＋5個畫素行及該第m＋2個畫素列的該畫素的該第二主動元件電性連接至位於該畫素之該第二側的該第十二資料線；該第n＋5個畫素行及該第m＋3個畫素列的一畫素的該第一主動元件電性連接至位於該畫素之該第二側的該第十二資料線，且該第n＋5個畫素行及該第m＋3個畫素列的該畫素的該第二主動元件電性連接至位於該畫素之該第一側的該第十一資料線。 The pixel array substrate of claim 3, wherein the first active element of a pixel in the n+3 th pixel row and the m+2 th pixel row is electrically connected to the first side of the pixel the seventh data line, and the second active element of the pixel in the n+3th pixel row and the m+2th pixel row is electrically connected to the eighth data line on the second side of the pixel String; The first active element of a pixel of the n+3th pixel row and the m+3th pixel row is electrically connected to the eighth data line on the second side of the pixel, and the n+3th pixel the second active element of the pixel of the pixel row and the m+3th pixel row is electrically connected to the seventh data line located on the first side of the pixel; The first active element of a pixel of the n+4th pixel row and the m+2th pixel row is electrically connected to the tenth data line on the second side of the pixel, and the n+4th pixel the second active element of the pixel of the pixel row and the m+2th pixel row is electrically connected to the ninth data line located on the first side of the pixel; The first active element of a pixel of the n+4th pixel row and the m+3th pixel row is electrically connected to the tenth data line on the second side of the pixel, and the n+4th pixel the second active element of the pixel of the pixel row and the m+3th pixel row is electrically connected to the ninth data line located on the first side of the pixel; The first active element of a pixel of the n+5th pixel row and the m+2th pixel row is electrically connected to the eleventh data line located on the first side of the pixel, and the n+5th pixel the second active element of the pixel in the pixel row and the m+2th pixel row is electrically connected to the twelfth data line on the second side of the pixel; The first active element of a pixel of the n+5th pixel row and the m+3th pixel row is electrically connected to the twelfth data line on the second side of the pixel, and the n+5th pixel The second active element of the pixel of the pixel row and the m+3th pixel row is electrically connected to the eleventh data line located on the first side of the pixel.

如請求項1所述的畫素陣列基板，更包括：一轉接線，在該第二方向上延伸，且電性連接至一掃描線，其中在該畫素陣列基板的俯視圖中，該轉接線位於相鄰的兩畫素行之間。 The pixel array substrate according to claim 1, further comprising: A patch cord extends in the second direction and is electrically connected to a scan line, wherein in a plan view of the pixel array substrate, the patch cord is located between two adjacent pixel rows.

如請求項1所述的畫素陣列基板，更包括：一共用線，在該第二方向上延伸，其中在該畫素陣列基板的俯視圖中，該共用線位於相鄰的兩畫素行之間。 The pixel array substrate according to claim 1, further comprising: A common line extends in the second direction, wherein in the top view of the pixel array substrate, the common line is located between two adjacent pixel rows.