TWI755679B - Capacitor structure and method of fabricating the same - Google Patents

Capacitor structure and method of fabricating the same Download PDF

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TWI755679B
TWI755679B TW109102061A TW109102061A TWI755679B TW I755679 B TWI755679 B TW I755679B TW 109102061 A TW109102061 A TW 109102061A TW 109102061 A TW109102061 A TW 109102061A TW I755679 B TWI755679 B TW I755679B
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electrode plate
layer
dielectric layer
lower electrode
capacitor
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TW109102061A
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TW202129983A (en
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李世平
黃彬傑
林欣怡
黃國芳
王長岳
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力晶積成電子製造股份有限公司
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Priority to CN202010080562.7A priority patent/CN113224038A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A capacitor structure including a bottom electrode plate on a substrate, wherein the bottom electrode plate is provided with multiple recesses. A capacitor dielectric layer on the bottom electrode plate and the recesses, and a top electrode plate on the capacitor dielectric layer, wherein the edges of capacitor dielectric layer and top electrode plate are provided with vertically extending portions extending in a direction perpendicular to the top surface of bottom electrode plate.

Description

電容結構以及其製作方法 Capacitor structure and method of making the same

本發明大體上與一種電容結構有關，更具體言之，其係關於一種金屬-絕緣體-金屬(Metal-Insulator-Metal,MIM)電容結構，具有多個凹槽與邊緣的垂直延伸部位來增加其電容值。 The present invention generally relates to a capacitor structure, and more particularly, it relates to a metal-insulator-metal (MIM) capacitor structure having a plurality of vertically extending portions of grooves and edges to increase its capacitance value.

目前，半導體元件中的電容器按照結構大致可以分為多晶矽-絕緣體-多晶矽(Poly-Insulator-Poly,PIP)電容器、金屬-氧化層-矽基底(Metal-Oxide-Silicon,MOS)結構、以及金屬-絕緣體-金屬(Metal-Insulator-Metal,MIM)電容器。在實際應用中，可以根據半導體元件的特性選擇性地使用這些電容器。例如在高頻半導體元件中可以選用MIM電容器。 At present, capacitors in semiconductor devices can be roughly divided into polysilicon-insulator-polysilicon (Poly-Insulator-Poly, PIP) capacitors, metal-oxide layer-silicon substrate (Metal-Oxide-Silicon, MOS) structure according to the structure, and metal- Insulator-Metal (Metal-Insulator-Metal, MIM) capacitors. In practical applications, these capacitors can be selectively used according to the characteristics of the semiconductor element. For example, MIM capacitors can be used in high-frequency semiconductor components.

近年來，隨著無線通訊技術的快速發展，業界強烈希望將可適用於系統晶片(SoC)、具有高性能解耦與濾波功能的電容器植入到積體電路的金屬互連後段製程中，以獲得功能強勁的射頻系統。要達到這樣的設計所植入的電容必須具有高電容密度、理想的電壓線性值、精確的電容值控制以及高可靠性等特性。傳統的PIP電容或MOS電容因為具有很大的電壓線性值、較大的寄生電阻和電容損耗等缺點，其無法滿足千兆赫頻率下的應用。因此，採用MIM電容將是射頻和類比/混合信號積體電路發展的必然選擇。由於MIM採用金屬電極，其可有效降低了寄生電容以及電極的接觸電阻，大大提高了元件的性能。 In recent years, with the rapid development of wireless communication technology, the industry strongly hopes to implant capacitors suitable for system-on-chip (SoC) with high-performance decoupling and filtering functions into the back-end process of metal interconnection of integrated circuits. Get a powerful RF system. To achieve such a design, the implanted capacitor must have high capacitance density, ideal voltage linearity, precise capacitance control, and high reliability. Traditional PIP capacitors or MOS capacitors cannot meet applications at gigahertz frequencies due to their large voltage linearity value, large parasitic resistance, and capacitance loss. Therefore, the use of MIM capacitors will be an inevitable choice for the development of RF and analog/mixed-signal integrated circuits. Since the MIM uses metal electrodes, it can effectively reduce the parasitic capacitance and the contact resistance of the electrodes, and greatly improve the performance of the element.

然而，隨著射頻技術的發展，對於MIM電容的電容密度的要求將越來越高，同時還要保持很小的電壓線性值和良好的絕緣性能。因此，如何達到MIM電容在這方面的需求將是未來無線通訊技術革新是否成功的關鍵因素之一。 However, with the development of radio frequency technology, the requirements for the capacitance density of MIM capacitors will become higher and higher, while maintaining a small voltage linearity value and good insulation performance. Therefore, how to meet the needs of MIM capacitors in this regard will be one of the key factors for the success of future wireless communication technology innovations.

針對前述現有MIM電容需要提高其電容密度並提供良好絕緣性能的需求，本發明特此提出了一種新穎的電容結構，其利用蝕刻製程固有的微負載效應(micro loading effect)來形成特製凹槽，並可透過額外的回拉製程增加凹槽的表面積，進而增加電容結構整體的電容值。此外，額外的製程處理使得所形成的MIM電容具有良好的絕緣特性。 In response to the above-mentioned requirements of increasing the capacitance density and providing good insulation performance of the existing MIM capacitors, the present invention hereby proposes a novel capacitor structure, which utilizes the inherent micro loading effect of the etching process to form a special groove, and The surface area of the groove can be increased through an additional pull-back process, thereby increasing the overall capacitance of the capacitor structure. In addition, the additional process treatment enables the formed MIM capacitor to have good insulating properties.

本發明的面向之一在於提出一種電容結構，包含一基底、一下電極板，位於該基底上，其中該下電極板上具有複數個凹槽、一電容介電層，位於該下電極板上與該些凹槽上、以及一上電極板，位於該電容介電層上，其中該電容介電層與該上電極板的邊緣具有往與該下電極板的頂面垂直的方向延伸的垂直延伸部位。 One aspect of the present invention is to provide a capacitor structure comprising a substrate and a lower electrode plate on the substrate, wherein the lower electrode plate has a plurality of grooves and a capacitor dielectric layer on the lower electrode plate and The grooves and an upper electrode plate are located on the capacitor dielectric layer, wherein the capacitor dielectric layer and the edge of the upper electrode plate have vertical extensions extending in a direction perpendicular to the top surface of the lower electrode plate part.

本發明的另一面向在於提出一種電容結構的製作方法，包含在一基底上形成一下電極材料層、進行一第一光刻製程圖案化該下電極材料層以形成一下電極板，其中該第一光刻製程同時在該下電極板上形成多個凹槽、在該下電極板上形成氧化層、進行一第二光刻製程移除部分的該氧化層以形成含括該些凹槽的一電容凹槽，該電容凹槽裸露出該些凹槽、在該電容凹槽與該氧化層的表面依序形成一電容介電層與一上電極板、以及移除位於該氧化層的頂面上的該電容介電層與該上電極板，使得該電容介電層與該上電極板的邊緣具有位於該氧化層的側壁上的垂直延伸部位。 Another aspect of the present invention is to provide a method for fabricating a capacitor structure, comprising forming a lower electrode material layer on a substrate, performing a first photolithography process to pattern the lower electrode material layer to form a lower electrode plate, wherein the first The photolithography process simultaneously forms a plurality of grooves on the lower electrode plate, forms an oxide layer on the lower electrode plate, and performs a second photolithography process to remove a portion of the oxide layer to form a groove including the grooves Capacitor grooves, the capacitor grooves expose the grooves, a capacitor dielectric layer and an upper electrode plate are sequentially formed on the surfaces of the capacitor grooves and the oxide layer, and the top surface of the oxide layer is removed the capacitor dielectric layer and the upper electrode plate on the upper electrode plate, so that the edges of the capacitor dielectric layer and the upper electrode plate have vertical extension parts located on the sidewall of the oxide layer.

本發明的這類目的與其他目的在閱者讀過下文中以多種圖示與繪圖來描述的較佳實施例之細節說明後應可變得更為明瞭顯見。 These and other objects of the present invention should become more apparent to the reader after reading the following detailed description of the preferred embodiment described in the various figures and drawings.

100:基底/介電層 100: Substrate/Dielectric Layer

102:下電極材料層 102: Lower electrode material layer

104:氮化鈦層 104: Titanium nitride layer

106:鋁層 106: Aluminum layer

108:氮化鈦層 108: Titanium nitride layer

110:光阻 110: Photoresist

112:下電極板 112: Lower electrode plate

114a,114b:凹槽 114a, 114b: grooves

116:介電層 116: Dielectric layer

118:光阻 118: Photoresist

120:電容凹槽 120: Capacitor groove

122:電容介電層 122: Capacitive dielectric layer

122a:垂直延伸部位 122a: Vertical extension

124:上電極板 124: Upper electrode plate

124a:垂直延伸部位 124a: Vertical extension

124b:氧化部位 124b: Oxidation site

126:有機平坦層 126: organic flat layer

128:介電層 128: Dielectric layer

130:接觸件 130: Contacts

132:金屬層 132: metal layer

134:下電極層 134: lower electrode layer

134a:垂直延伸部位 134a: Vertical extension

134b:氧化部位 134b: Oxidation site

136:側壁 136: Sidewall

本說明書含有附圖併於文中構成了本說明書之一部分，俾使閱者對本發明實施例有進一步的瞭解。該些圖示係描繪了本發明一些實施例並連同本文描述一起說明了其原理。在該些圖示中：第1圖至第8圖為根據本發明較佳實施例中一電容結構的製作流程的截面示意圖；第9圖與第10圖為根據本發明另一實施例中一電容結構與其製作步驟的截面示意圖；第11圖為根據本發明又一實施例中一電容結構的製作步驟的截面示意圖；第12圖為根據本發明又另一實施例中一電容結構的製作步驟的截面示意圖；以及第13圖與第14圖為根據本發明又另一實施例中一電容結構的放大示意圖。 This specification contains accompanying drawings, which constitute a part of this specification, so as to enable readers to have a further understanding of the embodiments of the present invention. The drawings depict some embodiments of the invention and together with the description herein explain the principles thereof. Among these figures: Figures 1 to 8 are schematic cross-sectional views of a manufacturing process of a capacitor structure according to a preferred embodiment of the present invention; Figures 9 and 10 are a schematic diagram of a capacitor structure according to another embodiment of the present invention A schematic cross-sectional view of a capacitor structure and its fabrication steps; FIG. 11 is a cross-sectional schematic view of a fabrication step of a capacitor structure according to yet another embodiment of the present invention; FIG. 12 is a fabrication step of a capacitor structure according to yet another embodiment of the present invention ; and FIG. 13 and FIG. 14 are enlarged schematic views of a capacitor structure according to yet another embodiment of the present invention.

須注意本說明書中的所有圖示皆為圖例性質，為了清楚與方便圖示說明之故，圖示中的各部件在尺寸與比例上可能會被誇大或縮小地呈現，一般而言，圖中相同的參考符號會用來標示修改後或不同實施例中對應或類似的元件特徵。 It should be noted that all the illustrations in this specification are of the nature of illustrations. For the sake of clarity and convenience of illustration, the sizes and proportions of the components in the illustrations may be exaggerated or reduced. The same reference characters will be used to designate corresponding or similar element features in modified or different embodiments.

現在下文將詳細說明本發明的示例性實施例，其會參照附圖示出所描述之特徵以便閱者理解並實現技術效果。閱者將可理解文中之描述僅透過例 示之方式來進行，而非意欲要限制本案。本案的各種實施例和實施例中彼此不衝突的各種特徵可以以各種方式來加以組合或重新設置。在不脫離本發明的精神與範疇的情況下，對本案的修改、等同物或改進對於本領域技術人員來說是可以理解的，並且旨在包含在本案的範圍內。 Exemplary embodiments of the present invention will now be described in detail below, which will illustrate the described features with reference to the accompanying drawings to facilitate the reader's understanding and to achieve technical effects. The reader will understand that the description in the text is only by way of example to proceed in the manner indicated, and is not intended to limit the case. The various embodiments of the present invention and various features of the embodiments that do not conflict with each other may be combined or rearranged in various ways. Modifications, equivalents or improvements to the present invention will be understood by those skilled in the art without departing from the spirit and scope of the present invention, and are intended to be included within the scope of the present invention.

閱者應能容易理解，本案中的「在…上」、「在…之上」和「在…上方」的含義應當以廣義的方式被解讀，以使得「在…上」不僅表示「直接在」某物「上」而且還包括在某物「上」且其間有居間特徵或層的含義，並且「在…之上」或「在…上方」不僅表示「在」某物「之上」或「上方」的含義，而且還可以包括其「在」某物「之上」或「上方」且其間沒有居間特徵或層(即，直接在某物上)的含義。 Readers should be able to easily understand that the meanings of "on", "on" and "above" in this case should be interpreted in a broad sense, so that "on" not only means "directly on" "on" something but also includes the meaning of "on" something with intervening features or layers, and "on" or "over" means not only "on" something "on" or The meaning of "above", but can also include its meaning "on" or "over" something without intervening features or layers (ie, directly on something).

此外，諸如「在…之下」、「在…下方」、「下部」、「在…之上」、「上部」等空間相關術語在本文中為了描述方便可以用於描述一個元件或特徵與另一個或多個元件或特徵的關係，如在附圖中示出的。 Furthermore, spatially relative terms such as "below", "below", "lower", "above", "upper" and the like may be used herein for descriptive convenience to describe one element or feature with another The relationship of one or more elements or features as illustrated in the accompanying drawings.

如本文中使用的，術語「基底」是指向其上增加後續材料的材料。可以對基底自身進行圖案化。增加在基底的頂部上的材料可以被圖案化或可以保持不被圖案化。此外，基底可以包括廣泛的半導體材料，例如矽、鍺、砷化鎵、磷化銦等。或者，基底可以由諸如玻璃、塑膠或藍寶石晶圓的非導電材料製成。 As used herein, the term "substrate" refers to a material upon which subsequent materials are added. The substrate itself can be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Additionally, the substrate may comprise a wide variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic or sapphire wafer.

如本文中使用的，術語「層」是指包括具有厚度的區域的材料部分。層可以在下方或上方結構的整體之上延伸，或者可以具有小於下方或上方結構範圍的範圍。此外，層可以是厚度小於連續結構的厚度的均質或非均質連續結構的區域。例如，層可以位於在連續結構的頂表面和底表面之間或在頂表面和底表面處的任何水平面對之間。層可以水準、豎直和/或沿傾斜表面延伸。基底可以是層，其中可以包括一個或多個層，和/或可以在其上、其上方和/或其下方 具有一個或多個層。層可以包括多個層。例如，互連層可以包括一個或多個導體和接觸層(其中形成觸點、互連線和/或通孔)和一個或多個介電層。 As used herein, the term "layer" refers to a portion of a material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any horizontal faces at the top and bottom surfaces. Layers can extend horizontally, vertically and/or along inclined surfaces. The substrate may be a layer, may include one or more layers, and/or may be on, over and/or under have one or more layers. Layers may include multiple layers. For example, the interconnect layer may include one or more conductor and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

現在下文的實施例將依序根據第1圖至第8圖的截面結構來說明本發明電容結構的製作流程。須注意，本發明所提出的結構與方法雖然是以金屬-絕緣體-金屬(Metal-Insulator-Metal,MIM)電容器為主，然而本領域的技術人士應能理解其所揭露之內容在不違反邏輯性、方法性以及結構性的前提下也能合理地應用到其他組成相似的電容器類別中。 Now, the following embodiments will sequentially illustrate the fabrication process of the capacitor structure of the present invention according to the cross-sectional structures shown in FIG. 1 to FIG. 8 . It should be noted that although the structure and method proposed in the present invention are mainly metal-insulator-metal (MIM) capacitors, those skilled in the art should understand that the disclosed content does not violate the logic It can also be reasonably applied to other capacitor categories with similar composition under the premise of nature, method and structure.

首先請參照第1圖。本發明的電容結構可以建構在一半導體基底上，如一P型矽基底，其上可能形成有淺溝渠隔離結構(STI)並界定出主動區域，而主動區域上可進一步形成有各種主動元件與被動元件，如場效電晶體、二極體、記憶體等元件。由於本發明的電容結構較佳為在後段製程(BEOL)中形成，這類前段製程(FEOL)中的結構與元件並非本發明之重點且與本發明特徵沒有關係，為了圖示與說明書的簡明之故，圖中將省略這些元件，僅以一形成在該半導體基底上的介電層100來代表基底，如一金屬間介電層(IMD)。在本發明實施例中，介電層100的材料較佳為低介電常數材料(k<3.0)或是氧化矽，其可以旋轉塗佈或是化學氣相沉積等製程方式形成在基底上。 Please refer to Figure 1 first. The capacitor structure of the present invention can be constructed on a semiconductor substrate, such as a P-type silicon substrate, on which a shallow trench isolation structure (STI) may be formed to define an active area, and various active elements and passive components may be further formed on the active area. Components, such as field effect transistors, diodes, memories and other components. Since the capacitor structure of the present invention is preferably formed in the back end of the process (BEOL), the structures and components in the front end of the process (FEOL) are not the focus of the present invention and have nothing to do with the features of the present invention, for the sake of simplicity of illustration and description For this reason, these elements are omitted from the drawings, and only a dielectric layer 100 formed on the semiconductor substrate is used to represent the substrate, such as an intermetal dielectric (IMD). In the embodiment of the present invention, the material of the dielectric layer 100 is preferably a low dielectric constant material (k<3.0) or silicon oxide, which can be formed on the substrate by processes such as spin coating or chemical vapor deposition.

復參照第1圖。在介電層100上形成電容結構的下電極材料層102。在本發明實施例中，下電極材料層102可為三層的複層結構，其可能包含下氮化鈦層104-鋁層106-上氮化鈦層108，其中上下兩氮化鈦層104,108的厚度會遠小於中間的鋁層106。複層態樣的下電極材料層102有助於降低電容的串聯電阻並改進其品質因子。在其他實施例中，該鋁層也可能是銅鋁合金層，該氮化鈦層也可能是鈦、鉭或是氮化鉭。在一些實施例中，下電極材料層102可為後段製程中的其中一金屬層，較佳為頂金屬層之前的金屬層，其可以物理氣相沉積製程(PVD)或是各種化學氣相沉積(CVD)製程形成在介電層100上。 Refer back to Figure 1. The lower electrode material layer 102 of the capacitor structure is formed on the dielectric layer 100 . In the embodiment of the present invention, the lower electrode material layer 102 may be a three-layer composite structure, which may include a lower titanium nitride layer 104 - an aluminum layer 106 - an upper titanium nitride layer 108 , wherein the upper and lower titanium nitride layers 104 and 108 will be much smaller than the middle aluminum layer 106 . The lower electrode material layer 102 in the multi-layer configuration helps to reduce the series resistance of the capacitor and improve its quality factor. In other embodiments, the aluminum layer may also be a copper-aluminum alloy layer, and the titanium nitride layer may also be titanium, tantalum or tantalum nitride. In some embodiments, the lower electrode material layer 102 can be one of the metal layers in the back-end process, preferably the metal layer before the top metal layer, which can be physical vapor deposition (PVD) or various chemical vapor deposition processes (CVD) process is formed on the dielectric layer 100 .

接下來請參照第2圖。在下電極材料層102形成後，接著進行光刻製程在下電極材料層102上形成圖案化的光阻110，並以該光阻110為蝕刻遮罩進行乾蝕刻圖案化下電極材料層102，以形成下電極板112，並同時在其上形成多個凹槽114a。須注意在本發明實施例中，下電極板112上的凹槽114a的寬度會明顯小於下電極板112周圍的凹槽114b的寬度，在此情況下，由於微負載效應的緣故，蝕刻後凹槽114a的深度會小於凹槽114b的深度。如第2圖所示，下電極板112上的凹槽114a會向下穿過上氮化鈦層108延伸至鋁層106，而下電極板112周圍的凹槽114b會進一步穿過下氮化鈦層104而暴露出介電層100，甚至延伸至介電層100內，以此分開下電極板112與周圍的下電極材料層102。上述本發明實施例利用蝕刻製程固有的微負載效應，可在同一道蝕刻製程中界定出下電極板112並同時形成下電極板112上吾人所需之凹槽114a結構。此方式較之一般做法的優點在於可以減少一道光罩以及蝕刻製程的成本，並增加產能。 Next please refer to Figure 2. After the lower electrode material layer 102 is formed, a photolithography process is then performed to form a patterned photoresist 110 on the lower electrode material layer 102, and the photoresist 110 is used as an etching mask to perform dry etching to pattern the lower electrode material layer 102 to form a patterned photoresist 110. the lower electrode plate 112, and at the same time a plurality of grooves 114a are formed thereon. It should be noted that in the embodiment of the present invention, the width of the groove 114a on the lower electrode plate 112 is significantly smaller than the width of the groove 114b around the lower electrode plate 112. The depth of the grooves 114a may be less than the depth of the grooves 114b. As shown in FIG. 2, the grooves 114a on the lower electrode plate 112 extend downward through the upper titanium nitride layer 108 to the aluminum layer 106, and the grooves 114b around the lower electrode plate 112 further penetrate through the lower nitride layer The titanium layer 104 exposes the dielectric layer 100 and even extends into the dielectric layer 100 , thereby separating the lower electrode plate 112 from the surrounding lower electrode material layer 102 . The above-mentioned embodiments of the present invention utilize the inherent micro-loading effect of the etching process to define the lower electrode plate 112 and simultaneously form the desired groove 114a structure on the lower electrode plate 112 in the same etching process. The advantage of this method compared with the general practice is that it can reduce the cost of a mask and an etching process, and increase the production capacity.

在其他實施例中，如第11圖所示，下電極板112上的凹槽114a也可以穿過鋁層106而暴露出下氮化鈦層104。此實施例做法的優點在於可以獲得較為一致的凹槽114a深度，因為在一般的蝕刻製程中，蝕刻製程對於靠近晶圓中心與靠近晶圓邊緣的部位會有不同的蝕刻速率，如此會導致位於晶圓中心的凹槽114a的深度與位於晶圓邊緣的凹槽114a的深度相差過大。此實施例做法利用氮化鈦與鋁蝕刻速度不同的性質，以下氮化鈦層104做為一蝕刻停止層，如此下電極板112上的凹槽114a可被控制成均勻地延伸至下氮化鈦層104表面，而利用微負載效應又可使下電極板112周圍的凹槽114b被控制成穿過氮化鈦層104延伸至下方的介電層100內，以界定出下電極板112。 In other embodiments, as shown in FIG. 11 , the grooves 114 a on the lower electrode plate 112 may also pass through the aluminum layer 106 to expose the lower titanium nitride layer 104 . The advantage of this embodiment is that a more consistent depth of the groove 114a can be obtained, because in a general etching process, the etching process will have different etching rates for the parts near the center of the wafer and near the edge of the wafer. The depth of the groove 114a at the center of the wafer is too different from the depth of the groove 114a at the edge of the wafer. This embodiment utilizes the different etching speed of titanium nitride and aluminum. The lower titanium nitride layer 104 is used as an etch stop layer, so that the grooves 114a on the lower electrode plate 112 can be controlled to extend uniformly to the lower nitride layer. The surface of the titanium layer 104 , and the grooves 114 b around the lower electrode plate 112 can be controlled to extend through the titanium nitride layer 104 into the underlying dielectric layer 100 by using the micro-loading effect to define the lower electrode plate 112 .

接下來請參照第3圖。在下電極板112形成後，接著進行灰化製程以及清潔製程將光阻110移除，之後再形成另一介電層116覆蓋下電極板112。與下方的介電層100相同，介電層116可為一金屬間介電層，其材料較佳為低介電常數 材料(k<3.0)或是氧化矽，可以旋轉塗佈或是化學氣相沉積等製程方式形成在基底上。此步驟可以在第一次介電層沉積後先施行化學機械研磨(CMP)製程來平坦化介電層116的表面，之後再做第二次沉積來達到預定的介電層116厚度。 Next please refer to Figure 3. After the lower electrode plate 112 is formed, an ashing process and a cleaning process are performed to remove the photoresist 110 , and then another dielectric layer 116 is formed to cover the lower electrode plate 112 . Like the underlying dielectric layer 100, the dielectric layer 116 may be an intermetal dielectric layer, preferably made of a low dielectric constant material The material (k<3.0) or silicon oxide can be formed on the substrate by processes such as spin coating or chemical vapor deposition. In this step, a chemical mechanical polishing (CMP) process may be performed after the first deposition of the dielectric layer to planarize the surface of the dielectric layer 116 , and then a second deposition may be performed to achieve a predetermined thickness of the dielectric layer 116 .

接下來請參照第4圖。在介電層116形成後，接著進行光刻製程在介電層116上形成圖案化的光阻118，並以該光阻118為蝕刻遮罩蝕刻介電層116，以形成位於下電極板112上的電容凹槽120。在本發明實施例中，該蝕刻製程可為濺射蝕刻、離子束蝕刻、或電漿蝕刻等，所形成的電容凹槽120會含括所有先前所形成位於下電極板112上的的凹槽114a。 Next please refer to Figure 4. After the dielectric layer 116 is formed, a photolithography process is then performed to form a patterned photoresist 118 on the dielectric layer 116 , and the photoresist 118 is used as an etching mask to etch the dielectric layer 116 to form the lower electrode plate 112 Capacitor groove 120 on it. In the embodiment of the present invention, the etching process may be sputter etching, ion beam etching, or plasma etching, etc. The formed capacitor groove 120 includes all the grooves previously formed on the lower electrode plate 112 114a.

接下來請參照第5圖。在電容凹槽120形成後，接著進行灰化製程以及清潔製程將光阻118移除，之後再於介電層116與電容凹槽120的表面上依序形成一共形的電容介電層122以及一上電極板124。如圖所示，上電極板124會填滿凹槽114a中的空間。而在其他實施例中，填入凹槽114a中的上電極板124內可能會有空隙形成。在本發明實施例中，電容介電層122的材料可為高介電常數材料，包含氧化鋁(Al2O3)、氧化鉿(HfO2)、氧化矽(SiO2)、氮化矽(SiN)、五氧化二鉭(Ta2O5)、氮氧化鉭(TaON)、氧化鈦(TiO2)、氧化鋯(ZrO2)、四乙氧基矽烷(TEOS)、旋塗式玻璃(SOG)、或氟矽玻璃(FSG)等，其可採用PVD、CVD、原子層沉積(ALD)、或是分子束磊晶(MBE)等製程來形成。上電極板124的材料可為氮化鈦、鈦、鉭、氮化鉭或是鎢，其可以物理氣相沉積製程或是各種化學氣相沉積製程形成在電容介電層122上。從圖中可以看出，在本發明實施例中由於凹槽114a存在的緣故，晶圓單位面積下的電容的電極面積可以獲得顯著的提升。凹槽114a數目越多，所增加的電極面積多，進而增加電容結構整體的電容值。 Next please refer to Figure 5. After the capacitor groove 120 is formed, an ashing process and a cleaning process are performed to remove the photoresist 118, and then a conformal capacitor dielectric layer 122 and An upper electrode plate 124 . As shown, the upper electrode plate 124 fills the space in the groove 114a. In other embodiments, voids may be formed in the upper electrode plate 124 filled in the groove 114a. In the embodiment of the present invention, the material of the capacitor dielectric layer 122 may be a high dielectric constant material, including aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), silicon oxide (SiO 2 ), silicon nitride ( SiN), tantalum pentoxide (Ta 2 O 5 ), tantalum oxynitride (TaON), titanium oxide (TiO 2 ), zirconium oxide (ZrO 2 ), tetraethoxysilane (TEOS), spin-on glass (SOG) ), or fluorosilicate glass (FSG), etc., which can be formed by PVD, CVD, atomic layer deposition (ALD), or molecular beam epitaxy (MBE) processes. The material of the upper electrode plate 124 can be titanium nitride, titanium, tantalum, tantalum nitride or tungsten, which can be formed on the capacitor dielectric layer 122 by a physical vapor deposition process or various chemical vapor deposition processes. As can be seen from the figure, in the embodiment of the present invention, due to the existence of the groove 114a, the electrode area of the capacitor under the unit area of the wafer can be significantly improved. The greater the number of the grooves 114a, the more the area of the electrodes is increased, thereby increasing the overall capacitance of the capacitor structure.

接下來請參照第6圖。在電容介電層122與上電極板124形成後，接著在上電極板124上形成一層有機平坦層(OPL)126。從圖中可以看到有機平坦層126覆蓋了整個基底並填充了電容凹槽120，其作用是為後續製程提供平坦的表面。 有機平坦層126的材料可為有機矽氧烷(organosiloxane)或碳塗層(Spin-On-Carbon,SOC)，其可以旋轉塗佈的方式形成在上電極板124上並提供良好的凹槽填充效果。 Next, please refer to Figure 6. After the capacitor dielectric layer 122 and the upper electrode plate 124 are formed, an organic planarization layer (OPL) 126 is then formed on the upper electrode plate 124 . It can be seen from the figure that the organic flat layer 126 covers the entire substrate and fills the capacitor groove 120, and its function is to provide a flat surface for subsequent processes. The material of the organic planarization layer 126 can be organosiloxane or carbon coating (Spin-On-Carbon, SOC), which can be formed on the upper electrode plate 124 by spin coating and provide good groove filling Effect.

接下來請參照第7圖。在有機平坦層126形成後，進行一回蝕刻製程或是化學機械研磨製程來移除一定厚度的層結構。此移除步驟會移除位於介電層116頂面上的有機平坦層126、上電極板124、以及電容介電層122，如此以分隔界定出各個電容結構。因此步驟之故，電容介電層122與上電極板124的邊緣會具有往與下電極板112的頂面垂直的方向延伸的垂直延伸部位122a,124a。 Next please refer to Figure 7. After the organic planarization layer 126 is formed, an etching back process or a chemical mechanical polishing process is performed to remove the layer structure with a certain thickness. This removal step removes the organic planar layer 126 , the upper electrode plate 124 , and the capacitive dielectric layer 122 on the top surface of the dielectric layer 116 , thus defining each capacitive structure in isolation. Therefore, due to the steps, the edges of the capacitor dielectric layer 122 and the upper electrode plate 124 have vertically extending portions 122 a and 124 a extending in a direction perpendicular to the top surface of the lower electrode plate 112 .

最後請參照第8圖。在分隔各個電容結構之後，接著移除剩餘的有機平坦層126，並在整個基底上覆蓋另一介電層128。介電層128的相關製程如第3圖中的介電層116所述，此處不再贅述。隨後，在介電層116與128中形成接觸件130分別連接電容結構的上電極板124與下電極板112，其步驟可包括：以上電極板124與下電極板112為蝕刻停止層進行光刻製程形成位於介電層116,128中的導孔，之後在導孔中填入如銅、鋁、鈦、鎢等金屬材料而形成接觸件130。接觸件130形成後，之後再於介電層128上方形成與之連接的圖案化金屬層132，如此即完成了電容結構之製作。 Finally, please refer to Figure 8. After separating the individual capacitive structures, the remaining organic planarization layer 126 is then removed and another dielectric layer 128 is covered over the entire substrate. The related process of the dielectric layer 128 is as described in the dielectric layer 116 in FIG. 3 , and will not be repeated here. Then, contact members 130 are formed in the dielectric layers 116 and 128 to connect the upper electrode plate 124 and the lower electrode plate 112 of the capacitor structure, respectively. The steps may include: performing photolithography on the upper electrode plate 124 and the lower electrode plate 112 as an etch stop layer. The process forms via holes in the dielectric layers 116 , 128 , and then fills the via holes with metal materials such as copper, aluminum, titanium, tungsten, etc. to form the contacts 130 . After the contact member 130 is formed, a patterned metal layer 132 is then formed on the dielectric layer 128 to be connected thereto, thus completing the fabrication of the capacitor structure.

以上實施例為本發明電容結構之製作流程說明。根據上述製作流程，本發明也於此提出了一種電容結構，如第8圖所示，其包含一基底100、一下電極板112，位於基底100上，其中下電極板112上具有複數個凹槽114a、一電容介電層122，位於下電極板112上與該些凹槽114a上、以及一上電極板124，位於電容介電層122上，其中電容介電層122與上電極板124的邊緣具有往與下電極板112的頂面垂直的方向延伸的垂直延伸部位122a,124a。 The above embodiment is an illustration of the manufacturing process of the capacitor structure of the present invention. According to the above manufacturing process, the present invention also proposes a capacitor structure, as shown in FIG. 8 , which includes a substrate 100 and a lower electrode plate 112 on the substrate 100 , wherein the lower electrode plate 112 has a plurality of grooves 114a, a capacitor dielectric layer 122, located on the lower electrode plate 112 and the grooves 114a, and an upper electrode plate 124, located on the capacitor dielectric layer 122, wherein the capacitor dielectric layer 122 and the upper electrode plate 124 The edge has vertically extending portions 122 a and 124 a extending in a direction perpendicular to the top surface of the lower electrode plate 112 .

接下來請參照第9圖與第10圖，其為根據本發明另一實施例中一電容結構與其製作步驟的截面示意圖。在本發明實施例中，可以在下電極板112上的 凹槽114a形成後再施加一額外的回拉(pullback)製程來改變凹槽114a的外型，以進一步增加電極面積。此回拉製程可使用對鋁與氮化鈦具有不同蝕刻選擇比的溶液(例如稀釋硫過氧化物(DSP))，以浸蝕的方式蝕刻凹槽114a的側壁136，使其呈弧形向外凸出。如此弧形外凸的凹槽側壁136可以提供比第4圖所示常規筆直型態的凹槽側壁更多的電極面積。 Next, please refer to FIG. 9 and FIG. 10 , which are schematic cross-sectional views of a capacitor structure and its fabrication steps according to another embodiment of the present invention. In the embodiment of the present invention, the electrodes on the lower electrode plate 112 may be After the groove 114a is formed, an additional pullback process is applied to change the shape of the groove 114a to further increase the electrode area. The pullback process may use solutions with different etch selectivity ratios for aluminum and titanium nitride, such as dilute sulfur peroxide (DSP), to etch the sidewalls 136 of the recess 114a so that they arc outwardly bulge. Such arcuate convex groove sidewalls 136 can provide more electrode area than the conventional straight groove sidewalls shown in FIG. 4 .

接下來請參照第12圖，其為根據本發明又另一實施例中一電容結構的製作步驟的截面示意圖。在本發明實施例中，在第4圖形成電容凹槽120之後與形成電容介電層122之前，可以先在電容凹槽120表面上形成一額外的下電極層134。下電極層134的材料可為氮化鈦、鈦、鉭、氮化鉭或是鎢，其可以物理氣相沉積製程或是各種化學氣相沉積製程等方式形成。如此，如第12圖所示，與電容介電層122以及上電極板124相同，下電極層134同樣會具有位於介電層116側壁上的垂直延伸部位。於前述的實施例相比，由於此下電極層134垂直延伸部位的存在，該垂直延伸部位也可以提供有效的電極面積，進一步增加整體電容結構的電容值。 Next, please refer to FIG. 12 , which is a schematic cross-sectional view of a manufacturing step of a capacitor structure according to yet another embodiment of the present invention. In the embodiment of the present invention, after the capacitor groove 120 is formed in FIG. 4 and before the capacitor dielectric layer 122 is formed, an additional lower electrode layer 134 may be formed on the surface of the capacitor groove 120 first. The material of the lower electrode layer 134 can be titanium nitride, titanium, tantalum, tantalum nitride or tungsten, which can be formed by physical vapor deposition process or various chemical vapor deposition processes. Thus, as shown in FIG. 12 , like the capacitor dielectric layer 122 and the upper electrode plate 124 , the lower electrode layer 134 also has a vertically extending portion located on the sidewall of the dielectric layer 116 . Compared with the foregoing embodiments, due to the existence of the vertically extending portion of the lower electrode layer 134, the vertically extending portion can also provide an effective electrode area, thereby further increasing the capacitance value of the overall capacitor structure.

接下來請參照第13圖，其為根據本發明又另一實施例中一電容結構的放大示意圖。承第12圖之實施例，在有額外形成下電極層134的情況下，可以在第7圖分隔各個電容結構後的步驟階段進行一額外的蝕刻製程，移除部分的上電極板124與下電極層134，使其垂直延伸部位124a,134a的長度小於電容介電層122垂直延伸部位122a的長度，如第13圖所示，如此可以確保上電極板124與下電極層134的垂直延伸部位的邊緣不會因為接觸而造成元件失效。 Next, please refer to FIG. 13 , which is an enlarged schematic view of a capacitor structure according to yet another embodiment of the present invention. According to the embodiment of FIG. 12, in the case where the lower electrode layer 134 is additionally formed, an additional etching process may be performed in the step stage after separating each capacitor structure in FIG. 7 to remove part of the upper electrode plate 124 and the lower electrode plate 124. For the electrode layer 134, the length of the vertically extending parts 124a and 134a is smaller than the length of the vertically extending part 122a of the capacitor dielectric layer 122, as shown in FIG. 13, so that the vertical extending parts of the upper electrode plate 124 and the lower electrode layer 134 can be ensured The edges will not cause component failure due to contact.

接下來請參照第14圖，其為根據本發明又另一實施例中一電容結構的放大示意圖。承第12圖之實施例，在有額外形成下電極層134的情況下，可以在第7圖分隔各個電容結構後的步驟階段進行一額外的氧化製程，使得上電極板124與下電極層134的垂直延伸部位124a,134a頂端氧化成為氧化部位124b,134b， 如第14圖所示，如此可以確保上電極板124與下電極層134垂直延伸部位的邊緣達成絕緣而不會造成元件失效。 Next, please refer to FIG. 14 , which is an enlarged schematic diagram of a capacitor structure according to yet another embodiment of the present invention. According to the embodiment shown in FIG. 12 , in the case where the lower electrode layer 134 is additionally formed, an additional oxidation process may be performed in the steps after the capacitor structures are separated in FIG. 7 , so that the upper electrode plate 124 and the lower electrode layer 134 are formed. The tops of the vertically extending parts 124a, 134a are oxidized to become oxidized parts 124b, 134b, As shown in FIG. 14 , this can ensure that the upper electrode plate 124 and the edge of the vertically extending portion of the lower electrode layer 134 are insulated without causing device failure.

根據上述本發明實施例所述之電容結構及其製作方法，其利用蝕刻製程固有的微負載效應來形成特製凹槽，並可透過額外的回拉製程增加凹槽的表面積，進而增加電容結構整體的電容值。此外，額外的蝕刻或氧化製程處理使得所形成的MIM電容具有良好的絕緣特性，是為一兼具區別性特徵與功效性特徵的發明。 According to the capacitor structure and the manufacturing method thereof according to the above-mentioned embodiments of the present invention, the special groove is formed by utilizing the inherent micro-loading effect of the etching process, and the surface area of the groove can be increased through an additional pull-back process, thereby increasing the overall capacitor structure. capacitance value. In addition, the additional etching or oxidation process enables the formed MIM capacitor to have good insulating properties, which is an invention with both distinctive and functional features.

以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100:基底/介電層 100: Substrate/Dielectric Layer

102:下電極材料層 102: Lower electrode material layer

104:氮化鈦層 104: Titanium nitride layer

106:鋁層 106: Aluminum layer

108:氮化鈦層 108: Titanium nitride layer

112:下電極板 112: Lower electrode plate

114a:凹槽 114a: groove

116:介電層 116: Dielectric layer

122:電容介電層 122: Capacitive dielectric layer

122a:垂直延伸部位 122a: Vertical extension

124:上電極板 124: Upper electrode plate

124a:垂直延伸部位 124a: Vertical extension

128:介電層 128: Dielectric layer

130:接觸件 130: Contacts

132:金屬層 132: metal layer

Claims (18)

一種電容結構，包含：一基底；一下電極板，位於該基底上，其中該下電極板具有複數個凹槽；一電容介電層，位於該下電極板上；一上電極板，位於該電容介電層上並且伸入該些凹槽，其中該電容介電層與該上電極板具有與該下電極板的頂面垂直的垂直延伸部位；以及一下電極層，設置在該下電極板上，並且該電容介電層係設置於該下電極層與該上電極板之間。 A capacitor structure, comprising: a substrate; a lower electrode plate on the substrate, wherein the lower electrode plate has a plurality of grooves; a capacitor dielectric layer on the lower electrode plate; an upper electrode plate on the capacitor on the dielectric layer and extending into the grooves, wherein the capacitor dielectric layer and the upper electrode plate have a vertical extension part perpendicular to the top surface of the lower electrode plate; and a lower electrode layer, arranged on the lower electrode plate , and the capacitor dielectric layer is arranged between the lower electrode layer and the upper electrode plate. 根據申請專利範圍第1項所述之電容結構，其中該下電極板為氮化鈦層-鋁層-氮化鈦層的複層結構，該些凹槽穿過該氮化鈦層延伸到該鋁層。 The capacitor structure according to claim 1, wherein the lower electrode plate is a multi-layer structure of a titanium nitride layer-aluminum layer-titanium nitride layer, and the grooves extend through the titanium nitride layer to the aluminum layer. 根據申請專利範圍第1項所述之電容結構，其中該些凹槽的側壁呈弧形向外凸出。 According to the capacitor structure described in claim 1, the sidewalls of the grooves protrude outwardly in an arc shape. 根據申請專利範圍第1項所述之電容結構，其中該下電極層具有與該下電極板的頂面垂直的垂直延伸部位。 The capacitor structure according to claim 1, wherein the lower electrode layer has a vertically extending portion perpendicular to the top surface of the lower electrode plate. 根據申請專利範圍第4項所述之電容結構，其中該下電極層的垂直延伸部位的長度小於該電容介電層的垂直延伸部位的長度。 The capacitor structure according to claim 4, wherein the length of the vertically extending portion of the lower electrode layer is smaller than the length of the vertically extending portion of the capacitor dielectric layer. 根據申請專利範圍第4項所述之電容結構，其中該下電極層的垂直延伸部位的頂端具有氧化部位。 The capacitor structure according to claim 4, wherein the top of the vertically extending portion of the lower electrode layer has an oxidized portion. 根據申請專利範圍第1項所述之電容結構，其中該下電極層的材料為氮化鈦或鈦。 According to the capacitor structure described in claim 1, the material of the lower electrode layer is titanium nitride or titanium. 根據申請專利範圍第1項所述之電容結構，其中該上電極板的垂直延伸部位的長度小於該電容介電層的垂直延伸部位的長度。 The capacitor structure according to claim 1, wherein the length of the vertically extending portion of the upper electrode plate is smaller than the length of the vertically extending portion of the capacitor dielectric layer. 根據申請專利範圍第1項所述之電容結構，其中該上電極板的垂直延伸部位的頂端具有氧化部位。 The capacitor structure according to claim 1, wherein the top of the vertically extending portion of the upper electrode plate has an oxidized portion. 根據申請專利範圍第1項所述之電容結構，其中該電容介電層的材料包含高介電常數材料或是氮化矽。 According to the capacitor structure described in claim 1, the material of the capacitor dielectric layer comprises a high dielectric constant material or silicon nitride. 根據申請專利範圍第1項所述之電容結構，其中該上電極板的材料為氮化鈦或鈦。 According to the capacitor structure described in claim 1, the material of the upper electrode plate is titanium nitride or titanium. 一種電容結構的製作方法，包含：在一基底上形成一下電極材料層；進行一第一光刻製程圖案化該下電極材料層以形成一下電極板，其中該第一光刻製程同時在該下電極板上形成多個凹槽；在該下電極板上形成一介電層；進行一第二光刻製程移除部分的該介電層以裸露出含括該些凹槽的部分該下電極板；在該下電極板與該介電層的表面依序形成一電容介電層與一上電極板；以 及移除位於該介電層的頂面上的該電容介電層與該上電極板，使得該電容介電層與該上電極板的邊緣具有位於該介電層的側壁上的垂直延伸部位。 A method for fabricating a capacitor structure, comprising: forming a lower electrode material layer on a substrate; patterning the lower electrode material layer by a first photolithography process to form a lower electrode plate, wherein the first photolithography process is simultaneously performed on the lower electrode plate. forming a plurality of grooves on the electrode plate; forming a dielectric layer on the lower electrode plate; performing a second photolithography process to remove part of the dielectric layer to expose the part of the lower electrode including the grooves plate; sequentially form a capacitor dielectric layer and an upper electrode plate on the surface of the lower electrode plate and the dielectric layer; to and removing the capacitor dielectric layer and the upper electrode plate on the top surface of the dielectric layer, so that the edges of the capacitor dielectric layer and the upper electrode plate have vertically extending portions on the sidewalls of the dielectric layer . 根據申請專利範圍第12項所述之電容結構的製作方法，其中移除位於該介電層的頂面上的該電容介電層與該上電極板的步驟包含：在該上電極板上形成一有機平坦層；以及進行回蝕刻製程移除部分的該有機平坦層、位於該介電層的頂面上的該上電極板以及該電容介電層。 According to the manufacturing method of the capacitor structure described in claim 12, wherein the step of removing the capacitor dielectric layer and the upper electrode plate on the top surface of the dielectric layer comprises: forming on the upper electrode plate an organic planarization layer; and performing an etch-back process to remove a portion of the organic planarization layer, the upper electrode plate on the top surface of the dielectric layer, and the capacitor dielectric layer. 根據申請專利範圍第12項所述之電容結構的製作方法，其中移除位於該介電層的頂面上的該電容介電層與該上電極板的步驟包含：在該上電極板上形成一有機平坦層；以及進行化學機械研磨製程移除部分的該有機平坦層、位於該介電層頂面上的該上電極板以及該電容介電層。 According to the manufacturing method of the capacitor structure described in claim 12, wherein the step of removing the capacitor dielectric layer and the upper electrode plate on the top surface of the dielectric layer comprises: forming on the upper electrode plate an organic planarization layer; and a chemical mechanical polishing process to remove a portion of the organic planarization layer, the upper electrode plate on the top surface of the dielectric layer, and the capacitor dielectric layer. 根據申請專利範圍第12項所述之電容結構的製作方法，更包含在形成該些凹槽後進行一回拉製程，使得該些凹槽的側壁呈弧形向外凸出。 According to the method for fabricating the capacitor structure described in claim 12, the method further includes performing a pulling process after forming the grooves, so that the sidewalls of the grooves protrude outward in an arc shape. 根據申請專利範圍第12項所述之電容結構的製作方法，更包含在形成該電容介電層之前先在該介電層以及該下電極板的表面上形成一下電極層，並且移除位於該介電層的頂面上的該電容介電層與該上電極板的步驟也會同時移除位於該介電層的頂面上的該下電極層，使得該下電極層的邊緣具有位於該介電層的側壁上的垂直延伸部位。 According to the method for fabricating the capacitor structure described in claim 12, before forming the capacitor dielectric layer, a lower electrode layer is formed on the surface of the dielectric layer and the lower electrode plate, and the bottom electrode layer is removed on the surface of the lower electrode plate. The steps of the capacitor dielectric layer and the upper electrode plate on the top surface of the dielectric layer also simultaneously remove the lower electrode layer on the top surface of the dielectric layer, so that the edge of the lower electrode layer has Vertical extensions on the sidewalls of the dielectric layer. 根據申請專利範圍第17項所述之電容結構的製作方法，更包含進行一氧化製程使得該上電極板與該下電極層的該垂直延伸部位的頂端氧化形成氧化部位。 According to the method for fabricating the capacitor structure described in claim 17, the method further comprises performing an oxidation process to oxidize the tops of the vertically extending portions of the upper electrode plate and the lower electrode layer to form oxide portions. 根據申請專利範圍第17項所述之電容結構的製作方法，更包含進行一蝕刻製程移除部分的該上電極板與該下電極層的該垂直延伸部位，使得該上電極板與該下電極層的垂直延伸部位的長度小於該電容介電層的垂直延伸部位的長度。 According to the method for fabricating the capacitor structure described in claim 17, the method further comprises performing an etching process to remove part of the vertically extending portion of the upper electrode plate and the lower electrode layer, so that the upper electrode plate and the lower electrode The length of the vertically extending portion of the layer is less than the length of the vertically extending portion of the capacitive dielectric layer.
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