TWI755460B

TWI755460B - Appearance inspection method

Info

Publication number: TWI755460B
Application number: TW106143095A
Authority: TW
Inventors: 大美英一; 稲生翔太
Original assignee: 日商東麗工程股份有限公司
Priority date: 2017-02-10
Filing date: 2017-12-08
Publication date: 2022-02-21
Also published as: JP2018128406A; WO2018146887A1; TW201834102A

Abstract

本發明提供一種於具有互不相同之圖案之複數個元件晶片混合存在之狀態下，可縮短檢查所需之時間之外觀檢查裝置。 The present invention provides a visual inspection apparatus that can shorten the time required for inspection in a state where a plurality of element wafers having mutually different patterns are mixed.

本發明之外觀檢查裝置100具備：攝像部40，其拍攝檢查對象之元件晶片210；記憶部50，其預先記憶有互不相同之圖案A~D之成為元件晶片210之檢查基準的良品圖像P；及檢查部61，其識別由攝像部40拍攝之檢查對象之元件晶片210之圖案A~D之種類，且比較由攝像部40拍攝之檢查對象之元件晶片210之圖像、與經識別之檢查對象之元件晶片210之圖案所對應之良品圖像P，藉此進行檢查對象之元件晶片210是否為良品之判別。 The visual inspection apparatus 100 of the present invention includes: an imaging unit 40 for photographing the element wafer 210 to be inspected; P; and the inspection unit 61, which recognizes the types of patterns A to D of the element wafer 210 to be inspected photographed by the imaging unit 40, and compares the image of the element wafer 210 to be inspected photographed by the imaging unit 40 with the identified The good product image P corresponding to the pattern of the component wafer 210 of the inspection object is used to judge whether the component wafer 210 of the inspection object is a good product.

Description

外觀檢查方法 Appearance inspection method

本發明係關於外觀檢查裝置，尤其是關於具備藉由與良品圖像比較，而進行檢查對象之元件晶片是否為良品之判別之檢查部的外觀檢查裝置。 The present invention relates to an appearance inspection apparatus, and more particularly, to an appearance inspection apparatus including an inspection section that judges whether a component wafer to be inspected is a good product by comparing it with a good product image.

先前以來，已知有一種具備藉由與良品圖像比較，而進行檢查對象之元件晶片是否為良品之判別之檢查部的外觀檢查裝置(例如參照專利文獻1)。 Conventionally, there has been known a visual inspection apparatus including an inspection section that judges whether a component wafer to be inspected is a good product by comparing it with a good product image (for example, refer to Patent Document 1).

於上述專利文獻1，揭示一種求出標準圖像(良品圖像)與檢查圖像之差，並基於標準圖像與檢查圖像之差檢查工件之缺陷的外觀檢查方法。於該檢查方法中，首先，於教示過程中進行大量良品工件之拍攝，並求出圖像之每一像素之濃淡值之平均值(標準圖像)。接著，於檢查過程中，進行工件之拍攝，並基於拍攝之檢查對象之工件之檢查圖像、與良品工件之標準圖像之比較而判定缺陷之有無(是否為良品)。另，作為良品工件之標準圖像僅使用1種良品工件之標準圖像。 The above-mentioned Patent Document 1 discloses an appearance inspection method for obtaining a difference between a standard image (good product image) and an inspection image, and inspecting a workpiece for defects based on the difference between the standard image and the inspection image. In this inspection method, first, during the teaching process, a large number of good workpieces are photographed, and the average value of the shading value of each pixel of the image (standard image) is obtained. Next, during the inspection process, the workpiece is photographed, and the presence or absence of defects (whether it is a good product or not) is determined based on the photographed inspection image of the inspection object workpiece and the comparison with the standard image of the good workpiece. In addition, as a standard image of a good workpiece, only one standard image of a good workpiece is used.

[先前技術文獻] [Prior Art Literature] [專利文獻] [Patent Literature]

[專利文獻1]日本專利特開平10-123064號公報 [Patent Document 1] Japanese Patent Laid-Open No. 10-123064

於上述專利文獻1所記載之缺陷檢查方法中，作為良品工件之標準圖像，僅使用1種良品工件之標準圖像，因而於對所有工件設置同一圖案之情形時，可基於1種良品工件之標準圖像判定工件是否為良品。另一方面，於具有互不相同之圖案之複數個工件混合存在之狀態中，必須準備具有互不相同之圖案之複數種良品工件之標準圖像。於該情形時，首先，於已準備複數種中之1種良品工件之標準圖像之狀態(已於記憶體等叫出之狀態)，依序進行複數個工件之拍攝。例如，藉由使攝像部對複數個工件掃描而進行拍攝。接著，將拍攝之複數個工件之檢查圖像依序與良品工件之標準圖像比較，而判定各個工件是否為良品。進而，準備與檢查結束之種類(圖案)不同之種類(圖案)之良品工件之標準圖像，且拍攝複數個工件，而判定各個工件是否為良品。 In the defect inspection method described in the above-mentioned Patent Document 1, only one standard image of a good workpiece is used as a standard image of a good workpiece, so when the same pattern is set for all the workpieces, it can be based on one good workpiece. The standard image of the workpiece determines whether the workpiece is a good product. On the other hand, in a state where a plurality of workpieces having mutually different patterns coexist, it is necessary to prepare standard images of a plurality of good workpieces having mutually different patterns. In this case, first, in a state where a standard image of one good workpiece among a plurality of types has been prepared (a state that has been called out from a memory or the like), a plurality of workpieces are sequentially photographed. For example, imaging is performed by causing the imaging unit to scan a plurality of workpieces. Next, the photographed inspection images of a plurality of workpieces are sequentially compared with standard images of good workpieces to determine whether each workpiece is a good product. Furthermore, a standard image of a good workpiece of a type (pattern) different from the type (pattern) that has been inspected is prepared, a plurality of workpieces are photographed, and it is determined whether each workpiece is a good product.

如此，於如上述專利文獻1所記載之先前之缺陷檢查方法中，進行複數次之攝像部之掃描，該掃描之次數為圖案之種類數。因此，為了進行所有工件(元件晶片)之檢查而有需要相對較長時間之問題點。 In this way, in the conventional defect inspection method as described in the above-mentioned Patent Document 1, the scanning of the imaging unit is performed a plurality of times, and the number of times of the scanning is the number of patterns. Therefore, there is a problem that a relatively long time is required to perform inspection of all the workpieces (element wafers).

本發明係為了解決如上所述之課題而完成者，本發明之1個目的在於提供一種於具有互不相同之圖案之複數個元件晶片混合存在之狀態下，可縮短檢查所需時間之外觀檢查裝置。 The present invention has been made in order to solve the above-mentioned problems, and an object of the present invention is to provide a visual inspection that can shorten the time required for inspection in a state where a plurality of element wafers having mutually different patterns coexist device.

為了達成上述目的，本發明一態樣之外觀檢查裝置係於具有互不相同之圖案之複數個元件晶片混合存在之狀態下，分別檢查複數個元件晶片者，且具備：攝像部，其拍攝檢查對象之元件晶片；記憶部，其預先記憶有互不相同之圖案之成為元件晶片之檢查基準的良品圖像；及檢查部，其識別由攝像部拍攝之檢查對象之元件晶片之圖案種類，且比較由攝像部拍攝之檢查對象之元件晶片之圖像、與經識別之檢查對象之元件晶片之圖案所對應之良品圖像，藉此進行檢查對象之元件晶片是否為良品之判別。 In order to achieve the above object, a visual inspection apparatus according to an aspect of the present invention inspects a plurality of element wafers respectively in a state where a plurality of element wafers having mutually different patterns are mixed, and includes an imaging unit for photographing and inspecting a target device wafer; a memory section that pre-stores a good image with patterns different from each other that serves as an inspection reference for the device wafer; and an inspection section that recognizes the pattern type of the inspection target device wafer captured by the imaging section, and The comparison was taken by the camera department The image of the component wafer of the inspection object is photographed, and the image of the good product corresponding to the pattern of the recognized component wafer of the inspection object, so as to judge whether the component wafer of the inspection object is a good product.

於本發明一態樣之外觀檢查裝置中，如上所述，具備檢查部，其識別由攝像部拍攝之檢查對象之元件晶片之圖案種類，且比較由攝像部拍攝之檢查對象之元件晶片之圖像、與經識別之檢查對象之元件晶片之圖案所對應之良品圖像，藉此進行檢查對象之元件晶片是否為良品之判別。藉此，由於由檢查部識別所拍攝之檢查對象之元件晶片之圖案種類，故可依拍攝之檢查對象之元件晶片之每一者，自記憶部讀出與所拍攝之檢查對象之元件晶片之圖案對應之良品圖像。其結果，於具有互不相同之圖案之複數個元件晶片混合存在之狀態下，無須反覆由攝像部對複數個元件晶片之拍攝(攝像部之掃描)，而可藉由1次之掃描進行元件晶片是否為良品之判別。藉此，於具有互不相同之圖案之複數個元件晶片混合存在之狀態下，可縮短檢查所需之時間。 In the appearance inspection apparatus of one aspect of the present invention, as described above, an inspection unit is provided which recognizes the pattern type of the component wafer to be inspected photographed by the imaging unit, and compares the images of the component wafer to be inspected photographed by the imaging unit. The image and the image of the good product corresponding to the pattern of the recognized component wafer of the inspection object are used to judge whether the component wafer of the inspection object is a good product. In this way, since the pattern type of the photographed component wafers to be inspected is recognized by the inspection unit, it is possible to read out from the memory unit the relationship between the photographed component wafers to be inspected for each of the photographed component wafers to be inspected. The good image corresponding to the pattern. As a result, in a state where a plurality of element wafers having mutually different patterns coexist, it is not necessary to repeatedly photograph the plurality of element wafers by the imaging unit (scanning of the imaging unit), and the element can be performed by one scan. The judgment of whether the chip is good or not. Thereby, in a state where a plurality of element wafers having mutually different patterns coexist, the time required for inspection can be shortened.

於上述一態樣之外觀檢查裝置中，較佳構成為複數個元件晶片設置於基板上，且於記憶部預先記憶有設置於基板上之任一位置之元件晶片具有何種圖案之晶片配置資訊，檢查部基於記憶於記憶部之晶片配置資訊，識別由攝像部拍攝之檢查用之元件晶片之圖案種類。依據如此構成，由於於記憶部預先記憶有設置於基板上之任一位置之元件晶片具有何種圖案之晶片配置資訊，故與藉由圖像辨識(圖像彼此之比較)等辨識所拍攝之檢查用之元件晶片之圖案對應於何一良品圖像之情形相比，可進一步縮短檢查所需之時間。 In the appearance inspection apparatus of the above-mentioned aspect, it is preferable that a plurality of element chips are disposed on the substrate, and the memory portion pre-stores the chip arrangement information of which pattern the element chip disposed at any position on the substrate has. , the inspection unit recognizes the pattern type of the component wafer for inspection photographed by the imaging unit based on the chip configuration information stored in the memory unit. According to such a configuration, since the chip arrangement information of the pattern of the element chip disposed at any position on the substrate is pre-stored in the memory portion, it is compared with the image captured by image recognition (comparison of images with each other) or the like. Compared with the case where the pattern of the component wafer used for inspection corresponds to any good image, the time required for inspection can be further shortened.

於該情形時，較佳於基板上設置複數個各自包含分別形成有互不相同圖案之複數個元件晶片之元件晶片群，且元件晶片群之分別形成有互不相同圖案之複數個元件晶片之配置位置於元件晶片群各者中均相同，於記憶部預先記憶有包含複數個元件晶片群之複數個元件晶片之晶片配置資訊。依據如此構成，由於複數個元件晶片之配置位置於元件晶片群之各者中均相同，故可使用相同之遮罩於每一個元件晶片群形成元件晶片。 In this case, it is preferable to dispose a plurality of element chip groups each including a plurality of element chips with different patterns formed on the substrate, and the element chip groups are respectively formed with different patterns. The arrangement positions of the plurality of element chips of the same pattern are the same in each of the element chip groups, and the chip arrangement information of the plurality of element chips including the plurality of element chip groups is pre-stored in the memory unit. According to this configuration, since the arrangement positions of the plurality of device chips are the same in each of the device chip groups, the device chips can be formed using the same mask for each device chip group.

於將上述複數個元件晶片設置於基板上之外觀檢查裝置中，較佳構成為依序對設置於基板上之複數個檢查用之元件晶片之每一者進行：以基板與攝像部相對移動之狀態，由攝像部拍攝檢查用之元件晶片；由檢查部識別所拍攝之檢查用之元件晶片之圖案種類；將良品圖像切換為具有與經識別之檢查用之元件晶片之圖案對應之圖案的良品圖像；及比較檢查用之元件晶片之圖像與良品圖像而進行元件晶片是否為良品之判別。依據如此構成，於具有互不相同之圖案之複數個元件晶片混合存在之狀態下，亦可連續順利地進行複數個元件晶片之檢查。 In the appearance inspection apparatus for arranging the above-mentioned plural element chips on the substrate, it is preferably configured to sequentially perform the inspection for each of the plural inspecting element chips disposed on the substrate: the relative movement of the substrate and the imaging unit is performed. In the state, the imaging unit takes pictures of the component wafer for inspection; the inspection unit recognizes the pattern type of the component wafer for inspection photographed; the good image is switched to one having a pattern corresponding to the identified pattern of the component wafer for inspection. Good product image; and compare the image of the component wafer used for inspection with the good product image to judge whether the component wafer is a good product. According to such a configuration, in a state where a plurality of device wafers having mutually different patterns coexist, the inspection of a plurality of device wafers can be performed continuously and smoothly.

根據本發明，如上所述，於具有互不相同之圖案之複數個元件晶片混合存在之狀態下，可縮短檢查所需之時間。 According to the present invention, as described above, in a state where a plurality of element wafers having mutually different patterns coexist, the time required for inspection can be shortened.

10:移動載台 10: Mobile stage

11:X軸滑塊 11: X-axis slider

12:Y軸滑塊 12: Y-axis slider

20:基台部 20: Abutment part

30:載置平台 30: Placing the platform

40:攝像部 40: Camera Department

41:鏡筒 41: Lens barrel

42:半反射鏡 42: Half mirror

43:對物透鏡 43: Object lens

44:攝像相機 44: Camcorder

44a:受光元件 44a: light receiving element

50:記憶部 50: Memory Department

60:控制部 60: Control Department

61:檢查部 61: Inspection Department

100:外觀檢查裝置 100: Appearance inspection device

210:元件晶片 210: Component wafer

210a~210d:元件晶片 210a~210d: Component wafer

211:有效區域 211: Valid area

212:周緣區域 212: Peripheral area

213:缺陷 213: Defect

220:晶圓(基板) 220: Wafer (substrate)

230:元件晶片群 230: Component wafer group

A:圖案 A: Pattern

B:圖案 B: Pattern

B:路徑 B: path

C:圖案 C: Pattern

D:圖案 D: pattern

P:良品圖像 P: Good image

P1~P4:良品圖像 P1~P4: Good image

S1~S4:步驟 S1~S4: Steps

S11~S21:步驟 S11~S21: Steps

S31~S41:步驟 S31~S41: Steps

X:方向 X: direction

X1:方向 X1: direction

X2:方向 X2: direction

Y:方向 Y: direction

Y1:方向 Y1: direction

Y2:方向 Y2: direction

Z:方向 Z: direction

圖1係本發明一實施形態之外觀檢查裝置之整體圖。 FIG. 1 is an overall view of a visual inspection apparatus according to an embodiment of the present invention.

圖2係用以說明本發明一實施形態之外觀檢查裝置之攝像部之動作的圖。 FIG. 2 is a diagram for explaining the operation of the imaging unit of the visual inspection apparatus according to the embodiment of the present invention.

圖3(a)~(d)係顯示良品圖像(良品之元件晶片之圖像)之圖。 FIGS. 3( a ) to ( d ) are diagrams showing images of good products (images of component wafers of good products).

圖4係顯示檢查用之元件晶片之圖。 FIG. 4 is a diagram showing a device wafer for inspection.

圖5係顯示設置於晶圓之複數個元件晶片之圖。 FIG. 5 is a diagram showing a plurality of device chips disposed on a wafer.

圖6係顯示設置於晶圓之具有互不相同之圖案之複數個元件晶片的圖。 FIG. 6 shows a plurality of device chips with mutually different patterns disposed on the wafer. picture.

圖7係顯示元件晶片群之複數個元件晶片之配置位置的圖。 FIG. 7 is a diagram showing the arrangement positions of a plurality of element chips in the element chip group.

圖8係用以說明本發明一實施形態之外觀檢查裝置之條件設定之動作的流程圖。 FIG. 8 is a flowchart for explaining the operation of the condition setting of the visual inspection apparatus according to one embodiment of the present invention.

圖9係用以說明本發明一實施形態之外觀檢查裝置之用於產生良品圖像之動作的流程圖。 FIG. 9 is a flow chart for explaining the operation of the appearance inspection apparatus for generating a good product image according to an embodiment of the present invention.

圖10係用以說明本發明一實施形態之外觀檢查裝置檢查元件晶片之動作的流程圖。 FIG. 10 is a flowchart for explaining the operation of the visual inspection apparatus according to the embodiment of the present invention to inspect the element wafer.

圖11係顯示不良品之元件晶片之圖。 FIG. 11 is a diagram showing a defective component wafer.

以下，基於圖式說明將本發明具體化之實施形態。 Hereinafter, embodiments that embody the present invention will be described based on the drawings.

[本實施形態] [this embodiment]

(外觀檢查裝置之構造) (Structure of Appearance Inspection Device)

參照圖1~圖7，對本實施形態之外觀檢查裝置100之構造進行說明。外觀檢查裝置100構成為於具有互不相同之圖案之複數個元件晶片210(參照圖4)混合存在之狀態，分別檢查複數個元件晶片210。 1-7, the structure of the visual inspection apparatus 100 of this embodiment is demonstrated. The appearance inspection apparatus 100 is configured to inspect a plurality of element wafers 210 in a state where a plurality of element wafers 210 (refer to FIG. 4 ) having mutually different patterns coexist.

如圖1所示，外觀檢查裝置100具備移動載台10。移動載台10包含X軸滑塊11與Y軸滑塊12。X軸滑塊11配置於基台部20上。又，Y軸滑塊12配置於X軸滑塊11上。 As shown in FIG. 1 , the appearance inspection apparatus 100 includes a mobile stage 10 . The moving stage 10 includes an X-axis slider 11 and a Y-axis slider 12 . The X-axis slider 11 is arranged on the base portion 20 . In addition, the Y-axis slider 12 is arranged on the X-axis slider 11 .

又，外觀檢查裝置100具備載置平台30。載置平台30配置於Y軸滑塊12上。且，載置平台30構成為藉由移動載台10而朝X方向及Y方向移動。又，載置平台30以載置晶圓220(檢查對象之元件晶片210，參照圖4)之方式構成。另，晶圓220係申請專利範圍之「基板」之一例。 Moreover, the visual inspection apparatus 100 is provided with the mounting platform 30 . The mounting platform 30 is arranged on the Y-axis slider 12 . In addition, the mounting platform 30 is configured to move in the X direction and the Y direction by moving the stage 10 . Moreover, the mounting stage 30 is comprised so that the wafer 220 (the device wafer 210 of an inspection object, refer FIG. 4) may be mounted. In addition, the wafer 220 is an example of a "substrate" within the scope of the patent application.

又，外觀檢查裝置100具備攝像部40。攝像部40係構成為拍攝檢查對象之元件晶片210、及拍攝用以作成成為檢查基準之良品圖像P(良品元件晶片210之圖像，參照圖3)之良品元件晶片210。攝像部40包含：鏡筒41、半反射鏡42、對物透鏡43、及攝像相機44。攝像相機44包含受光元件44a。且，攝像相機44構成為將拍攝之元件晶片210之圖像輸出至後述之控制部60。 In addition, the visual inspection apparatus 100 includes an imaging unit 40 . The imaging unit 40 is configured to photograph the component wafer 210 to be inspected, and the good component wafer 210 for creating a good image P (an image of the good component wafer 210 , see FIG. 3 ) serving as an inspection reference. The imaging unit 40 includes a lens barrel 41 , a half mirror 42 , an objective lens 43 , and an imaging camera 44 . The imaging camera 44 includes a light receiving element 44a. And the imaging camera 44 is comprised so that the image of the element wafer 210 which image|photographed is output to the control part 60 mentioned later.

又，如圖2所示，攝像部40構成為依序拍攝對於攝像部40相對移動之複數個元件晶片210。具體而言，元件晶片210藉由移動載台10對於攝像部40朝X方向或Y方向相對地移動。 Furthermore, as shown in FIG. 2 , the imaging unit 40 is configured to sequentially image a plurality of element wafers 210 that are relatively moved with respect to the imaging unit 40 . Specifically, the element wafer 210 is moved relatively in the X direction or the Y direction with respect to the imaging unit 40 by moving the stage 10 .

又，如圖1所示，外觀檢查裝置100具備記憶部50。如圖3所示，於記憶部50，預先記憶有互不相同之圖案(圖案A~D)之成為元件晶片210之檢查基準的良品圖像P。另，「預先」意指於檢查檢查對象之元件晶片210之前。又，記憶複數個良品圖像P。例如，如圖3所示，良品圖像P包含：對應於圖案A之良品圖像P1(參照圖3(a))、對應於圖案B之良品圖像P2(參照圖3(b))、對應於圖案C之良品圖像P3(參照圖3(c))、及對應於圖案D之良品圖像P4(參照圖3(d))。又，良品圖像P1~P4個別地記憶於記憶部50。 Moreover, as shown in FIG. 1, the visual inspection apparatus 100 is provided with the memory|storage part 50. As shown in FIG. As shown in FIG. 3 , in the memory unit 50 , a good image P serving as an inspection reference for the element wafer 210 is stored in advance with patterns (patterns A to D) different from each other. In addition, "preliminarily" means before the device wafer 210 to be inspected is inspected. Also, a plurality of good product images P are memorized. For example, as shown in FIG. 3 , the good image P includes: a good image P1 corresponding to the pattern A (refer to FIG. 3( a )), a good image P2 corresponding to the pattern B (refer to FIG. 3( b )), The good image P3 corresponding to the pattern C (refer to FIG. 3( c )), and the good image P4 corresponding to the pattern D (refer to FIG. 3( d )). In addition, the good-quality images P1 to P4 are individually stored in the memory unit 50 .

良品圖像P1~P4分別係以設置於有效區域211之配線圖案互不相同之方式構成之良品元件晶片210a~210d(參照圖4)之圖像。例如，配線圖案之配置位置、大小等互不相同。另，於圖4中，元件晶片210a~210d各者之包圍有效區域211之周緣區域212彼此具有相同之圖案，另一方面，元件晶片210a~210d之周緣區域212之圖案亦可互不相同。 The good quality images P1 to P4 are images of good quality element chips 210 a to 210 d (refer to FIG. 4 ), which are formed in such a way that the wiring patterns provided in the effective area 211 are different from each other. For example, the arrangement positions and sizes of the wiring patterns are different from each other. In addition, in FIG. 4, the peripheral regions 212 surrounding the effective region 211 of each of the device chips 210a-210d have the same pattern. On the other hand, the patterns of the peripheral regions 212 of the device chips 210a-210d may also be different from each other.

又，如圖5所示，複數個元件晶片210設置於晶圓220上。晶圓220具有俯視時大致圓形狀。又，複數個元件晶片210矩陣狀地設置於晶圓220 上。且，於本實施形態中，如圖6所示，於記憶部50預先記憶有設置於晶圓220上之任一位置之元件晶片210具有何種圖案A~D之晶片配置資訊。具體而言，將矩陣狀設置於晶圓220上之複數個元件晶片210對應於良品圖像P1~P4中之何一良品圖像P(具有與何一良品圖像P相同之圖案A~D)相關之配置資訊預先記憶於記憶部50。另，晶片配置資訊係於檢查用之元件晶片210之檢查前，由例如使用者輸入。另，於圖6中，於一部分之元件晶片210記載有圖案A~D，但實際上將所有之元件晶片210之圖案A~D預先記憶於記憶部50。 Furthermore, as shown in FIG. 5 , a plurality of device chips 210 are provided on the wafer 220 . The wafer 220 has a substantially circular shape in plan view. In addition, a plurality of device chips 210 are arranged in a matrix on the wafer 220 superior. In addition, in this embodiment, as shown in FIG. 6 , the memory unit 50 pre-stores the chip arrangement information of which patterns A to D of the device chip 210 disposed at any position on the wafer 220 has. Specifically, the plurality of device chips 210 arranged in a matrix on the wafer 220 correspond to any good image P (with the same patterns A to D as any good image P) among the good images P1 ˜ P4 ) related configuration information is stored in the memory unit 50 in advance. In addition, the wafer configuration information is input by, for example, a user before inspection of the device wafer 210 for inspection. In addition, in FIG. 6 , the patterns A to D are described in a part of the device chips 210 , but actually, the patterns A to D of all the device chips 210 are stored in the memory portion 50 in advance.

又，於本實施形態中，如圖6所示，於晶圓220上設置有複數個各自包含分別形成有互不相同之圖案之複數個元件晶片210(檢查用之元件晶片210)之元件晶片群230(以圖6之粗線之四角形包圍之區域)。例如，如圖7所示，於1個元件晶片群230包含分別形成有互不相同之圖案之4個元件晶片210a~210d。且，元件晶片群230之分別形成有互不相同之圖案之複數個元件晶片210a~210d之配置位置於元件晶片群230各者中均相同。例如，於1個元件晶片群230中，4個元件晶片210a~210d以2列2行之狀態配置。且，於左上方配置元件晶片210a，於右上方配置元件晶片210b。又，於左下方配置元件晶片210c，於右下方配置元件晶片210d。該配置位置於任一元件晶片群230中均相同。 Furthermore, in this embodiment, as shown in FIG. 6 , a plurality of element chips each including a plurality of element chips 210 (element chips 210 for inspection) each having a pattern formed with different patterns are provided on the wafer 220 . Cluster 230 (area enclosed by the square of the thick line in FIG. 6 ). For example, as shown in FIG. 7 , one element wafer group 230 includes four element wafers 210 a to 210 d in which patterns different from each other are formed, respectively. In addition, the arrangement positions of the plurality of element wafers 210 a to 210 d in the element wafer group 230 in which the patterns different from each other are formed are the same in each of the element wafer groups 230 . For example, in one element wafer group 230, four element wafers 210a to 210d are arranged in a state of 2 rows and 2 rows. And the element wafer 210a is arrange|positioned at the upper left, and the element wafer 210b is arrange|positioned at the upper right. Moreover, the element wafer 210c is arrange|positioned in the lower left, and the element wafer 210d is arrange|positioned in the lower right. This arrangement position is the same in any element wafer group 230 .

另，如圖6所示，於晶圓220之外緣側，因晶圓220為大致圓形狀故無法配置4個元件晶片210a~210d。因此，於晶圓220之外緣側中，成為於1個元件晶片群230中，欠缺4個元件晶片210a~210d中之任一個(或複數個)之狀態。另，元件晶片210a~210d之配置位置於元件晶片群230各者中均相同之理由在於：於將元件晶片210a~210d形成於晶圓220上時，使用相同之遮罩(未圖示)形成元件晶片210a~210d之故。 In addition, as shown in FIG. 6 , on the outer edge side of the wafer 220 , the wafer 220 has a substantially circular shape, so that the four element chips 210 a to 210 d cannot be arranged. Therefore, on the outer edge side of the wafer 220 , in one device chip group 230 , any one (or a plurality of) of the four device chips 210 a to 210 d is missing. The reason why the arrangement positions of the element chips 210a to 210d are the same in each of the element chip groups 230 is that when the element chips 210a to 210d are formed on the wafer 220, the The same mask (not shown) forms the device chips 210a-210d.

且，於本實施形態中，於記憶部50預先記憶有包含複數個元件晶片群230之複數個元件晶片210之晶片配置資訊。即，於記憶部50預先記憶如圖6所示之晶片配置資訊。 In addition, in the present embodiment, the chip arrangement information of the plurality of device chips 210 including the plurality of device chip groups 230 is pre-stored in the memory unit 50 . That is, the chip arrangement information shown in FIG. 6 is pre-stored in the memory unit 50 .

又，如圖1所示，外觀檢查裝置100具備檢查部61。檢查部61係例如包含於由CPU(Central Processing Unit：中央處理單元)等構成之控制部60。另，控制部60構成為控制外觀檢查裝置100之整體動作。此處，於本實施形態中，檢查部61識別由攝像部40拍攝之檢查對象之元件晶片210之圖案A~D之種類。接著，檢查部61比較由攝像部40拍攝之檢查對象之元件晶片210之圖像、與經識別之檢查對象之元件晶片210之圖案A~D所對應之良品圖像P，藉此進行檢查對象之元件晶片210是否為良品之判別。具體而言，檢查部61構成為基於記憶於記憶部50之晶片配置資訊(參照圖6)識別由攝像部40拍攝之檢查用之元件晶片210之圖案A~D之種類。 Furthermore, as shown in FIG. 1 , the appearance inspection apparatus 100 includes an inspection unit 61 . The inspection part 61 is included in the control part 60 which consists of a CPU (Central Processing Unit: Central Processing Unit) etc., for example. Moreover, the control part 60 is comprised so that the whole operation|movement of the visual inspection apparatus 100 may be controlled. Here, in the present embodiment, the inspection unit 61 recognizes the types of patterns A to D of the element wafer 210 to be inspected captured by the imaging unit 40 . Next, the inspection unit 61 compares the image of the component wafer 210 to be inspected photographed by the imaging unit 40 with the image P of the good product corresponding to the identified patterns A to D of the component wafer 210 to be inspected, thereby performing inspection. It is used to judge whether the component chip 210 is a good product. Specifically, the inspection unit 61 is configured to recognize the types of patterns A to D of the element wafer 210 for inspection photographed by the imaging unit 40 based on the wafer arrangement information (see FIG. 6 ) stored in the memory unit 50 .

(外觀檢查裝置之動作) (Operation of Appearance Inspection Device)

接著，參照圖8~圖11對外觀檢查裝置100之動作進行說明。 Next, the operation of the appearance inspection apparatus 100 will be described with reference to FIGS. 8 to 11 .

<條件設定> <Condition setting>

參照圖8對條件設定之動作(流程)進行說明。另，以下說明之登錄係藉由例如將受理資訊之畫面顯示於未圖示之顯示部等，且由使用者輸入資訊而進行。又，登錄(輸入)之資訊登錄(記憶)於記憶部50。 The operation (flow) of the condition setting will be described with reference to FIG. 8 . In addition, the registration described below is performed by, for example, displaying a screen for accepting information on a display unit (not shown), etc., and inputting information by the user. In addition, the registered (input) information is registered (stored) in the storage unit 50 .

首先，於步驟S1中，登錄映射資訊。具體而言，登錄晶圓220之尺寸、或元件晶片210之尺寸等。 First, in step S1, the mapping information is registered. Specifically, the size of the registration wafer 220, the size of the device chip 210, and the like.

接著，於步驟S2中，進行元件晶片210之圖案之登錄。具體而言，如圖6所示，登錄設置於晶圓220上之任一位置之元件晶片210具有何種圖案之晶片配置資訊。 Next, in step S2, the pattern registration of the element wafer 210 is performed. Specifically, as shown in FIG. 6 , what kind of pattern does the device chip 210 arranged at any position on the wafer 220 have? chip configuration information.

接著，於步驟S3中，進行元件晶片210之全域對準資訊之登錄。例如，登錄元件晶片210之角度或中心位置等資訊。 Next, in step S3, the registration of the global alignment information of the device wafer 210 is performed. For example, information such as the angle or the center position of the device chip 210 is registered.

接著，於步驟S4中，登錄檢查條件。具體而言，登錄由攝像部40進行元件晶片210之拍攝時之光學條件、或元件晶片210上之檢查區域等。另，檢查區域係例如於圖4之元件晶片210上以虛線包圍之區域。藉此，條件設定動作結束。 Next, in step S4, check conditions are registered. Specifically, the optical conditions at the time of imaging the element wafer 210 by the imaging unit 40 , the inspection area on the element wafer 210 , and the like are registered. In addition, the inspection area is, for example, an area surrounded by a dotted line on the device wafer 210 in FIG. 4 . Thereby, the condition setting operation ends.

<良品圖像之作成> <Creation of good quality image>

參照圖9對良品圖像P之作成(訓練)動作(流程)進行說明。另，良品圖像P之作成由控制部60進行。又，作成之良品圖像P登錄於記憶部50。又，良品圖像P之作成(訓練)於進行後述之檢查用之元件晶片210之檢查前預先進行。 The creation (training) operation (flow) of the good image P will be described with reference to FIG. 9 . In addition, the creation of the good image P is performed by the control unit 60 . In addition, the created good product image P is registered in the memory unit 50 . Incidentally, the creation (training) of the good image P is performed in advance before the inspection of the element wafer 210 for inspection, which will be described later, is performed.

首先，於步驟S11中，自記憶部50讀出檢查條件。檢查條件係於上述步驟S4中登錄者。 First, in step S11 , the inspection conditions are read out from the memory unit 50 . The inspection conditions are those registered in the above-mentioned step S4.

接著，於步驟S12中搬送晶圓220。具體而言，晶圓220載置於移動載台10(載置平台30)。又，晶圓220係以具有互不相同之圖案之複數個元件晶片210混合存在之狀態配置。另，配置於晶圓220之複數個元件晶片210可全部為良品元件晶片210，亦可於複數個元件晶片210中之任一者包含不良品之元件晶片210。另，使用者(控制部60)預先認知到複數個元件晶片210中之何者為良品元件晶片210，複數個元件晶片210中之何者為不良品之元件晶片210之資訊。 Next, in step S12, the wafer 220 is transferred. Specifically, the wafer 220 is placed on the moving stage 10 (the placement stage 30 ). In addition, the wafer 220 is arranged in a state where a plurality of device chips 210 having mutually different patterns coexist. In addition, the plurality of device chips 210 disposed on the wafer 220 may all be good device chips 210 , or any one of the plurality of device chips 210 may include a defective device chip 210 . In addition, the user (the control unit 60 ) knows in advance which one of the plurality of device chips 210 is a good device chip 210 and which one of the plurality of device chips 210 is a defective device chip 210 .

接著，於步驟S13中，進行晶圓220(元件晶片210)之全域對準。例如，確定元件晶片210之角度或中心位置等。另，全域對準之資訊於上述步驟S3中登錄。 Next, in step S13, global alignment of the wafer 220 (device wafer 210) is performed. For example, the angle or the center position of the element wafer 210 is determined. In addition, the information of global alignment is in the above Login in step S3.

接著，於步驟S14中，於目標之元件晶片210之上方，使攝像部40相對移動。具體而言，藉由使晶圓220以移動載台10移動，而將目標之元件晶片210配置於攝像部40之正下方。將複數個元件晶片210中之哪個元件晶片210設為目標元件晶片210係預先登錄於記憶部50。例如，若晶圓220上之複數個元件晶片210全部為良品，則可以所有之元件晶片210為目標。又，若於晶圓220上之複數個元件晶片210包含不良品，則僅將良品元件晶片210設為目標元件晶片210即可。又，亦可不以所有之良品元件晶片210為目標，而以一部分良品元件晶片210為目標。 Next, in step S14 , the imaging unit 40 is relatively moved above the target device wafer 210 . Specifically, by moving the wafer 220 with the moving stage 10 , the target device wafer 210 is placed directly below the imaging unit 40 . Which element wafer 210 of the plurality of element wafers 210 is set as the target element wafer 210 is registered in the memory unit 50 in advance. For example, if the plurality of device chips 210 on the wafer 220 are all good products, all the device chips 210 can be targeted. In addition, if the plurality of device chips 210 on the wafer 220 include defective products, only the good device chips 210 may be set as the target device chips 210 . In addition, instead of targeting all of the good-quality device chips 210, a part of the good-quality device chips 210 may be targeted.

接著，於步驟S15中，拍攝目標之元件晶片210。元件晶片210係依元件晶片210逐一地拍攝。 Next, in step S15, the target device wafer 210 is photographed. The device wafers 210 are photographed one by one according to the device wafers 210 .

接著，於步驟S16中，辨識由攝像部40拍攝之良品元件晶片210之圖案之種類。即，辨識所拍攝之良品元件晶片210對應於圖案A~D中之哪一種。另，配置於晶圓220上之複數個元件晶片210之圖案對應於圖案A~D中之哪一種係與元件晶片210之晶圓220上之位置(座標)對應而預先記憶於記憶部50。接著，基於攝像部40對於晶圓220之位置資訊(座標)，辨識本次拍攝之元件晶片210之圖案對應於圖案A~D中之哪一種。 Next, in step S16 , the type of the pattern of the good-quality device wafer 210 photographed by the imaging unit 40 is identified. That is, it is identified which of the patterns A to D the photographed good component wafer 210 corresponds to. In addition, the patterns of the plurality of device chips 210 disposed on the wafer 220 are stored in the memory portion 50 in advance corresponding to which of the patterns A to D corresponds to the position (coordinate) of the device chips 210 on the wafer 220 . Next, based on the position information (coordinates) of the imaging unit 40 with respect to the wafer 220 , it is identified which of the patterns A to D the pattern of the component wafer 210 photographed this time corresponds to.

接著，於步驟S17中，進行拍攝之元件晶片210之對準。例如，基於預先設置於元件晶片210之對準標記，使元件晶片210之有效區域211(形成有元件之區域，參照圖4)及周緣區域212(包圍有效區域211之未形成元件之區域)對準。 Next, in step S17, alignment of the photographed device wafer 210 is performed. For example, based on the alignment marks set in advance on the element wafer 210, the effective area 211 of the element wafer 210 (the area where the element is formed, see FIG. 4) and the peripheral area 212 (the area surrounding the effective area 211 where the element is not formed) are aligned with each other. allow.

接著，於步驟S18中，將所拍攝之良品元件晶片210之圖像(良品圖像P)分配給圖案A~D之每一者並記憶於記憶部50。 Next, in step S18 , the photographed image of the good-quality element wafer 210 (good-quality image P) is assigned to each of the patterns A to D and stored in the memory unit 50 .

接著，於步驟S19中，判斷目標之所有良品元件晶片210之拍攝等是否已結束。於判斷為目標之所有良品元件晶片210之拍攝等未結束之情形時，返回至步驟S14。於判斷為目標之所有良品元件晶片210之拍攝等已結束之情形時，進行至步驟S20。 Next, in step S19, it is determined whether the photographing and the like of all the good-quality component wafers 210 of the target have ended. When it is determined that the photographing of all the good-quality device wafers 210 that are the target has not been completed, the process returns to step S14. When it is determined that the photographing of all the good-quality device wafers 210 that are the target has ended, the process proceeds to step S20.

另，上述步驟S14~步驟S19之動作係於晶圓220與攝像部40相對移動之狀態連續進行。例如，如圖6之路徑B所示，以一筆劃狀地拍攝設置於晶圓220上之複數個元件晶片210之方式使晶圓220與攝像部40相對移動。具體而言，晶圓220對於攝像部40朝Y1方向相對移動，並進行沿著Y方向配置之複數個元件晶片210之拍攝(及識別、登錄、對準、登錄)。接著，於配置於Y1方向側端部之元件晶片210之拍攝結束後，使晶圓220對於攝像部40朝X1方向相對移動1個元件晶片210之大小之量。隨後，晶圓220對於攝像部40朝Y2方向相對移動，並進行沿著Y方向配置之複數個元件晶片210之拍攝。接著，於配置於Y2方向側端部之元件晶片210之拍攝結束後，使晶圓220對於攝像部40朝X1方向相對移動1個元件晶片210之大小之量。隨後，反覆上述動作。 In addition, the operations of the above-mentioned steps S14 to S19 are continuously performed in a state in which the wafer 220 and the imaging unit 40 are relatively moved. For example, as shown in the route B of FIG. 6 , the wafer 220 and the imaging unit 40 are moved relative to each other so as to photograph a plurality of device chips 210 disposed on the wafer 220 in a stroke-like manner. Specifically, the wafer 220 is relatively moved in the Y1 direction with respect to the imaging unit 40 , and imaging (and identification, registration, alignment, and registration) of a plurality of element wafers 210 arranged along the Y direction is performed. Next, after the imaging of the element wafer 210 arranged at the end portion in the Y1 direction is completed, the wafer 220 is moved relative to the imaging unit 40 in the X1 direction by the size of one element wafer 210 . Then, the wafer 220 is relatively moved in the Y2 direction with respect to the imaging unit 40, and a plurality of element wafers 210 arranged along the Y direction are photographed. Next, after the imaging of the element wafer 210 arranged at the end portion in the Y2 direction is completed, the wafer 220 is moved relative to the imaging unit 40 in the X1 direction by the size of one element wafer 210 . Then, the above-mentioned actions are repeated.

接著，於步驟S20中，產生良品圖像P(訓練資料)。具體而言，於圖案A~D之每一者各自記憶(保存)複數個良品元件晶片210之圖像。接著，於對每個像素加上良品元件晶片210之圖像之亮度值後予以平均化。該加法運算及平均化於圖案A~D之每一者個別地進行。藉此，於圖案A~D產生良品圖像P(良品圖像P1~P4)。 Next, in step S20, a good image P (training data) is generated. Specifically, images of a plurality of good-quality device chips 210 are respectively memorized (saved) in each of the patterns A to D. As shown in FIG. Next, the luminance value of the image of the good component wafer 210 is added to each pixel and averaged. The addition and averaging are performed individually for each of patterns A-D. Thereby, the good images P (good images P1 to P4 ) are generated in the patterns A to D. FIG.

接著，於步驟S21中，將晶圓220收納於特定之位置，良品圖像P之產生動作結束。 Next, in step S21, the wafer 220 is accommodated in a specific position, and the operation of generating the good product image P is completed.

<元件晶片之檢查> <Inspection of device wafer>

參照圖10及圖11，對元件晶片210之檢查動作(流程)進行說明。另，元件晶片210之檢查由檢查部61(控制部60)進行。 10 and 11, the inspection operation (flow) of the element wafer 210 will be described. In addition, the inspection of the element wafer 210 is performed by the inspection part 61 (control part 60).

首先，於步驟S31中，自記憶部50讀出檢查條件。檢查條件係於上述步驟S4中登錄者。 First, in step S31 , the inspection conditions are read out from the memory unit 50 . The inspection conditions are those registered in the above-mentioned step S4.

接著，於步驟S32中搬送晶圓220。具體而言，晶圓220載置於移動載台10(載置平台30)。又，於晶圓220係以具有互不相同之圖案之複數個元件晶片210混合存在之狀態配置。另，配置於晶圓220之複數個元件晶片210可被劃線亦可不被劃線。 Next, in step S32, the wafer 220 is transferred. Specifically, the wafer 220 is placed on the moving stage 10 (the placement stage 30 ). In addition, the wafer 220 is arranged in a state where a plurality of device chips 210 having mutually different patterns coexist. In addition, the plurality of device chips 210 disposed on the wafer 220 may or may not be scribed.

接著，於步驟S33中，進行晶圓220(元件晶片210)之元件晶片210之全域對準。例如，確定元件晶片210之角度或中心位置等資訊。另，全域對準資訊於上述步驟S3中登錄。 Next, in step S33, global alignment of the device chips 210 of the wafer 220 (device chips 210) is performed. For example, information such as the angle or the center position of the component wafer 210 is determined. In addition, the global alignment information is registered in the above step S3.

接著，於步驟S34中，於目標(檢查對象)之元件晶片210之上方，使攝像部40相對移動。具體而言，藉由使晶圓220藉移動載台10移動，而將目標之元件晶片210配置於攝像部40之正下方。 Next, in step S34 , the imaging unit 40 is relatively moved above the target (inspection object) element wafer 210 . Specifically, by moving the wafer 220 by the moving stage 10 , the target device wafer 210 is placed directly below the imaging unit 40 .

接著，於步驟S35中，拍攝目標(檢查對象)之元件晶片210。元件晶片210係依元件晶片210逐一地拍攝。又，以晶圓220與攝像部40相對移動之狀態，依元件晶片210逐一連續地拍攝複數個元件晶片210。 Next, in step S35, the device wafer 210 of the target (inspection object) is photographed. The device wafers 210 are photographed one by one according to the device wafers 210 . In addition, in a state in which the wafer 220 and the imaging unit 40 are relatively moved, a plurality of element chips 210 are continuously photographed one by one according to the element chips 210 .

接著，於本實施形態中，於步驟S36中，辨識由攝像部40拍攝之檢查對象之元件晶片210之圖案之種類(圖案A~D)。於記憶部50預先記憶有設置於晶圓220上之任一位置之元件晶片210具有何種圖案A~D之晶片配置資訊。例如，設置於晶圓220上之任一位置之元件晶片210具有何種圖案係與元件晶片210之在晶圓220上之位置(座標)對應而記憶。接著，檢查部61基於記憶於記憶部50之晶片配置資訊識別由攝像部40拍攝之檢查用之元件晶片210之圖案之種類。例如，基於攝像部40對於晶圓220之位置資訊(座標)，辨識本次拍攝之元件晶片210之圖案對應於圖案A~D中之哪一種。 Next, in the present embodiment, in step S36 , the types of patterns (patterns A to D) of the device wafer 210 to be inspected captured by the imaging unit 40 are identified. The memory portion 50 pre-stores the chip arrangement information of which patterns A to D of the device chip 210 disposed at any position on the wafer 220 has. For example, the pattern of the device chip 210 disposed at any position on the wafer 220 is memorized in correspondence with the position (coordinate) of the device chip 210 on the wafer 220 . Next, the inspection unit 61 recognizes the image captured by the imaging unit 40 for inspection based on the chip arrangement information stored in the memory unit 50 . The type of the pattern of the device wafer 210 . For example, based on the position information (coordinates) of the imaging unit 40 with respect to the wafer 220 , it is identified which of the patterns A to D the pattern of the component wafer 210 photographed this time corresponds to.

接著，於步驟S37中，進行經拍攝之元件晶片210之對準。例如，基於預先設置於元件晶片210之對準標記，使元件晶片210之有效區域211(形成元件之區域，參照圖4)及周緣區域212(包圍有效區域211之未形成元件之區域)對準。 Next, in step S37, alignment of the imaged device wafer 210 is performed. For example, based on the alignment marks set in advance on the element wafer 210, the effective area 211 of the element wafer 210 (the area in which the element is formed, see FIG. 4) and the peripheral area 212 (the area in which the element is not formed surrounding the effective area 211) are aligned. .

接著，於步驟S38中，自記憶部50讀出具有對應於拍攝之檢查對象之元件晶片210之圖案之良品圖像P。例如，若拍攝之檢查對象之元件晶片210之圖案為圖案A，則自記憶部50讀出具有圖案A之良品圖像P1。即，與由攝像部40拍攝之檢查對象之元件晶片210之圖案對應而切換良品圖像P。 Next, in step S38 , the good product image P having the pattern corresponding to the photographed inspection object element wafer 210 is read out from the memory unit 50 . For example, if the photographed pattern of the device wafer 210 to be inspected is the pattern A, the good image P1 having the pattern A is read out from the memory unit 50 . That is, the good product image P is switched in accordance with the pattern of the element wafer 210 to be inspected captured by the imaging unit 40 .

接著，於步驟S39中，於本實施形態中，比較由攝像部40拍攝之檢查對象之元件晶片210之圖像、與經識別之檢查對象之元件晶片210之圖案所對應之良品圖像P，藉此進行檢查對象之元件晶片210是否為良品之判別。例如，比較所拍攝之具有圖案A之檢查對象之元件晶片210之圖像、與具有圖案A之良品圖像P1。具體而言，比較兩個圖像之每一像素之亮度值。且，於比較之亮度值之差相對較大之情形時，檢查對象之元件晶片210之圖像與良品圖像P1之圖像不同。於該情形時，有於檢查對象之元件晶片210之亮度值之差相對較大之部分產生缺陷之情形。例如，如圖11所示之元件晶片210，於元件晶片210有缺陷213之情形時，於對應於缺陷213之像素中，與良品圖像P1之亮度值之差增大。因此，於比較之亮度值之差相對較大之情形時，判斷檢查對象之元件晶片210並非良品(不良品)。 Next, in step S39, in this embodiment, the image of the component wafer 210 to be inspected captured by the imaging unit 40 is compared with the image P of the good product corresponding to the pattern of the identified pattern of the component wafer 210 to be inspected, Thereby, it is judged whether the component wafer 210 to be inspected is a good product. For example, a photographed image of the component wafer 210 of the inspection object having the pattern A is compared with the good image P1 having the pattern A. Specifically, the luminance value of each pixel of the two images is compared. In addition, when the difference between the compared luminance values is relatively large, the image of the device wafer 210 to be inspected is different from the image of the good product image P1. In this case, a defect may occur in a portion where the difference in luminance value of the element wafer 210 to be inspected is relatively large. For example, in the device wafer 210 shown in FIG. 11, when the device wafer 210 has a defect 213, the difference between the luminance value of the pixel corresponding to the defect 213 and the good image P1 increases. Therefore, when the difference between the compared luminance values is relatively large, it is determined that the device wafer 210 to be inspected is not a good product (defective). Taste).

又，結束由檢查部61判別是否為良品之檢查用元件晶片210之圖像於每當檢查用之元件晶片210是否為良品之判別結束時予以刪除。藉此，可抑制記憶於記憶體(未圖示)之元件晶片210之資料容量增大。 In addition, the image of the inspection element wafer 210 for which the inspection part 61 has completed the determination of whether or not it is a good product is deleted every time the determination of whether or not the inspection element wafer 210 is a good product is completed. Thereby, the data capacity of the device chip 210 stored in the memory (not shown) can be suppressed from increasing.

接著，於步驟S40中，判斷所有檢查對象之元件晶片210之檢查是否結束。於判斷為所有檢查對象之元件晶片210之檢查未結束之情形時，返回至步驟S34。另，上述步驟S34~步驟S40之動作係於晶圓220與攝像部40相對移動之狀態連續進行。例如，如圖6之路徑B所示，以一筆劃狀地拍攝設置於晶圓220上之複數個元件晶片210之方式使晶圓220與攝像部40相對移動。藉此，由於可使晶圓220與攝像部40不進行如遵照路徑之無用之移動地作相對移動，故可縮短所有元件晶片210之拍攝所需之時間。另，晶圓220與攝像部40之相對移動之動作與上述良品圖像作成時之動作相同。如此，於本實施形態中，構成為依序對設置於晶圓220之複數個檢查用之元件晶片210之每一者進行：以晶圓220與攝像部40相對移動之狀態，進行以攝像部40拍攝檢查用之元件晶片210；以檢查部61識別所拍攝之檢查用之元件晶片210之圖案種類；將良品圖像P切換為具有與經識別之檢查用之元件晶片210之圖案對應之圖案的良品圖像P；及比較檢查用之元件晶片210之圖像與良品圖像P而進行元件晶片210是否為良品之判別。 Next, in step S40, it is determined whether the inspection of all the device wafers 210 to be inspected is completed. When it is determined that the inspection of all the device wafers 210 to be inspected has not ended, the process returns to step S34. In addition, the operations of the above steps S34 to S40 are continuously performed in a state in which the wafer 220 and the imaging unit 40 are relatively moved. For example, as shown in the route B of FIG. 6 , the wafer 220 and the imaging unit 40 are moved relative to each other so as to photograph a plurality of device chips 210 disposed on the wafer 220 in a stroke-like manner. Thereby, since the wafer 220 and the imaging unit 40 can be moved relative to each other without unnecessary movement according to the path, the time required for imaging of all the element wafers 210 can be shortened. In addition, the relative movement of the wafer 220 and the imaging unit 40 is the same as the above-mentioned operation when the good product image is created. In this way, in the present embodiment, it is configured such that each of the plurality of inspection component wafers 210 set on the wafer 220 is sequentially performed: the imaging section is performed in a state in which the wafer 220 and the imaging section 40 are relatively moved. 40 Photograph the element wafer 210 for inspection; identify the pattern type of the element wafer 210 for inspection photographed by the inspection section 61 ; switch the good image P to have a pattern corresponding to the identified pattern of the element wafer 210 for inspection and compare the image of the component wafer 210 for inspection with the good product image P to determine whether the component wafer 210 is a good product.

又，於步驟S40中，於判斷所有之檢查對象之元件晶片210之檢查結束之情形時，進行至步驟S41。 Moreover, in step S40, when it is judged that the inspection of all the component wafers 210 to be inspected has ended, the process proceeds to step S41.

接著，於步驟S41中，將晶圓220收納於特定之位置，檢查對象之元件晶片210之檢查動作結束。 Next, in step S41, the wafer 220 is accommodated in a specific position, and the inspection operation of the device wafer 210 to be inspected ends.

(本實施形態之效果) (Effect of this embodiment)

接著，對本實施形態之效果進行說明。 Next, the effects of this embodiment will be described.

於本實施形態中，如上所述，具備檢查部61，其識別由攝像部40拍攝之檢查對象之元件晶片210之圖案A~D之種類，且比較由攝像部40拍攝之檢查對象之元件晶片210之圖像、與經識別之檢查對象之元件晶片210之圖案(A~D)所對應之良品圖像P，藉此進行檢查對象之元件晶片210是否為良品之判別。藉此，由於由檢查部61識別所拍攝之檢查對象之元件晶片210之圖案種類，故可依拍攝之檢查對象之元件晶片210之每一者，自記憶部50讀出拍攝之檢查對象之元件晶片210之圖案所對應之良品圖像P。其結果，於具有互不相同之圖案之複數個元件晶片210混合存在之狀態下，無須反覆以攝像部40拍攝複數個元件晶片210(攝像部40之掃描)，而可藉由1次之掃描進行元件晶片210是否為良品之判別。藉此，於具有互不相同之圖案之複數個元件晶片210混合存在之狀態下，可縮短檢查所需之時間。 In the present embodiment, as described above, the inspection unit 61 is provided, which recognizes the types of patterns A to D of the component wafer 210 to be inspected photographed by the imaging unit 40 and compares the component wafers to be inspected photographed by the imaging unit 40 The image of 210 and the good product image P corresponding to the pattern (A to D) of the identified inspection object element wafer 210 are used to judge whether the inspection object element wafer 210 is a good product. Thereby, since the pattern type of the photographed inspection object element wafer 210 is recognized by the inspection unit 61 , the photographed inspection object element can be read from the memory unit 50 according to each of the photographed inspection object element wafers 210 . The good image P corresponding to the pattern of the wafer 210 . As a result, in a state where a plurality of element wafers 210 having mutually different patterns coexist, it is not necessary to repeatedly photograph the plurality of element wafers 210 with the imaging unit 40 (scanning of the imaging unit 40 ), but one scan can be performed. Whether the device wafer 210 is a good product is judged. Accordingly, in a state where a plurality of element wafers 210 having mutually different patterns coexist, the time required for inspection can be shortened.

又，於本實施形態中，如上所述，構成為複數個元件晶片210設置於晶圓220上，且於記憶部50預先記憶有設置於晶圓220上之任一位置之元件晶片210具有何種圖案之晶片配置資訊，檢查部61基於記憶於記憶部50之晶片配置資訊，識別由攝像部40拍攝之檢查用之元件晶片210之圖案種類。藉此，於記憶部50預先記憶有設置於晶圓220上之任一位置之元件晶片210具有何種圖案之晶片配置資訊，因而與藉由圖像辨識(圖像彼此之比較)等辨識所拍攝之檢查用之元件晶片210之圖案對應於何一良品圖像P之情形相比，可進一步縮短檢查所需之時間。 Furthermore, in the present embodiment, as described above, a plurality of device chips 210 are arranged on the wafer 220 , and the memory unit 50 stores in advance what the device chips 210 arranged at any position on the wafer 220 have. The inspection unit 61 recognizes the pattern type of the element wafer 210 for inspection photographed by the imaging unit 40 based on the wafer configuration information stored in the memory unit 50 . In this way, the chip arrangement information of which pattern the device chip 210 disposed at any position on the wafer 220 has is pre-stored in the memory portion 50 , which is different from the image recognition (comparison of images with each other) and the like. Compared with the case where the photographed pattern of the component wafer 210 for inspection corresponds to any good product image P, the time required for inspection can be further shortened.

又，於本實施形態中，如上所述，於晶圓220上設置複數個各自包含分別形成有互不相同之圖案之複數個元件晶片210之元件晶片群230，且元件晶片群230之分別形成有互不相同之圖案之複數個元件晶片210之配置位置於元件晶片群230各者中均相同，於記憶部50預先記憶有包含複數個元件晶片群230之複數個元件晶片210之晶片配置資訊。藉此，由於複數個元件晶片210之配置位置於元件晶片群230之各者中均相同，故可使用相同之遮罩(未圖示)於每一個元件晶片群230形成元件晶片210。 Furthermore, in the present embodiment, as described above, a plurality of the The element wafer group 230 of the plurality of element wafers 210 having mutually different patterns formed respectively, and the arrangement positions of the plurality of element wafers 210 having mutually different patterns respectively formed in the element wafer group 230 are in each of the element wafer groups 230 The same as in the above, the chip configuration information of the plurality of device chips 210 including the plurality of device chip groups 230 is pre-stored in the memory unit 50 . Thus, since the arrangement positions of the plurality of device wafers 210 are the same in each of the device wafer groups 230 , the same mask (not shown) can be used to form the device wafers 210 in each device wafer group 230 .

又，於本實施形態中，如上所述，構成為依序對設置於晶圓220上之複數個檢查用之元件晶片210之每一者進行：以晶圓220與攝像部40相對移動之狀態，進行以攝像部40拍攝檢查用之元件晶片210；以檢查部61識別所拍攝之檢查用之元件晶片210之圖案種類；將良品圖像P切換為具有與經識別之檢查用之元件晶片210之圖案對應之圖案的良品圖像P；及比較檢查用之元件晶片210之圖像與良品圖像P而進行元件晶片210是否為良品之判別。藉此，於具有互不相同之圖案之複數個元件晶片210混合存在之狀態下，亦可連續順利地進行複數個元件晶片210之檢查。 Furthermore, in the present embodiment, as described above, it is configured such that the wafer 220 and the imaging unit 40 are relatively moved for each of the plurality of component wafers 210 for inspection provided on the wafer 220 in sequence. , to photograph the component wafer 210 for inspection with the imaging unit 40 ; identify the pattern type of the photographed component wafer 210 for inspection with the inspection unit 61 ; switch the good image P to the component wafer 210 with the identified component wafer 210 for inspection A good product image P of the pattern corresponding to the pattern; and comparing the image of the component wafer 210 for inspection with the good product image P to determine whether the component wafer 210 is a good product. In this way, in a state where a plurality of device wafers 210 having mutually different patterns coexist, the inspection of the plurality of device wafers 210 can be performed continuously and smoothly.

[變化例] [Variation example]

另，應理解本次揭示之實施形態及實施例係所有方面均為例示而非限制性者。本發明之範圍由申請專利範圍表示而非上述之實施形態及實施例之說明，再者，亦包含與專利申請範圍均等之涵義及範圍內之所有變更(變化例)。 In addition, it should be understood that the embodiments and examples disclosed this time are illustrative and non-restrictive in all respects. The scope of the present invention is indicated by the scope of the patent application rather than the description of the above-mentioned embodiments and examples, and also includes the meaning equivalent to the scope of the patent application and all changes (modifications) within the scope.

例如，於上述實施形態中，顯示檢查部61包含於控制部60之例，但本發明並非限定於此。例如，檢查部61可與控制部60個別地設置。 For example, in the above-described embodiment, the example in which the inspection unit 61 is included in the control unit 60 is displayed, but the present invention is not limited to this. For example, the inspection unit 61 may be provided separately from the control unit 60 .

又，於上述實施形態中，顯示互不相同之4個圖案之元件晶片210混合存在之例，但本發明並非限定於此。例如，元件晶片210之圖案之數量可為4個以外之數量。 In addition, in the said embodiment, although the element wafer 210 which showed 4 mutually different patterns coexisted, this invention is not limited to this. For example, the number of patterns of the device wafer 210 Can be any number other than 4.

又，於上述實施形態中，顯示於記憶部50預先記憶有設置於晶圓220上之任一位置之元件晶片210具有何種圖案之晶片配置資訊之例，但本發明並非限定於此。例如，可於每當拍攝元件晶片210時，比較所拍攝之檢查用之元件晶片210之圖像、與複數個良品圖像P，而識別所拍攝之檢查用之元件晶片210之圖案與複數個良品圖像P中之哪一種圖案一致。 In addition, in the above-mentioned embodiment, the memory unit 50 pre-stores the chip arrangement information of which pattern the device chip 210 disposed at any position on the wafer 220 has, but the present invention is not limited to this. For example, every time the element wafer 210 is photographed, the photographed image of the element wafer 210 for inspection can be compared with a plurality of good images P, and the pattern of the element wafer 210 for inspection photographed and a plurality of images can be identified. Which of the patterns in the good product images P matches.

又，於上述實施形態中，顯示元件晶片群230之分別形成有互不相同之圖案之複數個元件晶片210之配置位置於元件晶片群230各者中均相同之例，但本發明並非限定於此。例如，元件晶片群230之分別形成有互不相同之圖案之複數個元件晶片210之配置位置可於每個元件晶片群230不同。 Moreover, in the above-mentioned embodiment, the arrangement position of the plurality of element chips 210 having mutually different patterns formed in the element wafer group 230 is shown to be the same in each element wafer group 230, but the present invention is not limited to this. For example, the arrangement positions of the plurality of element wafers 210 having mutually different patterns formed in the element wafer group 230 may be different for each element wafer group 230 .

又，於上述實施形態中，顯示檢查設置於晶圓220上之元件晶片210之例，但本發明並非限定於此。例如，可檢查不設置於晶圓220上之元件晶片210。 In addition, in the above-described embodiment, the example of inspecting the element wafer 210 provided on the wafer 220 is shown, but the present invention is not limited to this. For example, the device wafer 210 not disposed on the wafer 220 can be inspected.

10:移動載台 10: Mobile stage

11:X軸滑塊 11: X-axis slider

12:Y軸滑塊 12: Y-axis slider

20:基台部 20: Abutment part

30:載置平台 30: Placing the platform

40:攝像部 40: Camera Department

41:鏡筒 41: Lens barrel

42:半反射鏡 42: Half mirror

43:對物透鏡 43: Object lens

44:攝像相機 44: Camcorder

44a:受光元件 44a: light receiving element

50:記憶部 50: Memory Department

60:控制部 60: Control Department

61:檢查部 61: Inspection Department

100:外觀檢查裝置 100: Appearance inspection device

220:晶圓(基板) 220: Wafer (substrate)

X:方向 X: direction

Y:方向 Y: direction

Z:方向 Z: direction

Claims

一種外觀檢查方法，其係使用如下之外觀檢查裝置進行檢查者，該外觀檢查裝置係於具有互不相同之圖案之複數個元件晶片混合存在之狀態，分別檢查複數個上述元件晶片，且具備：攝像部，其拍攝檢查對象之上述元件晶片；記憶部，其預先記憶有成為互不相同之圖案之上述元件晶片之檢查基準的良品圖像；及檢查部，其識別由上述攝像部拍攝之檢查對象之上述元件晶片之圖案種類，且比較由上述攝像部拍攝之檢查對象之上述元件晶片之圖像、與經識別之檢查對象之上述元件晶片之圖案所對應之上述良品圖像，藉此進行檢查對象之上述元件晶片是否為良品之判別；其中複數個上述元件晶片設置於基板上，於上述記憶部預先記憶有設置於上述基板上之任一位置之上述元件晶片具有何種圖案之晶片配置資訊，上述檢查部構成為基於記憶於上述記憶部之上述晶片配置資訊，識別由上述攝像部拍攝之檢查用之上述元件晶片之圖案種類；且上述外觀檢查方法係構成為依序對設置於上述基板上之複數個檢查用之上述元件晶片之每一者進行：以上述基板與上述攝像部相對移動之狀態，由上述攝像部拍攝檢查用之上述元件晶片；由上述檢查部識別經拍攝之檢查用之上述元件晶片之圖案種類；將上述良品圖像切換為具有與經識別之檢查用之上述元件晶片之圖案對應之圖案的上述良品圖像；及藉由比較檢查用之上述元件晶片之圖像與上述良品圖像而進行上述元件晶片是否為良品之判別。 A visual inspection method, which uses the following visual inspection apparatus for inspection, the visual inspection apparatus is in a state where a plurality of element wafers having mutually different patterns coexist, respectively inspects a plurality of the above-mentioned element wafers, and has: an imaging unit for photographing the above-mentioned element wafers to be inspected; a memory unit for pre-recording images of good products serving as inspection standards for the above-mentioned element wafers having patterns different from each other; and an inspection unit for recognizing the inspections photographed by the above-mentioned imaging unit The pattern type of the above-mentioned element wafer of the object is compared, and the image of the above-mentioned element wafer of the inspection object photographed by the above-mentioned imaging unit is compared with the recognized image of the above-mentioned good product corresponding to the pattern of the above-mentioned element wafer of the inspection object. To determine whether the above-mentioned component wafers to be inspected are good products; wherein a plurality of the above-mentioned component wafers are arranged on a substrate, and the memory portion pre-stores the chip arrangement of which pattern the above-mentioned component wafers arranged at any position on the above-mentioned substrate have. information, the inspection unit is configured to identify the pattern type of the element wafer for inspection photographed by the imaging unit based on the wafer arrangement information stored in the memory unit; and the appearance inspection method is configured to sequentially pair the Each of a plurality of the above-mentioned element wafers for inspection on a substrate is performed: the above-mentioned element wafers for inspection are photographed by the above-mentioned imaging unit in a state in which the above-mentioned substrate and the above-mentioned imaging unit are relatively moved; and the photographed inspection is recognized by the above-mentioned inspection unit. The pattern type of the above-mentioned element wafer used; the above-mentioned good product image is switched to the above-mentioned good product image having a pattern corresponding to the pattern of the above-mentioned element wafer used for inspection; and the image of the above-mentioned element wafer used for inspection is compared by comparing Whether the above-mentioned device wafer is carried out like the above-mentioned good product image For the judgment of good quality.

一種外觀檢查方法，其係使用如下之外觀檢查裝置進行檢查者，該外觀檢查裝置係於具有互不相同之圖案之複數個元件晶片混合存在之狀態，分別檢查複數個上述元件晶片，且具備：攝像部，其拍攝檢查對象之上述元件晶片；記憶部，其預先記憶有成為互不相同之圖案之上述元件晶片之檢查基準的良品圖像；及檢查部，其識別由上述攝像部拍攝之檢查對象之上述元件晶片之圖案種類，且比較由上述攝像部拍攝之檢查對象之上述元件晶片之圖像、與經識別之檢查對象之上述元件晶片之圖案所對應之上述良品圖像，藉此進行檢查對象之上述元件晶片是否為良品之判別；其中複數個上述元件晶片設置於基板上，於上述記憶部預先記憶有設置於上述基板上之任一位置之上述元件晶片具有何種圖案之晶片配置資訊，上述檢查部構成為基於記憶於上述記憶部之上述晶片配置資訊，識別由上述攝像部拍攝之檢查用之上述元件晶片之圖案種類；其中於上述基板上設置有複數個各自包含分別形成有互不相同之圖案之複數個上述元件晶片之元件晶片群，上述元件晶片群之分別形成有互不相同之圖案之複數個上述元件晶片之配置位置於上述元件晶片群各者中均相同，於上述記憶部預先記憶有包含複數個上述元件晶片群之複數個上述元件晶片之上述晶片配置資訊；且上述外觀檢查方法係構成為依序對設置於上述基板上之複數個檢查用之上述元件晶片之每一者進行：以上述基板與上述攝像部相對移動之狀態，由上述攝像部拍攝檢查用之上述元件晶片；由上述檢查部識別經拍攝之檢查用之上述元件晶片之圖案種類；將上述良品圖像切換為具有與經識別之檢查用之上述元件晶片之圖案對應之圖案的上述良品圖像；及藉由比較檢查用之上述元件晶片之圖像與上述良品圖像而進行上述元件晶片是否為良品之判別。 A visual inspection method, which uses the following visual inspection apparatus for inspection, the visual inspection apparatus is in a state where a plurality of element wafers having mutually different patterns coexist, respectively inspects a plurality of the above-mentioned element wafers, and has: an imaging unit for photographing the above-mentioned element wafers to be inspected; a memory unit for pre-recording images of good products serving as inspection standards for the above-mentioned element wafers having patterns different from each other; and an inspection unit for recognizing the inspections photographed by the above-mentioned imaging unit The pattern type of the above-mentioned element wafer of the object is compared, and the image of the above-mentioned element wafer of the inspection object photographed by the above-mentioned imaging unit is compared with the recognized image of the above-mentioned good product corresponding to the pattern of the above-mentioned element wafer of the inspection object. To determine whether the above-mentioned component wafers to be inspected are good products; wherein a plurality of the above-mentioned component wafers are arranged on a substrate, and the memory portion pre-stores the chip arrangement of which pattern the above-mentioned component wafers arranged at any position on the above-mentioned substrate have. information, the inspection unit is configured to recognize the pattern type of the element wafer for inspection photographed by the imaging unit based on the wafer configuration information stored in the memory unit; wherein the substrate is provided with a plurality of The device wafer group of a plurality of the above-mentioned device wafers with mutually different patterns, and the arrangement positions of the plurality of the above-mentioned device wafers having mutually different patterns respectively formed in the above-mentioned device wafer group are the same in each of the above-mentioned device wafer groups, in The memory unit pre-stores the chip configuration information of the plurality of the device chips including the plurality of the device chip groups; and The above-mentioned appearance inspection method is configured to sequentially perform each of a plurality of the above-mentioned element wafers for inspection provided on the above-mentioned substrate: in a state in which the above-mentioned substrate and the above-mentioned imaging unit are relatively moved, the above-mentioned imaging unit photographs and inspects each of the above-mentioned element wafers. The above-mentioned element wafer; the pattern type of the above-mentioned element wafer for inspection photographed by the inspection unit is recognized; the above-mentioned good product image is switched to the above-mentioned good product image having a pattern corresponding to the identified pattern of the above-mentioned element wafer for inspection ; and by comparing the image of the above-mentioned component wafer for inspection with the above-mentioned good product image to judge whether the above-mentioned component wafer is a good product or not.