TWI755277B

TWI755277B - High electron mobility transistor and fabrication method thereof

Info

Publication number: TWI755277B
Application number: TW110104852A
Authority: TW
Inventors: 林永豐; 周鈺傑; 林琮翔; 莊理文
Original assignee: 世界先進積體電路股份有限公司
Priority date: 2021-02-09
Filing date: 2021-02-09
Publication date: 2022-02-11
Also published as: TW202232754A

Abstract

A high electron mobility transistor includes a semiconductor channel layer, a semiconductor barrier layer, a patterned semiconductor protection layer, a patterned semiconductor capping layer, an interlayer dielectric layer, and a gate electrode. The semiconductor channel layer and the semiconductor barrier layer are disposed on the substrate. The patterned semiconductor protection layer is disposed on the semiconductor barrier layer, and the patterned semiconductor capping layer is disposed between the patterned semiconductor protection layer and the semiconductor barrier layer. The interlayer dielectric layer covers the patterned semiconductor capping layer and the patterned semiconductor protection layer, and the interlayer dielectric layer includes a gate contact hole. The gate electrode is disposed in the gate contact hole and electrically coupled to the patterned semiconductor capping layer, where a portion of the patterned semiconductor protection layer is disposed between the gate electrode and the patterned semiconductor capping layer. The resistivity of the patterned semiconductor protection layer is between the resistivity of the patterned semiconductor capping layer and the resistivity of the interlayer dielectric layer.

Description

高電子遷移率電晶體及其製作方法 High electron mobility transistor and method of making the same

本揭露涉及電晶體的領域，特別是涉及一種高電子遷移率電晶體及其製作方法。 The present disclosure relates to the field of transistors, and in particular, to a high electron mobility transistor and a fabrication method thereof.

在半導體技術中，III-V族的半導體化合物可用於形成各種積體電路裝置，例如：高功率場效電晶體、高頻電晶體或高電子遷移率電晶體(high electron mobility transistor,HEMT)。HEMT是屬於具有二維電子氣(two dimensional electron gas,2DEG)的一種電晶體，其2DEG會鄰近於能隙不同的兩種材料之間的接合面(亦即，異質接合面)。由於HEMT並非使用摻雜區域作為電晶體的載子通道，而是使用2DEG作為電晶體的載子通道，因此相較於習知的金氧半場效電晶體(MOSFET)，HEMT具有多種吸引人的特性，例如：高電子遷移率及以高頻率傳輸信號之能力。對於習知的HEMT，可以包括依序堆疊的化合物半導體通道層、化合物半導體阻障層、P型化合物半導體蓋層、金屬蓋層、及閘極電極。利用閘極電極向P型化合物半導體蓋層施加偏壓，可以調控位於P型化合物半導體蓋層下方的化合物半導體通道層中的二維電子氣濃度，進而調控HEMT的開關。 In semiconductor technology, group III-V semiconductor compounds can be used to form various integrated circuit devices, such as high power field effect transistors, high frequency transistors or high electron mobility transistors (HEMTs). A HEMT is a transistor with two dimensional electron gas (2DEG), and the 2DEG is adjacent to a junction (ie, a heterojunction) between two materials with different energy gaps. Since the HEMT does not use the doped region as the carrier channel of the transistor, but uses the 2DEG as the carrier channel of the transistor, compared with the conventional MOSFET, HEMT has various attractive properties. Characteristics such as high electron mobility and the ability to transmit signals at high frequencies. For a conventional HEMT, a compound semiconductor channel layer, a compound semiconductor barrier layer, a P-type compound semiconductor capping layer, a metal capping layer, and a gate electrode may be sequentially stacked. Using the gate electrode to bias the P-type compound semiconductor cap layer, the two-dimensional electron gas concentration in the compound semiconductor channel layer under the P-type compound semiconductor cap layer can be regulated, thereby regulating the switching of the HEMT.

對於設置於P型化合物半導體蓋層及閘極電極之間的金屬蓋層而言，製作此金屬蓋層的步驟通常會包括濕式的側向蝕刻製程。然而，由於側向蝕刻製程的蝕刻程度難以被精確控制，因此會導致各HEMT的金屬蓋層具有不同的寬度，進而降低了各HEMT的電性表現的一致性。 For the metal cap layer disposed between the P-type compound semiconductor cap layer and the gate electrode, the step of forming the metal cap layer usually includes a wet side etching process. However, due to the lateral The etching degree of the etching process is difficult to precisely control, so that the metal cap layers of each HEMT have different widths, thereby reducing the uniformity of the electrical performance of each HEMT.

有鑑於此，有必要提出一種改良的高電子遷移率電晶體，以改善習知高電子遷移率電晶體所存在之缺失。 In view of this, it is necessary to propose an improved high electron mobility transistor to improve the shortcomings of the conventional high electron mobility transistor.

根據本揭露的一實施例，係提供一種高電子遷移率電晶體，包括半導體通道層、半導體阻障層、圖案化半導體保護層、圖案化半導體蓋層、層間介電層、及閘極電極。半導體通道層及半導體阻障層設置於基底上。圖案化半導體保護層設置於半導體阻障層上，且圖案化半導體蓋層設置於圖案化半導體保護層及半導體阻障層之間。層間介電層覆蓋圖案化半導體蓋層及圖案化半導體保護層，且層間介電層包括閘極接觸洞。閘極電極設置於閘極接觸洞內且電連接該圖案化半導體蓋層，其中閘極電極及圖案化半導體蓋層之間存在圖案化半導體保護層。圖案化半導體保護層的電阻率介於圖案化半導體蓋層的電阻率及層間介電層的電阻率之間。 According to an embodiment of the present disclosure, a high electron mobility transistor is provided, including a semiconductor channel layer, a semiconductor barrier layer, a patterned semiconductor protective layer, a patterned semiconductor cap layer, an interlayer dielectric layer, and a gate electrode. The semiconductor channel layer and the semiconductor barrier layer are disposed on the substrate. The patterned semiconductor protective layer is disposed on the semiconductor barrier layer, and the patterned semiconductor capping layer is disposed between the patterned semiconductor protective layer and the semiconductor barrier layer. The interlayer dielectric layer covers the patterned semiconductor capping layer and the patterned semiconductor protective layer, and the interlayer dielectric layer includes a gate contact hole. The gate electrode is arranged in the gate contact hole and is electrically connected to the patterned semiconductor cap layer, wherein a patterned semiconductor protective layer exists between the gate electrode and the patterned semiconductor cap layer. The resistivity of the patterned semiconductor protective layer is between the resistivity of the patterned semiconductor capping layer and the resistivity of the interlayer dielectric layer.

根據本揭露的另一實施例，係提供一種高電子遷移率電晶體的製作方法，包括：提供基底，其上依序設置有一半導體通道層、一半導體阻障層、一半導體蓋層、以及一半導體保護層；蝕刻半導體蓋層及半導體保護層，以形成圖案化半導體蓋層及圖案化半導體保護層；形成層間介電層，覆蓋住圖案化半導體蓋層及圖案化半導體保護層；形成閘極接觸洞於層間介電層中，其中閘極接觸洞的底面會暴露出圖案化半導體保護層且分離於圖案化半導體蓋層；以及形成閘極電極於閘極接觸洞中，其中閘極電極及圖案化半導體蓋層之間存在部分的圖案化半導體保護層，其中，圖案化半導體保護層的電阻率介於圖案化半導體蓋層的電阻率及層間介電層的電阻率之間。 According to another embodiment of the present disclosure, a method for fabricating a high electron mobility transistor is provided, including: providing a substrate on which a semiconductor channel layer, a semiconductor barrier layer, a semiconductor cap layer, and a semiconductor channel layer are sequentially disposed. Semiconductor protective layer; etching the semiconductor capping layer and the semiconductor protective layer to form a patterned semiconductor capping layer and a patterned semiconductor protective layer; forming an interlayer dielectric layer to cover the patterned semiconductor capping layer and the patterned semiconductor protective layer; forming a gate electrode A contact hole is in the interlayer dielectric layer, wherein the bottom surface of the gate contact hole exposes the patterned semiconductor protective layer and is separated from the patterned semiconductor cap layer; and a gate electrode is formed in the gate contact hole, wherein the gate electrode and Part of the patterned semiconductor protective layer exists between the patterned semiconductor cap layers, wherein the resistivity of the patterned semiconductor cap layer is between the resistivity of the patterned semiconductor cap layer and the resistivity of the interlayer dielectric layer.

根據本揭露的實施例，由於圖案化半導體保護層的電阻率高於上方閘極電極的電阻率，因此即便不對圖案化半導體保護層的側面進行側向蝕刻，圖案化半導體保護層的側面也不易產生尖端放電，藉此可以避免不必要的閘極漏電流。再者，由於在製作閘極接觸洞時，閘極接觸洞的底面不會穿透圖案化半導體保護層，因此可以避免蝕刻劑接觸圖案化半導體蓋層，而可維持圖案化半導體蓋層的原始電特性。 According to the embodiments of the present disclosure, since the resistivity of the patterned semiconductor protective layer is higher than that of the upper gate electrode, even if the side surfaces of the patterned semiconductor protective layer are not etched sideways, the side surfaces of the patterned semiconductor protective layer are not easily etched. A tip discharge is generated, whereby unnecessary gate leakage current can be avoided. Furthermore, when the gate contact hole is fabricated, the bottom surface of the gate contact hole will not penetrate the patterned semiconductor protective layer, so the etchant can be prevented from contacting the patterned semiconductor capping layer, and the original pattern of the patterned semiconductor capping layer can be maintained. electrical characteristics.

10-1:高電子遷移率電晶體 10-1: High Electron Mobility Transistors

10-2:高電子遷移率電晶體 10-2: High Electron Mobility Transistors

10-3:高電子遷移率電晶體 10-3: High Electron Mobility Transistors

20:半導體結構 20: Semiconductor Structure

102:基底 102: Substrate

104:緩衝層 104: Buffer layer

106:半導體通道層 106: Semiconductor channel layer

106a:二維電子氣區域 106a: two-dimensional electron gas region

106b:二維電子氣截斷區域 106b: Two-dimensional electron gas cut-off region

108:半導體阻障層 108: Semiconductor barrier layer

109:半導體蓋層 109: Semiconductor capping layer

110:圖案化半導體蓋層 110: Patterned semiconductor capping layer

111:半導體保護層 111: Semiconductor protective layer

110S:側面 110S: Side

110T:頂面 110T: Top surface

120:圖案化半導體保護層 120: Patterned semiconductor protective layer

120B:底面 120B: Bottom

120S:側面 120S: Side

122:第一部份 122: Part 1

124:第二部份 124: Part II

124T:頂面 124T: top surface

126:凹槽 126: Groove

126B:底面 126B: Bottom

126S:側面 126S: Side

128:遮罩層 128:Mask layer

130:層間介電層 130: Interlayer dielectric layer

132:閘極接觸洞 132: Gate contact hole

134:開孔 134: Opening

140:閘極電極 140: gate electrode

140C:底角 140C: Bottom corner

142:第一導電層 142: the first conductive layer

144:第二導電層 144: the second conductive layer

150:層間介電層 150: interlayer dielectric layer

152:源/汲極接觸洞 152: source/drain contact hole

152B:底面 152B: Bottom

154:源/汲極電極 154: source/drain electrodes

156:源/汲極電極 156: source/drain electrodes

160:鈍化層 160: Passivation layer

200:方法 200: Method

202:步驟 202: Steps

204:步驟 204: Steps

206:步驟 206: Steps

208:步驟 208: Steps

210:步驟 210: Steps

A:區域 A: area

D1:寬度 D1: width

D2:寬度 D2: width

D3:寬度 D3: width

D4:寬度 D4: width

T1:厚度 T1: Thickness

T2:厚度 T2: Thickness

為了使下文更容易被理解，在閱讀本揭露時可同時參考圖式及其詳細文字說明。透過本文中之具體實施例並參考相對應的圖式，俾以詳細解說本揭露之具體實施例，並用以闡述本揭露之具體實施例之作用原理。此外，為了清楚起見，圖式中的各特徵可能未按照實際的比例繪製，因此某些圖式中的部分特徵的尺寸可能被刻意放大或縮小。 In order to make the following easier to understand, reference is made to both the drawings and their detailed description while reading the present disclosure. The specific embodiments of the present disclosure will be explained in detail through the specific embodiments herein and the corresponding drawings will be referred to, and the working principles of the specific embodiments of the present disclosure will be described. Furthermore, for clarity, the features in the drawings may not be drawn to actual scale and thus the dimensions of some of the features in some of the drawings may be intentionally exaggerated or reduced in size.

第1圖是根據本揭露一實施例所繪示的高電子遷移率電晶體(HEMT)的剖面示意圖。 FIG. 1 is a schematic cross-sectional view of a high electron mobility transistor (HEMT) according to an embodiment of the present disclosure.

第2圖是根據本揭露一實施例所繪示的高電子遷移率電晶體的局部區域的放大剖面示意圖。 FIG. 2 is an enlarged cross-sectional schematic diagram of a partial region of a high electron mobility transistor according to an embodiment of the present disclosure.

第3圖是根據本揭露一變化型實施例所繪示的高電子遷移率電晶體的局部區域的放大剖面示意圖。 FIG. 3 is an enlarged schematic cross-sectional view of a partial region of a high electron mobility transistor according to a variant embodiment of the present disclosure.

第4圖是根據本揭露一變化型實施例所繪示的高電子遷移率電晶體的剖面示意圖。 FIG. 4 is a schematic cross-sectional view of a high electron mobility transistor according to a variant embodiment of the present disclosure.

第5圖是根據本揭露一實施例所繪示的製作高電子遷移率電晶體的剖面示意圖，其中包括依序堆疊的半導體層。 FIG. 5 is a schematic cross-sectional view of a high electron mobility transistor according to an embodiment of the present disclosure, which includes sequentially stacked semiconductor layers.

第6圖是根據本揭露一實施例所繪示的製作高電子遷移率電晶體的剖面示意圖，其中包括圖案化半導體蓋層、圖案化半導體保護層、及遮罩層。 FIG. 6 is a schematic cross-sectional view of a high electron mobility transistor according to an embodiment of the present disclosure, which includes a patterned semiconductor cap layer, a patterned semiconductor protective layer, and a mask layer.

第7圖是根據本揭露一實施例所繪示的製作高電子遷移率電晶體的剖面示意圖，其中包括設置於層間介電層中的閘極接觸洞。 FIG. 7 is a schematic cross-sectional view of a high electron mobility transistor according to an embodiment of the present disclosure, which includes a gate contact hole disposed in an interlayer dielectric layer.

第8圖是根據本揭露一實施例所繪示的製作高電子遷移率電晶體的剖面示意圖，其中包括閘極電極。 FIG. 8 is a schematic cross-sectional view of a high electron mobility transistor including a gate electrode according to an embodiment of the present disclosure.

第9圖是根據本揭露一實施例所繪示的製作高電子遷移率電晶體的剖面示意圖，其中包括設置於層間介電層中的源/汲極接觸洞。 FIG. 9 is a schematic cross-sectional view of a high electron mobility transistor including source/drain contact holes disposed in an interlayer dielectric layer according to an embodiment of the present disclosure.

第10圖是本揭露一實施例的製作高電子遷移率電晶體的流程圖。 FIG. 10 is a flow chart of fabricating a high electron mobility transistor according to an embodiment of the present disclosure.

本揭露提供了數個不同的實施例，可用於實現本揭露的不同特徵。為簡化說明起見，本揭露也同時描述了特定構件與佈置的範例。提供這些實施例的目的僅在於示意，而非予以任何限制。舉例而言，下文中針對「第一特徵形成在第二特徵上或上方」的敘述，其可以是指「第一特徵與第二特徵直接接觸」，也可以是指「第一特徵與第二特徵間另存在有其他特徵」，致使第一特徵與第二特徵並不直接接觸。此外，本揭露中的各種實施例可能使用重複的參考符號和/或文字註記。使用這些重複的參考符號與註記是為了使敘述更簡潔和明確，而非用以指示不同的實施例及/或配置之間的關聯性。 The present disclosure provides several different embodiments for implementing different features of the present disclosure. For simplicity of illustration, the present disclosure also describes examples of specific components and arrangements. These examples are provided for illustrative purposes only and are not intended to be limiting in any way. For example, the following description of "the first feature is formed on or over the second feature" may mean "the first feature is in direct contact with the second feature" or "the first feature is in direct contact with the second feature". There are other features between features", so that the first feature is not in direct contact with the second feature. Additionally, various embodiments in the present disclosure may use repeated reference symbols and/or textual notation. These repeated reference signs and notations are used for brevity and clarity of description, rather than to indicate associations between different embodiments and/or configurations.

另外，針對本揭露中所提及的空間相關的敘述詞彙，例如：「在...之下」，「低」，「下」，「上方」，「之上」，「下」，「頂」，「底」和類似詞彙時，為便於敘述，其用法均在於描述圖式中一個元件或特徵與另一個(或多個)元件或特徵的相對關係。除了圖式中所顯示的擺向外，這些空間相關詞彙也用來描述半導體裝置在使用中以及操作時的可能擺向。隨著半導體裝置的擺向的不同(旋轉90度或其它方位)，用以描述其擺向的空間相關敘述亦應透過類似的方式予以解釋。 In addition, for the space-related narrative words mentioned in this disclosure, for example: "below", "low", "below", "above", "above", "below", "top" ”, “bottom” and similar words, for ease of description, are used to describe the relative relationship of one element or feature to another (or more) elements or features in the drawings. In addition to the pendulum shown in the drawings, these space-related terms are also used to describe the possible pendulum orientations of the semiconductor device during use and operation. Depending on the swing direction of the semiconductor device (spin 90 degrees or other orientations), the space-related descriptions used to describe the direction of its swing should also be interpreted in a similar way.

雖然本揭露使用第一、第二、第三等等用詞，以敘述種種元件、部件、區域、層、及/或區塊(section)，但應了解此等元件、部件、區域、層、及/或區塊不應被此等用詞所限制。此等用詞僅是用以區分某一元件、部件、區域、層、及/或區塊與另一個元件、部件、區域、層、及/或區塊，其本身並不意含及代表該元件有任何之前的序數，也不代表某一元件與另一元件的排列順序、或是製造方法上的順序。因此，在不背離本揭露之具體實施例之範疇下，下列所討論之第一元件、部件、區域、層、或區塊亦可以第二元件、部件、區域、層、或區塊之詞稱之。 Although the present disclosure uses the terms first, second, third, etc. to describe various elements, components, regions, layers, and/or sections, it should be understood that such elements, components, regions, layers, and/or blocks should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and/or block from another element, component, region, layer, and/or block, and do not by themselves imply or represent that element The presence of any preceding ordinal numbers does not imply the order in which an element is arranged relative to another element, or the order of the method of manufacture. Thus, a first element, component, region, layer or block discussed below could be termed a second element, component, region, layer or block without departing from the scope of the specific embodiments of the present disclosure Of.

本揭露中所提及的「約」或「實質上」之用語通常表示在一給定值或範圍的20%之內，較佳是10%之內，且更佳是5%之內，或3%之內，或2%之內，或1%之內，或0.5%之內。應注意的是，說明書中所提供的數量為大約的數量，亦即在沒有特定說明「約」或「實質上」的情況下，仍可隱含「約」或「實質上」之含義。 The terms "about" or "substantially" referred to in this disclosure generally mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range, or Within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, the meaning of "about" or "substantially" can still be implied without the specific description of "about" or "substantially".

在本揭露中，「三五族半導體(group III-V semiconductor)」係指包含至少一III族元素與至少一V族元素的化合物半導體。其中，III族元素可以是硼(B)、鋁(Al)、鎵(Ga)或銦(In)，而V族元素可以是氮(N)、磷(P)、砷(As)或銻(Sb)。進一步而言，「III-V族半導體」可以包括：氮化鎵(GaN)、磷化銦(InP)、砷化鋁(AlAs)、砷化鎵(GaAs)、氮化鋁鎵(AlGaN)、氮化銦鋁鎵(InAlGaN)、氮化銦鎵(InGaN)、氮化鋁(AlN)、磷化鎵銦(GaInP)、砷化鋁鎵(AlGaAs)、砷化鋁銦(InAlAs)、砷化鎵銦(InGaAs)、氮化鋁(AlN)、磷化鎵銦(GaInP)、砷化鋁鎵(AlGaAs)、砷化鋁銦(InAlAs)、砷化鎵銦(InGaAs)、其類似物或上述化合物的組合，但不限於此。此外，端視需求，III-V族半導體內亦可包括摻質，而為具有特定導電型的III-V族半導體，例如 N型或P型III-V族半導體。 In the present disclosure, "group III-V semiconductor" refers to a compound semiconductor including at least one group III element and at least one group V element. Among them, the group III element can be boron (B), aluminum (Al), gallium (Ga) or indium (In), and the group V element can be nitrogen (N), phosphorus (P), arsenic (As) or antimony ( Sb). Further, "III-V semiconductors" may include: gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), Indium Aluminum Gallium Nitride (InAlGaN), Indium Gallium Nitride (InGaN), Aluminum Nitride (AlN), Gallium Indium Phosphide (GaInP), Aluminum Gallium Arsenide (AlGaAs), Aluminum Indium Arsenide (InAlAs), Arsenide Gallium Indium (InGaAs), Aluminum Nitride (AlN), Gallium Indium Phosphide (GaInP), Aluminum Gallium Arsenide (AlGaAs), Aluminum Indium Arsenide (InAlAs), Gallium Indium Arsenide (InGaAs), the like or the above A combination of compounds, but not limited thereto. In addition, depending on the requirements, the III-V group semiconductor may also include dopants, which are III-V group semiconductors with a specific conductivity type, such as N-type or P-type III-V semiconductors.

雖然下文係藉由具體實施例以描述本揭露的發明，然而本揭露的發明原理亦可應用至其他的實施例。此外，為了不致使本發明之精神晦澀難懂，特定的細節會被予以省略，該些被省略的細節係屬於所屬技術領域中具有通常知識者的知識範圍。 Although the invention of the present disclosure is described below with reference to specific embodiments, the inventive principles of the present disclosure can also be applied to other embodiments. Furthermore, in order not to obscure the spirit of the present invention, certain details will be omitted, which are within the knowledge of those having ordinary skill in the art.

本揭露係關於一種高電子遷移率電晶體(HEMT)，其可以作為電壓轉換器應用之功率切換電晶體。相較於矽功率電晶體，由於III-V HEMT具有較寬的能帶間隙，因此具有低導通電阻(on-state resistance)與低切換損失之特徵。 The present disclosure relates to a high electron mobility transistor (HEMT), which can be used as a power switching transistor for voltage converter applications. Compared with silicon power transistors, III-V HEMTs have the characteristics of low on-state resistance and low switching losses due to their wider energy bandgap.

第1圖是根據本揭露一實施例所繪示的高電子遷移率電晶體(HEMT)的剖面示意圖。如第1圖所示，根據本揭露一實施例，高電子遷移率電晶體10-1，例如增強型高電子遷移率電晶體，係設置在基底102上，且基底102上依序可設置有半導體通道層106、半導體阻障層108、圖案化半導體蓋層110、圖案化半導體保護層120、及層間介電層130，且層間介電層130可以設置有閘極電極140。其中，圖案化半導體保護層120的電阻率介於圖案化半導體蓋層110的電阻率及層間介電層130的電阻率之間。根據本揭露一實施例，層間介電層130可覆蓋圖案化半導體蓋層110及圖案化半導體保護層120，且層間介電層130內設置有閘極接觸洞132，用於容納閘極電極140。閘極電極140及圖案化半導體蓋層110之間存在部分的圖案化半導體保護層120。 FIG. 1 is a schematic cross-sectional view of a high electron mobility transistor (HEMT) according to an embodiment of the present disclosure. As shown in FIG. 1 , according to an embodiment of the present disclosure, a high electron mobility transistor 10 - 1 , such as an enhancement type high electron mobility transistor, is disposed on the substrate 102 , and the substrate 102 may be disposed on the substrate 102 in sequence. The semiconductor channel layer 106 , the semiconductor barrier layer 108 , the patterned semiconductor cap layer 110 , the patterned semiconductor protective layer 120 , and the interlayer dielectric layer 130 , and the interlayer dielectric layer 130 may be provided with a gate electrode 140 . The resistivity of the patterned semiconductor protective layer 120 is between the resistivity of the patterned semiconductor cap layer 110 and the resistivity of the interlayer dielectric layer 130 . According to an embodiment of the present disclosure, the interlayer dielectric layer 130 can cover the patterned semiconductor cap layer 110 and the patterned semiconductor protective layer 120 , and the interlayer dielectric layer 130 is provided with a gate contact hole 132 for accommodating the gate electrode 140 . Part of the patterned semiconductor protective layer 120 exists between the gate electrode 140 and the patterned semiconductor cap layer 110 .

根據本揭露一實施例，基底102和半導體通道層106之間可以設置選擇性的緩衝層104。層間介電層130的上方可以選擇性地設置層間介電層150。至少二源/汲極接觸洞152均可以貫穿層間介電層130、150，以分別用於容納至少二源/汲極電極154、156。 According to an embodiment of the present disclosure, an optional buffer layer 104 may be disposed between the substrate 102 and the semiconductor channel layer 106 . An interlayer dielectric layer 150 may be selectively disposed above the interlayer dielectric layer 130 . At least two source/drain contact holes 152 can penetrate through the interlayer dielectric layers 130 and 150 to accommodate at least two source/drain electrodes 154 and 156 , respectively.

根據本揭露的一實施例，上述基底102可以是塊矽基板、碳化矽(SiC)基板、藍寶石(sapphire)基板、絕緣層上覆矽(silicon on insulator，SOI)基板或絕緣層上覆鍺(germanium on insulator，GOI)基板，但不限定於此。於另一實施例中，基底102更包含單一或多層的絕緣材料層以及/或其他合適的材料層(例如半導體層)與一核心層。絕緣材料層可以是氧化物、氮化物、氮氧化物、或其他合適的絕緣材料。核心層可以是碳化矽(SiC)、氮化鋁(AlN)、氮化鋁鎵(AlGaN)、氧化鋅(ZnO)或氧化鎵(Ga₂O₃)、或其他合適的陶瓷材料。於一實施例中，單一或多層的絕緣材料層以及/或其他合適的材料層包覆核心層。 According to an embodiment of the present disclosure, the substrate 102 may be a bulk silicon substrate, a silicon carbide (SiC) substrate, a sapphire (sapphire) substrate, a silicon on insulator (SOI) substrate, or a germanium on insulator (germanium-on-insulator). germanium on insulator, GOI) substrate, but not limited to this. In another embodiment, the substrate 102 further includes a single or multiple layers of insulating material and/or other suitable material layers (eg, semiconductor layers) and a core layer. The insulating material layer may be oxide, nitride, oxynitride, or other suitable insulating material. The core layer may be silicon carbide (SiC), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), zinc oxide (ZnO) or gallium oxide (Ga ₂ O ₃ ), or other suitable ceramic materials. In one embodiment, a single or multiple layers of insulating material and/or other suitable material layers coat the core layer.

緩衝層104可以用於降低存在於基底102和在半導體通道層106之間的應力或晶格不匹配的程度。根據本揭露的一實施例，緩衝層104可以包括複數個子半導體，且其整體的電阻值會高於基底102上其他層的電阻值。具體而言，緩衝層104中的部分元素的比例，例如金屬元素，會由基底102往半導體通道層106的方向逐漸改變。舉例而言，對於基底102和半導體通道層106分別為矽基底和i-GaN層的情形，緩衝層104可以是組成比例漸變的氮化鋁鎵(Al_xGa_(1-x)N)，且順著基底102往半導體通道層106的方向，所述X值會以連續或階梯變化方式自0.9降低至0.15。 The buffer layer 104 may be used to reduce the degree of stress or lattice mismatch that exists between the substrate 102 and the semiconductor channel layer 106 . According to an embodiment of the present disclosure, the buffer layer 104 may include a plurality of sub-semiconductors, and the overall resistance of the buffer layer 104 may be higher than that of other layers on the substrate 102 . Specifically, the proportion of some elements in the buffer layer 104 , such as metal elements, will gradually change from the substrate 102 to the direction of the semiconductor channel layer 106 . For example, where substrate 102 and semiconductor channel layer 106 are silicon substrates and i-GaN layers, respectively, buffer layer 104 may be graded aluminum gallium nitride ( _AlxGa _(1-x) N), and The X value decreases from 0.9 to 0.15 in a continuous or stepwise manner along the direction of the substrate 102 toward the semiconductor channel layer 106 .

上述半導體通道層106可包含一層或多層III-V族半導體層，III-V族半導體層的成份可以是GaN、AlGaN、InGaN或InAlGaN，但不限定於此。此外，半導體通道層106亦可以是被摻雜的一層或多層III-V族半導體層，例如是P型的III-V族半導體層。對P型的III-V族半導體層而言，其摻質可以是C、Fe、Mg或Zn，或不限定於此。上述半導體阻障層108可包含一層或多層III-V族半導體層，且其組成會不同於半導體通道層106的III-V族半導體。舉例來說，半導體阻障層108可包含AlN、Al_yGa_(1-y)N(0<y<1)或其組合。根據一實施例，半導體通道層106可以是未經摻雜的GaN層，而半導體阻障層108可以是本質上為N型的AlGaN層。由於半導體通道層106和半導體阻障層108間具有不連續的能隙，藉由將半導體通道層106和半導體阻障層108互相堆疊設置，電子會因壓電效應(piezoelectric effect)而被聚集於半導體通道層106和半導體阻障層108之間的異質接面，因而產生高電子遷移率的薄層，亦即二維電子氣(2DEG)區域106a。相較之下，針對被圖案化半導體蓋層110所覆蓋的區域，由於不會形成二維電子氣，因此可視為是二維電子氣截斷區域106b。 The above-mentioned semiconductor channel layer 106 may include one or more III-V semiconductor layers, and the composition of the III-V semiconductor layers may be GaN, AlGaN, InGaN or InAlGaN, but is not limited thereto. In addition, the semiconductor channel layer 106 may also be one or more doped III-V semiconductor layers, such as P-type III-V semiconductor layers. For the P-type III-V semiconductor layer, the dopant may be C, Fe, Mg or Zn, or not limited thereto. The semiconductor barrier layer 108 may include one or more III-V semiconductor layers, and its composition may be different from the III-V semiconductor of the semiconductor channel layer 106 . For example, the semiconductor barrier layer 108 may include AlN, _AlyGa _(1-y) N (0<y<1), or a combination thereof. According to an embodiment, the semiconductor channel layer 106 may be an undoped GaN layer, and the semiconductor barrier layer 108 may be an N-type AlGaN layer in nature. Since there is a discontinuous energy gap between the semiconductor channel layer 106 and the semiconductor barrier layer 108, by stacking the semiconductor channel layer 106 and the semiconductor barrier layer 108 on each other, electrons will be collected in the piezoelectric effect (piezoelectric effect) The heterojunction between the semiconductor channel layer 106 and the semiconductor barrier layer 108 thus produces a thin layer of high electron mobility, ie, a two-dimensional electron gas (2DEG) region 106a. In contrast, the area covered by the patterned semiconductor capping layer 110 can be regarded as the two-dimensional electron gas blocking area 106b because the two-dimensional electron gas will not be formed.

設置於半導體阻障層108上方的圖案化半導體蓋層110可包含一層或多層III-V族半導體層，且III-V族半導體層的成份可以是GaN、AlGaN、InGaN或InAlGaN，但不限定於此。圖案化半導體蓋層110可以是被摻雜的一層或多層III-V族半導體層，例如是P型的III-V族半導體層。對於P型的III-V族半導體層而言，其摻質可以是C、Fe、Mg或Zn，但不限定於此。根據本揭露的一實施例，圖案化半導體蓋層110可以是P型的GaN層。 The patterned semiconductor capping layer 110 disposed above the semiconductor barrier layer 108 may include one or more III-V semiconductor layers, and the composition of the III-V semiconductor layers may be GaN, AlGaN, InGaN or InAlGaN, but not limited to this. The patterned semiconductor capping layer 110 may be one or more doped III-V semiconductor layers, such as P-type III-V semiconductor layers. For the P-type III-V semiconductor layer, the dopant may be C, Fe, Mg or Zn, but is not limited thereto. According to an embodiment of the present disclosure, the patterned semiconductor capping layer 110 may be a P-type GaN layer.

圖案化半導體保護層120實質上可以完整覆蓋住下方的圖案化半導體蓋層110，使其側邊可以和下方的圖案化半導體蓋層110切齊，或是些許內縮或外突(各側邊的內縮或外突的長度可以為1-10nm，但不限定於此)。圖案化半導體保護層120之組成係為相異於圖案化半導體蓋層110的半導體。根據本揭露一實施例，圖案化半導體保護層120之組成可以包括含矽半導體或含矽材料，例如是矽、碳化矽、氧化矽、碳化矽、氮化矽、氮氧化矽、碳氮化矽、碳氧化矽、碳氮氧化矽、金屬矽化物或前述之組合，且圖案化半導體保護層120的晶態可以是單晶(single crystalline)、多晶(polycrystalline)或非晶(amorphous)。舉例而言，圖案化半導體保護層120可以是低溫多晶矽(low temperature polysilicon)。圖案化半導體保護層120的電阻率可以高於下方的圖案化半導體蓋層110，例如為10至1000Ω‧m，且其縱向的電阻可為1x10⁴至1x10⁶Ω，例如是1x10⁴Ω、1x10⁵Ω或1x10⁶Ω，但不限定於此。 The patterned semiconductor protective layer 120 can substantially completely cover the underlying patterned semiconductor capping layer 110, so that its sides can be flush with the underlying patterned semiconductor capping layer 110, or slightly shrink or protrude (each side The length of the indentation or protrusion can be 1-10nm, but not limited thereto). The composition of the patterned semiconductor protective layer 120 is a semiconductor different from that of the patterned semiconductor capping layer 110 . According to an embodiment of the present disclosure, the composition of the patterned semiconductor protective layer 120 may include a silicon-containing semiconductor or a silicon-containing material, such as silicon, silicon carbide, silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, and silicon carbonitride , silicon oxycarbide, silicon oxycarbonitride, metal silicide, or a combination thereof, and the crystalline state of the patterned semiconductor protective layer 120 may be single crystalline, polycrystalline or amorphous. For example, the patterned semiconductor protective layer 120 may be low temperature polysilicon. The resistivity of the patterned semiconductor protective layer 120 may be higher than that of the underlying patterned semiconductor capping layer 110, for example, 10 to 1000 Ω·m, and its longitudinal resistance may be 1×10 ⁴ to 1×10 ⁶ Ω, for example, 1×10 ⁴ Ω, 1×10 ⁵ Ω or 1x10 ⁶ Ω, but not limited to this.

閘極電極140可以和下方的圖案化半導體蓋層110以蕭特基接觸產生電連接，且閘極電極140的底部可以被埋設於圖案化半導體保護層120之中，但仍縱向分離於下方的圖案化半導體蓋層110。因此，圖案化半導體保護層120可以包括位於周邊的第一部份122及位於中間的第二部份124。根據本揭露一實施例，閘極電極140可以是單層或多層的結構，例如是包括第一導電層142和第二導電層144的雙層結構。其中，第一導電層142可以直接接觸圖案化半導體保護層120，且其組成包括蕭特基接觸金屬。其中，蕭特基接觸金屬係指可以和半導體層產生蕭特基接觸(Schottky contact)的金屬、合金或其堆疊層，例如是TiN、W、Pt、Ni或Ni，但不限定於此。第二導電層144的組成可以包括Ti、Al、Au、Mo，但不限定於此。根據本揭露的一實施例，第一導電層142可以包括含有耐火性金屬的金屬氮化物，且耐火性金屬可選自由鈦、鋯、鉿、釩、鈮、鉭、鉻、鉬、鎢、錳、鎝、錸、釕、鋨、銠及銥所構成之群組。 The gate electrode 140 can be electrically connected with the underlying patterned semiconductor capping layer 110 through Schottky contact, and the bottom of the gate electrode 140 can be buried in the patterned semiconductor protective layer 120, but still It is longitudinally separated from the underlying patterned semiconductor capping layer 110 . Therefore, the patterned semiconductor protective layer 120 may include the first portion 122 at the periphery and the second portion 124 at the middle. According to an embodiment of the present disclosure, the gate electrode 140 may be a single-layer or multi-layer structure, for example, a double-layer structure including a first conductive layer 142 and a second conductive layer 144 . The first conductive layer 142 can directly contact the patterned semiconductor protective layer 120, and its composition includes Schottky contact metal. The Schottky contact metal refers to a metal, an alloy or a stacked layer thereof that can make Schottky contact with the semiconductor layer, such as TiN, W, Pt, Ni or Ni, but not limited thereto. The composition of the second conductive layer 144 may include Ti, Al, Au, Mo, but is not limited thereto. According to an embodiment of the present disclosure, the first conductive layer 142 may include a metal nitride containing a refractory metal, and the refractory metal may be selected from titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, and manganese , onium, rhenium, ruthenium, osmium, rhodium and iridium.

層間介電層130、150可以依序設置於半導體阻障層108之上，且其材質可以獨立選自Si₃N₄、AlN、Al₂O₃、SiO₂、或前述之組合，但不限定於此。層間介電層130、150可以覆蓋住圖案化半導體保護層120、圖案化半導體蓋層110、半導體阻障層108及半導體通道層106。其中，層間介電層130、150的電阻率可高於圖案化半導體保護層120的電阻率。舉例而言，層間介電層130、150的電阻率可為1x10¹⁰至1x10¹⁶Ω‧m，例如是1x10¹³Ω‧m，但不限定於此。 The interlayer dielectric layers 130 and 150 can be disposed on the semiconductor barrier layer 108 in sequence, and their materials can be independently selected from Si ₃ N ₄ , AlN, Al ₂ O ₃ , SiO ₂ , or a combination of the foregoing, but not limited to here. The interlayer dielectric layers 130 and 150 may cover the patterned semiconductor protective layer 120 , the patterned semiconductor capping layer 110 , the semiconductor barrier layer 108 and the semiconductor channel layer 106 . The resistivity of the interlayer dielectric layers 130 and 150 may be higher than that of the patterned semiconductor protection layer 120 . For example, the resistivity of the interlayer dielectric layers 130 and 150 may be 1× ^{10 10} to 1×10 ¹⁶ Ω·m, such as 1×10 ¹³ Ω·m, but not limited thereto.

源/汲極電極154、156可以各自貫穿層間介電層130、150，並且電連接至下方的半導體阻障層108及半導體通道層106。根據本揭露一實施例，源/汲極154、156可以是單層或多層的結構，且其組成可以包括歐姆接觸金屬。其中，歐姆接觸金屬係指可以和半導體層產生歐姆接觸(ohmic contact)的金屬、合金或其堆疊層，例如是Ti、Ti/Al、Ti/Al/Ti/TiN、Ti/Al/Ti/Au、Ti/Al/Ni/Au或Ti/Al/Mo/Au，但不限定於此。 The source/drain electrodes 154 , 156 may each penetrate the interlayer dielectric layers 130 , 150 and be electrically connected to the underlying semiconductor barrier layer 108 and the semiconductor channel layer 106 . According to an embodiment of the present disclosure, the source/drain electrodes 154 and 156 may be a single-layer or multi-layer structure, and the composition may include ohmic contact metal. Wherein, the ohmic contact metal refers to a metal, alloy or its stacked layer that can make ohmic contact with the semiconductor layer, such as Ti, Ti/Al, Ti/Al/Ti/TiN, Ti/Al/Ti/Au , Ti/Al/Ni/Au or Ti/Al/Mo/Au, but not limited thereto.

第2圖是本揭露一實施例的高電子遷移率電晶體的局部區域的放大剖面示意圖，其可對應至第1圖實施例所示之區域A。如第2圖所示，圖案化半導體保護層120的底面120B可以和圖案化半導體蓋層110的頂面110T重合。且圖案化半導體保護層120的側面120S可以實質上切齊圖案化半導體蓋層110的側面110S，使得圖案化半導體保護層120及圖案化半導體蓋層110的橫向尺寸，例如寬度D2，可以實質上彼此相等。根據本揭露一實施例，圖案化半導體保護層120的表面可以設置有凹槽126，使得凹槽126的底面126B及側面126S可以和圖案化半導體保護層120的表面重合。凹槽126的橫向尺寸，例如寬度D1，可以小於圖案化半導體蓋層110的寬度D2，使得圖案化半導體保護層120的第一部分122可以鄰近於凹槽126的周邊，而圖案化半導體保護層120的第二部分124可以設置於凹槽126的正下方。其中，位於凹槽126周邊的各第一部分122的橫向尺寸，例如寬度，可以分別是寬度D3、D4。舉例而言，寬度D3、D4可以為20至350nm，且寬度D3、D4可以彼此相同或不同，但不限定於此。此外，第一部分122的厚度T1可以大於第二部分124的厚度T2。舉例而言，厚度T2可以為10至100nm，但不限定於此。閘極電極140的下部可以填滿凹槽126而具有寬度D1，且閘極電極140的至少一底角140C可以直接接觸圖案化半導體保護層120，或進一步被圖案化半導體保護層120包覆。 FIG. 2 is an enlarged cross-sectional schematic diagram of a partial region of the high electron mobility transistor according to an embodiment of the present disclosure, which may correspond to the region A shown in the embodiment of FIG. 1 . As shown in Figure 2, the patterned semiconductor The bottom surface 120B of the bulk protection layer 120 may coincide with the top surface 110T of the patterned semiconductor capping layer 110 . And the side surface 120S of the patterned semiconductor capping layer 120 can be substantially aligned with the side surface 110S of the patterned semiconductor capping layer 110 , so that the lateral dimension of the patterned semiconductor capping layer 120 and the patterned semiconductor capping layer 110 , such as the width D2 , can be substantially equal to each other. According to an embodiment of the present disclosure, grooves 126 may be provided on the surface of the patterned semiconductor protective layer 120 , so that the bottom surface 126B and the side surface 126S of the grooves 126 may overlap with the surface of the patterned semiconductor protective layer 120 . The lateral dimension of the groove 126 , such as the width D1 , may be smaller than the width D2 of the patterned semiconductor capping layer 110 such that the first portion 122 of the patterned semiconductor capping layer 120 may be adjacent to the perimeter of the groove 126 while the patterned semiconductor capping layer 120 is The second portion 124 of the can be disposed just below the groove 126 . The lateral dimension, such as the width, of each of the first portions 122 located at the periphery of the groove 126 may be widths D3 and D4, respectively. For example, the widths D3 and D4 may be 20 to 350 nm, and the widths D3 and D4 may be the same or different from each other, but not limited thereto. Also, the thickness T1 of the first portion 122 may be greater than the thickness T2 of the second portion 124 . For example, the thickness T2 may be 10 to 100 nm, but is not limited thereto. The lower portion of the gate electrode 140 can fill the groove 126 to have a width D1 , and at least one bottom corner 140C of the gate electrode 140 can directly contact the patterned semiconductor protection layer 120 or be further covered by the patterned semiconductor protection layer 120 .

根據本揭露的實施例，由於圖案化半導體保護層120的電阻率高於上方閘極電極140的電阻率，因此即便不對圖案化半導體保護層120的側面120S進行側向蝕刻，圖案化半導體保護層120也不會產生尖端放電，因此可以避免不必要的閘極漏電流。再者，由於圖案化半導體保護層120的寬度D2可以實質上相同於圖案化蓋層的寬度D2，因此即便是不同批次所產出的半導體元件，各半導體元件之間仍可維持良好的電性一致性。另外，由於閘極電極140的底角140C可以被電阻率相對較高的圖案化半導體保護層120包覆，因此圖案化半導體保護層120可被用於緩衝源自閘極電極140的底角140C的高壓電場，因此可以提升半導體元件的穩定性。 According to the embodiment of the present disclosure, since the resistivity of the patterned semiconductor protective layer 120 is higher than that of the upper gate electrode 140 , even if the side surface 120S of the patterned semiconductor protective layer 120 is not laterally etched, the patterned semiconductor protective layer 120 also does not generate tip discharge, so unnecessary gate leakage current can be avoided. Furthermore, since the width D2 of the patterned semiconductor protective layer 120 can be substantially the same as the width D2 of the patterned capping layer, even semiconductor elements produced in different batches can still maintain good electrical power between the semiconductor elements. Sexual consistency. In addition, since the bottom corner 140C of the gate electrode 140 may be covered by the patterned semiconductor protective layer 120 having a relatively high resistivity, the patterned semiconductor protective layer 120 may be used to buffer the bottom corner 140C originating from the gate electrode 140 The high-voltage electric field can improve the stability of semiconductor components.

第3圖是本揭露一變化型實施例的高電子遷移率電晶體的局部區域的放大剖面示意圖。第3圖實施例中所示的高電子遷移率電晶體10-2大致相同於第2圖實施例中所示的高電子遷移率電晶體10-1，兩者之間的主要差異處在於，高電子遷移率電晶體10-2的閘極電極140的底面未埋設於圖案化半導體保護層120之中。因此對於圖案化半導體層120的厚度T1而言，無論是位於閘極電極140的周邊或是正下方，圖案化半導體層120的厚度T1可以維持固定。此外，由於閘極電極140和圖案化半導體蓋層110之間的距離等於圖案化半導體層120的厚度T1，為了避免閘極電極140和圖案化半導體蓋層110之間的電阻值過大，圖案化半導體層120的厚度T1可為10至100nm。 FIG. 3 is an enlarged cross-sectional schematic diagram of a partial region of a high electron mobility transistor according to a variant embodiment of the present disclosure. The high electron mobility transistor 10-2 shown in the embodiment of FIG. 3 is substantially the same as the high electron mobility transistor 10-1 shown in the embodiment of FIG. 2, with the main difference between the two being, The bottom surface of the gate electrode 140 of the high electron mobility transistor 10 - 2 is not buried in the patterned semiconductor protective layer 120 . Therefore, for the thickness T1 of the patterned semiconductor layer 120 , the thickness T1 of the patterned semiconductor layer 120 can be kept constant whether it is located at the periphery of the gate electrode 140 or directly under the gate electrode 140 . In addition, since the distance between the gate electrode 140 and the patterned semiconductor capping layer 110 is equal to the thickness T1 of the patterned semiconductor layer 120, in order to avoid excessive resistance between the gate electrode 140 and the patterned semiconductor capping layer 110, the patterned The thickness T1 of the semiconductor layer 120 may be 10 to 100 nm.

第4圖是本揭露一變化型實施例的高電子遷移率電晶體的剖面示意圖。第4圖實施例中所示的高電子遷移率電晶體10-3大致相同於第1圖實施例中所示的高電子遷移率電晶體10-1，兩者之間的主要差異處在於，高電子遷移率電晶體10-3的層間介電層130和半導體阻障層108、圖案化半導體蓋層110、及圖案化半導體保護層120之間額外設置有順向性的鈍化層160。鈍化層160可用於消除或減少存在於半導體阻障層108的頂面、圖案化半導體蓋層110的側面110S、及圖案化半導體保護層120的側面120S的表面缺陷，進而提昇高電子遷移率電晶體10-3的電性表現。根據本揭露的一實施例，鈍化層160的電阻率高於圖案化半導體保護層120的電阻率，且鈍化層160的組成可以是氮化矽(Si₃N₄)、氮氧化矽(SiON)、氮化鋁(AlN)、氧化鋁(Al₂O₃)或氧化矽(SiO₂)，但不限定於此。 FIG. 4 is a schematic cross-sectional view of a high electron mobility transistor according to a variant embodiment of the present disclosure. The high electron mobility transistor 10-3 shown in the embodiment of FIG. 4 is substantially the same as the high electron mobility transistor 10-1 shown in the embodiment of FIG. 1, with the main difference between the two being, A forward passivation layer 160 is additionally disposed between the interlayer dielectric layer 130 of the high electron mobility transistor 10 - 3 and the semiconductor barrier layer 108 , the patterned semiconductor capping layer 110 , and the patterned semiconductor protective layer 120 . The passivation layer 160 can be used to eliminate or reduce surface defects existing on the top surface of the semiconductor barrier layer 108 , the side surface 110S of the patterned semiconductor capping layer 110 , and the side surface 120S of the patterned semiconductor protective layer 120 , thereby improving high electron mobility. Electrical performance of crystal 10-3. According to an embodiment of the present disclosure, the resistivity of the passivation layer 160 is higher than that of the patterned semiconductor protective layer 120 , and the passivation layer 160 may be composed of silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON) , aluminum nitride (AlN), aluminum oxide (Al ₂ O ₃ ) or silicon oxide (SiO ₂ ), but not limited thereto.

為了使本技術領域中具有通常知識者可據以實現本揭露的發明，以下進一步具體描述本揭露的高電子遷移率電晶體的製作方法。 In order to enable those with ordinary knowledge in the technical field to realize the invention of the present disclosure, the fabrication method of the high electron mobility transistor of the present disclosure is further described in detail below.

第5圖是根據本揭露一實施例所繪示的製作高電子遷移率電晶體的剖面示意圖，其中包括依序堆疊的半導體層。第10圖是本揭露一實施例的製作高電子遷移率電晶體的流程圖。根據本揭露的一實施例，可以施行製作方法200 的步驟202，以提供基底，且基底上依序設置有半導體通道層、半導體阻障層、半導體蓋層、以及半導體保護層。如第5圖所示，半導體結構20中的基底102之上可以依序設置有緩衝層104、半導體通道層106、半導體阻障層108、半導體蓋層109、以及半導體保護層111。可以透過任何合適的方式以形成基底102上的各堆疊層，例如可透過分子束磊晶(molecular-beam epitaxy，MBE)、金屬有機化學氣相沉積(metal-organic chemical vapor deposition，MOCVD)、氫化物氣相磊晶(hydride vapor phase epitaxy，HVPE)、原子層沉積(atomic layer deposition，ALD)或其他合適的方式。 FIG. 5 is a schematic cross-sectional view of a high electron mobility transistor according to an embodiment of the present disclosure, which includes sequentially stacked semiconductor layers. FIG. 10 is a flow chart of fabricating a high electron mobility transistor according to an embodiment of the present disclosure. According to an embodiment of the present disclosure, the fabrication method 200 may be implemented In step 202, a substrate is provided, and a semiconductor channel layer, a semiconductor barrier layer, a semiconductor cap layer, and a semiconductor protective layer are sequentially disposed on the substrate. As shown in FIG. 5 , a buffer layer 104 , a semiconductor channel layer 106 , a semiconductor barrier layer 108 , a semiconductor cap layer 109 , and a semiconductor protective layer 111 may be sequentially disposed on the substrate 102 in the semiconductor structure 20 . The stacked layers on the substrate 102 can be formed by any suitable method, such as through molecular-beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), hydrogenation hydride vapor phase epitaxy (HVPE), atomic layer deposition (ALD) or other suitable methods.

第6圖是根據本揭露一實施例所繪示的製作高電子遷移率電晶體的剖面示意圖，其中包括圖案化半導體蓋層、圖案化半導體保護層、及遮罩層。根據本揭露的一實施例，在第5圖實施例所示的步驟之後，可以施行光微影及蝕刻製程，以形成具有特徵圖案的遮罩層128。繼以施行步驟204，蝕刻半導體蓋層及半導體保護層，以形成圖案化半導體蓋層及圖案化半導體保護層。舉例而言，可利用遮罩層128作為蝕刻遮罩，施行蝕刻製程，以依序移除暴露出於遮罩層128的半導體保護層111及半導體蓋層109，藉此形成圖案化半導體保護層120及圖案化半導體蓋層110。根據本揭露一實施例，由於遮罩層128所定義的特徵圖案係藉由縱向的非等向性蝕刻而被轉移至下方的半導體保護層111及半導體蓋層109，因此遮罩層128、圖案化半導體保護層120、及圖案化半導體蓋層110可以具有實質上相同的橫向尺寸，例如寬度D2。因此，遮罩層128的側面128S、圖案化半導體蓋層110的側面110S、及圖案化半導體保護層120的側面120S實質上可以互相切齊。此外，針對未被圖案化半導體蓋層110所覆蓋的區域，會因為半導體通道層106和半導體阻障層108間所產生的壓電效應，致使二維電子氣可以被形成於二維電子氣區域106a中。相較之下，針對被圖案化半導體蓋層110所覆蓋的區域，由於不會形成二維電子氣，因此可視為是二維電子氣截斷區域106b。 FIG. 6 is a schematic cross-sectional view of a high electron mobility transistor according to an embodiment of the present disclosure, which includes a patterned semiconductor cap layer, a patterned semiconductor protective layer, and a mask layer. According to an embodiment of the present disclosure, after the steps shown in the embodiment of FIG. 5 , photolithography and etching processes may be performed to form a mask layer 128 having a characteristic pattern. Following step 204, the semiconductor cap layer and the semiconductor protective layer are etched to form a patterned semiconductor cap layer and a patterned semiconductor protective layer. For example, the mask layer 128 can be used as an etching mask to perform an etching process to sequentially remove the semiconductor protective layer 111 and the semiconductor capping layer 109 exposed on the mask layer 128, thereby forming a patterned semiconductor protective layer 120 and the patterned semiconductor capping layer 110 . According to an embodiment of the present disclosure, since the feature pattern defined by the mask layer 128 is transferred to the underlying semiconductor protective layer 111 and the semiconductor cap layer 109 by longitudinal anisotropic etching, the mask layer 128, pattern The patterned semiconductor capping layer 120 and the patterned semiconductor capping layer 110 may have substantially the same lateral dimension, eg, width D2. Therefore, the side surface 128S of the mask layer 128 , the side surface 110S of the patterned semiconductor cap layer 110 , and the side surface 120S of the patterned semiconductor protective layer 120 can be substantially aligned with each other. In addition, for the area not covered by the patterned semiconductor cap layer 110 , the two-dimensional electron gas can be formed in the two-dimensional electron gas region due to the piezoelectric effect generated between the semiconductor channel layer 106 and the semiconductor barrier layer 108 106a. In contrast, the area covered by the patterned semiconductor capping layer 110 can be regarded as the two-dimensional electron gas blocking area 106b because the two-dimensional electron gas will not be formed.

在製得圖案化半導體保護層120及圖案化半導體蓋層110之後，可以移除遮罩層128，以暴露出案化半導體保護層120的頂面。 After the patterned semiconductor protective layer 120 and the patterned semiconductor capping layer 110 are fabricated, the mask layer 128 may be removed to expose the top surface of the patterned semiconductor protective layer 120 .

第7圖是根據本揭露一實施例所繪示的製作高電子遷移率電晶體的剖面示意圖，其中包括設置於層間介電層中的閘極接觸洞。根據本揭露一實施例，施行步驟206，形成層間介電層，以覆蓋住圖案化半導體蓋層及圖案化半導體保護層。舉例而言，可以透過合適的沉積製程，以形成層間介電層130，而完整覆蓋圖案化半導體保護層120、圖案化半導體蓋層110、半導體阻障層108、及半導體通道層106。其中，移除遮罩層128之前和形成層間介電層130之後，圖案化半導體保護層120的寬度D2可維持固定，使得圖案化半導體蓋層110的側面110S及圖案化半導體保護層120的側面120S實質上可以互相切齊。層間介電層130的材質可以是Si₃N₄、AlN、Al₂O₃或SiO₂，但不限定於此。 FIG. 7 is a schematic cross-sectional view of a high electron mobility transistor according to an embodiment of the present disclosure, which includes a gate contact hole disposed in an interlayer dielectric layer. According to an embodiment of the present disclosure, step 206 is performed to form an interlayer dielectric layer to cover the patterned semiconductor capping layer and the patterned semiconductor protective layer. For example, the interlayer dielectric layer 130 can be formed through a suitable deposition process to completely cover the patterned semiconductor protective layer 120 , the patterned semiconductor cap layer 110 , the semiconductor barrier layer 108 , and the semiconductor channel layer 106 . Before removing the mask layer 128 and after forming the interlayer dielectric layer 130 , the width D2 of the patterned semiconductor protection layer 120 can be kept constant, so that the side surface 110S of the patterned semiconductor cap layer 110 and the side surface of the patterned semiconductor protection layer 120 can be maintained. The 120S can essentially be cut flush with each other. The material of the interlayer dielectric layer 130 may be Si ₃ N ₄ , AlN, Al ₂ O ₃ or SiO ₂ , but is not limited thereto.

接著，施行步驟208，形成閘極接觸洞於該層間介電層中，其中閘極接觸洞的底面會暴露出圖案化半導體保護層且分離於圖案化半導體蓋層。舉例而言，可以藉由施行光微影和蝕刻製程，以依序於層間介電層130中形成開孔134，並於圖案化半導體保護層120的表面形成凹槽126。其中，開孔134及凹槽126可構成閘極接觸洞132。因此，圖案化半導體保護層120可以自閘極接觸洞132暴露出。其中，閘極接觸洞132寬度D1可小於圖案化半導體保護層120的寬度D2。閘極接觸洞132的底面126B可以位於圖案化半導體保護層120之中，且分離於圖案化半導體蓋層110。因此，圖案化半導體保護層120的第一部分122的頂面122T可以高於第二部分124的頂面124T。根據本揭露一實施例，形成閘極接觸洞132的蝕刻製程可以包括乾蝕刻製程，例如電漿蝕刻製程。由於在施行蝕刻製程時，閘極接觸洞132的底面均不會穿透圖案化半導體保護層120，因此可以避免高能量的蝕刻劑(例如電漿蝕刻劑)接觸圖案化半導體蓋層110，進而可維持圖案化半導體蓋層110的原始電特性。 Next, step 208 is performed to form a gate contact hole in the interlayer dielectric layer, wherein the bottom surface of the gate contact hole exposes the patterned semiconductor protective layer and is separated from the patterned semiconductor capping layer. For example, by performing photolithography and etching processes, the openings 134 can be formed in the interlayer dielectric layer 130 in sequence, and the grooves 126 can be formed on the surface of the patterned semiconductor protective layer 120 . The opening 134 and the groove 126 may constitute the gate contact hole 132 . Therefore, the patterned semiconductor protective layer 120 may be exposed from the gate contact hole 132 . The width D1 of the gate contact hole 132 may be smaller than the width D2 of the patterned semiconductor protective layer 120 . The bottom surface 126B of the gate contact hole 132 may be located in the patterned semiconductor protective layer 120 and separated from the patterned semiconductor capping layer 110 . Therefore, the top surface 122T of the first portion 122 of the patterned semiconductor protective layer 120 may be higher than the top surface 124T of the second portion 124 . According to an embodiment of the present disclosure, the etching process for forming the gate contact hole 132 may include a dry etching process, such as a plasma etching process. Since the bottom surfaces of the gate contact holes 132 will not penetrate the patterned semiconductor protective layer 120 during the etching process, it is possible to prevent a high-energy etchant (eg, plasma etchant) from contacting the patterned semiconductor cap layer 110 , and further The original electrical properties of the patterned semiconductor capping layer 110 may be maintained.

第8圖是根據本揭露一實施例所繪示的製作高電子遷移率電晶體的剖面示意圖，其中包括閘極電極。根據本揭露一實施例，在第7圖實施例所示的步驟之後，可以施行步驟210，以形成閘極電極於閘極接觸洞中，其中閘極電極及圖案化半導體蓋層之間存在部分的圖案化半導體保護層。舉例而言，可以施行合適的沉積製程，以形成單層或多層的導電層(圖未示)於層間介電層130的頂面上及閘極接觸洞132內。之後，施行光微影和蝕刻製程，以圖案化導電層，而形成閘極電極140。根據本揭露的一實施例，對於開口面積較小的閘極接觸洞132而言，閘極電極140可能會完全填滿閘極接觸洞132，但不限定於此。根據本揭露一實施例，閘極電極140亦可以僅沿著閘極接觸洞132的內壁設置，而不填滿閘極接觸洞132。接著，於層間介電層130之上形成額外的層間介電層或是鈍化層，例如層間介電層150，以覆蓋住閘極電極140。 FIG. 8 is a schematic cross-sectional view of a high electron mobility transistor including a gate electrode according to an embodiment of the present disclosure. According to an embodiment of the present disclosure, after the step shown in the embodiment of FIG. 7, step 210 may be performed to form a gate electrode in the gate contact hole, wherein a portion exists between the gate electrode and the patterned semiconductor cap layer patterned semiconductor protective layer. For example, a suitable deposition process may be performed to form a single or multiple conductive layer (not shown) on the top surface of the interlayer dielectric layer 130 and in the gate contact hole 132 . After that, photolithography and etching processes are performed to pattern the conductive layer to form the gate electrode 140 . According to an embodiment of the present disclosure, for the gate contact hole 132 with a smaller opening area, the gate electrode 140 may completely fill the gate contact hole 132 , but it is not limited thereto. According to an embodiment of the present disclosure, the gate electrode 140 may also be disposed only along the inner wall of the gate contact hole 132 without filling the gate contact hole 132 . Next, an additional interlayer dielectric layer or passivation layer, such as the interlayer dielectric layer 150 , is formed on the interlayer dielectric layer 130 to cover the gate electrode 140 .

第9圖是根據本揭露一實施例所繪示的製作高電子遷移率電晶體的剖面示意圖，其中包括設置於層間介電層中的源/汲極接觸洞。如第9圖所示，可以藉由施行光微影和蝕刻製程，以於於閘極電極140的兩側形成至少一源/汲極接觸洞，例如分離設置的二源/汲極接觸洞152。當蝕刻製程完成時，各源/汲極接觸洞152的底面152B可位於半導體阻障層108中，或進一步延伸至半導體通道層106之中，以暴露出半導體通道層106。此外，由於源/汲極接觸洞152的底面152B可位於半導體通道層108或半導體通道層106之中，因此各源/汲極接觸洞152的下方會相應形成二維電子氣截斷區域106b。 FIG. 9 is a schematic cross-sectional view of a high electron mobility transistor including source/drain contact holes disposed in an interlayer dielectric layer according to an embodiment of the present disclosure. As shown in FIG. 9, at least one source/drain contact hole, such as two separate source/drain contact holes 152, can be formed on both sides of the gate electrode 140 by performing photolithography and etching processes. . When the etching process is completed, the bottom surface 152B of each source/drain contact hole 152 may be located in the semiconductor barrier layer 108 or further extend into the semiconductor channel layer 106 to expose the semiconductor channel layer 106 . In addition, since the bottom surface 152B of the source/drain contact hole 152 may be located in the semiconductor channel layer 108 or the semiconductor channel layer 106 , a two-dimensional electron gas blocking region 106b is correspondingly formed under each source/drain contact hole 152 .

接著，可以施行合適的沉積製程，以形成單層或多層的導電層(圖未示)於層間介電層150的頂面上及源/汲極接觸洞152內。之後，施行光微影和蝕刻製程，以圖案化導電層，而形成類似如第1圖所示的源/汲極電極154、156。 Next, a suitable deposition process may be performed to form a single-layer or multi-layer conductive layer (not shown) on the top surface of the interlayer dielectric layer 150 and in the source/drain contact holes 152 . After that, photolithography and etching processes are performed to pattern the conductive layer to form source/drain electrodes 154 and 156 similar to those shown in FIG. 1 .

以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

10-1:高電子遷移率電晶體 10-1: High Electron Mobility Transistors

110:圖案化半導體蓋層 110: Patterned semiconductor capping layer

110S:側面 110S: Side

110T:頂面 110T: Top surface

120:圖案化半導體保護層 120: Patterned semiconductor protective layer

120B:底面 120B: Bottom

120S:側面 120S: Side

122:第一部份 122: Part 1

124:第二部份 124: Part II

124T:頂面 124T: top surface

126:凹槽 126: Groove

126B:底面 126B: Bottom

126S:側面 126S: Side

130:層間介電層 130: Interlayer dielectric layer

132:閘極接觸洞 132: Gate contact hole

140:閘極電極 140: gate electrode

140C:底角 140C: Bottom corner

142:第一導電層 142: the first conductive layer

144:第二導電層 144: the second conductive layer

A:區域 A: area

D1:寬度 D1: width

D2:寬度 D2: width

D3:寬度 D3: width

D4:寬度 D4: width

T1:厚度 T1: Thickness

T2:厚度 T2: Thickness

Claims

一種高電子遷移率電晶體，包括：一半導體通道層及一半導體阻障層，設置於一基底上；一圖案化半導體保護層，設置於該半導體阻障層上；一圖案化半導體蓋層，設置於該圖案化半導體保護層及該半導體阻障層之間；一層間介電層，覆蓋該圖案化半導體蓋層及該圖案化半導體保護層，其中該層間介電層包括一閘極接觸洞；以及一閘極電極，設置於該閘極接觸洞內且電連接該圖案化半導體蓋層，其中該閘極電極及該圖案化半導體蓋層之間存在部分的該圖案化半導體保護層，其中，該圖案化半導體保護層的電阻率介於該圖案化半導體蓋層的電阻率及該層間介電層的電阻率之間。 A high electron mobility transistor, comprising: a semiconductor channel layer and a semiconductor barrier layer, disposed on a substrate; a patterned semiconductor protective layer, disposed on the semiconductor barrier layer; a patterned semiconductor cap layer, disposed between the patterned semiconductor protective layer and the semiconductor barrier layer; an interlayer dielectric layer covering the patterned semiconductor cap layer and the patterned semiconductor protective layer, wherein the interlayer dielectric layer includes a gate contact hole and a gate electrode disposed in the gate contact hole and electrically connected to the patterned semiconductor cap layer, wherein a portion of the patterned semiconductor protective layer exists between the gate electrode and the patterned semiconductor cap layer, wherein , the resistivity of the patterned semiconductor protective layer is between the resistivity of the patterned semiconductor cap layer and the resistivity of the interlayer dielectric layer.

如請求項1所述的高電子遷移率電晶體，其中該圖案化半導體保護層的側面切齊該圖案化半導體蓋層的側面。 The high electron mobility transistor of claim 1, wherein the side surface of the patterned semiconductor protective layer is flush with the side surface of the patterned semiconductor cap layer.

如請求項1所述的高電子遷移率電晶體，其中該閘極接觸洞的寬度小於該圖案化半導體保護層的寬度。 The high electron mobility transistor of claim 1, wherein the width of the gate contact hole is smaller than the width of the patterned semiconductor protective layer.

如請求項1所述的高電子遷移率電晶體，其中該閘極電極及該半導體蓋層之間係以蕭特基接觸產生電連接。 The high electron mobility transistor of claim 1, wherein the gate electrode and the semiconductor cap layer are electrically connected by Schottky contacts.

如請求項1所述的高電子遷移率電晶體，其中該圖案化半導體保護層的電阻率高於該閘極電極的電阻率。 The high electron mobility transistor of claim 1, wherein the patterned semiconductor protects The resistivity of the layer is higher than that of the gate electrode.

如請求項1所述的高電子遷移率電晶體，其中該閘極電極直接接觸該圖案化半導體保護層。 The high electron mobility transistor of claim 1, wherein the gate electrode directly contacts the patterned semiconductor protective layer.

如請求項6所述的高電子遷移率電晶體，其中該閘極電極包括一底角，該底角直接接觸該圖案化半導體保護層。 The high electron mobility transistor of claim 6, wherein the gate electrode comprises a bottom corner, and the bottom corner directly contacts the patterned semiconductor protective layer.

如請求項1所述的高電子遷移率電晶體，其中：該圖案化半導體蓋層之組成係為P型的III-V族半導體；該圖案化半導體保護層之組成係為含矽半導體；以及該閘極電極之組成包括金屬。 The high electron mobility transistor of claim 1, wherein: the composition of the patterned semiconductor capping layer is a P-type III-V semiconductor; the composition of the patterned semiconductor protective layer is a silicon-containing semiconductor; and The composition of the gate electrode includes metal.

如請求項1所述的高電子遷移率電晶體，其中該圖案化半導體保護層的表面包括一凹槽，且該閘極電極係填滿該凹槽。 The high electron mobility transistor of claim 1, wherein the surface of the patterned semiconductor protective layer includes a groove, and the gate electrode fills the groove.

如請求項9所述的高電子遷移率電晶體，其中該圖案化半導體保護層包括至少一第一部分和一第二部分，該至少一第一部分設置於該凹槽的週邊，該第二部分設置於該凹槽的下方，且該至少一第一部分的厚度大於該第二部分的厚度。 The high electron mobility transistor of claim 9, wherein the patterned semiconductor protective layer comprises at least a first part and a second part, the at least one first part is disposed around the groove, and the second part is disposed below the groove, and the thickness of the at least one first part is greater than the thickness of the second part.

如請求項1所述的高電子遷移率電晶體，另包括一鈍化層，順向性的設置於該半導體阻障層的頂面、該圖案化半導體蓋層的側面、及該圖案化半導體保護層的側面和頂面。 The high electron mobility transistor according to claim 1, further comprising a passivation layer disposed on the top surface of the semiconductor barrier layer, the side surface of the patterned semiconductor cap layer, and the patterned semiconductor protection layer The sides and top of the layer.

一種高電子遷移率電晶體的製作方法，包括：提供一基底，其上依序設置有一半導體通道層、一半導體阻障層、一半導體蓋層、以及一半導體保護層；蝕刻該半導體蓋層及該半導體保護層，以形成一圖案化半導體蓋層及一圖案化半導體保護層；形成一層間介電層，覆蓋住該圖案化半導體蓋層及該圖案化半導體保護層；形成一閘極接觸洞於該層間介電層中，其中該閘極接觸洞的底面會暴露出該圖案化半導體保護層且分離於該圖案化半導體蓋層；以及形成一閘極電極於該閘極接觸洞中，其中該閘極電極及該圖案化半導體蓋層之間存在部分的該圖案化半導體保護層，其中，該圖案化半導體保護層的電阻率介於該圖案化半導體蓋層的電阻率及該層間介電層的電阻率之間。 A method for manufacturing a high electron mobility transistor, comprising: providing a substrate on which a semiconductor channel layer, a semiconductor barrier layer, a semiconductor cap layer, and a semiconductor protective layer are sequentially disposed; etching the semiconductor cap layer and the The semiconductor protective layer is used to form a patterned semiconductor cap layer and a patterned semiconductor protective layer; an interlayer dielectric layer is formed to cover the patterned semiconductor cap layer and the patterned semiconductor protective layer; a gate contact hole is formed in the interlayer dielectric layer, wherein the bottom surface of the gate contact hole exposes the patterned semiconductor protective layer and is separated from the patterned semiconductor cap layer; and a gate electrode is formed in the gate contact hole, wherein Part of the patterned semiconductor protective layer exists between the gate electrode and the patterned semiconductor cap layer, wherein the resistivity of the patterned semiconductor cap layer is between the resistivity of the patterned semiconductor cap layer and the interlayer dielectric between the resistivities of the layers.

如請求項12所述的高電子遷移率電晶體的製作方法，其中在蝕刻該半導體蓋層及該半導體保護層之前，另包括在該半導體保護層之上形成一遮罩層，且在蝕刻該半導體蓋層及該半導體保護層時，會移除暴露出於該遮罩層的該半導體蓋層及該半導體保護層。 The method for fabricating a high electron mobility transistor as claimed in claim 12, wherein before etching the semiconductor cap layer and the semiconductor protective layer, further comprising forming a mask layer on the semiconductor protective layer, and etching the semiconductor cap layer and the semiconductor protective layer. When the semiconductor capping layer and the semiconductor protective layer are used, the semiconductor capping layer and the semiconductor protective layer exposed on the mask layer are removed.

如請求項13所述的高電子遷移率電晶體的製作方法，在形成該層間介電層之前，另包括移除該遮罩層，其中在移除該遮罩層之前和形成該層間介電層之後，該圖案化半導體保護層的寬度維持固定。 The method for fabricating a high electron mobility transistor as claimed in claim 13, before forming the interlayer dielectric layer, further comprising removing the mask layer, wherein before removing the mask layer and forming the interlayer dielectric layer After layering, the width of the patterned semiconductor protective layer remains fixed.

如請求項14所述的高電子遷移率電晶體的製作方法，其中在移除該遮罩層之前和形成該層間介電層之後，該圖案化半導體保護層的側面切齊該圖案化半導體蓋層的側面。 The method of fabricating a high electron mobility transistor as claimed in claim 14, wherein the removing Before the mask layer and after forming the interlayer dielectric layer, the side surfaces of the patterned semiconductor protective layer are flush with the side surfaces of the patterned semiconductor cap layer.

如請求項12所述的高電子遷移率電晶體的製作方法，其中形成該閘極接觸洞於該層間介電層中的步驟包括施行光微影及蝕刻製程。 The method for fabricating a high electron mobility transistor as claimed in claim 12, wherein the step of forming the gate contact hole in the interlayer dielectric layer includes performing photolithography and etching processes.

如請求項12所述的高電子遷移率電晶體的製作方法，其中該圖案化半導體保護層的電阻率低於該閘極電極的電阻率。 The method for fabricating a high electron mobility transistor according to claim 12, wherein the resistivity of the patterned semiconductor protective layer is lower than the resistivity of the gate electrode.

如請求項12所述的高電子遷移率電晶體的製作方法，其中該閘極電極直接接觸該圖案化半導體保護層。 The method for fabricating a high electron mobility transistor according to claim 12, wherein the gate electrode directly contacts the patterned semiconductor protective layer.

如請求項12所述的高電子遷移率電晶體的製作方法，其中在形成該閘極電極之後，該圖案化半導體保護層的表面包括一凹槽，且該閘極電極係填滿該凹槽。 The method for manufacturing a high electron mobility transistor according to claim 12, wherein after the gate electrode is formed, the surface of the patterned semiconductor protective layer includes a groove, and the gate electrode fills the groove .

如請求項19所述的高電子遷移率電晶體的製作方法，其中在形成該閘極電極之後，該圖案化半導體保護層包括至少一第一部分和一第二部分，該至少一第一部分設置於該凹槽的週邊，該第二部分設置於該凹槽的下方，且該至少一第一部分的厚度大於該第二部分的厚度。 The method for fabricating a high electron mobility transistor according to claim 19, wherein after the gate electrode is formed, the patterned semiconductor protective layer includes at least a first part and a second part, and the at least one first part is disposed on the At the periphery of the groove, the second portion is disposed below the groove, and the thickness of the at least one first portion is greater than the thickness of the second portion.