TWI754823B - 半導體裝置及其形成方法 - Google Patents
半導體裝置及其形成方法 Download PDFInfo
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- TWI754823B TWI754823B TW108121894A TW108121894A TWI754823B TW I754823 B TWI754823 B TW I754823B TW 108121894 A TW108121894 A TW 108121894A TW 108121894 A TW108121894 A TW 108121894A TW I754823 B TWI754823 B TW I754823B
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- layer
- gate
- gate spacer
- dielectric
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- 238000000034 method Methods 0.000 title claims abstract description 108
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 125000006850 spacer group Chemical group 0.000 claims abstract description 129
- 238000000231 atomic layer deposition Methods 0.000 claims abstract description 91
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 48
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 claims abstract description 32
- 238000000151 deposition Methods 0.000 claims abstract description 24
- 229910021529 ammonia Inorganic materials 0.000 claims abstract description 14
- 238000010926 purge Methods 0.000 claims abstract 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 128
- 229910052757 nitrogen Inorganic materials 0.000 claims description 66
- 238000000137 annealing Methods 0.000 claims description 54
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 36
- 229910052710 silicon Inorganic materials 0.000 claims description 31
- 239000010703 silicon Substances 0.000 claims description 23
- 229910052760 oxygen Inorganic materials 0.000 claims description 18
- 239000001301 oxygen Substances 0.000 claims description 16
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 14
- 238000007789 sealing Methods 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 230000007423 decrease Effects 0.000 claims description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- 229910052799 carbon Inorganic materials 0.000 claims description 10
- 239000007789 gas Substances 0.000 claims description 8
- 229910052739 hydrogen Inorganic materials 0.000 claims description 8
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 7
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 7
- 239000001257 hydrogen Substances 0.000 claims description 6
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims 1
- 229910000077 silane Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 153
- 238000005229 chemical vapour deposition Methods 0.000 description 20
- 238000002955 isolation Methods 0.000 description 19
- 239000000758 substrate Substances 0.000 description 19
- 239000000463 material Substances 0.000 description 18
- 230000015572 biosynthetic process Effects 0.000 description 15
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- 229910052581 Si3N4 Inorganic materials 0.000 description 11
- 230000006378 damage Effects 0.000 description 11
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 239000000203 mixture Substances 0.000 description 8
- 239000000126 substance Substances 0.000 description 8
- 238000005137 deposition process Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 125000004430 oxygen atom Chemical group O* 0.000 description 6
- 238000000059 patterning Methods 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- 125000004433 nitrogen atom Chemical group N* 0.000 description 5
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 4
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- CFOAUMXQOCBWNJ-UHFFFAOYSA-N [B].[Si] Chemical compound [B].[Si] CFOAUMXQOCBWNJ-UHFFFAOYSA-N 0.000 description 3
- 239000000460 chlorine Substances 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 230000009969 flowable effect Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000011148 porous material Substances 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- 238000006467 substitution reaction Methods 0.000 description 3
- IHGSAQHSAGRWNI-UHFFFAOYSA-N 1-(4-bromophenyl)-2,2,2-trifluoroethanone Chemical compound FC(F)(F)C(=O)C1=CC=C(Br)C=C1 IHGSAQHSAGRWNI-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- 229910008051 Si-OH Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910006358 Si—OH Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- -1 Yb 2 O 3 Inorganic materials 0.000 description 2
- CHYRFIXHTWWYOX-UHFFFAOYSA-N [B].[Si].[Ge] Chemical compound [B].[Si].[Ge] CHYRFIXHTWWYOX-UHFFFAOYSA-N 0.000 description 2
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 2
- IHLNQRLYBMPPKZ-UHFFFAOYSA-N [P].[C].[Si] Chemical compound [P].[C].[Si] IHLNQRLYBMPPKZ-UHFFFAOYSA-N 0.000 description 2
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 description 2
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005253 cladding Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 125000000524 functional group Chemical group 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910005542 GaSb Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910021193 La 2 O 3 Inorganic materials 0.000 description 1
- 229910018540 Si C Inorganic materials 0.000 description 1
- 229910018557 Si O Inorganic materials 0.000 description 1
- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- AUCDRFABNLOFRE-UHFFFAOYSA-N alumane;indium Chemical compound [AlH3].[In] AUCDRFABNLOFRE-UHFFFAOYSA-N 0.000 description 1
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- LVQULNGDVIKLPK-UHFFFAOYSA-N aluminium antimonide Chemical compound [Sb]#[Al] LVQULNGDVIKLPK-UHFFFAOYSA-N 0.000 description 1
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- VTYDSHHBXXPBBQ-UHFFFAOYSA-N boron germanium Chemical compound [B].[Ge] VTYDSHHBXXPBBQ-UHFFFAOYSA-N 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 150000001721 carbon Chemical group 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 125000001309 chloro group Chemical group Cl* 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 125000000325 methylidene group Chemical group [H]C([H])=* 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
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- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
- H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
- H01L21/02326—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen into a nitride layer, e.g. changing SiN to SiON
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- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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Abstract
一種形成半導體裝置的方法,包含形成閒置閘極堆疊於晶圓的半導體區域之上,以及使用原子層沉積(Atomic Layer Deposition,ALD)於閒置閘極堆疊的側壁上沉積閘極間隔物層。沉積閘極間隔物層包括執行原子層沉積(ALD)循環,以形成介電原子層。原子層沉積(ALD)循環包括引入矽烷化的甲基到晶圓上,清除矽烷化的甲基,引入氨到晶圓上,以及清除氨。
Description
本發明實施例係關於半導體技術,且特別關於一種在半導體裝置中的含氮低介電常數閘極間隔物及其形成方法。
電晶體是積體電路中的基本建構元件。在積體電路的先前發展中,電晶體的閘極從多晶矽閘極轉移到金屬閘極,金屬閘極通常以取代閘極形成。取代閘極的形成包括形成閒置閘極堆疊,在閒置閘極堆疊的側壁上形成閘極間隔物,移除閒置閘極堆疊以在閘極間隔物之間形成開口,沉積閘極介電層和金屬層到開口中,然後執行化學機械研磨(Chemical Mechanical Polishing,CMP)製程以移除閘極介電層和金屬層的剩餘部分。閘極介電層和金屬層的剩餘部分即為取代閘極。
一種形成半導體裝置的方法,包括:形成閒置閘極堆疊於晶圓的半導體區域上;以及使用原子層沉積法沉積閘極間隔物層於閒置閘極堆疊的側壁,其中沉積閘極間隔物層的步驟包括執行原子層沉積循環以形成介電原子層,其中原子層沉積循環包括引入矽烷化甲基到晶圓;清除上述矽烷化甲基;引入氨到晶圓;以及清除上述氨。
一種形成半導體裝置的方法,包括:形成閒置閘極堆疊於晶圓的半導體區域上;形成包括矽、氮、氧、碳及氫的介電層,其中介電層具有第一介電常數值;以及對介電層執行退火,其中在退火之後,介電層具有一第二介電常數值,第二介電常數值低於第一介電常數值。
一種半導體裝置,包括:半導體區域;閘極堆疊,於半導體區域之上;閘極間隔物,在閘極堆疊的側壁上,其中閘極間隔物包括矽、氮、氧、碳及氫,閘極間隔物為低介電常數介電層;以及源極/汲極區域,於閘極間隔物的一側。
以下內容提供了很多不同的實施例或範例,用於實現本發明實施例的不同部件。組件和配置的具體實施例或範例描述如下,以簡化本發明實施例。當然,這些僅僅是範例,並非用以限定本發明實施例。舉例來說,元件尺寸並未限於所揭露的範圍或數值,而可取決於製程條件及/或裝置期望的特性。再者,敘述中若提及第一部件形成於第二部件之上,可能包含形成第一和第二部件直接接觸的實施例,也可能包含額外的部件形成於第一和第二部件之間,使得第一和第二部件不直接接觸的實施例。另外,本發明實施例可能在許多範例中重複元件符號及/或字母。這些重複是為了簡化和清楚的目的,其本身並非代表所討論各種實施例及/或配置之間有特定的關係。
再者,此處可能使用空間上的相關用語,例如「在……之下」、「在……下方」、「下方的」、「在……上方」、「上方的」和其他類似的用語可用於此,以便描述如圖所示之一元件或部件與其他元件或部件之間的關係。此空間上的相關用語除了包含圖式繪示的方位外,也包含使用或操作中的裝置的不同方位。當裝置被轉至其他方位時(旋轉90度或其他方位),則在此所使用的空間相對描述可同樣依旋轉後的方位來解讀。
根據各種實施例提供了鰭式場效電晶體(FinFET)及其形成方法。根據一些實施例繪示出了形成鰭式場效電晶體(FinFET)的中間階段。討論了一些實施例的一些變化。在各種視圖和說明性實施例中,相同的元件符號用於表示相同的元件。根據本揭露的一些實施例,鰭式場效電晶體(FinFET)的閘極間隔物摻雜氮並且仍具有低介電常數值。隨著介電常數值的減少,在所得電路中的寄生電容減少。藉由添加氮,閘極間隔物更能抵抗在後續的閒置閘極移除製程中使用電漿所引起的損壞。
第1圖到第11圖係根據本揭露的一些實施例所繪示出形成鰭式場效電晶體(FinFET)的中間階段的透視圖和剖面圖。第1圖到第11圖中所示的步驟,也示意性地反映在第17圖所示之製程流程200中。
第1圖繪示出了初始結構的透視圖。初始結構包括晶圓10,而晶圓10更包括基板20。基板20可以是半導體基板,其可以是矽基板、矽鍺基板,或由其他半導體材料形成的基板。基板20可以摻雜p型或n型雜質。可以形成如淺溝槽隔離(Shallow Trench Isolation,STI)區域的隔離區域22,以從基板20的頂表面延伸到基板20中。相鄰淺溝槽隔離(STI)區域22之間的基板20部分被稱為半導體條24。根據一些實施例,半導體條24的頂表面和淺溝槽隔離(STI)區域22的頂表面可以大體上地彼此齊平。根據本揭露的一些實施例,半導體條24是原始基板20的一部分,因此半導體條24的材料與基板20的材料相同。根據本揭露的替代實施例,半導體條24是由蝕刻在淺溝槽隔離(STI)區域22之間部分的基板20以形成凹槽,並執行磊晶以在凹槽中再生長成另外的半導體材料而形成的取代條。因此,半導體條24由不同於基板20的半導體材料形成。根據本揭露的一些實施例,半導體條24由矽鍺、矽碳或III-V族化合物半導體材料形成。
淺溝槽隔離(STI)區域22可以包括襯層氧化物(未顯示),而襯層氧化物可以是藉由基板20的表層的熱氧化形成的熱氧化物。襯層氧化物也可以是沉積的氧化矽層,使用例如原子層沉積(Atomic Layer Deposition,ALD)、高密度電漿化學氣相沉積(High-Density Plasma Chemical Vapor Deposition,HDP-CVD)或化學氣相沉積(Chemical Vapor Deposition ,CVD)形成。淺溝槽隔離(STI)區域還可以包括襯層氧化物上方的介電材料,其中介電材料可以使用可流動化學氣相沉積(Flowable Chemical Vapor Deposition,FCVD)、旋轉塗佈等等形成。
參考第2圖,淺溝槽隔離(STI)區域是凹陷的(recessed),使得半導體條24的頂部比淺溝槽隔離(STI)區域22的剩餘部分的頂表面22A突出得更高,以形成突出的鰭片24'。上述相應的製程在第17圖的製程流程中繪示為製程202。可以使用乾蝕刻製程來執行蝕刻,其中HF3
和NH3
用作蝕刻氣體。根據本揭露的替代實施例,使用濕蝕刻製程執行淺溝槽隔離(STI)區域22的凹陷。蝕刻化學品可包括例如HF溶液。
在上述的實施例中,可以藉由任何適合的方法圖案化鰭片。例如,可以使用一個或多個微影製程來圖案化鰭片,包括雙重圖案化(Double Patterning)或多重圖案化(Multiple Patterning)製程。大致上而言,雙重圖案化或多重圖案化製程結合微影和自對準(Self-Aligned)製程,得以創造具有比,例如使用單一且直接微影製程可獲得的節距,更小節距的圖案。例如,在一實施例中,在基板上形成犧牲層並使用微影製程圖案化。使用自對準製程在圖案化的犧牲層旁邊形成間隔物。接著移除犧牲層,剩餘的間隔物或心軸可接續用來圖案化鰭片。
突出的鰭片24'的材料也可以用不同於基板20的材料來取代。例如,突出的鰭片24'可以由矽(Si)、矽磷(SiP)、碳化矽(SiC)、矽碳磷(SiCP)、矽鍺(SiGe)、矽鍺硼(SiGeB)、鍺(Ge)或 III-V族化合物半導體,例如磷化銦(InP)、砷化鎵(GaAs)、砷化鋁(AlAs)、砷化銦(InAs)、砷化鋁銦(InAlAs)、砷化銦鎵(InGaAs)等等。
參考第3A圖,形成與突出的鰭片24'交叉(cross)的閒置閘極堆疊30。上述相應的製程在第17圖的製程流程中繪示為製程204。閒置閘極堆疊30可以包括閒置閘極介電質32和閒置閘極介電質32上的閒置閘極電極34。閒置閘極介電質32可以由氧化矽或其他介電材料形成。閒置閘極電極34可以例如使用多晶矽形成,並且也可以使用其他材料。每個閒置閘極堆疊30還可以包括在閒置閘極電極34上方的一個(或多個)硬罩幕層36。硬罩幕層36可以由氮化矽、氧化矽、碳氮化矽或其多層膜形成。閒置閘極堆疊30可以跨越單一個或多個突出的鰭片24'及/或淺溝槽隔離(STI)區域22。閒置閘極堆疊30的長度方向(lengthwise direction)垂直於突出鰭片24'的長度方向。閒置閘極堆疊30的形成包括沉積閒置閘極介電質層,在閒置閘極介電質層上沉積閘極電極層,沉積硬罩幕層以及圖案化堆疊層。
根據替代實施例,如第3B圖所示,在沉積膜層之後,圖案化閘極電極層和硬罩幕層以形成閒置閘極堆疊30,而不圖案化閘極介電質32。因此,閒置閘極介電質層32覆蓋未被閒置閘極堆疊30覆蓋的突出鰭片24'的頂表面和側壁的部分。
接下來,參考第4A圖和第4B圖,閘極間隔物38形成在閒置閘極堆疊30的側壁上。上述相應的製程在第17圖的製程流程中繪示為製程206。第4A圖繪示出了基於第3A圖的結構而形成的結構,第4B圖繪示出了基於第3B圖的結構而形成的結構。閘極間隔物38的形成可以包括沉積具有垂直和水平部分的介電層,然後執行非等向性蝕刻以移除水平部分,留下垂直部分作為閘極間隔物38。在沉積製程中,介電質層可以在閘極介電質層32、閘極堆疊30和淺溝槽隔離(STI)區域22的暴露的表面上形成。根據本揭露的一些實施例,閘極間隔物38由包括Si、N、O、C和H的介電材料形成。另外,閘極間隔物38包括至少一些部分由介電常數值低於3.9的低介電常數介電材料形成。閘極間隔物38的至少一些部分的介電常數值,可以約在3.0和3.9之間。以下參照第4A圖和第4B圖以及第12圖至第15圖,說明了閘極間隔物38的形成。
第12圖繪示出了閘極間隔物層37的成長/沉積製程,然後以非等向性蝕刻,形成閘極間隔物38,如第4A圖和第4B圖所示。在沉積製程開始時,將晶圓10放置在原子層沉積(ALD)腔室中。第12圖中所示的中間結構以元件符號112、114、116、118和120表示,來區分每個階段所產生的結構。晶圓10包括基層110,而基層110可以表示閒置閘極電極34、閘極介電層32、淺溝槽隔離(STI)區域22、突出的鰭片24'等等,如第3A圖和第3B圖所示,只要它們在沉積製程開始時暴露即可。在所繪示的範例中,基層110顯示為包括矽,其可以是結晶矽(crystalline silicon),非晶矽(amorphous silicon)或多晶矽的形式。根據本揭露的一些實施例,由於天然氧化物的形成和水氣的接觸,在含矽層110的表面處形成Si-OH鍵。基層110可包括其他類型的含矽材料如氧化矽、氮化矽、碳氧化矽、氮氧化矽等等。第12圖中的沉積層37也可以沉積在其他非含矽層上。
進一步參考第12圖,在製程130中,將氨(NH3
)引入(introduce)/脈衝(pulse)到放置有晶圓10(第3A圖或第3B圖)的原子層沉積(ALD)腔室中。將晶圓10加熱至例如約在200℃至500℃之間的溫度。如結構112中所示的Si-OH鍵斷裂,並且矽原子與NH分子鍵結以形成Si-NH鍵。所得到的結構稱為結構114。根據本揭露的一些實施例,當引入NH3
時,不開啟(turn on)電漿。NH3
可以停留在腔室中約5秒至15秒的時間。
接下來,從相應的腔室中清除(purge)NH3
。原子層沉積(ALD)循環用於生長介電材料的原子層。原子層沉積(ALD)循環包括製程132和134以及在每個製程132和134之後相應的清除步驟。在製程132中,引入矽烷化甲基(silylated methyl)。矽烷化甲基可具有化學式(SiCl3
)2
CH2
。根據一些實施例,第13圖繪示出矽烷化甲基的化學式。化學式表示矽烷化甲基包括與兩個矽原子鍵結的氯原子,和與碳原子鍵結的兩個矽原子。藉由矽烷化甲基的引入/脈衝,晶圓10的溫度也保持在高溫,例如,約在200℃和500℃之間的溫度。也可以與引入NH3
的製程保持相同的溫度。根據本揭露的一些實施例,當引入矽烷化甲基時,不開啟電漿。矽烷化甲基可具有約0.5torr至10torr的壓力。
結構114與矽烷化甲基反應。所得到的結構稱為結構116。結構114中的N-H鍵斷裂,且每個矽原子的Si-Cl鍵斷裂,使得每個矽原子鍵結到一個氮原子上。因此,矽烷化甲基分子與兩個氮原子鍵結。在製程132中,矽烷化甲基可以停留在原子層沉積(ALD)腔室中約5秒至15秒的時間。然後從相應的腔室中清除矽烷化甲基。
接下來,進一步參考第12圖中的製程134,將NH3
引入原子層沉積(ALD)腔室,並且NH3
與結構116反應以形成結構118。如此一來,如結構116中所示的Si-Cl鍵斷裂,矽原子與NH分子鍵結形成Si-NH鍵。根據本揭露的一些實施例,在引入NH3
的期間,將晶圓10加熱至例如約200℃和約500℃之間的溫度。可以不開啟電漿。NH3
可以停留在原子層沉積(ALD)腔室中約5秒至約15秒的時間。NH3
可具有約0.5 torr至10 torr的壓力。接下來,從相應的腔室中清除NH3
。因此完成了製程132和134以及相應的清除製程的第一原子層沉積(ALD)循環。第一原子層沉積(ALD)循環形成了原子層39。
執行第二原子層沉積(ALD)循環(製程136)。執行第二原子層沉積(ALD)循環136,而第二原子層沉積(ALD)循環與包括製程132和134以及相應的清除製程的原子層沉積(ALD)循環實質上相同。同樣地,在第二原子層沉積(ALD)循環中引入矽烷化甲基時,結構118(在晶圓10上)與矽烷化甲基反應。一些N-H鍵(結構118)被破壞,並且在矽烷化甲基中的每個矽原子的Si-Cl鍵(第13圖)也被破壞,然後鍵結到氮原子上。因此,矽烷化甲基分子與兩個氮原子鍵結。矽烷化甲基可以停留在腔室中約5秒至15秒的時間。接下來,從相應的腔室中清除矽烷化甲基。然後引入NH3
,其導致Si-Cl鍵斷裂,且NH分子與矽原子鍵結。如第12圖所示,第二原子層沉積(ALD)循環導致另一個原子層生長。根據本揭露的一些實施例,在第二原子層沉積(ALD)循環期間,也加熱晶圓10,例如,到約200℃和500℃之間的溫度。在第二原子層沉積(ALD)循環期間可以不開啟電漿。第二原子層沉積(ALD)循環導致在先前形成的原子層39上形成另一原子層39。
然後執行多個原子層沉積(ALD)循環,在每個生長介電層37的原子層(類似於原子層39)期間,每個原子層沉積(ALD)循環基本上與第一原子層沉積(ALD)循環相同。每個原子層沉積(ALD)循環使得閘極間隔物38的厚度增加,或者例如增加約0.5 Å,並且最終形成閘極間隔物層37。在非等向性蝕刻製程中後續圖案化閘極間隔物層37,得到閘極間隔物38如第4A圖和第4B圖所示。根據本揭露的一些實施例,閘極間隔物層37(和相應的閘極間隔物38)的總厚度取決於設計需求,約大於20Å,並且可以在約20 Å和約70 Å之間。根據本揭露的一些實施例,在晶圓10保持在相同溫度的情況下執行原子層沉積(ALD)循環。根據替代實施例,可以在不同溫度下執行不同的原子層沉積(ALD)循環,如後續段落中所討論的。
應理解的是,所討論的製程不限於閘極間隔物的形成,並且可用於形成介電層和其他垂直介電部件。
使用包括SiNOCH的原子層沉積(ALD)循環,形成閘極間隔物層37(第12圖)和閘極間隔物38(第4A圖和第4B圖)。所形成的閘極間隔物38的介電常數值(在經過後續的退火製程之前)可以約高於7或更高。根據本揭露的一些實施例,通過原子層沉積(ALD)循環形成的閘極間隔物38具有約3%和約30%之間的氮原子百分比,這取決於製程條件。在閘極間隔物38中的氮原子百分比與原子層沉積(ALD)循環的溫度相關,並且較高的溫度導致較高的氮原子百分比,較低的溫度導致較低的氮原子百分比。
返回參考第4A圖和第4B圖,閘極間隔物38可以具有均勻的組成(具有均勻百分比的Si、O、C、H及/或N)。根據替代實施例,閘極間隔物38可以具有不同的組成的有不同的部分(子層),例如,不同的氮原子百分比。不同的部分由子層38A、38B、38C和38D示意性地表示。閘極間隔物38中的子層根據38A→38B→38C→38D的順序形成。
應當理解的是,在後續的步驟(第7B圖和第8圖)中移除閒置閘極堆疊,其可以涉及產生電漿的乾蝕刻。閘極間隔物38,特別是內部部分如子層38A,暴露於電漿的損壞,並且可能被不利地蝕刻掉。當閘極間隔物38具有較高的氮原子百分比時,它們更能抵抗由電漿引起的損壞。因此,根據本揭露的一些實施例,在移除閒置閘極堆疊30時(第8圖),子層38A可以形成具有比剩餘子層38B、38C和38D更高的氮原子百分比。
在沉積時,子層38A、38B、38C和38D(剛沉積時)可具有約3%和約30%之間的氮原子百分比。根據本揭露的一些實施例,剛沉積時的閘極間隔物38(包括所有子層38A、38B、38C和38D)的整體具有相同的氮原子百分比。根據替代實施例,在38A→38B→38C→38D的方向上,氮原子百分比逐漸減少。因為高氮的子層38A的存在,在第8圖所示的步驟中,由於子層38A暴露於電漿,閘極間隔物38改善了對電漿損壞的抵抗性。由於子層38B、38C和38D中的氮的減少,子層38B、38C和38D減少了介電常數值(k值),並且閘極間隔物38的總介電常數值(k值)減少,導致在相應的閘極與周遭的部件之間的寄生電容減少。因此,降低子層38A、38B、38C和38D的氮原子百分比可以改善閘極間隔物38對電漿損壞的抵抗性,同時仍然保持低的寄生電容。根據本揭露的一些實施例,從內側壁38'到外側壁38''的氮原子百分比持續減少。例如,這可以藉由在形成閘極間隔物38的期間,逐漸降低晶圓10的溫度來實現。例如,後面執行的原子層沉積(ALD)循環,可以在比先前執行的原子層沉積(ALD)循環更低的溫度下執行,而其他製程條件,如矽烷化甲基和NH3
的壓力、脈衝的持續時間等等,從一個原子層沉積(ALD)循環到另一個原子層沉積(ALD)循環,可以是相同的。溫度的降低可以是連續的或分階段的(in stages)。例如,第16A圖繪示出了一些可能的溫度分佈(temperature profile),其為相應的子層和內側壁38'的距離的函數(第4A圖和第4B圖)。線141表示溫度分佈,其中溫度在膜層37(第12圖)的整個沉積製程中是均勻的。線142表示溫度分佈,其中溫度是連續降低的。線144表示溫度分佈,其中溫度是分階段降低的,且每個階段可以對應於一個子層或多個子層的形成。所得到的氮原子百分比可以顯示出類似的連續降低或分階段降低的趨勢,如第16B圖中示意性地所示。應當理解的是,儘管第16B圖繪示出了退火後的氮原子百分比如線146和線148所示,如後續段落中所討論的,氮原子百分比在退火後顯示出類似的趨勢,除了退火後氮原子百分比的減少變得更平滑之外。
在閘極間隔物38的沉積(成長)之後,執行退火。可以在蝕刻閘極間隔層37(第12圖)之前或之後執行退火以形成閘極間隔物38(第4A圖和第4B圖)。根據本揭露的一些實施例,退火在含氧環境下進行,而含氧環境可以包括水蒸氣(H2
O)、氧氣(O2
)、氧自由基(O)或其組合。退火可以在約400℃和約500℃的溫度範圍內執行。退火可持續約30分鐘至約2小時。退火導致在閘極間隔物38中孔隙(pores)的形成,以及閘極間隔物38的介電常數值(k值)的減小。可以在開啟或不開啟電漿的情況下執行退火。根據本揭露的一些實施例,作為退火的結果,閘極間隔物38的介電常數值例如減少大於2.0的值。閘極間隔物38的介電常數值可以減少到低於3.9,因此閘極間隔物38可以變成低介電常數介電閘極間隔物。
第14圖繪示出了在退火之前和之後的閘極間隔物38的結構變化。如第14圖所示,由於退火,由圓圈150圈出的兩個NH鍵被氧原子取代,如圓圈152所示。此外,兩個矽原子的亞甲基橋(-CH2
)156也可被破壞,且額外的氫原子可以連接到碳上,以形成與一個矽原子連接的甲基(-CH3
)官能基(在圓圈159中)。然後將未與甲基官能基(在圓圈159中)連接的另一個矽原子與氧原子鍵結(在圓圈155中)。可以在這個製程中形成孔隙。有效地,Si-C鍵之一被Si-O鍵取代。第14圖繪示出了閘極間隔物38的一部分,其中CH2
(在圓圈157中)被CH3
(在圓圈159中)和氧原子(在圓圈155中)取代。應理解的是,每個新連接的氧原子(在圓圈155中)具有兩個鍵(未顯示出其他鍵),可以連接到其他矽原子上。第15圖繪示出了間隔物層37的一部分,其中兩個矽原子與新連接的氧原子鍵結。由於以氧取代NH基和形成的孔隙,減少了閘極間隔物38的介電常數值。
退火溫度和退火持續時間影響所得的閘極間隔物38的氮原子百分比和介電常數值。在退火之前,氮原子百分比高,而閘極間隔物38的介電常數值也高。例如,當氮原子百分比約高於10%時,閘極間隔物38的介電常數值約高於3.9。當退火溫度低時,隨著溫度的升高,更多的NH分子被氧原子取代,且更多的亞甲基橋(-CH2
)被破壞而形成Si-CH3
鍵。因此,介電常數值變低,氮原子百分比也變低。然而,當溫度進一步升高或退火進一步延長時,氮原子損失過多,介電常數值將再次增加。根據本揭露的一些實施例,閘極間隔物38(當具有低介電常數值時)具有從退火前約3%和約30%之間的氮原子百分比減少到約1%和約10%的氮原子百分比。根據本揭露的一些實施例,退火導致所得的介電層38/38'中的第一氮原子百分比降低至第二氮原子百分比,並且第二氮原子百分比與第一氮原子百分比的比例可以在約1/5和約1/2之間。
另外,氮原子百分比的降低導致閘極間隔物對電漿損壞的抵抗性降低。因此,期望在退火之後,閘極間隔物具有約1%和約10%之間的氮原子百分比,且可以在約1%和約5%之間的氮原子百分比。因此,退火溫度保持在約400℃和約500℃的理想範圍內,以實現低介電常數值,而不會降低(compromise)閘極間隔物對電漿損壞的抵抗能力。退火後閘極間隔物38中的氮原子百分比可以如第16B圖中示意性地所示,可看得出氮原子百分比的值比退火前還低。第16B圖繪示出了示意性氮原子百分比(第4A圖和第4B圖),其為和內側壁38'的距離的函數的。從內側壁38'到外側壁38''的方向上,氮原子百分比的減少可能是由於外部部分(更靠近外側壁38'')比內部部分(更靠近內側壁38')退火地更充分,因此外部部分比內部部分損失更多的氮。從內側壁38'到外側壁38的方向上,氮原子百分比的減少也可以歸因於如第16A圖所示的氮原子百分比分佈。
退火還導致閘極間隔物38的密度降低。例如,與退火前約高於2.3g/cm3
的密度相比,在退火之後,閘極間隔物38的密度可以降低到約低於2.0g/cm3
,並且可以落入約1.6g/cm3
到1.9g/cm3
之間。
根據本揭露的一些實施例,在退火之後,子層38A可以具有比閘極間隔物38的其他部分更高的介電常數值。因此,子層38A可以用作密封層以保護其他部分,例如子層38B、38C和38D,免於受到電漿的損壞。在退火之後,密封層38A可具有高於、等於或低於3.9的介電常數值。
根據本揭露的其他實施例,子層38A由氮化矽、碳氧化矽等等形成。除了製程氣體不同之外,還可以使用原子層沉積(ALD)形成。例如,當由氮化矽形成時,製程氣體可包含NH3
和二氯矽烷(DiChloroSilane,DCS)(SiH2
Cl2
)。所得到的密封層38A具有高於4.0的介電常數值,且介電常數值可以約在4.0和7.0之間。
在後續繪示出的圖式中,第4A圖中所示的結構用作示例。基於第4B圖所形成的結構亦可被理解。在後續的步驟中,形成源極/汲極區域,如第5圖和第6A圖和第6B圖所示。上述相應的製程在第17圖的製程流程中繪示為製程208。根據本揭露的一些實施例,執行蝕刻製程(下文中稱為鰭片凹蝕)以蝕刻突出的鰭片24'中未被閒置閘極堆疊30和閘極間隔物38覆蓋的部分,得到的結構如第5圖所示。如果介電層32(第4B圖)具有未被閒置閘極堆疊30和閘極間隔物38覆蓋的部分,則先蝕刻這些部分。突出的鰭片24'的凹陷可以是非等向性的,因此直接位於閒置閘極堆疊30和閘極間隔物38下面的鰭片24'受到保護,並且不被蝕刻。根據一些實施例,凹陷的半導體條24的頂表面可以低於淺溝槽隔離(STI)區域22的頂表面22A。因此,在淺溝槽隔離(STI)區域22之間形成凹槽40。凹槽40位於閒置閘極堆疊30的兩側。
接下來,藉由在凹槽40中選擇性地生長半導體材料來形成磊晶區域(源極/汲極區域)42,得到第6A圖中的結構。根據本揭露的一些實施例,磊晶區域42包括矽鍺、矽或矽碳。取決於所得的鰭式場效電晶體(FinFET)是p型鰭式場效電晶體(FinFET)或是n型鰭式場效電晶體(FinFET),可以藉由磊晶的進行原位(in-situ)摻雜p型或n型雜質。例如,當得到的鰭式場效電晶體(FinFET)是p型鰭式場效電晶體(FinFET)時,可以生長矽鍺硼(SiGeB)、鍺硼(GeB)等等。相反地,當得到的鰭式場效電晶體(FinFET)是n型鰭式場效電晶體(FinFET)時,可以生長矽磷(SiP)、矽碳磷(SiCP)等等。根據本揭露的替代實施例,磊晶區域42由III-V族化合物半導體形成,例如砷化鎵(GaAs)、磷化銦(InP)、氮化鎵(GaN)、砷化銦鎵(InGaAs),砷化鋁銦(InAlAs)、銻化鎵(GaSb)、銻化鋁(AlSb)、砷化鋁(AlAs)、磷化鋁(AlP)、磷化鎵(GaP)、其組合或其多層膜。在磊晶區域42完全填充凹槽40之後,磊晶區域42開始水平擴展,並且可以形成小刻面(facet)。
在磊晶步驟之後,可以以p型或n型雜質進一步植入磊晶區域42以形成源極和汲極區域,而源極和汲極區域也使用符號元件42表示。根據本揭露的替代實施例,當磊晶區域42在磊晶期間在原位摻雜p型或n型雜質以形成源極/汲極區域時,跳過佈植步驟。磊晶源極/汲極區域42包括形成在淺溝槽隔離(STI)區域22的下部分,以及形成在淺溝槽隔離(STI)區域22的頂表面上方的上部分。
第6B圖繪示出了根據本揭露的替代實施例的包層(cladding)源極/汲極區域42的形成。根據這些實施例,如第3圖所示的突出的鰭片24'不是凹陷的,並且磊晶區域41生長在突出的鰭片24'上。磊晶區域41的材料可以類似於磊晶半導體材料42的材料,如第6A圖所示,這取決於所得到的鰭式場效電晶體(FinFET)是p型或n型鰭式場效電晶體(FinFET)。因此,源極/汲極區域42包括突出的鰭片24'和磊晶區域41。可以(或不以)佈植來植入n型雜質或p型雜質。應當理解的是,如第6A圖和第6B圖所示的源極/汲極區域42可以彼此合併,或保持分離。
第7A圖繪示出了在形成接觸蝕刻停止層(Contact Etch Stop Layer,CESL)46和層間介電質(Inter-Layer Dielectric,ILD)48之後的結構的透視圖。上述相應的製程在第17圖的製程流程中繪示為製程210。接觸蝕刻停止層(CESL)46可以由氮化矽、碳氮化矽等等形成。可以使用例如原子層沉積(ALD)或化學氣相沉積(CVD)的共形沉積方法形成接觸蝕刻停止層(CESL)46。層間介電質(ILD)48可以包括使用例如可流動化學氣相沉積(FCVD)、旋轉塗佈、化學氣相沉積(CVD)或其他沉積方法形成的介電材料。層間介電質(ILD)48也可以由含氧介電材料形成,前述介電材料可以是基於氧化矽的材料,例如四乙氧基矽烷(Tetra Ethyl Ortho Silicate ,TEOS)氧化物,電漿化學氣相沉積(Plasma Enhanced Chemical Vapor Deposition ,PECVD)氧化物(SiO2
)、磷矽玻璃(Phospho-Silicate Glass, PSG)、硼矽玻璃(Boron-Silicon Glass,BSG)、硼磷矽玻璃(Boron-Doped Phospho-Silicate Glass,BPSG)等等。執行諸如化學機械研磨(CMP)製程或機械研磨(mechanical grinding)製程的平坦化製程以使層間介電質(ILD)48、閒置閘極堆疊30和閘極間隔物38的頂表面彼此齊平。
第7B圖中繪示出了第7A圖中所示的結構的剖面圖。剖面圖是從第7A圖中包含線7B-7B的垂直面所獲得的。如第7B圖所示,繪示出了一個閒置閘極堆疊30。
接下來,用取代閘極堆疊取代包括硬罩幕層36、閒置閘極電極34和閒置閘極介電質32的閒置閘極堆疊30。取代步驟包括在一個或多個蝕刻步驟中蝕刻硬罩幕層36,閒置閘極電極34和閒置閘極介電質32,如第7A圖和第7B圖所示,因此溝槽49形成在閘極間隔物38的相對側之間,如第8圖所示。上述相應的製程在第17圖的製程流程中繪示為製程212。例如可以使用乾蝕刻來執行蝕刻製程。也可以在蝕刻製程中開啟電漿。基於待蝕刻的材料選擇蝕刻氣體。例如,當硬罩幕36包括氮化矽時,蝕刻氣體可以包括含氟製程氣體,例如CF4
/O2
/N2
、NF3
/O2
、SF6
或SF6
/O2
等等。可以使用C2
F6
、CF4
、SO2
,或HBr、Cl2
和O2的混合物,或HBr、Cl2
和O2
的混合物,或HBr,Cl2
,O2
和CF2
的混合物等等來蝕刻閒置閘極電極34。可以使用NF3
和NH3
的混合物或HF和NH3
的混合物來蝕刻閒置閘極介電質32。
在閒置閘極堆疊30的蝕刻中,閘極間隔物38,特別是子層38A,暴露於電漿。子層38A可以包括氮,因此閘極間隔物38更能抵抗由電漿所引起的損壞。根據本揭露的一些實施例,閘極間隔物38的厚度約在20Å和50Å之間,並且損壞部分的厚度可以約小於10Å。密封層38A的厚度可以在蝕刻中減小,例如,從約15Å和約30Å之間的值減少到約5Å和約10 Å之間的值。由於密封層38A更能抵抗由電漿所引起的損壞,因此蝕刻後的密封層38A將保留一些部分以保護子層38B/ 38C/38D,又由於前述子層具有較低的氮原子百分比,因此容易受到傷害。
接下來,參考第9A圖和第9B圖,形成包括閘極介電層54和閘極電極56的(取代)閘極堆疊60。上述相應的製程在第17圖的製程流程中繪示為製程214。第9B圖繪示出了第9A圖中所示的剖面圖,前述剖面圖是從第9A圖中包含線9B-9B的垂直面所獲得的。形成閘極堆疊60包括形成/沉積多個膜層,然後執行平坦化製程,例如化學機械研磨(CMP)製程或機械研磨製程。閘極介電層54延伸到被移除的閒置閘極堆疊所留下的溝槽中。根據本揭露的一些實施例,閘極介電層54包括界面層(Interfacial Layer,IL)50(第9B圖)作為其下部。界面層(IL)50形成在突出的鰭片24'的暴露表面上。界面層(IL)50可以包括氧化物層,例如氧化矽層,其藉由突出的鰭片24'的熱氧化形成,或藉由化學氧化製程或沉積製程形成。閘極介電層54還可以包括在界面層(IL)50上形成的高介電常數介電層52(第9B圖)。高介電常數介電層52包括高介電常數介電材料,例如HfO2
、ZrO2
、HfZrOx、HfSiOx、HfSiON、ZrSiOx、HfZrSiOx、Al2
O3
、HfAlOx、HfAlN、ZrAlOx、La2
O3
、TiO2
、Yb2
O3
、氮化矽等等。高介電常數介電材料的介電常數(k值)高於3.9,並且可約高於7.0。形成高介電常數介電層52為作為共形層,並且在突出的鰭片24'的側壁和閘極間隔物38的側壁上延伸。根據本揭露的一些實施例,使用原子層沉積(ALD)或化學氣相沉積(CVD)形成高介電常數介電層52。
再次參考第9A圖和第9B圖,形成閘極電極56在閘極介電層54的頂部上,並填充被移除的閒置閘極堆疊所留下的溝槽的剩餘部分。閘極電極56中的子層未在第9A圖和第9B圖中單獨顯示,而實際上,由於它們的組成不同,子層可彼此區分。可以使用如原子層沉積(ALD)或化學氣相沉積(CVD)的共形沉積方法,來執行至少下部子層的沉積,使得閘極電極56(以及每個子層)的垂直部分的厚度和水平部分的厚度基本上彼此相等。
閘極電極56可包括多個膜層,包括但不限於氮化鈦矽(TSN)層、氮化鉭(TiN)層、氮化鈦(TiN)層、鈦鋁(TiAl)層、額外的氮化鉭(TiN)及/或氮化鉭(TaN)層,以及填充金屬。這些膜層中的一些定義了相應的鰭式場效電晶體(FinFET)的功函數。此外,p型鰭式場效電晶體(FinFET)的金屬層和n型鰭式場效電晶體(FinFET)的金屬層可以彼此不同,使得金屬層的功函數適合於各個p型或n型鰭式場效電晶體(FinFET)。填充金屬可包括鋁、銅或鈷。
接下來,如第10圖所示,形成硬罩幕62。上述相應的製程在第17圖的製程流程中繪示為製程216。根據本揭露的一些實施例,硬罩幕62的形成包括藉由蝕刻使取代閘極堆疊60凹陷以形成凹槽,填充介電材料到凹槽,並執行平坦化製程以移除介電材料的多餘部分。介電材料的剩餘部分是硬罩幕62。根據本揭露的一些實施例,硬罩幕62由氮化矽、氮氧化矽、碳氧化矽、碳氧氮化矽等等形成。
第11圖繪示出了用於形成接觸插塞的後續步驟。首先形成矽化物區域63和接觸插塞64以延伸到層間介電質(ILD)48和接觸蝕刻停止層(CESL)46中。上述相應的製程在第17圖的製程流程中繪示為製程218。然後形成蝕刻停止層66。根據本揭露的一些實施例,蝕刻停止層66由氮化矽(SiN)、碳氧化矽(SiCN)、碳化矽(SiC)、碳氧氮化矽(SiOCN)等等形成。形成方法可以包括電漿化學氣相沉積(PECVD)、原子層沉積(ALD)、化學氣相沉積(CVD)等等。接下來,在蝕刻停止層66上形成層間介電質(ILD)68。上述相應的製程在第17圖的製程流程中繪示為製程220。層間介電質(ILD)68的材料可以選自於形成層間介電質(ILD)48相同的候選材料(和方法),且層間介電質(ILD)48和68可以由相同或不同的介電材料形成。根據本揭露的一些實施例,層間介電質(ILD)68可使用電漿化學氣相沉積(PECVD)、可流動化學氣相沉積(FCVD)、旋轉塗佈等等形成,並且可以包括氧化矽(SiO2
)。
蝕刻層間介電質(ILD)68和蝕刻停止層66以形成開口。可以使用例如活性離子蝕刻(Reactive Ion Etch,RIE)來執行蝕刻。在隨後的步驟中,如第11圖所示,在開口中形成閘極接觸插塞70和源極/汲極接觸插塞72,以分別電連接到閘極電極56和源極/汲極接觸插塞64。上述相應的製程在第17圖的製程流程中繪示為製程222。因此形成鰭式場效電晶體(FinFET)74。
本揭露的實施例具有一些有利特徵。藉由在不增加閘極間隔物的介電常數值的情況下,將氮加入(incorporate)閘極間隔物中,使得閘極間隔物對電漿損壞的抵抗性(發生在閒置閘極堆疊的蝕刻中)得到改善,而閘極間隔物產生的寄生電容至少是沒有增加,且有可能減少。
根據本揭露的一些實施例,一種形成半導體裝置的方法,包括:形成閒置閘極堆疊於晶圓的半導體區域上;以及使用原子層沉積法沉積閘極間隔物層於閒置閘極堆疊的側壁,其中沉積閘極間隔物層的步驟包括執行原子層沉積循環以形成介電原子層,其中原子層沉積循環包括引入矽烷化甲基到晶圓;清除上述矽烷化甲基;引入氨到晶圓;以及清除上述氨。
在一實施例中,在閘極間隔物層形成之後,對晶圓執行退火,其中將晶圓放置在含氧氣體下執行退火。在一實施例中,約在400℃和約500℃的溫度範圍內執行退火。在一實施例中,在退火之前,閘極間隔物層具有第一氮原子百分比,以及在退火之後,閘極間隔物層的一部分具有低於第一氮原子百分比的第二氮原子百分比。在一實施例中,在退火之前,閘極間隔物層具有第一介電常數值,第一介電常數值高於氧化矽的介電常數值,以及在退火之後,閘極間隔物層的一部分具有第二介電常數值,第二介電常數值低於氧化矽的介電常數值。
在一實施例中,沉積閘極間隔物層的步驟更包括在執行原子層沉積循環之前,引入氨到晶圓。在一實施例中,對閘極間隔物層執行非等向性蝕刻,以於閒置閘極堆疊的兩側形成多個閘極間隔物;以及使用乾蝕刻移除閒置閘極堆疊。在一實施例中,沉積高介電常數介電層作為密封層,其中高介電常數介電層包括將閒置閘極堆疊與閘極間隔物層分開的一部分。在一實施例中,重複原子層沉積循環直到閘極間隔物層具有約大於20Å的厚度。
根據本揭露的一些實施例,一種形成半導體裝置的方法,包括:形成閒置閘極堆疊於晶圓的半導體區域上;形成包括矽、氮、氧、碳及氫的介電層,其中介電層具有第一介電常數值;以及對介電層執行退火,其中在退火之後,介電層具有一第二介電常數值,第二介電常數值低於第一介電常數值。
在一實施例中,在約400℃和約500℃的溫度範圍內執行退火。在一實施例中,使用原子層沉積形成介電層,以及原子層沉積包括交替地脈衝矽烷化甲基和氨。在一實施例中,在包括H2
O、O2
或氧自由基的含氧環境下執行退火。
在一實施例中,退火造成介電層的介電常數值從高於4.0的高介電常數值減少到小於3.9的低介電常數值。在一實施例中,退火造成在介電層中的氮原子百分比從第一值減少到第二值,其中第一值在約3%和約30%之間的範圍內,而第二值在約1%和約10%之間的範圍內。
根據本揭露的一些實施例,一種半導體裝置,包括:半導體區域;閘極堆疊,於半導體區域之上;閘極間隔物,在閘極堆疊的側壁上,其中閘極間隔物包括矽、氮、氧、碳及氫,閘極間隔物為低介電常數介電層;以及源極/汲極區域,於閘極間隔物的一側。
在一實施例中,閘極間隔物包括內側壁和外側壁,其中外側壁比內側壁更遠離閘極堆疊,以及在從內側壁到外側壁的方向上,氮原子百分比逐漸降低。在一實施例中,從內側壁到外側壁的閘極間隔物的整體具有約1%和約10%之間的氮原子百分比。在一實施例中,閘極間隔物更包括和閘極堆疊接觸的一高介電常數介電密封層。在一實施例中,高介電常數介電密封層具有比閘極間隔物的剩餘部分更高的氮原子百分比。
以上概述數個實施例之部件,以便在本發明所屬技術領域中具有通常知識者可以更加理解本發明實施例的觀點。在本發明所屬技術領域中具有通常知識者應理解,他們能輕易地以本發明實施例為基礎,設計或修改其他製程和結構,以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解,此類等效的結構並無悖離本發明的精神與範圍,且他們能在不違背本發明之精神和範圍下,做各式各樣的改變、取代和替換。因此,本發明之保護範圍當視後附之申請專利範圍所界定為準。
10:晶圓
20:基板
22:隔離區域/淺溝槽隔離(STI)區域
22A:頂表面
24:半導體條
24':(突出的)鰭片
30:(閒置)閘極堆疊
32:(閒置)閘極介電質(層)/介電層
34:閒置閘極電極
36:硬罩幕層/硬罩幕
37:閘極間隔物層/間隔物層/沉積層/介電層/膜層
38:閘極間隔物/介電層
38A:子層/密封層
38B:子層
38C:子層
38D:子層
38':內側壁/介電層
38'':外側壁
39:原子層
40:凹槽
41:磊晶區域
42:(包層)磊晶區域(源極/汲極區域)/磊晶半導體材料
46:接觸蝕刻停止層
48:層間介電質
49:溝槽
50:界面層
52:高介電常數介電層
54:閘極介電層
56:閘極電極
60:(取代)閘極堆疊
62:硬罩幕
63:矽化物區域
64:接觸插塞
66:蝕刻停止層
68:層間介電質
70:閘極接觸插塞
72:源極/汲極接觸插塞
74:鰭式場效電晶體
110:基層/含矽層
112、114、116、118、120:結構
130、132、134:製程
136:製程/第二原子層沉積循環
141:線
142:線
144:線
146:線
148:線
150:圓圈(-NH和-NH)
152:圓圈(O)
155:圓圈(O)
156:亞甲基橋(-CH2
)
157:圓圈(CH2
)
159:圓圈(CH3
)
200:製程流程
202、204、206、208、210:製程
212、214、216、218、220、222:製程
藉由以下的詳細描述配合所附圖式,可以更加理解本揭露實施例的內容。需強調的是,根據產業上的標準慣例,許多部件(feature)並未按照比例繪製。事實上,為了能清楚地討論,各種部件的尺寸可能被任意地放大或縮小。
第1圖、第2圖、第3A圖、第3B圖、第4A圖、第4B圖、第5圖、第6A圖、第6B圖、第7A圖、第7B圖、第8圖、第9A圖、第9B圖、第10圖到第11圖係根據一些實施例所繪示出鰭式場效電晶體(Fin Field-Effect Transistor,FinFET)形成的中間階段的剖面圖和透視圖。
第12圖係根據一些實施例所繪示出用於形成閘極間隔物的製程。
第13圖係根據一些實施例所繪示出矽烷化的甲基的化學式。
第14圖係根據一些實施例所繪示出在退火製程中的閘極間隔物的一部分的化學反應。
第15圖係根據一些實施例所繪示出在退火製程中的閘極間隔物的一部分的化學反應。
第16A圖係根據一些實施例所示意性地繪示出在退火之前的閘極間隔物的部分的氮原子百分比。
第16B圖係根據一些實施例所繪示出在退火之後的閘極間隔物的部分的氮原子百分比。
第17圖係根據一些實施例所繪示出用於形成鰭式場效電晶體(FinFET)的製程流程。
無
10:晶圓
20:基板
24':(突出的)鰭片
30:(閒置)閘極堆疊
32:(閒置)閘極介電質(層)/介電層
34:閒置閘極電極
36:硬罩幕層/硬罩幕
38:閘極間隔物/介電層
38A:子層/密封層
38B:子層
38C:子層
38D:子層
38':內側壁/介電層
38":外側壁
Claims (14)
- 一種形成半導體裝置的方法,包括:形成一閒置閘極堆疊於一晶圓的一半導體區域上;以及使用原子層沉積法沉積一閘極間隔物層於該閒置閘極堆疊的側壁,其中沉積該閘極間隔物層的步驟包括執行一原子層沉積循環以形成一介電原子層,其中該原子層沉積循環包括:引入矽烷化甲基(silylated methyl)到該晶圓;清除(purge)上述矽烷化甲基;引入氨到該晶圓;以及清除上述氨。
- 如申請專利範圍第1項所述之形成半導體裝置的方法,更包括在該閘極間隔物層形成之後,對該晶圓執行一退火,其中將該晶圓放置在一含氧氣體下執行該退火。
- 如申請專利範圍第2項所述之形成半導體裝置的方法,其中在約400℃和約500℃的溫度範圍內執行該退火。
- 如申請專利範圍第2項所述之形成半導體裝置的方法,其中在該退火之前,該閘極間隔物層具有一第一氮原子百分比,以及在該退火之後,該閘極間隔物層的一部分具有低於該第一氮原子百分比的一第二氮原子百分比。
- 如申請專利範圍第2項所述之形成半導體裝置的方法,其中在該退火之前,該閘極間隔物層具有一第一介電常數值,該第一介電常數值高於氧化矽的一介電常數值,以及在該退火之後,該閘極間隔物層的一部分具有一第二介電常數值,該第二介電常數值低於氧化矽的該介電常數值。
- 如申請專利範圍第1項至第5項中任一項所述之形成半導體裝置的方法,其中沉積該閘極間隔物層的步驟更包括在執行該原子層沉積循環之前,引入氨到該晶圓。
- 如申請專利範圍第1項至第5項中任一項所述之形成半導體裝置的方法,更包括沉積一高介電常數介電層作為一密封層(sealing layer),其中該高介電常數介電層包括將該閒置閘極堆疊與該閘極間隔物層分開的一部分。
- 一種形成半導體裝置的方法,包括:形成一閒置閘極堆疊於一晶圓的一半導體區域上;形成包括矽、氮、氧、碳及氫的一介電層,其中該介電層具有一第一介電常數值,其中該形成該介電層包括一原子層沉積循環,且該原子層沉積循環包括:引入矽烷化甲基到該晶圓;清除上述矽烷化甲基;引入氨到該晶圓;以及清除上述氨;以及對該介電層執行一退火,其中在該退火之後,該介電層具有一第二介電常數值,該第二介電常數值低於該第一介電常數值。
- 如申請專利範圍第8項所述之形成半導體裝置的方法,其中該退火造成該介電層的介電常數值從高於4.0的一高介電常數值減少到小於3.9的一低介電常數值。
- 如申請專利範圍第8項或第9項所述之形成半導體裝置的方法,其中該退火造成在該介電層中的氮原子百分比從一第一值減少到一第二值,其中該第一值在約3%和約30%之間的範圍內,而該第二值在約1%和約10%之間的範圍內。
- 一種半導體裝置,包括:一半導體區域; 一閘極堆疊,於該半導體區域之上;一閘極間隔物,在該閘極堆疊的側壁上,其中該閘極間隔物包括矽、氮、氧、碳及氫,該閘極間隔物為低介電常數介電層,其中該閘極間隔物包括一內側壁和一外側壁,其中該外側壁比該內側壁更遠離該閘極堆疊,以及在從該內側壁到該外側壁的方向上,氮原子百分比逐漸降低;以及一源極/汲極區域,於該閘極間隔物的一側。
- 如申請專利範圍第11項所述之半導體裝置,其中從該內側壁到該外側壁的該閘極間隔物的整體(entirety)具有約1%和約10%之間的氮原子百分比。
- 如申請專利範圍第11項或第12項所述之半導體裝置,其中該閘極間隔物更包括和該閘極堆疊接觸的一高介電常數介電密封層。
- 如申請專利範圍第13項所述之半導體裝置,其中該高介電常數介電密封層具有比該閘極間隔物的剩餘部分更高的氮原子百分比。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201862692088P | 2018-06-29 | 2018-06-29 | |
US62/692,088 | 2018-06-29 | ||
US16/057,308 | 2018-08-07 | ||
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US10692773B2 (en) * | 2018-06-29 | 2020-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming nitrogen-containing low-K gate spacer |
US10937892B2 (en) | 2018-09-11 | 2021-03-02 | International Business Machines Corporation | Nano multilayer carbon-rich low-k spacer |
CN111863963A (zh) * | 2019-04-24 | 2020-10-30 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
US11757020B2 (en) * | 2020-01-31 | 2023-09-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method |
US20210249310A1 (en) * | 2020-02-11 | 2021-08-12 | Nanya Technology Corporation | Semiconductor device with porous dielectric structure and method for fabricating the same |
US11217664B2 (en) * | 2020-02-11 | 2022-01-04 | Nanya Technology Corporation | Semiconductor device with porous dielectric structure |
US11217679B2 (en) * | 2020-04-01 | 2022-01-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
DE102020127567A1 (de) * | 2020-05-20 | 2021-11-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Halbleitervorrichtung und verfahren zu ihrer herstellung |
US11581259B2 (en) * | 2020-06-25 | 2023-02-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hybrid conductive structures |
US11522062B2 (en) * | 2020-08-14 | 2022-12-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing an etch stop layer and an inter-layer dielectric on a source/drain region |
US11380776B2 (en) * | 2020-09-29 | 2022-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Field-effect transistor device with gate spacer structure |
US20220238697A1 (en) * | 2021-01-28 | 2022-07-28 | Taiwan Semiconductor Manfacturing Co., Ltd. | Reducing K Values of Dielectric Films Through Anneal |
US11456182B1 (en) | 2021-04-22 | 2022-09-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit structure and fabrication thereof |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060131672A1 (en) * | 2004-12-20 | 2006-06-22 | Chih-Hao Wang | Nitrogen treatment to improve high-k gate dielectrics |
WO2017111774A1 (en) * | 2015-12-23 | 2017-06-29 | Intel Corporation | Transistor with inner-gate spacer |
US20180122643A1 (en) * | 2014-06-18 | 2018-05-03 | International Business Machines Corporation | Method and structure for enabling high aspect ratio sacrificial gates |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100558008B1 (ko) * | 2003-12-29 | 2006-03-06 | 삼성전자주식회사 | 반도체 소자의 배선 방법 |
KR101063591B1 (ko) * | 2004-10-27 | 2011-09-07 | 인터내셔널 비지네스 머신즈 코포레이션 | 금속간 유전체로서 사용된 낮은 k 및 극도로 낮은 k의 오가노실리케이트 필름의 소수성을 복원하는 방법 및 이로부터 제조된 물품 |
US9064948B2 (en) * | 2012-10-22 | 2015-06-23 | Globalfoundries Inc. | Methods of forming a semiconductor device with low-k spacers and the resulting device |
CN103943499B (zh) * | 2013-01-22 | 2016-08-31 | 中芯国际集成电路制造(上海)有限公司 | 鳍式场效应晶体管的形成方法 |
KR20160059861A (ko) | 2014-11-19 | 2016-05-27 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
US10269968B2 (en) * | 2015-06-03 | 2019-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including fin structures and manufacturing method thereof |
KR102396111B1 (ko) | 2015-06-18 | 2022-05-10 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
US9704759B2 (en) * | 2015-09-04 | 2017-07-11 | Globalfoundries Inc. | Methods of forming CMOS based integrated circuit products using disposable spacers |
KR102454894B1 (ko) * | 2015-11-06 | 2022-10-14 | 삼성전자주식회사 | 물질막, 이를 포함하는 반도체 소자, 및 이들의 제조 방법 |
US9806155B1 (en) | 2016-05-05 | 2017-10-31 | International Business Machines Corporation | Split fin field effect transistor enabling back bias on fin type field effect transistors |
US10269569B2 (en) * | 2016-11-29 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and methods of manufacture |
US10692773B2 (en) * | 2018-06-29 | 2020-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming nitrogen-containing low-K gate spacer |
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060131672A1 (en) * | 2004-12-20 | 2006-06-22 | Chih-Hao Wang | Nitrogen treatment to improve high-k gate dielectrics |
US20180122643A1 (en) * | 2014-06-18 | 2018-05-03 | International Business Machines Corporation | Method and structure for enabling high aspect ratio sacrificial gates |
WO2017111774A1 (en) * | 2015-12-23 | 2017-06-29 | Intel Corporation | Transistor with inner-gate spacer |
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