TWI752683B - Method for producing semiconductor wafers - Google Patents

Method for producing semiconductor wafers Download PDF

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TWI752683B
TWI752683B TW109136381A TW109136381A TWI752683B TW I752683 B TWI752683 B TW I752683B TW 109136381 A TW109136381 A TW 109136381A TW 109136381 A TW109136381 A TW 109136381A TW I752683 B TWI752683 B TW I752683B
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measurement
semiconductor wafer
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fabrication steps
semiconductor wafers
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TW202121524A (en
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安卓 路瑟
羅伯特 梅爾
佛雷德里奇 派賽克
卡信克 史瓦米娜生
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德商世創電子材料公司
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/418—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
    • G05B19/41875—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM] characterised by quality surveillance of production
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/30—Nc systems
    • G05B2219/32—Operator till task planning
    • G05B2219/32193—Ann, neural base quality management
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/30—Nc systems
    • G05B2219/32—Operator till task planning
    • G05B2219/32197—Inspection at different locations, stages of manufacturing
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
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    • G05B2219/30—Nc systems
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    • G05B2219/33218—Motor encoders, resolvers on common bus with drives, servo controllers
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/30—Nc systems
    • G05B2219/37—Measurements
    • G05B2219/37224—Inspect wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
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Abstract

A method for producing a semiconductor wafer, comprising: producing a single crystal, dividing up the single crystal into crystal pieces, a series of fabrication steps for fabricating semiconductor wafers, and a subsequent measurement in each case that provides position-related measurement results, with the number of distinguishable combinations of process step and measurement being greater than one, storing the position-related measurement results for the semiconductor wafer, and deciding whether the semiconductor wafer is intended for IC processing, wherein after the intended fabrication steps and measurements have been implemented, all of the measurement results are used for the deciding.

Description

製備半導體晶圓的方法Method for preparing semiconductor wafer

本發明涉及一種製備半導體晶圓的方法。The present invention relates to a method for preparing semiconductor wafers.

單晶半導體晶圓（或「切片」）是現代電子應用的基礎。在半導體晶圓上製備積體電路的期間，半導體晶圓經歷熱加工及高度複雜的塗佈加工。Single crystal semiconductor wafers (or "slices") are the foundation of modern electronics applications. During the fabrication of integrated circuits on semiconductor wafers, the semiconductor wafers undergo thermal processing and highly complex coating processes.

單晶半導體晶圓的製備本身非常複雜，且由多個高度發展的製造步驟組成。The preparation of single crystal semiconductor wafers is inherently complex and consists of multiple highly developed manufacturing steps.

半導體晶圓，特別是矽半導體晶圓，通常係首先藉由浮區法（FZ）或切克勞斯基法（CZ）提拉單晶棒來製備。因此，所製備的棒係藉由適合於該目的的鋸（諸如線鋸、內徑鋸或帶鋸）而被分成晶體片，然後通常在線鋸或內徑鋸中將這些片加工成半導體晶圓。Semiconductor wafers, especially silicon semiconductor wafers, are usually first prepared by pulling single crystal ingots by the float zone (FZ) or Czochralski (CZ) process. Thus, the prepared rods are divided into crystalline slices by saws suitable for the purpose, such as wire saws, ID saws or band saws, and these slices are then processed into semiconductor wafers, usually in wire saws or inside diameter saws. .

在進一步的機械、化學機械、及／或化學步驟之後，可視需要藉由CVD來施加磊晶層。After further mechanical, chemical-mechanical, and/or chemical steps, an epitaxial layer may be applied by CVD, if desired.

然後將這些由此製備的半導體晶圓用於建造積體電路（IC）。These thus prepared semiconductor wafers are then used to build integrated circuits (ICs).

適當的品質保證要求計量技術（metrology technique）的密集部署，該計量技術決定了所實施的製造步驟的成功與否。因此，通常在各自製造步驟之後使用不同的測量技術，以便監控製備過程，以及挑出被認為不可用的半導體晶圓。在此，通常僅使用單一測量方法的結果或一個測量參數來評估半導體晶圓。Proper quality assurance requires intensive deployment of metrology techniques that determine the success of the manufacturing steps performed. Therefore, different measurement techniques are usually used after the respective fabrication steps in order to monitor the fabrication process and to pick out semiconductor wafers that are considered unusable. Here, semiconductor wafers are generally only evaluated using the results of a single measurement method or one measurement parameter.

挑出半導體晶圓的理由是，如果僅在半導體晶圓在積體電路製造中進行加工時才檢測到半導體晶圓之不合適或有缺陷的本質，則會產生相當大的成本。另一方面，如果將材料錯誤地分類為不適合用於積體電路應用，則對半導體晶圓的製造商會不可避免地造成經濟損失。The semiconductor wafers are singled out because of the considerable cost involved if the unsuitable or defective nature of the semiconductor wafers is detected only while the semiconductor wafers are being processed in integrated circuit fabrication. On the other hand, if a material is incorrectly classified as unsuitable for integrated circuit applications, there will inevitably be financial losses to the manufacturers of semiconductor wafers.

由於這個原因，有價值的目標是，一方面僅對在積體電路製造期間缺陷風險最小的那些半導體晶圓進行積體電路加工，而另一方面使被錯誤丟棄的半導體晶圓的數量最小化。For this reason, it is a valuable goal to only perform IC processing on those semiconductor wafers with the least risk of defects during IC manufacturing on the one hand, and on the other hand to minimize the number of semiconductor wafers that are erroneously discarded .

半導體晶圓可能有各種缺陷。根據積體電路加工的不同，缺陷類型及其外觀（外觀的位置和形狀）都決定了就積體電路加工而言，該缺陷是被分類為有害的還是不重要的。Semiconductor wafers can have various defects. Depending on the IC processing, the defect type and its appearance (the location and shape of the appearance) determine whether the defect is classified as harmful or unimportant for IC processing.

例如，在半導體晶圓的內部（即，遠離表面）中可存在小孔（稱為針孔），而對於積體電路加工沒有任何可觀察到的後果。然而，如果針孔位於表面上或表面附近，則確實會在積體電路加工中產生不利的影響。For example, small holes (called pinholes) can exist in the interior of semiconductor wafers (ie, away from the surface) without any observable consequences for integrated circuit processing. However, pinholes do have a detrimental effect in integrated circuit processing if they are located on or near the surface.

因此，特別要求僅提供沒有嚴重缺陷的材料用於積體電路加工。一個清楚的要求是，必須盡可能明確地識別出缺陷，並基於這種分類對材料進行分類。Therefore, there is a special requirement to provide only materials free of serious defects for integrated circuit processing. A clear requirement is that defects must be identified as clearly as possible and materials are classified based on this classification.

實際上，每次測量都有誤差和不足之處。因此，缺陷的檢測或甚至識別可能是錯誤的或正確的。In fact, every measurement has errors and inadequacies. Therefore, the detection or even the identification of defects may be wrong or correct.

就此問題，US 2008/0032429 A1描述一種用於測量方法的技術，該測量方法在出現缺陷時會產生半導體晶圓上之缺陷區域的額外圖像，並使用該額外圖像來界定這個區域內的缺陷類型。缺陷一旦被系統識別出，則將藉由同一測量儀器上的另一測量資料再次進行測量，其中所作的決定因此被證實或者被證實為錯誤的。這需要增加分析工作量，因此增加了成本。In this regard, US 2008/0032429 A1 describes a technique for a measurement method that generates an additional image of a defective area on a semiconductor wafer when a defect occurs, and uses the additional image to define the area within this area. Defect type. Once the defect has been identified by the system, it is measured again by means of another measurement on the same measuring instrument, where the decision is thus confirmed or proved to be wrong. This requires increased analytical workload and therefore increased cost.

在US 2008/0163140 A1中，在識別出缺陷之後，儲存半導體晶圓上之缺陷的位置（即，座標），然後藉由第二測量方法對該缺陷進行檢測。此第二測量步驟之目的是明確地識別缺陷類型。在此，藉由使用進一步之測量方法也同樣會增加成本。In US 2008/0163140 A1, after a defect is identified, the position (ie, coordinates) of the defect on the semiconductor wafer is stored, and then the defect is detected by a second measurement method. The purpose of this second measurement step is to unambiguously identify the defect type. Here, too, costs are increased by using further measurement methods.

所描述之二種先前技術方法在發現缺陷時都能夠證實確為缺陷或不為缺陷。這被稱為缺陷複查。這二種技術都旨在於偵測到缺陷時，針對已經發現的缺陷使用額外實施的測量來明確地識別出缺陷。Both of the described prior art methods are able to prove to be a defect or not to be a defect when a defect is found. This is called a defect review. Both of these techniques aim to unambiguously identify defects when they are detected, using additional measurements performed against the defects that have already been discovered.

使用這種額外非常規的測量的原因是，目前在標準基礎上使用的測量技術僅能夠提供具有局限性的分類。The reason for this additional unconventional measurement is that the measurement techniques currently used on a standard basis are only able to provide a limited classification.

每種額外測量技術一方面都會產生成本，另一方面可能對半導體晶圓具有負面影響（例如，污染）。這些影響可能導致排除將如此分析的半導體晶圓用於積體電路加工。因此，這些技術不能應用於半導體晶圓的大規模製備中。Each additional measurement technique incurs costs on the one hand and may have negative effects on the semiconductor wafer (eg contamination) on the other. These effects may lead to the exclusion of semiconductor wafers thus analyzed for integrated circuit processing. Therefore, these techniques cannot be applied to large-scale fabrication of semiconductor wafers.

本發明目的在於改善在大規模製造中半導體晶圓上之缺陷的識別／分類，以及不僅增加產量，而且確保所供應之材料的品質，而不因引入額外的測量而產生額外的成本。The present invention aims to improve the identification/classification of defects on semiconductor wafers in large-scale manufacturing, and not only increase throughput, but also ensure the quality of the supplied material without incurring additional costs by introducing additional measurements.

本發明的目的係透過申請專利範圍中描述的方法來實現。術語定義 The objects of the present invention are achieved by the method described in the scope of the patent application. Definition of Terms

MWS（多線鋸）是指藉由鋸線從晶體片同時切割多個半導體晶圓。這種方法的一般性描述在WO18149631 A1中給出。MWS (Multi-Wire Saw) refers to the simultaneous cutting of multiple semiconductor wafers from a wafer by sawing wires. A general description of this method is given in WO18149631 A1.

ENG（邊緣缺口研磨）是指在DE102013212850 A1中一般性重現的邊緣圓整方法。ENG (Edge Notch Grinding) refers to the edge rounding method generally reproduced in DE102013212850 A1.

FAP（固定磨料拋光）是指使用黏結磨料進行拋光。這種方法在US8500516 B2中進行一般性描述。FAP (Fixed Abrasive Polishing) refers to polishing with bonded abrasives. This method is generally described in US8500516 B2.

CMP（化學機械拋光）是指拋光，其中使用未黏結磨料和合適的化學試劑，在半導體晶圓的一側進行燒蝕拋光。在例如DE 10 2008 045 534 B4中描述進一步的細節。CMP (Chemical Mechanical Polishing) refers to polishing in which an ablative polishing is performed on one side of a semiconductor wafer using unbonded abrasives and suitable chemicals. Further details are described, for example, in DE 10 2008 045 534 B4.

雙面拋光（DSP）是化學機械加工步驟（CMP）之群組中的一種方法。在例如US 2003/054650 A1中描述對半導體晶圓的DSP加工，以及在DE 100 07 390 A1中描述適用於這種目的之設備。DSP包括使用鹼的化學蝕刻，以及使用未黏結磨料的機械腐蝕，其中該未黏結磨料分散在水性介質中且藉由拋光布與半導體晶圓接觸，該拋光布不包含與半導體晶圓接觸的硬質物質；藉由這種方式，材料在壓力和交互運動下從半導體晶圓燒蝕。Double-sided polishing (DSP) is a method in the group of chemical mechanical processing steps (CMP). The DSP processing of semiconductor wafers is described, for example, in US 2003/054650 A1, and a device suitable for this purpose is described in DE 100 07 390 A1. DSP includes chemical etching using an alkali, and mechanical etching using an unbonded abrasive dispersed in an aqueous medium and in contact with the semiconductor wafer by a polishing cloth that does not contain hard materials in contact with the semiconductor wafer Matter; in this way, material is ablated from the semiconductor wafer under pressure and interactive motion.

CVD代表化學氣相沉積，並且在WO19020387 A1中進行一般性描述。CVD stands for Chemical Vapour Deposition and is generally described in WO19020387 A1.

DDG（雙面研磨）是一種用於在載體（例如，研磨盤）中使用黏結磨料進行機械燒蝕的技術。這種方法在DE102017215705 A1中進行說明性描述。DDG (Double-Sided Grinding) is a technique for mechanical ablation using bonded abrasives in a carrier such as a grinding disc. This method is illustratively described in DE102017215705 A1.

蝕刻是指以化學方式或鹼誘導的半導體燒蝕。這種方法在US7829467 B2中進行說明性描述。Etching refers to chemically or alkali-induced ablation of semiconductors. This method is illustratively described in US7829467 B2.

邊緣圓整是指對半導體晶圓邊緣進行的機械圓整。Edge rounding refers to the mechanical rounding of the edge of a semiconductor wafer.

邊緣拋光是指對半導體晶圓邊緣進行的拋光。Edge polishing refers to polishing the edges of semiconductor wafers.

電阻測量是指對單晶矽的電阻的測量。出於這個目的，較佳的是稱為四點測量的測量技術，但是也可以使用其他技術。Resistance measurement refers to the measurement of the resistance of single crystal silicon. For this purpose, a measurement technique known as four-point measurement is preferred, but other techniques may also be used.

光散射被理解為是指如下測量技術：例如MO6、MO4、LLS、IR-LST（局部光散射）。利用這種技術，用光束掃描待分析物體（即，矽晶圓），然後使用檢測器記錄反射的光及／或散射在表面不規則物處或體積內的光。在散射光的情況下，所使用的術語是暗場檢查；對反射光的檢測被稱為光場測量。（另請參見SEMI標準M52）。Light scattering is understood to mean the following measurement techniques: eg MO6, MO4, LLS, IR-LST (local light scattering). With this technique, the object to be analyzed (ie, a silicon wafer) is scanned with a beam of light, and a detector is used to record the reflected light and/or light scattered at surface irregularities or within the volume. In the case of scattered light, the term used is dark field inspection; the detection of reflected light is called light field measurement. (See also SEMI Standard M52).

使用紅外去極化（SIRD），半導體晶圓係使用紅外光束掃描。在這種掃描中，以空間解析度記錄反射或透射的雷射的極化不均勻性，以便測定材料中可能的局部應力。Using infrared depolarization (SIRD), semiconductor wafers are scanned using an infrared beam. In this scan, the polarization inhomogeneity of the reflected or transmitted laser is recorded with spatial resolution in order to determine possible localized stresses in the material.

在超聲波測量的情況下，用超聲波透射（trans-irradiate）樣品。在聲波撞擊不規則物的位置處，發生反射且檢測到該反射。在此再次掃描樣品。連同測量波的傳播時間，能夠精確地確定不規則物的局部位置。In the case of ultrasonic measurement, the sample is trans-irradiated with ultrasonic waves. At the location where the sound wave strikes the irregularity, a reflection occurs and is detected. Scan the sample again here. Together with measuring the travel time of the wave, the local location of the irregularity can be determined precisely.

少數電荷載子的壽命測量：根據對晶體缺陷和雜質上的脈衝回應，確定所生成之自由電荷載子進入在費米能級以下之狀態的再結合壽命。（參考：SEMI標準MF1535）。Minority Charge Carrier Lifetime Measurement: Determines the recombination lifetime of the generated free charge carriers into states below the Fermi level based on the response to pulses on crystal defects and impurities. (Reference: SEMI Standard MF1535).

少數電荷載子的自由路徑長度的測量：這是根據壽命和自由擴散常數（物理常數，參考：SEMI標準MF391）計算。Measurement of free path length of minority charge carriers: This is calculated from lifetime and free diffusion constant (physical constants, reference: SEMI standard MF391).

局部幾何形狀的測量：對於這種技術，樣品的平坦度及／或厚度的局部變化是藉由電容測量、干涉測量或三角測量確定。(另請參見SEMI標準M49)。Measurement of local geometry: For this technique, local variations in the flatness and/or thickness of the sample are determined by capacitance measurements, interferometry or triangulation. (See also SEMI Standard M49).

顯微術（電子顯微術、可見光波長範圍內的光學顯微術）：使用顯微鏡在對應的製造步驟之後常規性地監測矽片的特定區域。這些區域尤其包括邊緣區域、缺口區域、雷射標記區域、以及與晶圓處理及放置系統的接觸點。Microscopy (electron microscopy, optical microscopy in the visible wavelength range): The use of a microscope to routinely monitor specific areas of a silicon wafer after the corresponding fabrication step. These areas include, inter alia, edge areas, notch areas, laser marking areas, and points of contact with wafer handling and placement systems.

質譜法和X-射線螢光係常規地用於識別（在一些情況下以局部解析度識別）矽中的外來原子並確定此類原子的濃度。Mass spectrometry and X-ray fluorescence are routinely used to identify (in some cases at local resolution) foreign atoms in silicon and to determine the concentration of such atoms.

FTIR可用於確定層（例如，磊晶層或氧化物層）的厚度，且還經由光譜分析來確定諸如O、C、H、及N等外來原子的濃度。FTIR can be used to determine the thickness of layers (eg, epitaxial or oxide layers), and also to determine the concentration of foreign atoms such as O, C, H, and N via spectroscopic analysis.

LLS（局部光散射）藉由光散射識別在晶圓表面上辨認出的光散射點。LLS (Local Light Scattering) identifies identified light scattering points on the wafer surface by light scattering.

本發明的詳細說明及實施例Detailed Description and Examples of the Invention

在製備半導體晶圓的各個製造步驟之後，使用最適用於相關製造步驟的測量方法執行測量，並將其結果儲存在資料庫中。在此，測量結果被認為是關於如下的資訊：可能的異常或缺陷的本質、這種異常或缺陷的局部座標、所使用的測量技術（包括表現形式）、以及製造步驟的資訊。After each manufacturing step of preparing a semiconductor wafer, measurements are performed using the measurement method most suitable for the relevant manufacturing step, and the results are stored in a database. Here, measurement results are considered to be information about the nature of possible anomalies or defects, the local coordinates of such anomalies or defects, the measurement techniques used (including representations), and the manufacturing steps.

本發明人已經認識到，在實施的所有製造步驟及其分配的測量之後的測量結果之組合資訊導致實質上改善了相關特徵的表徵及識別。The inventors have realized that the combined information of the measurement results after all the manufacturing steps performed and their assigned measurements lead to substantially improved characterization and identification of relevant features.

相較於在相應的製造步驟之後對各個測量結果的資料進行評估，這種技術被證明是非常有利的。在不同的製造步驟之後組合測量資料使得可更精確地界定缺陷的來源及因此之缺陷的本質，以及缺陷在半導體晶圓表面上或半導體晶圓塊體中的精確位置。因此，缺陷識別的品質、以及相關連之對半導體晶圓評估其在積體電路加工中的適用性可被最佳化。This technique proves to be very advantageous compared to evaluating the profiles of the individual measurement results after the corresponding manufacturing steps. Combining the measurement data after the different manufacturing steps makes it possible to more precisely define the source of the defect and thus the nature of the defect, as well as the precise location of the defect on the surface of the semiconductor wafer or in the bulk of the semiconductor wafer. Thus, the quality of defect identification and associated evaluation of semiconductor wafers for their suitability in integrated circuit processing can be optimized.

因此，非必要地去除的半導體晶圓的數量可被減少，以及以他法會被缺陷性地批准用於積體電路加工的半導體晶圓的數量可被減少。Accordingly, the number of semiconductor wafers that are unnecessarily removed can be reduced, and the number of semiconductor wafers that would otherwise be defectively approved for integrated circuit processing can be reduced.

由隨後的測量步驟監測的製造步驟較佳是來自以下製造步驟的清單中者：MWS、ENG、FAP、CMP、DSP、CVD、DDG、蝕刻、邊緣圓整、邊緣拋光、磊晶。The fabrication steps monitored by subsequent measurement steps are preferably from the list of fabrication steps: MWS, ENG, FAP, CMP, DSP, CVD, DDG, etching, edge rounding, edge polishing, epitaxy.

在此情況下儲存的資料非常較佳地是來自以下參數的測量資料（包含位置資訊）：幾何形狀、奈米形貌（nanotopography）、LLS、局部粗糙度變化、在整個表面（邊緣、正面和背面）上以相機記錄的暗場和明場信號、來自材料的局部超聲波反射及透射、矽晶圓的體積內及／或表面上的紅外光散射中心、極化紅外光的局部去極化。The data stored in this case is very preferably measurement data (including positional information) from the following parameters: geometry, nanotopography, LLS, local roughness variation, over the entire surface (edge, front and Darkfield and brightfield signals recorded with cameras on the back), local ultrasonic reflections and transmissions from materials, infrared light scattering centers within the volume of the silicon wafer and/or on the surface, local depolarization of polarized infrared light.

如此收集的資料係組合使用以針對半導體晶圓之未來用途來評估半導體晶圓。這可藉由使用合適的資料處理系統來實現。在此情況下，自學習系統（人工智慧、圖形識別系統）是特別合適的。人工神經網路特別適合。清楚地，取決於缺陷類型，所採用的不同測量技術不同程度地促成改進的缺陷識別。實施例：對針孔型缺陷的技術應用 The data so collected is used in combination to evaluate the semiconductor wafers for their future use. This can be achieved by using a suitable data processing system. In this case, self-learning systems (artificial intelligence, pattern recognition systems) are particularly suitable. Artificial neural networks are particularly suitable. Clearly, depending on the defect type, the different measurement techniques employed contribute to improved defect identification to varying degrees. Example: Technical Application to Pinhole Defects

在製備多個標稱直徑為300毫米的單晶後，將單晶切割成長為10公分至30公分的晶體片，然後使用超聲波測量分析所述晶體片，並儲存結果（晶體中可能的不規則物的座標）。After preparing a number of single crystals with a nominal diameter of 300 mm, the single crystals are cut into pieces of 10 cm to 30 cm, which are then analyzed using ultrasonic measurements and the results are stored (possible irregularities in the crystals) coordinates of the object).

隨後，與已經獲得的結果無關地，藉由MWS將晶體片切片成半導體晶圓。然後，對由此獲得的半導體晶圓執行IR測量，然後儲存這些測量的結果，包括關於所偵測之特徵的位置／座標資訊。Subsequently, independent of the results already obtained, the wafers are sliced into semiconductor wafers by MWS. IR measurements are then performed on the semiconductor wafer thus obtained, and the results of these measurements are then stored, including position/coordinate information about the detected features.

在IR測量表現異常的位置處，如先前技術所提出地，以更高解析度進行進一步的IR測量來執行缺陷複查作為第二次測量，以作為對照。如先前技術所提出地，使用這些資料來獲得對異常的評估。然而，與現有技術相反，表現出可能有害的缺陷的半導體晶圓不會被丟棄，而是進行後續製造步驟。在後續步驟中也採用了相同的原理。如此獲得的額外資料最後被用作本發明技術的驗證的資料基礎。Where the IR measurement behaves abnormally, a further IR measurement at a higher resolution is performed to perform a defect review as a second measurement, as proposed in the prior art, as a control. As suggested in the prior art, these data are used to obtain an assessment of the anomaly. However, contrary to the prior art, semiconductor wafers exhibiting potentially detrimental defects are not discarded, but undergo subsequent manufacturing steps. The same principle is also used in subsequent steps. The additional data thus obtained was finally used as the data basis for the validation of the present technique.

在雙面拋光（DSP）後，對獲得的半導體晶圓進行IR測量，然後以包括位置資訊地儲存資料。After double-sided polishing (DSP), IR measurements are performed on the obtained semiconductor wafers, and the data is then stored including positional information.

在藉由CMP進一步處理半導體晶圓之後，對半導體晶圓進行SIRD測量並以空間解析度儲存測量的資料。此外，在CMP後，對半導體晶圓的正面和背面進行光散射測量，以包括位置資訊地儲存測量的資料。After further processing of the semiconductor wafer by CMP, SIRD measurements are performed on the semiconductor wafer and the measured data is stored with spatial resolution. In addition, after CMP, light scattering measurements are performed on the front and back sides of the semiconductor wafer to store the measured data including position information.

藉由CVD處理對一些所得的半導體晶圓進行後續加工，然後藉由對正面和背面的光散射測量來分析所述半導體晶圓，再次以包括位置資訊地儲存所有資料。Some of the resulting semiconductor wafers are subsequently processed by CVD processing and then analyzed by light scattering measurements on the front and back sides, again storing all data including positional information.

表1示出所使用的製造步驟以及與這些步驟相關而實施的測量的概述。Table 1 shows an overview of the manufacturing steps used and the measurements performed in relation to these steps.

最後，全面分析所有測量結果。本發明人在此認識到以下是有利的：首先執行晶圓製造所需的所有步驟並記錄測量結果，且在最後結合所有不同的測量結果以用於解釋。Finally, a comprehensive analysis of all measurement results. The inventors herein have realized that it is advantageous to first perform all steps required for wafer fabrication and record the measurements, and finally combine all the different measurements for interpretation.

在此被確認為有利的是，在隨後用於半導體積體電路的情況下，在各個製造步驟之後組合來自不同測量技術的不同測量資料提供了關於所發現之異常／缺陷的有害影響的更精確的資訊。在此不再需要如先前技術所提出之對可能有害的缺陷的額外非常規的測量。It has been found to be advantageous here that, in the case of subsequent use in semiconductor integrated circuits, combining different measurement data from different measurement techniques after the individual manufacturing steps provides more precise information on the detrimental effects of detected anomalies/defects information. Additional unconventional measurements of potentially detrimental defects as proposed in the prior art are no longer required here.

本發明人進一步認識到，在不同的製造步驟之後組合測量結果提供了進一步的有利效果：首先，可將表面上對於積體電路加工而言至關重要的針孔與非至關重要的亞表面針孔明確地分開。其次，針對針孔明確分類的紅外測量的檢測極限（目前約為20微米）可被提高到遠低於10微米。 製造步驟 製造步驟後的測量 對照測量 （第二次測量） 拉晶法 超聲波測量：晶體中不規則物的檢測 以更高解析度進行第二次局部超聲波測量 多線鋸 紅外測量 矽晶圓上／矽晶圓中不規則物的檢測 以更高解析度進行另外的局部紅外測量 雙面拋光 紅外測量 矽晶圓上／矽晶圓中不規則物的檢測和局部分類 以更高解析度進行另外的局部紅外測量 化學機械拋光 紅外去極化測量 以更高解析度進行另外的局部紅外去極化測量 化學氣相沉積 紅外去極化測量 矽晶圓上／矽晶圓中可能的應力場的檢測 以更高解析度進行另外的局部紅外去極化測量 化學機械拋光 正面和背面及邊緣的光散射測量 矽晶圓上／矽晶圓中不規則物的檢測和局部分類 以更高解析度進行另外的局部光散射測量 化學氣相沉積 正面和背面及邊緣的光散射測量 矽晶圓上／矽晶圓中不規則物的檢測和局部分類 以更高解析度進行另外的局部光散射測量 表1：實施例所進行的製造步驟和後續測量技術。當實施本發明方法時，不需要另外的對照測量。The inventors have further recognized that combining the measurement results after different manufacturing steps provides further advantageous effects: First, pinholes on surfaces that are critical to IC processing can be compared with subsurfaces that are not critical to IC processing The pinholes are clearly separated. Second, the detection limit of infrared measurements for a well-defined classification of pinholes (currently around 20 microns) can be improved to well below 10 microns. manufacturing steps Measurements after manufacturing steps Control measurement (second measurement) crystal pulling Ultrasonic Measurement: Detection of Irregularities in Crystals Second local ultrasonic measurement at higher resolution Multi-wire saw Infrared Measurements Detection of Irregularities on/in Silicon Wafers Additional local infrared measurements at higher resolution Double-sided polishing Infrared measurement detection and local classification of irregularities on/in silicon wafers Additional local infrared measurements at higher resolution chemical mechanical polishing Infrared depolarization measurement Additional local infrared depolarization measurements at higher resolution chemical vapor deposition Infrared Depolarization Measurements Detection of Possible Stress Fields on/In Silicon Wafers Additional local infrared depolarization measurements at higher resolution chemical mechanical polishing Front and back and edge light scattering measurements Detection and local classification of irregularities on/in silicon wafers Additional local light scattering measurements at higher resolution chemical vapor deposition Front and back and edge light scattering measurements Detection and local classification of irregularities on/in silicon wafers Additional local light scattering measurements at higher resolution Table 1 : Manufacturing steps and subsequent measurement techniques performed for the examples. When carrying out the methods of the present invention, no additional control measurements are required.

以上說明性實施態樣的描述應被理解為實施例。對應的揭露內容一方面使得技術人員能夠理解本發明以及與其相關聯的優點，另一方面，在本領域技術人員的理解範圍內，還包括對所描述的結構和方法的明顯修改和變更。因此，所有這種修改和變更以及等效物都旨在被申請專利範圍的保護範圍所涵蓋。The foregoing descriptions of illustrative embodiments should be understood as examples. The corresponding disclosure, on the one hand, enables the skilled person to understand the invention and the advantages associated therewith, and on the other hand, also includes obvious modifications and changes to the described structures and methods within the understanding of those skilled in the art. Accordingly, all such modifications and variations, and equivalents, are intended to be covered by the scope of the claims.

A:傳遞 AI:軟體 B:丟棄 C:缺陷／異常 CR:演算法／決定 DB:資料庫 F:製造步驟 M:測量步驟／測量方法 Mc :測量方法A: Pass AI: Software B: Discard C: Defect/Anomaly CR: Algorithm/Decision DB: Database F: Manufacturing Step M: Measurement Step/Measurement Method M c : Measurement Method

圖1示出先前技術的方法順序。每種情況中，在第i個製造步驟F之後是測量步驟M，所述測量步驟M分析半導體晶圓之可能的缺陷。然後使用第二種改進的測量方法Mc 來分析可能的缺陷／異常C （C1 、C2 、…Cn ）的位置。在這種分析結束時，簡單演算法CR決定是否將半導體晶圓丟棄B或者將其傳遞到下一個製造步驟F（i+1、i+2等）。假設測量級聯M和Mc 產生可靠的結果，在此使用的演算法CR僅針對與相應製造步驟相關的半導體晶圓上已知的關鍵缺陷的存在進行分析。Figure 1 shows the method sequence of the prior art. In each case, the ith manufacturing step F is followed by a measurement step M, which analyzes the semiconductor wafer for possible defects. Then using the second measuring method improved to analyze the possible M c defect / anomaly C (C 1, C 2, ... C n) position. At the end of this analysis, the simple algorithm CR decides whether to discard the semiconductor wafer B or pass it on to the next fabrication step F (i+1, i+2, etc.). Suppose M and M C measured cascade produce reliable results, the algorithms used herein CR analyzed for the presence of only known on a semiconductor wafer fabrication steps associated with a respective critical defects.

在最後的製造步驟（圖1中標題為「i+2」）之後可將被認為良好的半導體晶圓傳遞A給積體電路加工。After the final fabrication step (titled "i+2" in Figure 1), the semiconductor wafer that is considered good may be transferred to A for integrated circuit processing.

圖2示出本發明的方法順序。在第i個製造步驟F之後是測量步驟M，所述測量步驟M分析半導體晶圓可能的缺陷和異常。在這種情況下，將可能的缺陷和異常C（C1 、C2 、...Cn ）的位置座標與測量方法M和製造步驟F一起儲存在資料庫DB中。沒有決定是否將半導體晶圓引入至下一個（i+1、i+2等）製造步驟，因此所有晶圓都經過所有必要的製造步驟。Figure 2 shows the method sequence of the present invention. The ith manufacturing step F is followed by a measurement step M, which analyzes the semiconductor wafer for possible defects and anomalies. In this case, the position coordinates of the possible defects and abnormalities C (C 1 , C 2 , . . . C n ) are stored in the database DB together with the measurement method M and the manufacturing step F. There is no decision on whether to bring the semiconductor wafers to the next (i+1, i+2, etc.) fabrication step, so all wafers go through all necessary fabrication steps.

在半導體晶圓經過所有製造和測量步驟之後，使用軟體（AI）分析來自資料庫DB之相應半導體晶圓的資料，並據此決定（CR）是否將半導體晶圓丟棄（B）或者將其傳遞（A）給積體電路加工 。After a semiconductor wafer has gone through all fabrication and measurement steps, software (AI) is used to analyze the data of the corresponding semiconductor wafer from the database DB, and based on this, it is decided (CR) whether the semiconductor wafer should be discarded (B) or passed on (A) Processing of integrated circuits.

A:傳遞A: Pass

AI:軟體AI: software

B:丟棄B: discard

C:缺陷/異常C: Defect/Exception

CR:演算法/決定CR: Algorithm/Decision

DB:資料庫DB:Database

F:製造步驟F: Manufacturing steps

M:測量步驟/測量方法M: Measurement procedure/measurement method

Claims (6)

一種製備半導體晶圓的方法，其包括：製備單晶，分割該單晶成晶體片，及對該晶體片進行超聲波分析，且以包含空間資訊地儲存所獲得的資料，用於製造半導體晶圓的一系列製造步驟，以及在每種情況下提供與位置相關之測量結果的後續測量，其中製造步驟和測量的可區分組合數量大於一，儲存該半導體晶圓與位置相關之測量結果，以及決定該半導體晶圓是否用於積體電路加工，其中在實施該製造步驟和測量後，將所有測量結果用於該決定。 A method for preparing a semiconductor wafer, comprising: preparing a single crystal, dividing the single crystal into a crystal piece, and performing ultrasonic analysis on the crystal piece, and storing the obtained data with spatial information for manufacturing a semiconductor wafer a series of fabrication steps, and in each case subsequent measurements that provide position-dependent measurements, where the number of distinguishable combinations of fabrication steps and measurements is greater than one, store the position-dependent measurements of the semiconductor wafer, and determine Whether the semiconductor wafer is to be used for integrated circuit processing, where after the fabrication steps and measurements are performed, all measurements are used for this determination. 如請求項1所述的製備半導體晶圓的方法，其中該一系列製造步驟包含選自以下製造步驟清單中的選項：MWS、ENG、FAP、CMP、DSP、CVD、DDG、蝕刻、邊緣圓整、邊緣拋光，以及其中該測量包含選自以下清單中的選項：電阻測量、光散射、超聲波測量、SIRD、壽命、自由路徑長度、局部幾何形狀、顯微術、質譜法、紅外光譜法。 The method of making a semiconductor wafer of claim 1, wherein the series of fabrication steps comprises options selected from the following list of fabrication steps: MWS, ENG, FAP, CMP, DSP, CVD, DDG, etching, edge rounding , edge polishing, and wherein the measurement includes options selected from the list of: Resistance Measurement, Light Scattering, Ultrasonic Measurement, SIRD, Lifetime, Free Path Length, Local Geometry, Microscopy, Mass Spectrometry, Infrared Spectroscopy. 如請求項1或2所述的方法，其中使用該測量結果評估該半導體晶圓上的各局部區域。 The method of claim 1 or 2, wherein the measurement results are used to evaluate local areas on the semiconductor wafer. 如請求項1或2所述的方法，其中使用該測量結果評估各缺陷類型。 A method as claimed in claim 1 or 2, wherein the measurement results are used to evaluate each defect type. 如請求項1或2所述的方法，其中使用該測量結果評估各缺陷。 A method as claimed in claim 1 or 2, wherein each defect is evaluated using the measurement. 如請求項1或2所述的方法，其中使用人工智慧自動評估該測量結果。 A method as claimed in claim 1 or 2, wherein the measurement is automatically evaluated using artificial intelligence.
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Citations (2)

* Cited by examiner, † Cited by third party
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US20190302734A1 (en) * 2018-03-28 2019-10-03 Kla-Tencor Corporation Auto-Correlation of Wafer Characterization Data and Generation of Composite Wafer Metrics During Semiconductor Device Fabrication

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10007390B4 (en) 1999-03-13 2008-11-13 Peter Wolters Gmbh Two-disc polishing machine, in particular for processing semiconductor wafers
DE10132504C1 (en) 2001-07-05 2002-10-10 Wacker Siltronic Halbleitermat Method for simultaneously polishing both sides of semiconductor wafer mounted on cogwheel between central cogwheel and annulus uses upper and lower polishing wheel
US7747062B2 (en) 2005-11-09 2010-06-29 Kla-Tencor Technologies Corp. Methods, defect review tools, and systems for locating a defect in a defect review process
DE102006020823B4 (en) 2006-05-04 2008-04-03 Siltronic Ag Process for producing a polished semiconductor wafer
US7904845B2 (en) 2006-12-06 2011-03-08 Kla-Tencor Corp. Determining locations on a wafer to be reviewed during defect review
DE102008045534B4 (en) 2008-09-03 2011-12-01 Siltronic Ag Method for polishing a semiconductor wafer
DE102009052744B4 (en) 2009-11-11 2013-08-29 Siltronic Ag Process for polishing a semiconductor wafer
US8627251B2 (en) * 2012-04-25 2014-01-07 Taiwan Semiconductor Manufacturing Co., Ltd. Systems and methods of automatically detecting failure patterns for semiconductor wafer fabrication processes
DE102013212850A1 (en) 2013-07-02 2013-09-12 Siltronic Ag Method for polishing surface of edge of disk of semiconductor material e.g. silicon wafer, involves conveying polishing agent to surface of edge of semiconductor wafer disk through auxiliary borehole over suction opening at front side
US20180108579A1 (en) * 2015-06-18 2018-04-19 Aurora Solar Technologies (Canada) Inc. Solar cell emitter characterization using non-contact dopant concentration and minority carrier lifetime measurement
DE102017202314A1 (en) 2017-02-14 2018-08-16 Siltronic Ag Wire saw, wire guide roller, and method of simultaneously separating a plurality of disks from a rod
DE102017212799A1 (en) 2017-07-26 2019-01-31 Siltronic Ag Epitaxially coated semiconductor wafer of monocrystalline silicon and process for its preparation
DE102017215705A1 (en) 2017-09-06 2019-03-07 Siltronic Ag Apparatus and method for double-sided grinding of semiconductor wafers

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018192689A1 (en) * 2017-04-20 2018-10-25 Siltectra Gmbh Method for producing wafers with modification lines of defined orientation
US20190302734A1 (en) * 2018-03-28 2019-10-03 Kla-Tencor Corporation Auto-Correlation of Wafer Characterization Data and Generation of Composite Wafer Metrics During Semiconductor Device Fabrication

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