TWI751352B

TWI751352B - Substrate for an integrated radiofrequency device and method for manufacturing same

Info

Publication number: TWI751352B
Application number: TW107123383A
Authority: TW
Inventors: 克里斯朵維堤蘇; 派翠克雷納德; 奧列格科諾強克; 弗雷德里克奧利伯
Original assignee: 法商索泰克公司
Priority date: 2018-07-05
Filing date: 2018-07-05
Publication date: 2022-01-01
Also published as: TW202006896A

Abstract

The invention relates to a substrate (1) for applications in the fields of radiofrequency electronics and microelectronics comprising a base substrate (3); a single carbon layer (2) positioned on and directly in contact with the base substrate (3), with the carbon layer (2) having a thickness strictly ranging from 1nm to 5nm; an insulator layer (4) positioned on the carbon layer (2); a layer of devices (5) positioned on the insulator layer (4). The invention also relates to a method for manufacturing such substrate.

Description

集成射頻元件用底材及其製作方法Substrate for integrated radio frequency components and manufacturing method thereof

本發明係關於一種集成射頻元件（integrated radiofrequency device）用底材。本發明也涉及製作此類底材之方法。The present invention relates to a substrate for integrated radiofrequency devices. The present invention also relates to methods of making such substrates.

集成元件通常形成於底材上，該底材的主要作用為生產過程之支撐。隨著集成元件的集成程度與預期效能提升，導致集成元件之效能和在其上成形之底材特徵之耦合越來越緊密。這類情況尤其常見於處理訊號頻率在約3kHz至300GHz之間的RF設備中，該頻率尤其常用於電信領域（行動電話，Wi-Fi，藍牙等）。The integrated components are usually formed on a substrate, the primary function of which is to support the production process. As the degree of integration and expected performance of integrated devices increases, the performance of the integrated devices and the substrate features formed thereon are increasingly coupled. This type of situation is especially common in RF devices that process signal frequencies between about 3kHz and 300GHz, which are especially common in the telecommunications sector (mobile phones, Wi-Fi, Bluetooth, etc.).

以元件／底材之耦合為例，在元件中傳播的高頻率訊號所產生的電磁場會穿透至底材深處，並與存在該處的任何電荷載子進行交互作用。這會導致至少一部分之訊號功率因耦合損耗而造成非必要之消耗，也可能因串擾（crosstalk）而對組件之間造成影響。Taking the element/substrate coupling as an example, the electromagnetic field generated by the high frequency signal propagating in the element penetrates deep into the substrate and interacts with any charge carriers present there. This will cause unnecessary consumption of at least a portion of the signal power due to coupling loss, and may also affect components due to crosstalk.

根據第二耦合示例，底材之電荷載子可能產生不需要的諧波，該諧波可能會干擾在集成元件中傳播的訊號並降低其品質。According to a second coupling example, the charge carriers of the substrate may generate unwanted harmonics that may interfere with and degrade the quality of the signal propagating in the integrated device.

當使用之絕緣體上矽（silicon-on-isolator）類型之底材包括埋置絕緣體層時，尤其能夠觀察到此現象，該埋置絕緣體層位於支撐件及元件層之間，且集成元件形成於該元件層之上與之中。受困於絕緣體中的電荷，導致具有異極之電荷在支撐件中之絕緣體層下方累積，進而在該處形成導電平面。在該導電平面中，移動電荷可能與有用層之組件所產生的電磁場發生強烈交互作用。因此在位於埋置絕緣體層正下方之平面中，可觀察到支撐件之電阻率大幅降低，就算支撐件具有高電阻率特徵時也依然如此。This phenomenon is especially observed when a silicon-on-isolator type substrate is used that includes a buried insulator layer between the support and the device layer and the integrated device is formed in Above and in the element layer. The charge trapped in the insulator causes charges with opposite poles to accumulate under the insulator layer in the support, thereby forming a conductive plane there. In this conductive plane, mobile charges may strongly interact with the electromagnetic fields generated by the components of the useful layer. Thus, in the plane directly below the buried insulator layer, a substantial reduction in the resistivity of the support can be observed, even when the support has high resistivity features.

為了避免或限制該現象，已知可在埋置絕緣體與位於該絕緣體正下方之支撐件之間***電荷捕捉層，例如1微米至5微米之一多晶矽層。形成多晶之晶粒接合處會成為電荷載子之捕捉器，因該些電荷載子可能來自捕捉層本身，或來自其下之支撐件。因此，可避免絕緣體下方出現導電平面，以及避免支撐件之電阻率下降。例如在文件FR2860341、FR2933233、FR2953640、US2015115480、US7268060或US6544656之中，皆公開了此類底材的製作過程。To avoid or limit this phenomenon, it is known to interpose a charge trapping layer, such as a polysilicon layer of 1 to 5 microns, between the buried insulator and the support directly below the insulator. The grain junctions that form the polycrystalline become traps for charge carriers, as these charge carriers may come from the trapping layer itself, or from supports below it. Thus, a conductive plane under the insulator can be avoided, as well as a decrease in the resistivity of the support. For example, in documents FR2860341, FR2933233, FR2953640, US2015115480, US7268060 or US6544656, the production process of such substrates is disclosed.

文件US20150115480提出將捕捉層製作成多晶或非晶SiGe、鍺或SiC基本層（elementary layer）堆疊的形式，每一基本層可能有至少大約5奈米的厚度，且被厚度為數埃（Angstrom）之一鈍化層覆蓋。Document US20150115480 proposes to fabricate the capture layer in the form of a stack of polycrystalline or amorphous SiGe, germanium or SiC elementary layers, each elementary layer possibly having a thickness of at least about 5 nanometers, with a thickness of several angstroms (Angstrom) Covered by a passivation layer.

文件US2016071959描述一種絕緣體上矽類型的結構，其在一電阻性支撐件上包含有數奈米厚之一薄絕緣層及厚度在25奈米至7微米間之一碳摻雜非晶矽層。其碳濃度在1至10％之間。The document US2016071959 describes a silicon-on-insulator type structure comprising, on a resistive support, a thin insulating layer several nanometers thick and a carbon-doped amorphous silicon layer having a thickness between 25 nanometers and 7 micrometers. Its carbon concentration is between 1 and 10%.

文件US20130168835揭露一種用於製作絕緣體上矽底材的方法，其包括提供一支撐底材；在該支撐底材上製作一高電阻率材料層，該高電阻率材料層具有10 到50 微米間的厚度且包含非晶碳化矽、多晶碳化矽、非晶鑽石或多晶鑽石當中一者；在該高電阻率材料層上製作一絕緣層；以及將一施體晶圓組裝至該絕緣層之一上部表面，以形成所述絕緣體上矽底材。Document US20130168835 discloses a method for fabricating a silicon-on-insulator substrate, which includes providing a support substrate; fabricating a high-resistivity material layer on the support substrate, the high-resistivity material layer having a thickness and comprising one of amorphous silicon carbide, polycrystalline silicon carbide, amorphous diamond, or polycrystalline diamond; forming an insulating layer on the high resistivity material layer; and assembling a donor wafer to an upper portion of the insulating layer surface to form the silicon-on-insulator substrate.

這種以多晶或非晶半導體材料提供捕捉層的解決方案雖然頗有效果但相當昂貴，尤其在捕捉層很厚或由基本層堆疊構成時更是如此。此外，製作一厚層，例如數微米，可能造成該層下方的晶圓變形或導致該層特別粗糙，從而使製程變得特別困難。對於要求低射頻效能的集成元件而言，如此高昂的成本是說不過去的。This solution of providing the capture layer in polycrystalline or amorphous semiconductor material, although effective, is quite expensive, especially when the capture layer is very thick or consists of a stack of base layers. In addition, making a thick layer, such as a few microns, can cause deformation of the wafer beneath the layer or cause the layer to be particularly rough, making the process particularly difficult. Such a high cost is justified for integrated components that require low RF performance.

本發明之目的係提供一種用於射頻電子及微電子應用領域之底材，該底材很單純且造價不昂貴，卻具有比不包含捕捉層之絕緣體上矽類型之底材更高的效能。It is an object of the present invention to provide a substrate for radio frequency electronic and microelectronic applications that is simple and inexpensive to manufacture, yet has higher performance than silicon-on-insulator type substrates that do not include a trapping layer.

為了達成此目標，本發明之目的係提供一種用於射頻電子及微電子應用領域之底材，該底材包括： - 一基底底材； - 一單一碳層，其設於該基底底材上並直接與該基底底材接觸，該碳層嚴格地具有範圍1奈米到5奈米之厚度； - 一絕緣體層，其設於該碳層上； - 一元件層，其設於該絕緣體層上。In order to achieve this goal, an object of the present invention is to provide a substrate for radio frequency electronics and microelectronics applications, the substrate comprising: - a base substrate; - a single carbon layer disposed on the base substrate and in direct contact with the base substrate, the carbon layer strictly has a thickness in the range of 1 nm to 5 nm; - an insulator layer, which is provided on the carbon layer; - an element layer, which is provided on the insulator layer superior.

厚度很小之該碳層會形成一捕捉層，令人驚訝的是，該捕捉層可以非常有效率之方式輕易製作。The carbon layer of very small thickness forms a capture layer which, surprisingly, can be easily fabricated in a very efficient manner.

根據本發明其他有利且非限制性特徵，其可以單獨或以任何技術上可行之組合使用： - 該基底底材為具有小於100 ohm.cm電阻率之單晶矽底材； - 該基底底材為具有大於100或1,000 ohm.cm電阻率之單晶矽底材； - 該碳層具有範圍1奈米到3奈米之厚度； - 該底材更包括一鍵合層，其設於該碳層與該絕緣體層之間，並與該碳層與該絕緣體層接觸； - 該鍵合層具有小於10奈米之厚度； - 該鍵合層由非晶、多晶矽或二氧化矽製成； - 該絕緣體層由二氧化矽製成； - 該元件層包含矽； - 該元件層包含至少一射頻元件。According to other advantageous and non-limiting features of the invention, it can be used alone or in any technically feasible combination: - the base substrate is a monocrystalline silicon substrate having a resistivity of less than 100 ohm.cm; - the base substrate is a monocrystalline silicon substrate having a resistivity greater than 100 or 1,000 ohm.cm; - the carbon layer has a thickness ranging from 1 nm to 3 nm; - the substrate further includes a bonding layer disposed on the carbon between the layer and the insulator layer, and in contact with the carbon layer and the insulator layer; - the bonding layer has a thickness of less than 10 nm; - the bonding layer is made of amorphous, polysilicon or silicon dioxide; - The insulator layer is made of silicon dioxide; - the element layer includes silicon; - the element layer includes at least one radio frequency element.

一種用於製作射頻電子及微電子應用領域之底材之方法，該方法包括： - 將一基底底材(3)曝露在含碳前驅氣體中，以使該基底底材充滿前驅氣體所釋放之碳物種而飽和，以在該基底底材上形成厚度嚴格地在1奈米到5奈米範圍之單一碳層(2)之步驟； - 組裝該基底底材與該來源底材，以在該基底底材與該來源底材之間形成一絕緣體層之步驟； - 薄化該來源底材以形成一元件層之步驟。A method for making substrates for radio frequency electronic and microelectronics applications, the method comprising: - exposing a base substrate (3) to a carbon-containing precursor gas, so that the base substrate is filled with the gas released by the precursor gas the steps of saturating the base substrate with carbon species to form a single carbon layer (2) with a thickness strictly in the range of 1 nm to 5 nm on the base substrate; - assembling the base substrate and the source substrate to The step of forming an insulator layer between the base substrate and the source substrate; - the step of thinning the source substrate to form an element layer.

根據本發明其他有利且非限制性特徵，其可以單獨或以任何技術上可行之組合使用： - 該方法包括在曝露步驟後，於該碳層上形成厚度小於10奈米並與該碳層接觸之一鍵合層之步驟； - 形成該鍵合層之步驟包括沉積一鍵合材料及研磨該沉積鍵合材料； - 該來源底材為矽製，且形成該絕緣體層之步驟包括氧化該來源底材； - 該來源底材包含射頻元件，且所述形成該絕緣體層之步驟包括將二氧化矽層沉積在該來源底材上； - 薄化該來源底材之步驟包括以物理及／或化學薄化法逐漸減少該來源底材之部分厚度之步驟； - 薄化該來源底材之步驟包括在所述組裝步驟前，於該來源底材中形成一脆性平面之第一步驟，以及在組裝步驟後，在該脆性平面處使該來源底材斷裂之第二步驟； - 該碳層具有範圍嚴格地在1奈米到3奈米之厚度。According to other advantageous and non-limiting features of the present invention, which can be used alone or in any technically feasible combination: - The method comprises, after the exposure step, forming a thickness of less than 10 nm on the carbon layer and in contact with the carbon layer a bonding layer step; - the step of forming the bonding layer includes depositing a bonding material and grinding the deposited bonding material; - the source substrate is made of silicon, and the step of forming the insulator layer includes oxidizing the source a substrate; - the source substrate includes radio frequency components, and the step of forming the insulator layer includes depositing a silicon dioxide layer on the source substrate; - the step of thinning the source substrate includes physically and/or thinning the source substrate the step of chemically thinning gradually reducing a part of the thickness of the source substrate; - the step of thinning the source substrate comprising a first step of forming a brittle plane in the source substrate before the assembling step, and After the assembly step, a second step of breaking the source substrate at the brittle plane; - the carbon layer has a thickness in the range strictly 1 nm to 3 nm.

圖1係概要繪示根據本發明之一種用於製作射頻電子及微電子應用領域之底材1之第一實施例。FIG. 1 schematically shows a first embodiment of a substrate 1 according to the present invention for the fabrication of radio frequency electronic and microelectronic applications.

第一實施例之底材1包括基底底材3、設於該基底底材3上並直接與其接觸之碳層2，該碳層2具有範圍嚴格地在1奈米到5奈米之厚度，且較佳者為1奈米到3奈米之厚度；設於碳層2上之絕緣體層4，以及設於絕緣體層4上之元件層5。基底底材3與碳層2形成底材1之支撐件9。The substrate 1 of the first embodiment includes a base substrate 3, a carbon layer 2 disposed on the base substrate 3 and in direct contact therewith, the carbon layer 2 having a thickness in the range of strictly 1 nm to 5 nm, And preferably the thickness is 1 nm to 3 nm; the insulator layer 4 provided on the carbon layer 2 , and the element layer 5 provided on the insulator layer 4 . The base substrate 3 and the carbon layer 2 form a support 9 for the substrate 1 .

底材1可以是標準尺寸之圓形平板，例如直徑200公釐、300公釐或甚至450公釐。當底材，更詳細而言元件層5，不具有元件時，尤其如此。然而，本發明不限於這些尺寸與此形狀。The substrate 1 may be a round flat plate of standard size, eg 200mm, 300mm or even 450mm in diameter. This is especially true when the substrate, more specifically the element layer 5, has no elements. However, the present invention is not limited to these dimensions and shapes.

當底材1構成射頻元件成品或半成品之支撐件時，其會具有長方或立方縱截面的塊狀材料之形狀，其尺寸可從數公釐至數公分，符合集成元件的尺寸。When the substrate 1 constitutes a support for a finished or semi-finished radio frequency component, it will have the shape of a block material with a rectangular or cubic longitudinal section, and its size can range from several millimeters to several centimeters, which is in line with the size of the integrated components.

基底底材3具有數百微米之厚度。基底底材3較佳者為具有高電阻率，高於100或1,000 ohms.cm，而更佳者為高於3,000 ohms.cm。可能會在基底底材3中移動並因此影響該底材之RF效能之電荷密度，即電洞或電子密度，因此受到限制。但本發明不限於具有前述電阻率之基底底材，當基底底材具有更常見的電阻率，例如大約數百ohms.cm或100 ohms.cm或更低之電阻率時，本發明也能提供射頻效能方面之益處。The base substrate 3 has a thickness of several hundreds of microns. The base substrate 3 preferably has a high resistivity, higher than 100 or 1,000 ohms.cm, and more preferably higher than 3,000 ohms.cm. The charge density, ie the density of holes or electrons, which may move in the base substrate 3 and thus affect the RF performance of the substrate, is therefore limited. However, the present invention is not limited to the base substrate having the aforementioned resistivity, when the base substrate has a more common resistivity, such as a resistivity of about several hundred ohms.cm or 100 ohms.cm or lower, the present invention can also provide Benefits in RF performance.

出於可取得性與成本因素，基底底材3較佳者為矽製，詳言之由單晶矽所製成。其可為，舉例而言，包含少量間隙氧（interstitial oxygen）之柴氏底材（CZ substrate），眾所周知這類底材可具有高於1000 ohms.cm之電阻率。基底底材也可由其他材料製成：其可為，舉例而言，藍寶石、碳化矽、矽鍺、III-V族材料等。其也可為更標準之單晶柴氏底材，其電阻率低於100 ohms.cm。For reasons of availability and cost, the base substrate 3 is preferably made of silicon, specifically, made of monocrystalline silicon. It can be, for example, a CZ substrate containing a small amount of interstitial oxygen, which is known to have a resistivity higher than 1000 ohms.cm. The base substrate can also be made of other materials: it can be, for example, sapphire, silicon carbide, silicon germanium, III-V materials, and the like. It can also be a more standard single crystal Tzeiz's substrate with a resistivity below 100 ohms.cm.

底材1也包含一單一碳層2，其在基底底材3上方並直接與基底底材3接觸，該碳層具有範圍嚴格地在1奈米到5奈米之厚度，較佳者為1奈米到3奈米之厚度。碳層2之目的在於限制電阻率之損失，其通常可在絕緣體上矽類型之底材之位於絕緣體層下之支撐件中觀察到，如序言部分所述。The substrate 1 also includes a single carbon layer 2 overlying the base substrate 3 and in direct contact with the base substrate 3, the carbon layer having a thickness in the range strictly 1 nm to 5 nm, preferably 1 nanometer to 3 nanometer thickness. The purpose of the carbon layer 2 is to limit the loss of resistivity, which is usually observed in the support under the insulator layer of substrates of the silicon-on-insulator type, as described in the preamble.

在本發明之範疇內，「碳層」意指僅由碳原子所製成之層。該些原子在基底底材3厚度中之一些原子平面之上或之中之遷移或擴散，或在碳層2中構成基底底材3之原子之擴散，可能導致富含碳之層形成，但其可能包含其他物種，詳言之即構成基底底材之物種。In the context of the present invention, "carbon layer" means a layer made only of carbon atoms. The migration or diffusion of these atoms on or in the plane of atoms in the thickness of the base substrate 3, or the diffusion of atoms constituting the base substrate 3 in the carbon layer 2, may result in the formation of a carbon-rich layer, but It may contain other species, specifically the species that make up the base substrate.

讓人意外的是，已觀察到就算碳層2之厚度非常小，也能非常有效提升底材1之RF效能，詳言之其能夠限制甚至完全避免支撐件9與絕緣體層4之交界處之電阻率下降。舉例而言，相較於不具有碳層2之基底底材，將具有高於1,000 ohms.cm之電阻率且厚度為3奈米之碳層2沉積於基底底材3上，將於測量來自共面線（共面線）之二次諧波失真參數（second harmonic distortion parameter）時，獲得20dbm之效能。該特性測量詳細公開於SOITEC公司於2016年3月出版，名為《White paper – RF SOI Characterisation》之文件中。Surprisingly, it has been observed that even a very small thickness of the carbon layer 2 can very effectively improve the RF performance of the substrate 1, in particular it can limit or even completely avoid the interface between the support 9 and the insulator layer 4. Resistivity drops. For example, a carbon layer 2 having a resistivity higher than 1,000 ohms.cm and a thickness of 3 nanometers deposited on the base substrate 3 will be measured from When the second harmonic distortion parameter of the coplanar line (coplanar line) is used, the performance of 20dbm is obtained. This characteristic measurement is disclosed in detail in a document titled "White paper – RF SOI Characterisation" published by SOITEC in March 2016.

這是因為此類碳層包含高密度之缺陷，這些缺陷形成電荷載子捕捉器。相較於由矽、矽鍺、碳化矽或其他材料製成且具有相同厚度之半導體材料之晶體層或非晶層所能獲得的缺陷密度，此缺陷密度高出數個數量級。This is because such carbon layers contain a high density of defects that form charge carrier traps. This defect density is orders of magnitude higher than that obtained with a crystalline or amorphous layer of semiconductor material made of silicon, silicon germanium, silicon carbide, or other materials and having the same thickness.

由於碳層2僅有數奈米之極薄厚度，因此與習知技術之數微米厚且由多晶和非晶材料製成之捕捉層相比，碳層2之製作既不複雜且便宜。Since the carbon layer 2 is only a few nanometers in thickness, the fabrication of the carbon layer 2 is less complicated and less expensive than the prior art capture layers that are several micrometers thick and made of polycrystalline and amorphous materials.

如圖1所繪示，底材1包含直接設置在碳層2上之絕緣體層4。底材也包含元件層5，其接觸並位於絕緣體層4上。此二層之特徵非本發明之關鍵。舉例而言，絕緣體層4可包含二氧化矽或氮化矽，或由二氧化矽或氮化矽製成。其也可為該些材料之堆疊。絕緣體層4之厚度可從10奈米至10微米不等。元件層5通常由單晶矽製成，但也可由其他材料製成，且根據預計在其中形成之RF元件之性質，該些材料可具半導性也可不具半導性。因此，為了形成聲波元件，元件層5可由絕緣體製成，例如鉭酸鋰或鈮酸鋰。元件層之厚度可從10奈米至10微米不等。當元件層5由支撐件9承載時，元件可在該元件層5中形成，但如以下所公開之內容，元件也可在元件層被加到支撐件9上之前形成於此層中。很明顯地，該元件層是連續的，亦即，其覆蓋了底材1的大部分主要面，這樣該底材便可容納高密度的組件。As shown in FIG. 1 , the substrate 1 includes an insulator layer 4 disposed directly on the carbon layer 2 . The substrate also contains an element layer 5 , which is in contact with and rests on the insulator layer 4 . The features of these two layers are not critical to the present invention. For example, the insulator layer 4 may comprise or be made of silicon dioxide or silicon nitride. It can also be a stack of these materials. The thickness of the insulator layer 4 may vary from 10 nanometers to 10 micrometers. The element layer 5 is typically made of single crystal silicon, but can also be made of other materials, which may or may not be semiconducting depending on the nature of the RF element expected to be formed therein. Therefore, in order to form an acoustic wave element, the element layer 5 may be made of an insulator such as lithium tantalate or lithium niobate. The thickness of the device layer can vary from 10 nm to 10 microns. Elements may be formed in element layer 5 as it is carried by support 9 , but as disclosed below, elements may also be formed in this layer before the element layer is added to support 9 . Obviously, the element layer is continuous, ie it covers most of the major face of the substrate 1, so that the substrate can accommodate high density components.

圖2係概要繪示根據本發明之底材1之第二實施例。FIG. 2 schematically shows a second embodiment of the substrate 1 according to the invention.

第二實施例之底材1包含與第一實施例之底材1相同的基底底材3、相同的碳層2、相同的絕緣體層4及相同的元件層5。為保持精簡，其描述將不再重複，且與關於第一實施例之底材1之描述相同的評論，也將適用於第二實施例之底材1。The substrate 1 of the second embodiment includes the same base substrate 3 , the same carbon layer 2 , the same insulator layer 4 and the same element layer 5 as the substrate 1 of the first embodiment. In order to keep it concise, the description thereof will not be repeated, and the same comments as those described with respect to the substrate 1 of the first embodiment will also apply to the substrate 1 of the second embodiment.

從圖2中可明顯看出，底材1也包括位於碳層2和絕緣體層4之間並與兩者接觸之鍵合層7。As is evident from Figure 2, the substrate 1 also includes a bonding layer 7 between and in contact with the carbon layer 2 and the insulator layer 4.

如以下公開之細節，該鍵合層7之目的為便利底材1之製作。其可以由非晶、多晶矽或二氧化矽製成，但也可考慮其他材料。鍵合層可能對底材之RF效能水準造成之影響為次要。然而，必須小心避免其影響該效能。為了達到此目的，必須盡可能限制鍵合層之厚度與傳導性。鍵合層7較佳者為具有小於10奈米之厚度。當鍵合層7由半導體材料製成時，其具有之摻雜濃度低於每立方公分10 E14個原子。鍵合層可富含碳，以具有電阻性。The purpose of the bonding layer 7 is to facilitate the fabrication of the substrate 1 as detailed below. It can be made of amorphous, polysilicon or silicon dioxide, but other materials are also contemplated. The effect that the bonding layer may have on the RF performance level of the substrate is secondary. However, care must be taken to avoid it affecting this performance. To achieve this, the thickness and conductivity of the bonding layer must be limited as much as possible. The bonding layer 7 preferably has a thickness of less than 10 nm. When the bonding layer 7 is made of a semiconductor material, it has a doping concentration lower than 10 E14 atoms per cubic centimeter. The bonding layer may be enriched in carbon for electrical resistance.

無論選擇何種實施例，除單一碳層2及鍵合層7（若必要）外，底材1在基底底材3與絕緣體層4之間不包含任何其他層。RF效能之水準，尤其是位於絕緣體層2下之平面中之支撐件9之電阻率，主要由碳層2提供。Regardless of the embodiment chosen, the substrate 1 does not comprise any other layers between the base substrate 3 and the insulator layer 4, apart from the single carbon layer 2 and the bonding layer 7 (if necessary). The level of RF performance, especially the resistivity of the support 9 in the plane below the insulator layer 2 , is mainly provided by the carbon layer 2 .

本發明之底材1之優點之一在於碳層2對於該底材可能被曝露其中之熱處理不敏感。該底材不太可能因再結晶而失去其電荷捕捉效果，但習知的多晶或非晶捕捉層則會。因此，底材1，在其製作過程中或在RF元件於元件層5之中和之上形成的過程中，可被曝露於高溫中，例如當基底底材3與元件層5為矽製時，底材1可被曝露於高達1,200℃的溫度中。One of the advantages of the substrate 1 of the present invention is that the carbon layer 2 is insensitive to heat treatment to which the substrate may be exposed. The substrate is unlikely to lose its charge trapping effect due to recrystallization, as conventional polycrystalline or amorphous trapping layers do. Thus, substrate 1, during its fabrication or during the formation of RF elements in and on element layer 5, may be exposed to high temperatures, such as when base substrate 3 and element layer 5 are made of silicon , the substrate 1 can be exposed to temperatures up to 1,200°C.

請參閱圖3，現在將描述根據本發明之示例性製作方法。Referring to Figure 3, an exemplary fabrication method in accordance with the present invention will now be described.

一般而言，底材1之製作包含基底底材3之準備，以將其與碳層2一同提供（且很可能包括鍵合層7）以形成支撐件9，以及將元件層5移轉至支撐件9上。In general, the fabrication of substrate 1 includes the preparation of base substrate 3 to provide it with carbon layer 2 (and likely including bonding layer 7 ) to form support 9 , and transfer of element layer 5 to on the support 9.

基基底底材3之準備十分簡單，且以業界標準設備即可做到。基底底材3可被提供在傳統的沉積室中，或甚至在回火爐腔室中，氣體在該回火爐中可循環使用以控制其大氣環境。眾所周知，基底底材3可在曝露於含碳前驅氣體下之沉積前加以準備，以從其表面去除原生氧化層。Preparation of Substrate Substrate 3 is very simple and can be done with industry standard equipment. The base substrate 3 can be provided in a conventional deposition chamber, or even in a tempering furnace chamber, in which gas can be recycled to control its atmosphere. As is known, the base substrate 3 may be prepared prior to deposition by exposure to a carbon-containing precursor gas to remove native oxide layers from its surface.

如圖3a所概要繪示，接著使一含碳前驅氣體，例如C3H8，在大約1000℃，較佳者為高於1000℃的溫度下流入沉積室，以使基底底材3曝露在此前驅氣體中並形成碳層2。前驅氣體可包含或由以下所列者構成，例如，甲烷（CH4）、乙烷（C2H6）、丙烷（C3H8）、乙炔（C2H2）、乙烯（C2H4）等等。前驅氣體在高溫下釋放出的碳物種會與基底底材3曝露表面的原子物種結合。當該表面充滿碳（碳飽和）時，此一反應可自然中斷，從而形成一碳層2，其具有數個原子平面的厚度，嚴格來說在1至5奈米之間，更嚴格來說在1至3奈米之間。曝露的時間長短應足以使碳層覆蓋基底底材3的曝露表面且厚度嚴格地達到1至5奈米之間或1至3奈米之間。曝露時間大約為數分鐘，理想而言（但非限制性），為2到10分鐘之間，且在這段時間結束時，可將含碳前驅氣體或其中斷流量從沉積室排除出去。如前所述，碳原子有可能在基底底材3厚度中的某些原子平面上擴散。同理，基底底材的原子物種亦可遷移到沉積的碳層中。不論哪種情況，亦不論所形成層的確切性質為何，只有碳原子會被沉積以形成碳層。3a, a carbon-containing precursor gas, such as C3H8, is then flowed into the deposition chamber at a temperature of about 1000°C, preferably above 1000°C, to expose the base substrate 3 to the precursor gas and the carbon layer 2 is formed. The precursor gas may comprise or consist of, for example, methane (CH4), ethane (C2H6), propane (C3H8), acetylene (C2H2), ethylene (C2H4), and the like. The carbon species released from the precursor gas at high temperature will combine with atomic species on the exposed surface of the base substrate 3 . When the surface is filled with carbon (carbon saturated), this reaction can be interrupted naturally, forming a carbon layer 2 with a thickness of several atomic planes, strictly speaking between 1 and 5 nanometers, more strictly speaking between 1 and 3 nm. The exposure time should be long enough for the carbon layer to cover the exposed surface of the base substrate 3 and the thickness should be strictly between 1 and 5 nm or between 1 and 3 nm. The exposure time is on the order of a few minutes, ideally (but not limiting) between 2 and 10 minutes, and at the end of this time, the carbonaceous precursor gas or its interrupted flow can be removed from the deposition chamber. As previously mentioned, it is possible for carbon atoms to diffuse in certain atomic planes in the thickness of the base substrate 3 . Similarly, atomic species of the base substrate can also migrate into the deposited carbon layer. In either case, and regardless of the exact nature of the layer formed, only carbon atoms will be deposited to form the carbon layer.

此步驟完成時，可獲得如圖3b所示之支撐件9。該支撐件是為了組裝至一來源底材8（例如透過分子附著）。為此，應注意的是，碳層2的曝露表面不需要任何特別平滑化處理，尤其是研磨，這是因為該碳層事實上在形成後就已具有小於5A RMS的粗糙度，這個粗糙度已低到足以使該碳層組裝到來源底材8。也要注意的是，該特別薄的碳層在支撐件9的整個表面具有非常均勻的厚度。如此均勻的厚度及如此低的粗糙度，是無法以厚層獲得的，尤其是那些超過1或10微米的厚層。本發明的支撐件9不太可能在受到熱處理時因應變作用而變形，但這些應變作用卻很可能在厚層發生，因其具有相異的熱膨脹係數。When this step is completed, the support 9 as shown in Figure 3b can be obtained. The support is intended for assembly to a source substrate 8 (eg by molecular attachment). To this end, it should be noted that the exposed surface of the carbon layer 2 does not require any special smoothing treatment, especially grinding, since the carbon layer in fact already has a roughness of less than 5A RMS after it is formed, this roughness has been low enough for the carbon layer to be assembled to the source substrate 8 . Note also that this particularly thin carbon layer has a very uniform thickness over the entire surface of the support 9 . Such uniform thickness and such low roughness cannot be obtained with thick layers, especially those over 1 or 10 microns. The support 9 of the present invention is unlikely to be deformed by straining effects when subjected to heat treatment, but these straining effects are likely to occur in thick layers due to their differing coefficients of thermal expansion.

由於碳層2具有與來源底材8相異之性質，因此碳層2可能具有需要準備之表面，而該準備也與來源底材8之準備相異。因此，為了簡化製作方法，根據本方法之一替代方案，本發明可提供在碳層2上形成鍵合層7，該鍵合層7表面之準備方式可與來源底材之準備方式相同。其可以是，舉例而言，用由相同設備所供應之具有相同或相似成分之化學物質進行清潔。此方法有助於以低成本製作底材1。Since the carbon layer 2 has different properties from the source substrate 8 , the carbon layer 2 may have a surface that needs to be prepared, and the preparation is also different from that of the source substrate 8 . Therefore, in order to simplify the manufacturing method, according to an alternative of the present method, the present invention can provide for forming a bonding layer 7 on the carbon layer 2, the surface of the bonding layer 7 can be prepared in the same manner as the source substrate. It can be, for example, cleaning with chemicals of the same or similar composition supplied by the same equipment. This method facilitates the production of the substrate 1 at low cost.

根據該製作方法之一替代方案，想要在碳層2上形成鍵合層7時，可將第二前驅氣體引入至沉積室中一定時間，以取代或補足富含碳之前驅氣體，以沉積具有厚度之鍵合材料。應注意沉積厚度不要太厚，以盡可能限制底材1之製作時間與成本。該厚度可為，舉例而言，數十奈米至數百奈米不等。第二前驅氣體可由矽甲烷（SiH4）製成，以形成由多晶或非晶矽製成之鍵合層。According to an alternative to this fabrication method, when it is desired to form the bonding layer 7 on the carbon layer 2, a second precursor gas may be introduced into the deposition chamber for a certain period of time to replace or supplement the carbon-rich precursor gas for deposition Bonding material with thickness. Care should be taken that the deposition thickness is not too thick to limit the fabrication time and cost of the substrate 1 as much as possible. The thickness may vary, for example, from tens of nanometers to hundreds of nanometers. The second precursor gas can be made of silicon methane (SiH4) to form a bonding layer made of polycrystalline or amorphous silicon.

此種「原位」（in-situ）之實施例尤其有利，因為其可在單一步驟中與在單一設備上，結合形成碳層2與沉積用於製作鍵合層7之鍵合材料之步驟。然而，作為替代方法，鍵合材料之沉積可以在另一設備上進行，例如可沉積氧化矽材料之設備。無論鍵合材料之性質和在碳層2上沉積該鍵合材料所用設備為何，都必須小心將厚度限制在如上所述之數百奈米中。接著對鍵合材料進行準備，例如透過機械化學研磨法，以使其表面夠平滑，低於5A RMS，以使其能與來源底材8進行組裝。此係繪示於圖3c中。平滑步驟會使鍵合材料之厚度之薄化以提供鍵合層7，其厚度最好不應超過10奈米，以免過度影響底材之RF效能。完成此步驟後，如圖3d所繪示，即可獲得包含鍵合層7之支撐件9，該鍵合層7厚度不超過10奈米，直接設置在碳層2上，該碳層2本身直接設置在基底底材3上。This "in-situ" embodiment is particularly advantageous because it can combine the steps of forming the carbon layer 2 and depositing the bonding material used to make the bonding layer 7 in a single step and on a single device . However, as an alternative, the deposition of the bonding material can be performed on another device, such as one that can deposit silicon oxide material. Regardless of the nature of the bonding material and the equipment used to deposit it on the carbon layer 2, care must be taken to limit the thickness to hundreds of nanometers as described above. The bonding material is then prepared, for example by mechanochemical grinding, so that its surface is sufficiently smooth, below 5A RMS, to allow assembly with the source substrate 8 . This line is shown in Figure 3c. The smoothing step will reduce the thickness of the bonding material to provide the bonding layer 7, which preferably should not exceed 10 nm in thickness, so as not to unduly affect the RF performance of the substrate. After completing this step, as shown in FIG. 3d, a support member 9 including a bonding layer 7 can be obtained. The bonding layer 7 has a thickness of no more than 10 nm and is directly disposed on the carbon layer 2. The carbon layer 2 itself directly on the base substrate 3 .

無論選擇之支撐件9是否包含鍵合層，皆係透過組裝來源底材8之表面與支撐件9以進行元件層5之移轉。來源底材可包含RF元件，也可由一塊不含元件之材料形成。Regardless of whether the selected support 9 includes a bonding layer, the transfer of the element layer 5 is performed by assembling the surface of the source substrate 8 and the support 9 . The source substrate may contain RF components, or may be formed from a piece of material that does not contain components.

有利的是，該組裝步驟對應於使彼此接觸之底材8之表面與支撐件9之表面進行之分子附著鍵合。Advantageously, this assembly step corresponds to the molecular adhesive bonding of the surfaces of the substrate 8 and the support 9 in contact with each other.

移轉可包括在組裝步驟前，在支撐件9及／或來源底材8上，形成一厚度之絕緣體之步驟。在組裝步驟後，該厚度將形成絕緣體層4。當絕緣體係透過沉積形成時，該沉積步驟後可接著進行研磨步驟。絕緣體可包含，舉例而言，氧化矽或氮化矽。當來源底材係由矽製成且不包含元件時，形成絕緣體層之步驟可包括該層之氧化。圖3e係繪示設有絕緣體層之來源底材8。組裝來源底材8與支撐件9，將使絕緣體層4被設置於支撐件9與來源底材8之間，其中圖3f係繪示支撐件9不包含鍵合層之情況，而圖3g係繪示支撐件9包含鍵合層7之情況。The transfer may include the step of forming a thickness of insulator on the support 9 and/or the source substrate 8 prior to the assembly step. This thickness will form the insulator layer 4 after the assembly step. When the insulating system is formed by deposition, the deposition step may be followed by a grinding step. The insulator may comprise, for example, silicon oxide or silicon nitride. When the source substrate is made of silicon and does not contain components, the step of forming the insulator layer may include oxidation of the layer. Figure 3e shows the source substrate 8 provided with the insulator layer. Assembling the source substrate 8 and the support member 9 causes the insulator layer 4 to be disposed between the support member 9 and the source substrate 8, wherein FIG. 3f shows the case where the support member 9 does not include a bonding layer, and FIG. 3g shows the The case where the support 9 includes the bonding layer 7 is shown.

為了強化組裝，可考慮將圖3f與圖3g之結構曝露於熱回火中。如以下公開之內容，回火步驟可以在組裝步驟後及／或薄化步驟後直接進行。如上所述，回火步驟可包括將結構曝露於高溫中，而不需冒著影響製作完成後所獲得之底材之RF效能之風險。To enhance assembly, exposure of the structures of Figures 3f and 3g to thermal tempering may be considered. As disclosed below, the tempering step can be performed directly after the assembly step and/or after the thinning step. As noted above, the tempering step may include exposing the structure to elevated temperatures without risking affecting the RF performance of the resulting substrate after fabrication.

組裝步驟後，施體底材被薄化以形成元件層5。After the assembly step, the donor substrate is thinned to form element layer 5 .

薄化步驟可以物理及／或化學薄化法，逐漸減少來源底材的一部分厚度之方式進行。The thinning step may be performed by physical and/or chemical thinning methods by gradually reducing the thickness of a portion of the source substrate.

作為替代方法，此步驟也可根據Smart Cut^TM 技術的原理，在與支撐件進行組裝前，在預先於來源底材中形成之脆性平面處進行斷裂。As an alternative, this step can also be performed according to ^{the principle of the Smart Cut™} technology, by breaking at the brittle planes previously formed in the source substrate prior to assembly with the support.

在薄化步驟後，可接著進行元件層5之處理加工步驟，以及研磨步驟、在還原或中性氣體的環境中（在垂直爐、水平爐，或高速熱處理裝置中）之熱處理步驟，以及犧牲氧化步驟。After the thinning step, a processing step of the element layer 5 can be followed, as well as a grinding step, a heat treatment step in a reducing or neutral gas environment (in a vertical furnace, a horizontal furnace, or a high-speed heat treatment device), and sacrificial Oxidation step.

在薄化及視需要進行處理加工後，可獲得根據本發明之底材1，其中圖3h係繪示當支撐件9不包含鍵合層之情況，而圖3i係繪示當支撐件9包含鍵合層7之情況。After thinning and if necessary processing, the substrate 1 according to the invention can be obtained, wherein FIG. 3h shows the case when the support 9 does not contain a bonding layer, and FIG. 3i shows when the support 9 contains The case of bonding layer 7.

當來源底材8為簡單半導體底材，即不包含集成元件時，將因此獲得絕緣體上半導體類型之底材，其中元件層5為空白半導體層。該底材可接著被用於形成集成元件，尤其是射頻積體電路。When the source substrate 8 is a simple semiconductor substrate, ie does not contain integrated components, a substrate of the semiconductor-on-insulator type will thus be obtained, in which the component layer 5 is a blank semiconductor layer. The substrate can then be used to form integrated components, especially radio frequency integrated circuits.

當來源底材8已先經過處理以在其表面形成集成元件時，當本發明之方法完成時，即可獲得包含這些元件之元件層5。When the source substrate 8 has been previously treated to form integrated elements on its surface, the element layer 5 containing these elements can be obtained when the method of the present invention is completed.

當然，本發明不限於所述之實施例，且對於實施例所為之各種替代方案，均落入以下申請專利範圍所界定之範疇。Of course, the present invention is not limited to the described embodiments, and various alternatives to the embodiments fall within the scope defined by the following patent claims.

1‧‧‧底材2‧‧‧碳層3‧‧‧基底底材4‧‧‧絕緣體層5‧‧‧元件層7‧‧‧鍵合層8‧‧‧來源底材9‧‧‧支撐件1‧‧‧Substrate 2‧‧‧Carbon layer3‧‧‧Substrate 4‧‧‧Insulator layer5‧‧‧Component layer7‧‧‧Bonding layer8‧‧‧Source substrate9‧‧‧Support piece

下文之實施方式將更清楚說明本發明的其他特徵和優點，其內容可參照附圖，其中： - 圖1係繪示根據本發明第一實施例之底材； - 圖2係繪示根據本發明第二實施例之底材； - 圖3係繪示根據本發明之一種用於製作底材之方法。Further features and advantages of the invention will be more clearly explained in the following embodiments, the content of which can be referred to the accompanying drawings, in which: - Figure 1 shows a substrate according to a first embodiment of the invention; - Figure 2 shows a substrate according to the invention A substrate of the second embodiment of the invention; - Figure 3 shows a method for making a substrate according to the present invention.

1‧‧‧底材 1‧‧‧Substrate

2‧‧‧碳層 2‧‧‧Carbon layer

3‧‧‧基底底材 3‧‧‧Substrate

4‧‧‧絕緣體層 4‧‧‧Insulator layer

5‧‧‧元件層 5‧‧‧Component layer

9‧‧‧支撐件 9‧‧‧Support

Claims

一種用於射頻電子及微電子領域應用之底材(1)，該底材包括：- 一基底底材(3)；- 一單一碳層(2)，其設於該基底底材(3)上並直接與該基底底材(3)接觸，該碳層(2)具有嚴格地從1奈米到5奈米之厚度範圍；- 一絕緣體層(4)，其設於該碳層(2)上；- 一元件層(5)，其設於該絕緣體層(4)上。 A substrate (1) for applications in the fields of radio frequency electronics and microelectronics, the substrate comprising: - a base substrate (3); - a single carbon layer (2) provided on the base substrate (3) on and in direct contact with the base substrate (3), the carbon layer (2) having a thickness ranging strictly from 1 nm to 5 nm; an insulator layer (4) provided on the carbon layer (2) ); - an element layer (5) provided on the insulator layer (4).

如申請專利範圍第1項之底材(1)，其中該基底底材(3)為具有小於100ohm.cm電阻率之一單晶矽底材。 The substrate (1) of claim 1, wherein the base substrate (3) is a single-crystal silicon substrate with a resistivity less than 100 ohm.cm.

如申請專利範圍第1項之底材(1)，其中該基底底材(3)為具有大於100或1,000ohm.cm電阻率之一單晶矽底材。 The substrate (1) of claim 1, wherein the base substrate (3) is a single-crystal silicon substrate having a resistivity greater than 100 or 1,000 ohm.cm.

如申請專利範圍第1至3項任一項之底材(1)，其中該碳層(2)具有範圍1奈米到3奈米之厚度。 The substrate (1) according to any one of claims 1 to 3 of the claimed scope, wherein the carbon layer (2) has a thickness ranging from 1 nm to 3 nm.

如申請專利範圍第1項之底材(1)，其更包括一鍵合層(7)設於該碳層(2)與該絕緣體層(4)之間，並與該碳層(2)與該絕緣體層(4)接觸。 According to the substrate (1) of the first item of the patent application scope, it further comprises a bonding layer (7) disposed between the carbon layer (2) and the insulator layer (4), and connected to the carbon layer (2) in contact with the insulator layer (4).

如申請專利範圍第5項之底材(1)，其中該鍵合層(7)具有小於10奈米之厚度。 The substrate (1) according to claim 5 of the scope of application, wherein the bonding layer (7) has a thickness of less than 10 nanometers.

如申請專利範圍第5或6項之底材(1)，其中該鍵合層(7)為非晶、多晶矽製或二氧化矽製。 According to the substrate (1) of the claim 5 or 6 of the scope of the application, wherein the bonding layer (7) is made of amorphous, polysilicon or silicon dioxide.

如申請專利範圍第1項之底材(1)，其中該絕緣體層(4)為二氧化矽製。 According to the substrate (1) of claim 1, wherein the insulator layer (4) is made of silicon dioxide.

如申請專利範圍第1項之底材(1)，其中該元件層(5)包含矽。 As claimed in claim 1, the substrate (1), wherein the element layer (5) comprises silicon.

如申請專利範圍第1項之底材(1)，其中該元件層(5)包含至少一射頻元件。 According to the substrate (1) of claim 1, wherein the element layer (5) comprises at least one radio frequency element.

一種用於製作射頻電子及微電子領域應用之底材(1)之方法，該方法包括：- 將一基底底材(3)曝露在含碳前驅氣體中，以使其充滿前驅氣體所釋放之碳物種而飽和，以在該基底底材上形成厚度嚴格地在1奈米到5奈米範圍之單一碳層(2)之步驟；- 在該碳層(2)及/或一來源底材(8)上形成一厚度之絕緣體之步驟；- 組裝該基底底材(3)與該來源底材(8)以在該基底底材(3)與該來源底材(8)之間形成一絕緣體層(4)之步驟；- 薄化該來源底材(8)以形成一元件層(5)之步驟。 A method for making a substrate (1) for applications in the field of radio frequency electronics and microelectronics, the method comprising: - exposing a substrate (3) to a carbon-containing precursor gas so that it is saturated with the released gas from the precursor gas A step of saturating the carbon species to form a single carbon layer (2) with a thickness strictly in the range of 1 nm to 5 nm on the base substrate; - on the carbon layer (2) and/or on a source substrate (8) the step of forming an insulator of a thickness on it; - assembling the base substrate (3) and the source substrate (8) to form an insulator between the base substrate (3) and the source substrate (8) step of insulator layer (4); - step of thinning the source substrate (8) to form an element layer (5).

如申請專利範圍第11項之方法，其包括在所述曝露步驟後，於該碳層(2)上形成厚度小於10奈米並與該碳層(2)接觸之一鍵合層(7)之步驟。 The method of claim 11 of the claimed scope, comprising, after the exposing step, forming a bonding layer (7) with a thickness of less than 10 nm on the carbon layer (2) and in contact with the carbon layer (2) steps.

如申請專利範圍第12項之方法，其中所述形成該鍵合層(7)之步驟包括沉積一鍵合材料及研磨該沉積鍵合材料。 The method of claim 12, wherein the step of forming the bonding layer (7) comprises depositing a bonding material and grinding the deposited bonding material.

如申請專利範圍第11至13項任一項之方法，其中該來源底材(8)為矽製，且所述形成該絕緣體層(4)之步驟包括氧化該來源底材(8)。 The method of any one of claims 11 to 13, wherein the source substrate (8) is made of silicon, and the step of forming the insulator layer (4) comprises oxidizing the source substrate (8).

如申請專利範圍第11至13項任一項之方法，其中該來源底材(8)包含射頻元件，且所述形成該絕緣體層(4)之步驟包括將一二氧化矽層沉積在該來源底材(8)上。 The method of any one of claims 11 to 13 of the claimed scope, wherein the source substrate (8) comprises radio frequency components, and the step of forming the insulator layer (4) comprises depositing a silicon dioxide layer on the source on the substrate (8).

如申請專利範圍第11項之方法，其中所述薄化該來源底材(8)之步驟包括以物理及/或化學薄化法逐漸減少該來源底材(8)的一部分厚度之步驟。 The method of claim 11, wherein the step of thinning the source substrate (8) includes the step of gradually reducing a part of the thickness of the source substrate (8) by physical and/or chemical thinning methods.

如申請專利範圍第11項之方法，其中所述薄化該來源底材(8)之步驟包括在所述組裝步驟前，於該來源底材(8)中形成一脆性平面之第一步驟，以及在所述組裝步驟後，在該脆性平面處使該來源底材(8)斷裂之第二步驟。 The method of claim 11, wherein the step of thinning the source substrate (8) includes a first step of forming a brittle plane in the source substrate (8) before the assembling step, and a second step of breaking the source substrate (8) at the brittle plane after said assembly step.

如申請專利範圍第11項之方法，其中該碳層(2)具有嚴格地在1奈米到3奈米範圍之厚度。The method of claim 11, wherein the carbon layer (2) has a thickness strictly in the range of 1 nm to 3 nm.