TWI749642B - Semiconductor structure - Google Patents

Semiconductor structure Download PDF

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TWI749642B
TWI749642B TW109124186A TW109124186A TWI749642B TW I749642 B TWI749642 B TW I749642B TW 109124186 A TW109124186 A TW 109124186A TW 109124186 A TW109124186 A TW 109124186A TW I749642 B TWI749642 B TW I749642B
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bit line
semiconductor structure
source line
local
memory cell
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TW109124186A
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TW202205632A (en
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葉騰豪
呂函庭
胡志瑋
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旺宏電子股份有限公司
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Abstract

A semiconductor structure includes a stack of memory cells and a CMOS structure. The CMOS structure is located below the stack of memory cells. The CMOS structure includes a source line transistor and a bit line transistor.

Description

半導體結構 Semiconductor structure

本發明是有關於一種半導體結構，且特別是有關於一種三維半導體結構。 The present invention relates to a semiconductor structure, and particularly relates to a three-dimensional semiconductor structure.

隨著半導體技術的發展，各式半導體元件不斷推陳出新。半導體元件經過適當地安排後可以實現各種電性功能。現今各種電子產品皆已大量應用各種半導體元件。 With the development of semiconductor technology, various types of semiconductor components are constantly being introduced. After proper arrangement, the semiconductor components can realize various electrical functions. Nowadays, various electronic products have applied various semiconductor components in large quantities.

其中隨著電子產品追求「輕、薄、短、小」的趨勢下，如何將半導體元件的體積縮小，提升半導體元件的晶片性能，已成為半導體產業一項重要研究發展方向。 Among them, with the trend of electronic products pursuing "light, thin, short, and small", how to reduce the size of semiconductor components and improve the chip performance of semiconductor components has become an important research and development direction of the semiconductor industry.

本發明係有關於一種半導體結構。藉由設置互補式金屬氧化物半導體結構(包括階梯解碼器)於記憶胞堆疊之下，能夠有效減小記憶體裝置之尺寸，進一步降低製造成本，從而提升晶片性能。再者，藉由使局部位元線與局部源極線係交替排列且 分別連接至位元線電晶體與源極線電晶體，能夠有效減少局部位元線與局部源極線的電阻電容延遲時間(RC delay time)。 The present invention relates to a semiconductor structure. By arranging a complementary metal oxide semiconductor structure (including a ladder decoder) under the memory cell stack, the size of the memory device can be effectively reduced, the manufacturing cost can be further reduced, and the chip performance can be improved. Furthermore, by alternately arranging the local bit lines and the local source lines and Connecting to the bit line transistor and the source line transistor respectively can effectively reduce the RC delay time of the local bit line and the local source line.

根據本發明之一方面，提出一種半導體結構。半導體結構包括一記憶胞堆疊以及一互補式金屬氧化物半導體結構。互補式金屬氧化物半導體結構位於記憶胞堆疊的下方，且互補式金屬氧化物半導體結構包括一源極線電晶體與一位元線電晶體。 According to one aspect of the present invention, a semiconductor structure is provided. The semiconductor structure includes a memory cell stack and a complementary metal oxide semiconductor structure. The complementary metal oxide semiconductor structure is located under the memory cell stack, and the complementary metal oxide semiconductor structure includes a source wire transistor and a bit wire transistor.

為了對本發明之上述及其他方面有更佳的瞭解，下文特舉實施例，並配合所附圖式詳細說明如下： In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are given in conjunction with the accompanying drawings to describe in detail as follows:

10,20,30,40,50:半導體結構 10, 20, 30, 40, 50: semiconductor structure

100:階梯解碼器 100: Ladder decoder

110:局部驅動器 110: local drive

120:位準偏移器 120: level shifter

130:其他電路 130: other circuits

200:源極線電晶體 200: source line transistor

300:位元線電晶體 300: bit line transistor

400:階梯區 400: step area

500,500_1,500_2...~500_K-1,500_K:記憶胞堆疊 500,500_1,500_2...~500_K-1,500_K: memory cell stacking

600:絕緣堆疊 600: Insulation stack

700:總體位元線 700: Overall bit line

800:總體源極線 800: overall source line

910:第一柱元件 910: The first column element

920:第二柱元件 920: second column element

930:第三柱元件 930: third column element

940:第四柱元件 940: Fourth column element

1000:感測放大器 1000: Sense amplifier

1100:通孔 1100: Through hole

1200:第一金屬層 1200: the first metal layer

1300:第二金屬層 1300: second metal layer

1400:局部位元線 1400: local bit line

1500:局部源極線 1500: local source line

1600:記憶胞 1600: memory cell

WL0,WL1,...WLj-1,WLj:字元線 WL 0 ,WL 1 ,...WL j-1 ,WL j : character line

第1A圖繪示依照本發明的第一實施例的半導體結構的部分上視圖；第1B圖繪示第1A圖的半導體結構的立體示意圖；第1C圖繪示第1A圖的半導體結構的階梯解碼器與記憶胞堆疊的佈局視圖；第2A圖繪示依照本發明的第二實施例的半導體結構的部份上視圖；第2B圖繪示第2A圖的半導體結構的局部放大圖；第2C圖繪示第2A圖的半導體結構的立體示意圖；第3圖繪示依照本發明的第三實施例的半導體結構的局部位元線、局部源極線、總體位元線與總體源極線的佈局視圖； 第4圖繪示依照本發明的第四實施例的半導體結構的局部位元線、局部源極線、總體位元線與總體源極線的佈局視圖；第5圖繪示依照本發明的第五實施例的半導體結構的局部位元線、局部源極線與總體位元線的佈局視圖。 Fig. 1A shows a partial top view of the semiconductor structure according to the first embodiment of the present invention; Fig. 1B shows a three-dimensional schematic diagram of the semiconductor structure of Fig. 1A; Fig. 1C shows the ladder decoding of the semiconductor structure of Fig. 1A A layout view of a stack of a device and a memory cell; Fig. 2A shows a partial top view of the semiconductor structure according to the second embodiment of the present invention; Fig. 2B shows a partial enlarged view of the semiconductor structure of Fig. 2A; Fig. 2C Shows a three-dimensional schematic diagram of the semiconductor structure of FIG. 2A; FIG. 3 shows the layout of local bit lines, local source lines, global bit lines, and global source lines of the semiconductor structure according to the third embodiment of the present invention view; Figure 4 shows a layout view of the local bit lines, local source lines, global bit lines, and global source lines of the semiconductor structure according to the fourth embodiment of the present invention; The layout view of the local bit lines, the local source lines, and the overall bit lines of the semiconductor structure of the fifth embodiment.

在下文的詳細描述中，為了便於解釋，係提供各種的特定細節以整體理解本揭露之實施例。然而，應理解的是，一或多個實施例能夠在不採用這些特定細節的情況下實現。在其他情況下，為了簡化圖式，已知的結構及元件係以示意圖表示。 In the following detailed description, for the convenience of explanation, various specific details are provided to understand the embodiments of the present disclosure as a whole. However, it should be understood that one or more embodiments can be implemented without employing these specific details. In other cases, in order to simplify the drawings, the known structures and elements are shown in schematic diagrams.

另外，說明書與請求項中所使用的序數例如「第一」、「第二」、「第三」等之用詞，以修飾請求項之元件，其本身並不意含及代表此元件有任何之前的序數，也不代表某一元件與另一元件的順序、或是製造方法上的順序，此些序數的使用僅用來使具有某命名的一元件得以和另一具有相同命名的元件能作出清楚區分。 In addition, the ordinal numbers used in the description and the request, such as the terms "first", "second", "third", etc., are used to modify the elements of the request, and they do not imply or represent any previous The ordinal number does not represent the order of a component and another component, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name and another component with the same name can be made Make a clear distinction.

<第一實施例> <First embodiment>

第1A圖繪示依照本發明的第一實施例的半導體結構10的部分上視圖。第1B圖繪示第1A圖的半導體結構10的立體示意圖。 FIG. 1A shows a partial top view of the semiconductor structure 10 according to the first embodiment of the present invention. FIG. 1B is a three-dimensional schematic diagram of the semiconductor structure 10 of FIG. 1A.

請同時參照第1A及1B圖，半導體結構10包括互補式金屬氧化物半導體結構(包括源極線電晶體200、位元線電晶 體300與階梯解碼器100)、記憶胞堆疊500與絕緣堆疊600。 Please refer to FIGS. 1A and 1B at the same time, the semiconductor structure 10 includes a complementary metal oxide semiconductor structure (including source line transistor 200, bit line transistor The body 300 and the ladder decoder 100), the memory cell stack 500 and the insulating stack 600.

一實施例中，互補式金屬氧化物半導體結構位於記憶胞堆疊500的下方。記憶胞堆疊500在縱方向(例如Z方向)上重疊於其中一部分的互補式金屬氧化物半導體結構，並與另一部分的互補式金屬氧化物半導體結構錯開。 In one embodiment, the complementary metal oxide semiconductor structure is located under the memory cell stack 500. The memory cell stack 500 overlaps a part of the complementary metal oxide semiconductor structure in the longitudinal direction (for example, the Z direction), and is staggered from the other part of the complementary metal oxide semiconductor structure.

一實施例中，源極線電晶體200與位元線電晶體300設置於記憶胞堆疊500的相對兩側。換言之，在縱方向(例如Z方向)上，記憶胞堆疊500並未重疊源極線電晶體200與位元線電晶體300。源極線電晶體200與位元線電晶體300可沿著X方向延伸。舉例而言，源極線電晶體200與位元線電晶體300可以是背對背金屬氧化物半導體場效電晶體(back-to-back MOSFET transistor)，然本發明並不限於此。 In one embodiment, the source line transistor 200 and the bit line transistor 300 are disposed on opposite sides of the memory cell stack 500. In other words, in the longitudinal direction (for example, the Z direction), the memory cell stack 500 does not overlap the source line transistor 200 and the bit line transistor 300. The source line transistor 200 and the bit line transistor 300 may extend along the X direction. For example, the source line transistor 200 and the bit line transistor 300 may be back-to-back MOSFET transistors, but the invention is not limited thereto.

一實施例中，階梯解碼器100位於記憶胞堆疊500的下方。換言之，在縱方向(例如Z方向)上，階梯解碼器100至少部分重疊記憶胞堆疊500。一般來說，相較於互補式金屬氧化物半導體結構之中的其他元件而言，階梯解碼器100佔有較大的空間。因此，藉由將階梯解碼器100設置於記憶胞堆疊500的下方，將有利於小尺寸的半導體結構10製成。此外，記憶胞堆疊500可包括多個陣列區塊(array block)，多個陣列區塊可組成一陣列片(array tile)，且每個陣列片可具有設置於下方的一階梯解碼器100並可獨立操作及控制每個陣列區塊。由於每個陣列區塊屬於較小的單元，其本身具有輕盈的電阻電容延遲時間，因此可 進行高速的操作。 In one embodiment, the ladder decoder 100 is located below the memory cell stack 500. In other words, in the longitudinal direction (for example, the Z direction), the ladder decoder 100 at least partially overlaps the memory cell stack 500. Generally speaking, compared with other components in the complementary metal oxide semiconductor structure, the ladder decoder 100 occupies a larger space. Therefore, by disposing the ladder decoder 100 below the memory cell stack 500, it is advantageous to manufacture the small-sized semiconductor structure 10. In addition, the memory cell stack 500 may include a plurality of array blocks, and the plurality of array blocks may form an array tile, and each array tile may have a ladder decoder 100 disposed below and Each array block can be operated and controlled independently. Since each array block belongs to a smaller unit, it has a light resistance and capacitance delay time, so it can be Perform high-speed operations.

相較於互補式金屬氧化物半導體結構是位於記憶胞堆疊的周邊區域而非位於記憶胞堆疊之下的比較例而言，在本發明的半導體結構10中，互補式金屬氧化物半導體結構是設置於記憶胞堆疊500之下，故能夠有效減小記憶體裝置之尺寸，進一步降低製造成本，從而提升晶片性能。 Compared with the comparative example in which the complementary metal oxide semiconductor structure is located in the peripheral area of the memory cell stack instead of under the memory cell stack, in the semiconductor structure 10 of the present invention, the complementary metal oxide semiconductor structure is provided with Under the memory cell stack 500, the size of the memory device can be effectively reduced, the manufacturing cost is further reduced, and the chip performance is improved.

一實施例中，絕緣堆疊600位於源極線電晶體200與位元線電晶體300的上方。換言之，在縱方向(例如Z方向)上，源極線電晶體200與位元線電晶體300至少部分重疊絕緣堆疊600。 In one embodiment, the insulating stack 600 is located above the source line transistor 200 and the bit line transistor 300. In other words, in the longitudinal direction (for example, the Z direction), the source line transistor 200 and the bit line transistor 300 at least partially overlap the insulating stack 600.

一實施例中，記憶胞堆疊500可包括交替堆疊的導電層與絕緣層。記憶胞堆疊500例如是三維及閘型記憶體陣列(3D-AND type memory array)，然本發明並不以此為限。 In an embodiment, the memory cell stack 500 may include conductive layers and insulating layers stacked alternately. The memory cell stack 500 is, for example, a 3D-AND type memory array, but the invention is not limited thereto.

一實施例中，記憶胞堆疊500包括階梯區400。在縱方向(例如Z方向)上，階梯解碼器100至少部分重疊階梯區400。 In one embodiment, the memory cell stack 500 includes a step area 400. In the longitudinal direction (for example, the Z direction), the stepped decoder 100 at least partially overlaps the stepped area 400.

請參照第1B圖，半導體結構10可更包括總體位元線700、總體源極線(亦可稱作共同源極線)800、第一柱元件910、第二柱元件920、第三柱元件930、第四柱元件940、局部位元線1400與局部源極線1500。 Referring to FIG. 1B, the semiconductor structure 10 may further include an overall bit line 700, an overall source line (also referred to as a common source line) 800, a first pillar element 910, a second pillar element 920, and a third pillar element 930, the fourth pillar element 940, the local bit line 1400, and the local source line 1500.

一實施例中，絕緣堆疊600係相鄰於記憶胞堆疊500。記憶胞堆疊500與絕緣堆疊600可交替排列，然本發明並不限於 此。舉例而言，記憶胞堆疊500與絕緣堆疊600可沿著Y方向上排列。 In one embodiment, the insulating stack 600 is adjacent to the memory cell stack 500. The memory cell stack 500 and the insulating stack 600 can be alternately arranged, but the present invention is not limited to this. For example, the memory cell stack 500 and the insulating stack 600 can be arranged along the Y direction.

一實施例中，絕緣堆疊600可包括交替堆疊的兩種介電層，例如氧化物層與氮化物層。舉例而言，絕緣堆疊600可包括交替堆疊的二氧化矽(SiO2)層以及四氮化三矽(Si3N4)層，然本發明並不限於此。 In an embodiment, the insulating stack 600 may include two types of dielectric layers stacked alternately, such as an oxide layer and a nitride layer. For example, the insulating stack 600 may include alternately stacked silicon dioxide (SiO 2 ) layers and silicon tetranitride (Si 3 N 4 ) layers, but the present invention is not limited thereto.

一實施例中，局部位元線1400與局部源極線1500位於記憶胞堆疊500與絕緣堆疊600的上方，並分別電性連接於記憶胞堆疊500中之記憶胞串列的源極或汲極。局部位元線1400與局部源極線1500的延伸方向可平行於記憶胞堆疊500與絕緣堆疊600的延伸方向。局部位元線1400與局部源極線1500係沿著Y方向上延伸。舉例而言，局部位元線1400與局部源極線1500可以交替排列，然本發明並不限於此。局部位元線1400與局部源極線1500可包括合適的導電材料，例如銅(Cu)或鎢(W)。 In one embodiment, the local bit line 1400 and the local source line 1500 are located above the memory cell stack 500 and the insulating stack 600, and are respectively electrically connected to the source or drain of the memory cell series in the memory cell stack 500 . The extension direction of the local bit line 1400 and the local source line 1500 may be parallel to the extension direction of the memory cell stack 500 and the insulation stack 600. The local bit line 1400 and the local source line 1500 extend along the Y direction. For example, the local bit lines 1400 and the local source lines 1500 can be alternately arranged, but the invention is not limited thereto. The local bit line 1400 and the local source line 1500 may include suitable conductive materials, such as copper (Cu) or tungsten (W).

一實施例中，總體位元線700與總體源極線800位於記憶胞堆疊500與絕緣堆疊600的上方。舉例而言，總體位元線700與總體源極線800可位於局部位元線1400與局部源極線1500的上方。總體位元線700與總體源極線800的延伸方向可平行於記憶胞堆疊500與絕緣堆疊600的延伸方向。總體位元線700與總體源極線800係沿著Y方向上延伸。總體位元線700與總體源極線800可包括合適的導電材料，例如鋁銅合金(AlCu alloy)。 In one embodiment, the overall bit line 700 and the overall source line 800 are located above the memory cell stack 500 and the insulating stack 600. For example, the global bit line 700 and the global source line 800 may be located above the local bit line 1400 and the local source line 1500. The extending direction of the overall bit line 700 and the overall source line 800 may be parallel to the extending direction of the memory cell stack 500 and the insulating stack 600. The global bit line 700 and the global source line 800 extend along the Y direction. The overall bit line 700 and the overall source line 800 may include suitable conductive materials, such as AlCu alloy.

一實施例中，第一柱元件910、第二柱元件920、第三柱元件930與第四柱元件940穿過絕緣堆疊600。第一柱元件910、第二柱元件920、第三柱元件930與第四柱元件940係在縱方向(例如Z方向)上延伸。第一柱元件910、第二柱元件920、第三柱元件930與第四柱元件940可包括合適的導電材料，例如鎢(W)。 In an embodiment, the first pillar element 910, the second pillar element 920, the third pillar element 930, and the fourth pillar element 940 pass through the insulating stack 600. The first pillar element 910, the second pillar element 920, the third pillar element 930, and the fourth pillar element 940 extend in the longitudinal direction (for example, the Z direction). The first pillar element 910, the second pillar element 920, the third pillar element 930, and the fourth pillar element 940 may include a suitable conductive material, such as tungsten (W).

一實施例中，局部位元線1400藉由第一柱元件910電性連接至位元線電晶體300，位元線電晶體300藉由第二柱元件920電性連接至總體位元線700。根據本實施例，局部位元線1400連接第一柱元件910，第一柱元件910連接位元線電晶體300，位元線電晶體300連接第二柱元件920，且第二柱元件920連接總體位元線700。 In one embodiment, the local bit line 1400 is electrically connected to the bit line transistor 300 through the first pillar element 910, and the bit line transistor 300 is electrically connected to the overall bit line 700 through the second pillar element 920 . According to this embodiment, the local bit line 1400 is connected to the first column element 910, the first column element 910 is connected to the bit line transistor 300, the bit line transistor 300 is connected to the second column element 920, and the second column element 920 is connected The overall bit line is 700.

一實施例中，局部源極線1500藉由第三柱元件930電性連接至源極線電晶體200，源極線電晶體200藉由第四柱元件940電性連接至總體源極線800。根據本實施例，局部源極線1500連接第三柱元件930，第三柱元件930連接源極線電晶體200，源極線電晶體200連接第四柱元件940，且第四柱元件940連接總體源極線800。 In one embodiment, the local source line 1500 is electrically connected to the source line transistor 200 through the third pillar element 930, and the source line transistor 200 is electrically connected to the overall source line 800 through the fourth pillar element 940 . According to this embodiment, the local source line 1500 is connected to the third pillar element 930, the third pillar element 930 is connected to the source line transistor 200, the source line transistor 200 is connected to the fourth pillar element 940, and the fourth pillar element 940 is connected The overall source line 800.

藉由使局部位元線1400與局部源極線1500交替排列且分別連接至位元線電晶體300與源極線電晶體200，能夠有效減少局部位元線1400與局部源極線1500的電阻電容延遲時間。 By alternately arranging the local bit line 1400 and the local source line 1500 and connecting them to the bit line transistor 300 and the source line transistor 200, the resistance of the local bit line 1400 and the local source line 1500 can be effectively reduced. Capacitor delay time.

第1C圖繪示第1A圖的半導體結構10的階梯解碼器100與記憶胞堆疊500_1,500_2...500_K-1,500_K的佈局視圖。 FIG. 1C shows a layout view of the ladder decoder 100 and the memory cell stack 500_1,500_2...500_K-1,500_K of the semiconductor structure 10 in FIG. 1A.

請參照第1C圖，半導體結構10更包括多個階梯解碼器100與記憶胞堆疊500_1,500_2...500_K-1,500_K。 Please refer to FIG. 1C, the semiconductor structure 10 further includes a plurality of ladder decoders 100 and memory cells stacked 500_1,500_2...500_K-1,500_K.

一實施例中，多個階梯解碼器100分別位於記憶胞堆疊500_1、記憶胞堆疊500_2...、記憶胞堆疊500_K-1與記憶胞堆疊500_K的下方。換言之，在縱方向上，多個階梯解碼器100可分別至少部分重疊記憶胞堆疊500_1、記憶胞堆疊500_2...、記憶胞堆疊500_K-1與記憶胞堆疊500_K。 In one embodiment, a plurality of ladder decoders 100 are respectively located below the memory cell stack 500_1, the memory cell stack 500_2..., the memory cell stack 500_K-1, and the memory cell stack 500_K. In other words, in the longitudinal direction, the plurality of ladder decoders 100 may at least partially overlap the memory cell stack 500_1, the memory cell stack 500_2..., the memory cell stack 500_K-1, and the memory cell stack 500_K, respectively.

一實施例中，階梯解碼器100包括局部驅動器110、位準偏移器(level shifter)120與其他電路130。 In one embodiment, the ladder decoder 100 includes a local driver 110, a level shifter 120, and other circuits 130.

舉例而言，局部驅動器110可包括NMOS、PMOS、互補式金屬氧化物半導體反相器(CMOS inverter)、二極體或雙極性電晶體(BJT)。 For example, the local driver 110 may include NMOS, PMOS, CMOS inverter, diode, or bipolar transistor (BJT).

舉例而言，其他電路130可包括泵激電路(pumping circuit)、解碼電路(decoding circuit)或控制電路。 For example, the other circuit 130 may include a pumping circuit, a decoding circuit, or a control circuit.

<第二實施例> <Second Embodiment>

第2A圖繪示依照本發明的第二實施例的半導體結構20的部份上視圖。第2B圖繪示第2A圖的半導體結構20的局部放大圖。第2C圖繪示第2A圖的半導體結構20的立體示意圖。 FIG. 2A shows a partial top view of the semiconductor structure 20 according to the second embodiment of the present invention. FIG. 2B is a partial enlarged view of the semiconductor structure 20 in FIG. 2A. FIG. 2C is a three-dimensional schematic diagram of the semiconductor structure 20 of FIG. 2A.

請同時參照第2A、2B及2C圖，半導體結構20包括互補式金屬氧化物半導體結構(包括源極線電晶體200與位元線電晶體300)、記憶胞堆疊500、絕緣堆疊600、總體位元線700、總體源極線800、第一柱元件910、第二柱元件920、第三柱元件930、第四柱元件940、通孔1100、第一金屬層1200與第二金屬層1300。 Please refer to FIGS. 2A, 2B, and 2C at the same time, the semiconductor structure 20 includes a complementary metal oxide semiconductor structure (including source line transistor 200 and bit line transistor 300), memory cell stack 500, insulating stack 600, and overall bit The element line 700, the overall source line 800, the first pillar element 910, the second pillar element 920, the third pillar element 930, the fourth pillar element 940, the through hole 1100, the first metal layer 1200 and the second metal layer 1300.

第二實施例之半導體結構20和第一實施例之半導體結構10類似，其主要差異在於，源極線電晶體200係相鄰於位元線電晶體300。 The semiconductor structure 20 of the second embodiment is similar to the semiconductor structure 10 of the first embodiment. The main difference is that the source line transistor 200 is adjacent to the bit line transistor 300.

一實施例中，源極線電晶體200與位元線電晶體300係沿著第一方向延伸，第一金屬層1200係沿著第二方向延伸，此第一方向係相異於此第二方向。另一實施例中，此第一方向可定義為實質上平行於記憶胞堆疊500的延伸方向，此第二方向可定義為實質上垂直於記憶胞堆疊500的延伸方向。換言之，第一方向可實質上垂直於第二方向。 In one embodiment, the source line transistor 200 and the bit line transistor 300 extend along a first direction, and the first metal layer 1200 extends along a second direction. The first direction is different from the second direction. direction. In another embodiment, the first direction can be defined as being substantially parallel to the extending direction of the memory cell stack 500, and the second direction can be defined as being substantially perpendicular to the extending direction of the memory cell stack 500. In other words, the first direction may be substantially perpendicular to the second direction.

一實施例中，記憶胞堆疊500係沿著第一方向延伸，總體位元線700、總體源極線800與第一金屬層1200係沿著第二方向延伸，此第一方向係相異於此第二方向。另一實施例中，此第二方向可定義為實質上垂直於記憶胞堆疊500的延伸方向。換言之，第一方向可實質上垂直於第二方向。 In one embodiment, the memory cell stack 500 extends along a first direction, and the global bit line 700, the global source line 800, and the first metal layer 1200 extend along a second direction, and the first direction is different from This second direction. In another embodiment, the second direction can be defined as a direction substantially perpendicular to the extending direction of the memory cell stack 500. In other words, the first direction may be substantially perpendicular to the second direction.

一實施例中，第一柱元件910、第二柱元件920、第三柱元件930與第四柱元件940是在縱方向上延伸，此縱方向 可定義為源極線電晶體200的頂表面的法線方向，此縱方向亦可定義為位元線電晶體300的頂表面的法線方向。 In an embodiment, the first pillar element 910, the second pillar element 920, the third pillar element 930, and the fourth pillar element 940 extend in the longitudinal direction, and the longitudinal direction It can be defined as the normal direction of the top surface of the source line transistor 200, and this longitudinal direction can also be defined as the normal direction of the top surface of the bit line transistor 300.

一實施例中，第一柱元件910、第二柱元件920、第三柱元件930與第四柱元件940位於第一金屬層1200的上方。另一實施例中，第一柱元件910、第二柱元件920、第三柱元件930與第四柱元件940位於第一金屬層1200與第二金屬層1300的上方。又一實施例中，第一柱元件910、第二柱元件920、第三柱元件930與第四柱元件940位於局部位元線1400與位元線電晶體300之間，第一柱元件910、第二柱元件920、第三柱元件930與第四柱元件940位於局部源極線1500與源極線電晶體200之間。 In an embodiment, the first pillar element 910, the second pillar element 920, the third pillar element 930, and the fourth pillar element 940 are located above the first metal layer 1200. In another embodiment, the first pillar element 910, the second pillar element 920, the third pillar element 930, and the fourth pillar element 940 are located above the first metal layer 1200 and the second metal layer 1300. In another embodiment, the first pillar element 910, the second pillar element 920, the third pillar element 930, and the fourth pillar element 940 are located between the local bit line 1400 and the bit line transistor 300, and the first pillar element 910 The second pillar element 920, the third pillar element 930, and the fourth pillar element 940 are located between the local source line 1500 and the source line transistor 200.

一實施例中，第一金屬層1200位於源極線電晶體200與位元線電晶體300的上方。第一金屬層1200可包括合適的導電材料，例如鎢(W)。 In one embodiment, the first metal layer 1200 is located above the source line transistor 200 and the bit line transistor 300. The first metal layer 1200 may include a suitable conductive material, such as tungsten (W).

一實施例中，第二金屬層1300位於第一金屬層1200的上方。另一實施例中，第二金屬層1300位於第一金屬層1200以及第二柱元件920之間，或位於第一金屬層1200以及第四柱元件940之間。第二金屬層1300可包括合適的導電材料，例如鎢(W)。 In one embodiment, the second metal layer 1300 is located above the first metal layer 1200. In another embodiment, the second metal layer 1300 is located between the first metal layer 1200 and the second pillar element 920 or between the first metal layer 1200 and the fourth pillar element 940. The second metal layer 1300 may include a suitable conductive material, such as tungsten (W).

一實施例中，通孔1100位於總體位元線700與第二柱元件920之間。另一實施例中，通孔1100位於總體源極線800與第四柱元件940之間。通孔1100可包括合適的導電材料， 例如鎢(W)。 In an embodiment, the through hole 1100 is located between the global bit line 700 and the second pillar element 920. In another embodiment, the through hole 1100 is located between the overall source line 800 and the fourth pillar element 940. The through hole 1100 may include a suitable conductive material, For example, tungsten (W).

一實施例中，局部位元線1400藉由第一柱元件910電性連接至該位元線電晶體300。亦即，第一柱元件910可將局部位元線1400中的訊號傳遞至位元線電晶體300。另一實施例中，第一柱元件910可直接接觸局部位元線1400或位元線電晶體300的其中之一。又一實施例中，第一柱元件910可直接接觸局部位元線1400以及位元線電晶體300。換言之，第一柱元件910可作為局部位元線1400以及位元線電晶體300之間的連接導體，然本發明並不限於此。 In one embodiment, the local bit line 1400 is electrically connected to the bit line transistor 300 through the first pillar element 910. That is, the first pillar element 910 can transmit the signal in the local bit line 1400 to the bit line transistor 300. In another embodiment, the first pillar element 910 may directly contact one of the local bit line 1400 or the bit line transistor 300. In another embodiment, the first pillar element 910 may directly contact the local bit line 1400 and the bit line transistor 300. In other words, the first pillar element 910 can be used as a connecting conductor between the local bit line 1400 and the bit line transistor 300, but the present invention is not limited to this.

一實施例中，位元線電晶體300藉由第一金屬層1200、第二金屬層1300、第二柱元件920與通孔1100電性連接至總體位元線700。亦即，流入位元線電晶體300中的訊號可依序經由第一金屬層1200、第二金屬層1300、第二柱元件920與通孔1100傳遞至總體位元線700。 In one embodiment, the bit line transistor 300 is electrically connected to the overall bit line 700 through the first metal layer 1200, the second metal layer 1300, the second pillar element 920, and the through hole 1100. That is, the signal flowing into the bit line transistor 300 can be sequentially transmitted to the overall bit line 700 through the first metal layer 1200, the second metal layer 1300, the second pillar element 920 and the through hole 1100.

一實施例中，局部源極線1500藉由第三柱元件930電性連接至源極線電晶體200。亦即，第三柱元件930可將局部源極線1500中的訊號傳遞至源極線電晶體200。另一實施例中，第三柱元件930可直接接觸局部源極線1500或源極線電晶體200的其中之一。又一實施例中，第三柱元件930可直接接觸局部源極線1500以及源極線電晶體200。換言之，第三柱元件930可作為局部源極線1500以及源極線電晶體200之間的連接導體，然本發明並不限於此。 In one embodiment, the local source line 1500 is electrically connected to the source line transistor 200 through the third pillar element 930. That is, the third pillar element 930 can transmit the signal in the local source line 1500 to the source line transistor 200. In another embodiment, the third pillar element 930 may directly contact one of the local source line 1500 or the source line transistor 200. In another embodiment, the third pillar element 930 may directly contact the local source line 1500 and the source line transistor 200. In other words, the third pillar element 930 can be used as a connecting conductor between the local source line 1500 and the source line transistor 200, but the present invention is not limited to this.

一實施例中，源極線電晶體200藉由第一金屬層1200、第二金屬層1300、第四柱元件940與通孔1100電性連接至總體源極線800。亦即，流入源極線電晶體200中的訊號可依序經由第一金屬層1200、第二金屬層1300、第四柱元件940與通孔1100傳遞至總體源極線800。 In one embodiment, the source line transistor 200 is electrically connected to the overall source line 800 through the first metal layer 1200, the second metal layer 1300, the fourth pillar element 940, and the through hole 1100. That is, the signal flowing into the source line transistor 200 can be sequentially transmitted to the overall source line 800 through the first metal layer 1200, the second metal layer 1300, the fourth pillar element 940 and the through hole 1100.

請參照第2C圖，總體位元線700與總體源極線800可交替排列，然本發明並不限於此。 Referring to FIG. 2C, the global bit lines 700 and the global source lines 800 can be alternately arranged, but the present invention is not limited to this.

<第三實施例> <Third Embodiment>

第3圖繪示依照本發明的第三實施例的半導體結構30的局部位元線1400、局部源極線1500、總體位元線700與總體源極線800的佈局視圖。 FIG. 3 shows a layout view of the local bit lines 1400, the local source lines 1500, the global bit lines 700, and the global source lines 800 of the semiconductor structure 30 according to the third embodiment of the present invention.

請參照第3圖，半導體結構30包括多個局部位元線1400、多個局部源極線1500、互補式金屬氧化物半導體結構(包括源極線電晶體200、位元線電晶體300與階梯解碼器100)、總體位元線700、總體源極線800與感測放大器1000。 Referring to FIG. 3, the semiconductor structure 30 includes a plurality of local bit lines 1400, a plurality of local source lines 1500, and a complementary metal oxide semiconductor structure (including source line transistors 200, bit line transistors 300, and steps). The decoder 100), the overall bit line 700, the overall source line 800 and the sense amplifier 1000.

一實施例中，階梯解碼器100係位於記憶胞堆疊500(未繪示)的下方。換言之，在縱方向上，階梯解碼器100至少部分重疊記憶胞堆疊500。 In one embodiment, the ladder decoder 100 is located below the memory cell stack 500 (not shown). In other words, in the longitudinal direction, the ladder decoder 100 at least partially overlaps the memory cell stack 500.

一實施例中，多個局部位元線1400、多個局部源極線1500、總體位元線700與總體源極線800位於記憶胞堆疊500(未繪示)的上方，總體位元線700與總體源極線800位於多個局 部位元線1400與多個局部源極線1500的上方。 In one embodiment, a plurality of local bit lines 1400, a plurality of local source lines 1500, a global bit line 700, and a global source line 800 are located above the memory cell stack 500 (not shown), and the global bit line 700 And the overall source line 800 is located in multiple offices The location element line 1400 and the multiple local source lines 1500 are above.

一實施例中，多個局部源極線1500係電性連接至多個源極線電晶體200，此些源極線電晶體200係電性連接至總體源極線800。多個局部位元線1400係電性連接至多個位元線電晶體300，此些位元線電晶體300係電性連接至該總體位元線700。另一實施例中，電性連接至總體源極線800之局部源極線1500的數量是大於電性連接至總體位元線700之局部位元線1400的數量。舉例而言，電性連接至總體源極線800之局部源極線1500的數量是電性連接至總體位元線700之局部位元線1400的數量的2倍，然本發明並不限於此。 In one embodiment, the multiple local source lines 1500 are electrically connected to the multiple source line transistors 200, and the source line transistors 200 are electrically connected to the overall source line 800. The multiple local bit lines 1400 are electrically connected to the multiple bit line transistors 300, and the bit line transistors 300 are electrically connected to the overall bit line 700. In another embodiment, the number of local source lines 1500 electrically connected to the overall source line 800 is greater than the number of local bit lines 1400 electrically connected to the overall bit line 700. For example, the number of local source lines 1500 electrically connected to the overall source line 800 is twice the number of local bit lines 1400 electrically connected to the overall bit line 700, but the present invention is not limited to this .

一實施例中，總體位元線700係電性連接至感測放大器1000。 In one embodiment, the overall bit line 700 is electrically connected to the sense amplifier 1000.

根據本實施例，由於電性連接至總體源極線之局部源極線的數量是大於電性連接至總體位元線之局部位元線的數量可具有降低電阻、降低短路機率、減少線路(wiring)之使用等優點。 According to this embodiment, since the number of local source lines that are electrically connected to the overall source line is greater than the number of local bit lines that are electrically connected to the overall bit line, the resistance can be reduced, the probability of short circuits is reduced, and the number of lines ( Wiring) and other advantages.

<第四實施例> <Fourth embodiment>

第4圖繪示依照本發明的第四實施例的半導體結構40的局部位元線1400、局部源極線1500、總體位元線700與總體源極線800的佈局視圖。 FIG. 4 shows a layout view of the local bit lines 1400, the local source lines 1500, the global bit lines 700, and the global source lines 800 of the semiconductor structure 40 according to the fourth embodiment of the present invention.

請參照第4圖，半導體結構40包括多個局部位元線 1400、多個局部源極線1500、互補式金屬氧化物半導體結構(包括源極線電晶體200、位元線電晶體300與階梯解碼器100)、總體位元線700、總體源極線800與感測放大器1000。 Please refer to FIG. 4, the semiconductor structure 40 includes a plurality of local bit lines 1400, multiple local source lines 1500, complementary metal oxide semiconductor structures (including source line transistors 200, bit line transistors 300, and ladder decoder 100), overall bit lines 700, and overall source lines 800 With sense amplifier 1000.

第四實施例之半導體結構40和第三實施例之半導體結構30類似，其主要差異在於，電性連接至總體源極線800之局部源極線1500的數量是等於電性連接至總體位元線700之局部位元線1400的數量。 The semiconductor structure 40 of the fourth embodiment is similar to the semiconductor structure 30 of the third embodiment. The main difference is that the number of local source lines 1500 that are electrically connected to the overall source line 800 is equal to that of the overall bit. The number of local bit lines 1400 of line 700.

一實施例中，總體源極線800係連接至頁面緩衝電路(page buffer circuit)。 In one embodiment, the global source line 800 is connected to a page buffer circuit.

根據本實施例，由於電性連接至總體源極線之局部源極線的數量是等於電性連接至總體位元線之局部位元線的數量，可提升陣列操作彈性(array operation flexibility)，且能夠避免電流擁擠效應(current crowding effect)。 According to this embodiment, since the number of local source lines electrically connected to the overall source line is equal to the number of local bit lines electrically connected to the overall bit line, the array operation flexibility can be improved, And can avoid the current crowding effect (current crowding effect).

<第五實施例> <Fifth Embodiment>

第5圖繪示依照本發明的第五實施例的半導體結構50的局部位元線1400、局部源極線1500與總體位元線700的佈局視圖。 FIG. 5 shows a layout view of the local bit lines 1400, the local source lines 1500, and the global bit lines 700 of the semiconductor structure 50 according to the fifth embodiment of the present invention.

請參照第5圖，半導體結構50包括互補式金屬氧化物半導體結構(包括源極線電晶體200與位元線電晶體300)、總體位元線700、局部位元線1400、局部源極線1500與記憶胞堆疊500。記憶胞堆疊500包括多個記憶胞串列及多個字元線 WL0,WL1,...WLj-1,WLj。記憶胞串列與字元線WL0,WL1,...WLj-1,WLj的每個交叉點係形成多個記憶胞1600。局部位元線1400與局部源極線1500可分別電性連接於記憶胞1600的源極或汲極。 Referring to FIG. 5, the semiconductor structure 50 includes a complementary metal oxide semiconductor structure (including source line transistor 200 and bit line transistor 300), overall bit line 700, local bit line 1400, and local source line 1500 stacks 500 with memory cells. The memory cell stack 500 includes a plurality of memory cell strings and a plurality of word lines WL 0 , WL 1 ,... WL j-1 , WL j . Each intersection of the memory cell string and the word lines WL 0 , WL 1 ,...WL j-1 , WL j forms a plurality of memory cells 1600. The local bit line 1400 and the local source line 1500 can be electrically connected to the source or drain of the memory cell 1600, respectively.

一實施例中，多個局部位元線1400係分別電性連接至多個位元線電晶體300，此些位元線電晶體300係電性連接至總體位元線700。 In one embodiment, the multiple local bit lines 1400 are electrically connected to the multiple bit line transistors 300 respectively, and the bit line transistors 300 are electrically connected to the overall bit line 700.

一實施例中，多個局部源極線1500係分別電性連接至多個源極線電晶體200，此些源極線電晶體200透過局部佈線(local routing)進行接地。 In one embodiment, the plurality of local source lines 1500 are electrically connected to the plurality of source line transistors 200, and the source line transistors 200 are grounded through local routing.

根據上述實施例，本發明提供一種半導體結構。半導體結構包括一記憶胞堆疊以及一互補式金屬氧化物半導體結構。互補式金屬氧化物半導體結構位於記憶胞堆疊的下方，且互補式金屬氧化物半導體結構包括一源極線電晶體與一位元線電晶體。 According to the above-mentioned embodiments, the present invention provides a semiconductor structure. The semiconductor structure includes a memory cell stack and a complementary metal oxide semiconductor structure. The complementary metal oxide semiconductor structure is located under the memory cell stack, and the complementary metal oxide semiconductor structure includes a source wire transistor and a bit wire transistor.

相較於互補式金屬氧化物半導體結構是位於記憶胞堆疊的周邊區域而非位於記憶胞堆疊之下的比較例而言，本發明的半導體結構藉由設置互補式金屬氧化物半導體結構於記憶胞堆疊之下，能夠有效減小記憶體裝置之尺寸，進一步降低製造成本，從而提升晶片性能。再者，藉由使局部位元線與局部源極線係交替排列且分別連接至位元線電晶體與源極線電晶體，能夠有效減少局部位元線與局部源極線的電阻電容延遲時間。 Compared with the comparative example in which the complementary metal oxide semiconductor structure is located in the peripheral area of the memory cell stack instead of under the memory cell stack, the semiconductor structure of the present invention is provided by the complementary metal oxide semiconductor structure in the memory cell. Under the stack, the size of the memory device can be effectively reduced, the manufacturing cost is further reduced, and the chip performance is improved. Furthermore, by alternately arranging the local bit lines and the local source lines and connecting them to the bit line transistors and the source line transistors respectively, the resistance and capacitance delays of the local bit lines and the local source lines can be effectively reduced. time.

綜上所述，雖然本發明已以實施例揭露如上，然其 並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In summary, although the present invention has been disclosed as above in embodiments, its It is not intended to limit the present invention. Those with ordinary knowledge in the technical field of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to those defined by the attached patent scope.

200:源極線電晶體 200: source line transistor

300:位元線電晶體 300: bit line transistor

910:第一柱元件 910: The first column element

920:第二柱元件 920: second column element

930:第三柱元件 930: third column element

940:第四柱元件 940: Fourth column element

1200:第一金屬層 1200: the first metal layer

1300:第二金屬層 1300: second metal layer

Claims (10)

一種半導體結構，包括：一記憶胞堆疊，包括一階梯區；以及一互補式金屬氧化物半導體結構，位於該記憶胞堆疊的下方；其中，該互補式金屬氧化物半導體結構包括一階梯解碼器、一源極線電晶體與一位元線電晶體，其中在縱方向上，該階梯解碼器至少部分重疊該階梯區。 A semiconductor structure includes: a memory cell stack including a step region; and a complementary metal oxide semiconductor structure located below the memory cell stack; wherein the complementary metal oxide semiconductor structure includes a ladder decoder, A source line transistor and a bit line transistor, wherein in the longitudinal direction, the ladder decoder at least partially overlaps the ladder region. 如請求項1所述之半導體結構，其中該源極線電晶體係相鄰於該位元線電晶體。 The semiconductor structure according to claim 1, wherein the source line transistor system is adjacent to the bit line transistor. 如請求項1所述之半導體結構，更包括：一局部位元線，位於該記憶胞堆疊的上方；以及一第一柱元件，位於該局部位元線與該位元線電晶體之間；其中該局部位元線藉由該第一柱元件電性連接至該位元線電晶體。 The semiconductor structure according to claim 1, further comprising: a local bit line located above the memory cell stack; and a first pillar element located between the local bit line and the bit line transistor; The local bit line is electrically connected to the bit line transistor through the first column element. 如請求項1所述之半導體結構，更包括：一第一金屬層，位於該位元線電晶體的上方；一第二柱元件，位於該第一金屬層的上方；以及一總體位元線，位於該記憶胞堆疊的上方；其中，該位元線電晶體係藉由該第一金屬層以及該第二柱元件電性連接至該總體位元線。 The semiconductor structure according to claim 1, further comprising: a first metal layer located above the bit line transistor; a second pillar element located above the first metal layer; and an overall bit line , Located above the memory cell stack; wherein, the bit line electro-crystalline system is electrically connected to the overall bit line through the first metal layer and the second pillar element. 如請求項4所述之半導體結構，其中，該位元線電晶體係沿著一第一方向延伸，該第一金屬層係沿著一第二方向延伸，且該第一方向係相異於該第二方向。 The semiconductor structure according to claim 4, wherein the bit line transistor system extends along a first direction, the first metal layer extends along a second direction, and the first direction is different from The second direction. 如請求項1所述之半導體結構，更包括：一局部源極線，位於該記憶胞堆疊的上方；以及一第三柱元件，位於該局部源極線與該源極線電晶體之間；其中該局部源極線藉由該第三柱元件電性連接至該源極線電晶體。 The semiconductor structure according to claim 1, further comprising: a local source line located above the memory cell stack; and a third pillar element located between the local source line and the source line transistor; The local source line is electrically connected to the source line transistor through the third column element. 如請求項1所述之半導體結構，更包括：一第一金屬層，位於該源極線電晶體的上方；一第四柱元件，位於該第一金屬層的上方；以及一總體源極線，位於該記憶胞堆疊的上方；其中，該源極線電晶體係藉由該第一金屬層以及該第四柱元件電性連接至該總體源極線。 The semiconductor structure according to claim 1, further comprising: a first metal layer located above the source line transistor; a fourth pillar element located above the first metal layer; and an overall source line , Located above the memory cell stack; wherein, the source line electro-crystalline system is electrically connected to the overall source line through the first metal layer and the fourth column element. 如請求項7所述之半導體結構，其中，該源極線電晶體係沿著一第一方向延伸，該第一金屬層係沿著一第二方向延伸，且該第一方向係相異於該第二方向。 The semiconductor structure according to claim 7, wherein the source line transistor system extends along a first direction, the first metal layer extends along a second direction, and the first direction is different from The second direction. 如請求項1所述之半導體結構，更包括： 複數個局部源極線，位於該記憶胞堆疊的上方；一總體源極線，位於該記憶胞堆疊的上方；其中，該些局部源極線係電性連接至複數個該源極線電晶體，且該些源極線電晶體係電性連接至該總體源極線；複數個局部位元線，位於該記憶胞堆疊的上方；以及一總體位元線，位於該記憶胞堆疊的上方；其中，該些局部位元線係電性連接至複數個該位元線電晶體，且該些位元線電晶體係電性連接至該總體位元線；其中，電性連接至該總體源極線之該些局部源極線的數量是大於或等於電性連接至該總體位元線之該些局部位元線的數量。 The semiconductor structure described in claim 1, further including: A plurality of local source lines are located above the memory cell stack; a global source line is located above the memory cell stack; wherein, the local source lines are electrically connected to a plurality of the source line transistors , And the source line transistor systems are electrically connected to the overall source line; a plurality of local bit lines are located above the memory cell stack; and a global bit line is located above the memory cell stack; Wherein, the local bit lines are electrically connected to a plurality of bit line transistors, and the bit line transistor systems are electrically connected to the overall bit line; wherein, they are electrically connected to the overall source The number of the local source lines of the polar line is greater than or equal to the number of the local bit lines electrically connected to the overall bit line. 如請求項1所述之半導體結構，其中，該源極線電晶體與該位元線電晶體係設置於該記憶胞堆疊的相對兩側。 The semiconductor structure according to claim 1, wherein the source line transistor and the bit line transistor system are disposed on opposite sides of the memory cell stack.
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